REGISTROS INTERNOS PIC18Fxx

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TOSU Top-of-Stack Upper Byte (TOS<20:16>) ---0
TOSH Top-of-Stack High Byte (TOS<15:8>)
TOSL Top-of-Stack Low Byte (TOS<7:0>)
STKPTR STKFUL STKUNF SP4 SP3 SP2 SP1 SP0
PCLATU Holding Register for PC<20:16>
PCLATH Holding Register for PC<15:8>
PCL PC Low Byte (PC<7:0>)
TBLPTRU bit 21 (1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT Program Memory Table Latch
PRODH Product Register High Byte
PRODL Product Register Low Byte
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP
INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF
INDF0 Uses contents of FSR0 to address data memory value of FSR0 not changed (not a physical register)
POSTINC0 Uses contents of FSR0 to address data memory value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory value of FSR0 post-decremented (not a physical register)
PREINC0 Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
PLUSW0 Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register) value of FSR0 offset by W
FSR0H Indirect Data Memory Address Pointer 0 High Byte
FSR0L Indirect Data Memory Address Pointer 0 Low Byte
WREG Working Register
INDF1 Uses contents of FSR1 to address data memory value of FSR1 not changed (not a physical register)
POSTINC1 Uses contents of FSR1 to address data memory value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory value of FSR1 post-decremented (not a physical register)
PREINC1 Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
PLUSW1 Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register) value of FSR1 offset by W
FSR1H Indirect Data Memory Address Pointer 1 High Byte
FSR1L Indirect Data Memory Address Pointer 1 Low Byte
BSR Bank Select Register
INDF2 Uses contents of FSR2 to address data memory value of FSR2 not changed (not a physical register)
POSTINC2 Uses contents of FSR2 to address data memory value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory value of FSR2 post-decremented (not a physical register)
PREINC2 Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register)
PLUSW2 Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register) value of FSR2 offset by W
FSR2H Indirect Data Memory Address Pointer 2 High Byte
FSR2L Indirect Data Memory Address Pointer 2 Low Byte
STATUS N OV Z DC C
TMR0H Timer0 Register High Byte
TMR0L Timer0 Register Low Byte
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
WDTCON SWDTEN
RCON IPEN SBOREN(2) RI TO PD POR BOR
TMR1H Timer1 Register High Byte
TMR1L Timer1 Register Low Byte
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TMR2 Timer2 Register
PR2 Timer2 Period Register
T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
SSPBUF MSSP Receive Buffer/Transmit Register
SSPADD MSSP Address Register in I2C Slave mode. MSSP Baud Rate Reload Register in I2C Master mode.
SSPSTAT SMP CKE D/A P S R/W UA BF
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/
SSPCON2 GCEN ACKSTAT SEN
ADMSK5(7) ADMSK4(7) ADMSK3(7) ADMSK2(7) ADMSK1(7)
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
ADCON2 ADFM ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCPR1L Capture/Compare/PWM Register 1 Low Byte
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPR2H Capture/Compare/PWM Register 2 High Byte
CCPR2L Capture/Compare/PWM Register 2 Low Byte
CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN
ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3)
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3)
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
TMR3H Timer3 Register High Byte
TMR3L Timer3 Register Low Byte
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
SPBRGH EUSART Baud Rate Generator Register High Byte
SPBRG EUSART Baud Rate Generator Register Low Byte
 File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RCREG EUSART Receive Register
TXREG EUSART Transmit Register
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
EEADR EEPROM Address Register
EEDATA EEPROM Data Register
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1 EEPGD CFGS FREE WRERR WREN WR RD
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
OSCTUNE INTSRC TUN4 TUN3 TUN2 TUN1 TUN0
TRISE(3) TRISE2 TRISE1 TRISE0
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISC0
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISA TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
LATE(3) LATE2 LATE1 LATE0
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
LATC LATC7 LATC6 LATC2 LATC1 LATC0
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
LATA LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
PORTE RDPU(3) RE3(5) RE2(3) RE1(3) RE0(3)
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
PORTC RC7 RC6 RC5(6) RC4(6) RC2 RC1 RC0
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
PORTA RA6(4) RA5 RA4 RA3 RA2 RA1 RA0
UEP15 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP14 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP13 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP12 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP11 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP10 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP9 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP8 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP7 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP6 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP5 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP4 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP3 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP2 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP1 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP0 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UCFG UTEYE UOEMON UPUEN UTRDIS FSEN PPB1 PPB0
UADDR ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
UCON PPBRST SE0 PKTDIS USBEN RESUME SUSPND
USTAT ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI
UEIE BTSEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE
UEIR BTSEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF
UIE SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
UIR SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF
UFRMH FRM10 FRM9 FRM8
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0
SPPCON(3) SPPOWN SPPEN
SPPEPS(3) RDSPP WRSPP SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Note
1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as 0.
3: These registers and/or bits are not implemented on 28-pin devices and are read as 0. Reset values are shown for 40/44-pin devices; individual unimplemented bits should
be interpreted as - .
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read 0.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as 0.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C Slave mode only
PIC18FXXXX INSTRUCTION SET

Mnemonic, Description Cycles 16-Bit Instruction Word Status Affected Notes

Operands MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF f s, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with borrow 1 0101 01da ffff ffff C, DC, Z, OV, N
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with borrow 1 0101 10da ffff ffff C, DC, Z, OV, N
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None 1, 2
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None 1, 2
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None 3, 4
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None 3, 4
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None 1, 2
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n,s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP No Operation 1 0000 0000 0000 0000 None
NOP No Operation 1 1111 xxxx xxxx xxxx None 4
POP Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
 RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f,k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None

Note
1. When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins
themselves. For example, if the data latch is 1 for a pin configured as an input and is driven low by an external device, the data will be written
back with a 0.
2. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned.
3. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a
NOP.
4. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the
instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.