Adiabatic Switching

A Survey of Reversible Computation Circuits

Benjamin Bobich, 2004

 Agenda for Today
1. The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

2. Early Adiabatic Circuit Structures

3. Modern Adiabatic Logic Families

4. Difficulties and Remedies for Adiabatic Circuits

5. Final Remarks
 Agenda for Today
¾ The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

Early Adiabatic Circuit Structures

Modern Adiabatic Logic Families

Difficulties and Remedies for Adiabatic Circuits

Final Remarks
 Basics of Adiabatic Logic

• Adiabatic: occurring without loss or gain of heat

Conventional CMOS Adiabatic CMOS

Changing value of bit requires
converting bit signal into heat
2 States: True, False
Speed is outstanding, but
power dissipation is now a
huge issue.
Returns value (energy) of
the bit back to the source
3 States: True, False, Off
Very low power dissipation
is achieved at expense of
speed.
 Theory of Reversible Computation

The energy dissipation (∆E) of combinational

logic can be made arbitrarily small by operating
the circuit slowly enough [1].

Q: What’s arbitrarily small, and what is slow?

 Power Dissipation in Adiabatic Charging

• Q=CV
“On resistance” • I=Q/T=CV/T
• E=I2RT (Resistor)
• =(CV/T)2RT
• =(2RC/T)(1/2 CV2)

Better than CMOS by

a factor of (2RC/T) [2]
Charging a load capacitance
through a switch
 Agenda for Today
The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

¾ Early Adiabatic Circuit Structures

Modern Adiabatic Logic Families

Difficulties and Remedies for Adiabatic Circuits

Final Remarks
 Early Adiabatic Circuit Structures [2]

Power Supply Adiabatic AND

 Early Adiabatic Latch [2]

(Latch) Adiabatic Switching, Low Energy Computing, and the Physics of Storing
and Erasing Information J. G. Koller W. C. Athas 1993
 Agenda for Today
The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

Early Adiabatic Circuit Structures

¾ Modern Adiabatic Logic Families

Difficulties and Remedies for Adiabatic Circuits

Final Remarks
 To Modern Adiabatic Logic Circuits
Original circuits were good conceptual models, but not very
practical practical circuits.

“Hot Clock NMOS” was published in 1985 by Charles

Seitz at Cal-Tech [3]. It included the idea of a power-clock, but
involved no charge recovery circuit.

In 1993, “Adiabatic Switching, Low Energy Computing, and the

Physics of Storing and Erasing Information” was published by William
Athas and Jeff Koller. (Previous slides came from it)

CMOS paper entitled “Low-Power Digital Systems Based on

Adiabatic Switching Principles,” was published by Athas
in Dec. of 1994 [4]
 Modern Adiabatic Logic Families

In June 1994 John Denker

came up with the 2N-2N2D
adiabatic logic family and
2N-2N2P Logic 1 year later
(Shown Right).

2N-2N2P Adiabatic AND [5]

 Modern Adiabatic Logic Families

Pass Trans. Adiabatic Logic (PAL) [6] Clocked CMOS Adiabatic Logic (CAL) [7]
*Different from CPERL, mentioned later
 Modern Adiabatic Logic Families

Complementary Pass Transistor Adiabatic Pseudo-Domino Logic

Energy Recovery Logic Inverter Inverter (APDL) [9]
(CPERL) [8] •Diodes are a problem
 Modern Adiabatic Logic Families
True Single Phase Energy Recovering Logic (TSEL) [10]

PMOS NMOS
•Paved the way for SCAL and SCAL-D
TSEL Timing Waveform [10]
 Most Promising Logic Families

• Source Coupled Adiabatic Logic with Diode Connected X’s

(SCAL-D) [11] First adiabatic technology designed specifically
for high speed.

• Positive Feedback Adiabatic Logic (PFAL) [12]

Best flip-flop based adiabatic solution as far as power and
drivability are concerned.

• Recent research suggests that SCAL-D and PFAL are the most
practical by today’s standards. [11,13]
Basic PFAL Adder, Inverter, and Timing [14]
SCAL-D Buffers (Enhancement of TSEL) [15]

PMOS Buffer NMOS Buffer

Cascaded PNPN in SCAL-D [15]

P N P N
 Agenda for Today
The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

Early Adiabatic Circuit Structures

Modern Adiabatic Logic Families

¾ Difficulties and Remedies for Adiabatic Circuits

Final Remarks
 Challenges of Recovery Circuits

There are two big challenges of energy recovering circuits:

1. Circuit implementation of time-varying power

sources

2. Computations should be implemented by low overhead circuit

structures that use standard MOSFET devices
Synchronous Resonant Power Clock Generator [16]
 Problems of Adiabatic Logic
It is very slow by today’s standards.

It requires 50% more area than conventional CMOS, and

simple circuit designs can be very complicated (consider
previous slides. However:

A multiplier built by Marios Papaefthymiou at the University of

Michigan operated at 200 MHz at .25 the power dissipation of
conventional CMOS (2003) [15]

A .13um 8 Bit Ripple Carry Adder was constructed at Infineon.

Significant Energy savings were only acheivable below 100 MHz,
with 6x less energy dissipation than CMOS at 20 MHz (2003) [14]
 Fixing the Speed Problem…
Adiabatic circuits face difficulties in speed for a number
Of reasons:

• Charging time is inherently much slower than CMOS

• Adiabatic circuits are difficult to pipeline.
• Increasing speed of adiabatic circuits enlarges power-clock data
sensitivity

Factors at work aiding the speed problem:

• Scaling decreases R and C, which naturally makes T smaller

• Multiple power-clock designs to handle pipelining
• New Technoligies (like SCAL) that use only X’s to eliminate DC lines.
SCAL is the first real speed oriented adiabatic technology.
 Agenda for Today
The Basics of Adiabatic Logic and the
Fundamentals of Adiabatic Charging

Early Adiabatic Circuit Structures

Modern Adiabatic Logic Families

Difficulties and Remedies for Adiabatic Circuits

¾ Final Remarks
 Final Remarks
Adiabatic circuitry will always be behind conventional CMOS in speed, but
as conventional CMOS gets faster Adiabatic circuitry will get faster as well.
It may become practical in the near future. Source Coupled Adiabatic
Logic is the most promising technology at this time.

Single phase clocking is less complicated to implement, but multiple phase

clocking is faster. Which will win?

If Source Coupled Adiabatic Logic prevails, great attention must go into

sinusoidal clock generator circuits.
 References
[1] Landauer, Rolf “Irreversibility and Heat Generation in the Computing Process”,
IBM Journal, July 1961, pp 183-191
[2] Koller, J. G., Athas, W. C. Adiabatic Switching, Low Energy Computing, and the
Physics of Storing and Erasing Information, Proceedings of the Workshop on
Physics and Computation, PhysComp’92, Dallas, Texas, Oct. 2-4, 1992 IEEE Press,
1993, pp 267-270
[3] Seitz, C., “Hot Clock nMOS,” Proceedings of the 1985 Chapel Hill Conference
on VLSI, Computer Science Press, 1985
[4] Athas, W.C. et.al, “Low-Power Digital Systems Based on Adiabatic Switching
Principles,” IEEE Transactions on VLSI Systems, Dec. 1994 pp 398-407
[5] Denker, John S. “A Review of Adiabatic Computing,” 1994 IEEE Symposium
on Low Power Electronics pp 94-97
[6] Oklobdzija, Maksimovic, Lin, “Pass-Transistor Adiabatic Logic Using Single Power
Clock Supply” IEEE Transactions on Circuits and Systems-II Analog and Digital
Signal Processing, Vol. 44, No. 10, Oct. 1997 pp 842-846
[7] Maksimovic, Oklobdzija, Nikolic, Current, “Clocked CMOS Adiabatic Logic with
Integrated Single-Phase Power Clock Supply, Experimental Results,” ACM, Inc.
August 1997 pp 323-327
 References
[8] Chang, Hung, Wang, “Complementary pass-transistor energy recovery logic for
low-power Applications,” IEE Proceedings March 2002 pp 146- 151
[9] Wong, H.H. Lau, K. T. “Adiabatic Pseudo-Domino Logic with Dual Rail Inputs,”
2001 pp 340-343
[10] Kim S. and Papaefthymiou M.C., “True single-phase energy-recovering logic for
low-power, high-speed VLSI,” Proc. Int. Symp. Low-Power Electron. Design,
Monterey, CA Aug. 1998 pp 167-172
[11] Kim, S. and Papaefthymiou, M. C. “True Single-Phase Adiabatic Circuitry”
IEEE Transactions on VLSI Systems, Vol. 9 No. 1 February 2001 pp 52-63
[12] Vetuli, A. Pascoli, S.D. Reyneri, L.M. “Positive Feedback in Adiabatic Logic”
Electronics Letters, 26th September 1996 Vol. 32 pp 1867-1869
[13] A. Blotti, S. Di Pascoli, R. Saletti, “A comparison of some circuit schemes for
semi-reversible adiabatic logic,” Int. J. Electronics, 2002, Vol. 89 pp 147-158
[14] Schmitt-Landsiedel, Doris; Amirante, Ettore; Jurgen, Fischer; “An Ultra Low-
Power Adiabatic Adder Embedded in a Standard .13um CMOS Environment,” April
2003 pp 599-602
[15] Papaefthymiou, Ziesler, Kim, “Design, Verification, and Test of a True Single-
Phase 8-bit Adiabatic Multiplier,” June 2001 pp 42-58
[16] Mahmoodi-Meimand, Afzali-Kusha, “Efficient Power Clock Generation For
Adiabatic Logic,” September 2001 pp 642-645
Questions?