IAETSD Journal for Advanced Research in Applied Sciences, Volume 4, Issue 1, Jan-June /2017

ISSN (Online): 2394-8442

Modeling behavior of high-speed ser/des links using C/C++

[1]
Dhruti H G. [2] Anoop Karunan, [3] Mrs. Swetha S
[1]
Dept. of ISE, [2] Analog Engineer, [3] Asst. Professor, Dept. of ISE
[1, 3]
R. V. College of Engineering, [2] Intel Technology India Pvt. Ltd.,
Bangalore, India
dhrutihgrao@gmail.com

ABSTRACT.

IBIS-AMI (I/O Buffer Information Specification-Algorithmic Modeling Interface) is an industry modeling

standard that is used for modeling high-speed SER/DES (Serializer/Deserializer) PHYs. The models are currently generated
using EDA tools or other analog simulation tools. These C/C++ models are system generated and hence it is difficult to modify
or reuse them as they would be customized for the particular model. Hence, it is useful to create a C/C++ model that can be
reused instead of using the system generated C/C++ model. The C/C++ model mimics the behavior of each block present in the
SER/DES architecture.

Keywords: IBIS-AMI, Behavioral modeling, SER/DES links

1. INTRODUCTION
The brute-force approach of simulating the SER/DES system is the traditional approach followed to model the SER/DES PHYs. The
whole process of simulation is time consuming and also the scaling limitations of the EDA tools cause delays in the release of the final model.
The scaling limitation of the EDA tool is that the whole SER/DES system cannot be modeled at a time. EDA tool allows to model only few
blocks simultaneously.

This is a major cause of concern. The solution is to create a behavioral model[1][2] of the system in a high-level programming
language. Often, the models are created in C/C++ as they are compatible with IBIS-AMI standards[3] which are very widely used. IBIS-AMI
C/C++ models are used to achieve a standardization and interoperability between various IC vendors and to support the models on various EDA
tools.

The behavioral models are converted into a .dll files[4] that enable IP protection of the vendor and at the same time ensures
interoperability and platform independence to run on various EDA tools. The use of C++ gives the advanatges of using the various libraries such
as STL(Standard Template Library), add-on libraries like odeint, GNU radio etc for implementing the signal processing functions. C/C++ being
open source also helps cut-down the cost factors when compared to the current use of EDA tools and Matlab tools that automate the process of
model generation in C/C++.

2. METHODOLOGY
The approach is to model the SER/DES system as a super-block consisting of multiple sub-blocks. Each sub-block is a component of
the SER/DES system. The behavioral model for each sub-block is created and coded in C/C++ and tested individually for determining whether
they meet expectations.

Later, they are integrated to form the overall super block. The C/C++ modules thus created are next aligned according to the IBIS-AMI
standrds, then compiled to genrate the .dll file and validated on an EDA tool. Each block can be compiled as an individual function that can be
called from AMI_Init() or AMI_Getwave() function depending on the mode of simulation.

To Cite This Article: Dhruti H G., Anoop Karunan and Mrs. Swetha S,. Modeling behavior of high-
speed ser/des links using C/C++. Journal for Advanced Research in Applied Sciences ; Pages: 146-150
147. Dhruti H G., Anoop Karunan and Mrs. Swetha S,. Modeling behavior of high-speed ser/des links using C/C++.
Journal for Advanced Research in Applied Sciences; Pages: 146-150

3. IMPLEMENTATION

Figure 1: Basic block diagram of a SER/DES link

A. Serializer

The serializer is a module that takes parallel data as input and produces serialized data on single line (single ended or differential pair
transmission) as output. The bits could be generated arbitrarily or a PRBS pattern can be generated by implementing shift registers. To
demonstrate the serializer functionality, the bits can be stored in an array and accessed by the module in a serial fashion.

B. Transmitter

The transmitter module contains an equalizer to equalize the energy among the high-frequency and low frequency bit patterns. The
transmitter equalizers perform a pre-emphasis [5] of the signal to be transmitted. This method will pre-distort the signal before transmitting
such that the channel distortion will cancel out this at the receiver. Usually Feed-Forward Equalizers [6] are used in this case. Based on the
design requirements, the FFE [7] filters can be designed. It provides flexibility to choose any number of taps (2,3, .n). The general equation of
an n-tap FFE filter is as shown below:

= + + + + (1)

Where W (z) is the equalized output and a1, a2. are the respective tap coefficients.

C. Channel

The channel can be modelled [8] either as a FIR filter or in terms of the RC constant of the channel. Passing the TX output through the
channel is equivalent to the convolution of the equalized bit pattern with the channel impulse response. The general transfer function to model a
channel in terms of RC constant is as shown below.

=
+

D. Receiver

The receiver module contains a CTLE and DFE where either one of them can be optional depending on the design requirements. All these
blocks run along with the help of the CDR (Clock Data Recovery) circuit that gives out the optimal sample points for recovering the data at the
receiver. In some circuits a CTLE is enough to recover the signal and some designs require a DFE circuit to cancel out the ISI(Inter Symbol
Interference) caused by the interference of other bits on the current bit.

a. CTLE

CTLE (Continuous Time Linear Equalization) module, boosts high-frequency patterns and attenuates the low-frequency patterns. This
helps to reduce the noise and ISI induced by the channel. CTLE is modeled in poles and zeroes notation of a transfer function. The general
equation of a CTLE is as shown below where z indicates zeroes, p indicates poles and A is the DC gain of the CTLE. To pass the receiver
input through the CTLE, convolve the receiver input with the CTLE impulse response. The frequency response of the CTLE is also found to
determine the frequencies at which the CTLE will boost the bit patterns energy by a certain magnitude. It is an optional block and is architecture
specific. Sometimes it is used along with the DFE to recover the accurate signals or sometimes used alone depending on the system architecture
design.

+ + . . +
=
+ + . . +

b. CDR

CDR (Clock and Data Recovery) circuit is used to synchronize the receiver clock with that of the transmitter clock [9]. Basically it is
used to find the optimal sampling points from the incoming signal at receiver. A CDR can be PLL based CDR. The phase detector (PD)
mechanism used in the CDR could be a linear phase detector like Hogged PD or a non-linear phase detector like Bang-Bang PD, Muller-Muller
PD etc [10].
148. Dhruti H G., Anoop Karunan and Mrs. Swetha S,. Modeling behavior of high-speed ser/des links using C/C++.
Journal for Advanced Research in Applied Sciences; Pages: 146-150

c. DFE

A DFE (Decision Feedback Equalizer) is an adaptive equalizer [11] that is used to remove the effect of ISI of one bit on the other bits.
The DFE can in turn use an adaptation algorithm to calculate ISI and eliminate it using a FIR or an IIR filter [12]. The adaptation algorithm used
in the DFE can be LMS (Least Mean Square error) or variants of LMS algorithm, MMSE (Minimum Mean Square Error) algorithm etc. The
weights given out by the adaptation algorithm form the co-efficients of the n-tap filter used to remove the ISI from the signal. Then the
calculated output is sent to a decision slicer to quantize it and decide whether the signal is a 1 or a 0 bit. Usually the decision inside the DFE
whether the incoming signal is 1 or 0 is made within 1 UI and also the ISI is calculated. To reduce this tight constraint, the concept of loop
unrolling is used in DFE. Loop unrolling is where the decision circuit calculates the ISI both in case of a 1 and a 0. Once the error converges, the
tap weights remain almost same. Not just standard LMS, but sign-sign LMS, Normalized LMS, MMSE etc algorithms can also be used for
adaptation.

d. Deserializer

Deserializer module converts serial data stream, back to parallel data, which will be used by receiver design. The module takes in the
serial data and converts it back to parallel data with recovered clock. For the modelling purpose, serial data is fed as input to this module, and
parallel data is checked against the transmitted stream, basically TX data and RX output data are compared.

4. RESULTS
According to the implementation carried out as stated above, following results are inferred. The behavior of the blocks are
implemented as modules and then integrated together to mimic the whole system. The data for graphs are generated by dumping data to the
proper formats and then plotting the required graphs using that data.

These graphs are plotted for analysis of the performance of the blocks.

Figure 2: A random bit pattern generated at 10GHz

Here, the common mode transmission is used where 0 accounts to 0V and 1 bit accounts to 1V.

Figure 3: Equalized pulse from a 3-tap FFE filter

A 3-tap FFE with -0.1, 0.75 and -0.15 are used as the tap weights and the FIR filter is implemented using equation 1. Similarly, any n-
tap equalizer can be used using the equation 1, to model the behavior of the FFE filter at the TX. The TX driver is also an important component,
but it is not modeled here as the equalized output is stored in an array and accessed sequentially hence, analog simulation is not required.
149. Dhruti H G., Anoop Karunan and Mrs. Swetha S,. Modeling behavior of high-speed ser/des links using C/C++.
Journal for Advanced Research in Applied Sciences; Pages: 146-150

Figure 4: Channel pulse response

Here, the channel is implemented in terms of RC constant denoted by in the equation 2. The equalized pulses are convolved with the
pulse response of the channel to obtain the channel output. The same procedure is used even if the channel is modeled as an n-tap FIR filter.

The CTLE block here, reduces the spread of the bit to the next UI. In some receivers, only CTLE is enough to recover the bits
correctly and hit the required bit error rate (BER).

Figure 5: CTLE impulse response

Figure 6: CTLE frequency response

Figure 7: LMS algorithm error convergence when steps size=0.02

150. Dhruti H G., Anoop Karunan and Mrs. Swetha S,. Modeling behavior of high-speed ser/des links using C/C++.
Journal for Advanced Research in Applied Sciences; Pages: 146-150

5. CONCLUSION
In this implementation, various generic blocks have been discussed along with their behaviors and the procedure to model them in C/C++
is covered. The C/C++ code can be either generic or specific to the architecture. Some generic blocks like Serializer, TX FFE, and De-serializer
can be reused instead of rewriting the code for the same. The convolution module has a high reusability factor. The main advantage of C/C++
modeling is that the model is reusable, quickly developed when compared to analog simulation. IP security concerns are also addressed as IP
from vendor are packaged into .dll files which is binary format and cannot be reverse engineered. It also enables quick and easy modifications
to code and supports both time-domain and statistical analysis methods with IBIS-AMI. Thus, it is advantageous to model the behavior of
SER/DES systems using C/C++ along with IBIS-AMI.

In future, a general framework or a template can be created that can be used to create IBIS-AMI compliant C/C++ models. A library
that contains modules specifically for SER/DES modeling can be created and used for the same. The library will provide a generic APIs that can
be called to execute the particular block. This will help in creating a layer of abstraction and also helps to protect the IP of the IC vendor. Thus,
there is lot of scope for improving the current traditional process of analog simulation of the SER/DES links by using IBIS-AMI C/C++ models.

REFERENCES
[1] A modern systems approach to building modern high-speed links, Vladimir Stojanovic, MIT, 2011.

[2] P.Noel, F. Zarkeshvari, T. Kwasniewski, Recent advances in high-speed serial I/O trends, standards and techniques, Canadian Conference
on Electrical & Computer Engineering, 2005, pp. 1292-1295.

[3] IBIS Modeling Cookbook for IBIS Version 6.0, The IBIS Open Forum, September 2013.

[4] Bob Sullivan, Michel Rose, Jason Boh, Simulating high-speed serial channels with IBIS-AMI models, Technology Whitepaper, Curtiss
Wright Controls Defense Solutions, 2011.

[5] L.Rabinier, Linear program design of finite impulse response digital filters, IEEE Transactions on Audio and Electro-acoustics, Volume:
20, Issue:4, Oct 1972, pp. 280-288.

[6]Litwin L., FIR and IIR Digital Filters, IEEE Potentials, 2002, pp. 28-31.

[7] Cetin, O.N. Gerek, Y. Yardimci, Equiripple FIR filter design by the FFT algorithm, IEEE Signal Processing Magazine, March 1997, pp.
60-64.

[8] J.L. Drewniak, Channel Modeling and Analysis for Signal Integrity in High-Speed Digital Designs, IEEE EMC chapter, 2014, pp. 25-29.

[9] Behzad Razavi, Challenges in the Design of High-Speed Clock and Data Recovery Circuits, IEEE Communications Magazine, 2002, pp.
94-101.

[10] Pavan Hanumolu, Clock and data recovery architectures and circuits, Intel India 2016.

[11] C.A. Belifore, J. H. Park, Decision Feedback Equalizers, Proceedings of the IEEE, Volume 67, June 2005, pp. 1143-1156.

[12] E Zhian Tabasy, A Shafuk, K. Lee, S Hoyos, S Palermo, A 6b10GS/s TI-SAR ADC with Low-Overhead Embedded FFE/DFE Equalization
for Wireline Reciever Applications, IEEE journal of solid state circuits, 2014.