2016 The 2nd International Conference on Contro), Automation and Robotics
Proposed Structure Hardware of the CNC for Machine Tools Based on System on
Chip
Do Van Can
Quy Nhon University
Quy Nhon City, Viet Nam
170 An Duong Vuong, Binh Dinh, Viet Nam
e-mail: dovancan@qnu.edu.vn
Abstract-The Computerized Numerical Control (CNC) of
the machine tool is very important role in the CNC
machining. They are developed constantly, from modular
discrete devices into integrated on a card one; from
complicated medium-speed circuits into high-speed
integrated ones. A product suitable for applied research for
the CNC is SoC FPGA. The SoC FPGA device is a single-die
system on a chip, that consists of two distinct parts - a Hard
Processor System (HPS) portion and an FPGA portion. The
NCK's software functions will perform on components HPS
and NCK's hardware functions are implemented on FPGA.
In this paper, the authors propose NCK hardware and
perform interpolation functions of NCK on hardware SoC
FPGA, to confirm the advantages of SoC FPGA. This result
of the study showed that the CNC-on-Chip will replace the
present CNC.
Keywords-HPS-FPGA; SoC FPGAs; CNC-on-Chip; NCK;
Hardware CNC
I. [NTRODUCTION
Currently, the world has many studies on the CNC.
Specifically, since 2009 the CNC study guide has been
integrated on a chip based on FPGA technology [1].
However, at the moment it does not have any FPGA can
support the full functionality of CNC. So, they need to use
additional cores externally [2], [3]. Through faster
processing advantages of FPGAs, many researchers have
exploited this to construct the interpolation algorithm ofthe
CNC [4], [5]. The study is presented in two projects [6]
and [7] shows that the ability to integrate components NCK,
on SoC FPGA were studied form of simulation, and can
not integrate the entire component (ex components PLC) of
the CNC on a single chip [2]. Many studies, build
interpolation algorithm has been irnplemented on FPGA.
The easy interpolation built in hardware [8], and the
complex interpolation or curve is done by software
algorithms on the processor core [5].
From these characteristics, the authors proposed
structure hardware ofthe CNC for Machine Tools base on
"System on Chip" (Fig. 1 Proposed Structure Hardware of
the CNC for Machine Tools base on System on Chip.
978-1-4673-9859-6/16/$31.00 20161EEE
Nguyen Quang Dich and Nguyen Phung Quang
Hanoi University of Science and Technology
01 Dai Co Viet, Ha Noi, Viet Nam
e-mail: dich.nguyenquang@hust.edu.vn
]JOPC
Software Hardware
Interface
I
Ethernet HPS llterpolator. Analog
Position Or Digital
]JO controller
Digital
(FPGA)
EPROM
JTAG
RAM
On Chip
I Input
Ene-oder
I
RTOS - 32bit
I
Figure I. Proposed structure hardware ofthe CNC
A. The structure and Function ofthe CNC
From a functional point of view, the CNC system
consists of the Man Machine Interface (MMI) unit, the
Numerical Control Kernel (NCK) unit, and the
Programmable Logic Control (PLC) unit. Fig. [ 1/0
ethernet unit offers the interface between NCK and the user,
executes the machine operation command, displays
machine status, and offers functions for editing the part
program and communication. The NCK unit, being the
core of the CNC system, interprets the part pro gram and
executes interpolation, position control, and error
compensation based on the interpreted part program.
Finally, this controls the servo system and causes the
worl<.piece to be machined. The PLC sequentially controls
tool change, spindie speed, workpiece change, and in/out
signal processing and plays the role of controlling
themachine's behavior with the exception of servo control
[9].
B. The Proposed Structure Hardware of the CNC Base
onSoC FPGA
Structure MM[ components: The controller is
connected to a computer running the Windows operating
system [9], in order to optimize the exploitation of
computer power. An EMAC File Transfer Protocol used to
transmit and receive data at 10/1 00/1 OOOMbps over
Ethernet connections with the IEEE 802.3 compliant
printed specification. [t was built on HPS. [ngredients used
MM[ HSSB cable (High Speed Serial Bus) bandwidth,
high-speed data bus to 32 bits. MMI functions proposed
building software pro gram on ARM cores
Structure NCK components:
243
 An interpreter plays the role of reading apart program, C. Building Configuration the Hardware CNC Using
interpreting the ASCII blocks in the part pro gram, and Qsys Tools
interna I memory storing interpreted print data for the The authors have proposed configuration of the CNC
interpolator. In general, it should have a large enough hardware block diagram as shown Fig. 2. Included
memory storing programs and data. Proposal support for components: HPS (ARM Dual cortex A9, DDRJ, EMACO
interpreter function is an implementation algorithm RGMII); Nios 11; Memory data 32bitst (Memory on chip,
software program. DDRam controller); System ID peripheral; Jtag to Avalon
If position control is executed by using the data Master Bridgee (Master HPss, master fpga); Jtag Uart, PIO,
generated from the interpolator, large mechanical vibration interpolator, position_controller and PLC logic.
and shock occur whenever part movement starts and stops.
In order to prevent mechanical vibration and shock, the
filtering for accelerationldeceleration control is executed
before interpolating data is sent to the position controller.
This component, the authors proposes the implementation
at FPGA portion.
The logic controller is used to execute sequential
control in a machine and an industry. In the past, logic
control was executed by using hardware that consisted of
relays, counters, timers, and circuits. Therefore, it was Figure 2. The architecture ofthe CNC-on-Chip based SoC FPGA.
considered as a hardware based logic controller. This
We can use Qsys IP components to create Qsys systems.
component, the authors proposes the implementation
Qsys interfaces include components appropriate for
hardware and software at FPGA portion.
streaming, high-speed data, reading and writing registers
SoC FPGA has many advantages such as: Allows users
and memory, controlling off-chip devices, and transporting
to design custom or IP configurations available from the
data between components. With an AXI bridge, we can
manufacturer, reducing power consumption and provides
influence the placement of resource intensive components,
faster when implementation in hardware algorithms ...
such as the width and burst adapters. We can also use an
Altera SoC FPGA (5CSEMA5F31) selected for the CNC-
AXI bridge to export AXI interfaces from Qsys systems 64
on-Chip.
bit. Results after the authors implemented as follows Fig. 3.

~: System C ontents &3 l Address Map &3 1 Interconnect Requirements &3 1 Device Family &3 1 Srnematic - Beta &3 1

.. .
<:? Use C... Name Description Export Clock Base End IRQ Tags
X
~
."'.
~
! 1I 1iI1~1
II hps_O Arria V/Cydone V Ha rd Processor System
,
multiple
,
'" mul t i p I s multi p l e

.
~ II sysilCqsys System ID Peripheral clk_O Ox OOOO_ 000 8 OxoOOO_ OOO f
:E ~ II milster_hps JTAG to Avalon M aster Bridge clk_O
~ II milster_fpgil JTAG to Avalon Master Bridge clk_O
.... ~ II nios2 Nios II Processor clk_O
'" Ox OOOO 1000 Ox OOOO 1 7ff

Z
~
~
~
II
II
II
onchip_memory
jtil9_uilrt
On-Chip Memory (RAM or ROM)
JTAG UART
position_controller...:O position_controller
clk_O
clk_O
'"
Ox OO0 2_0000
Ox OOOO 0000
Ox OOO <_ffff
Ox OOOO 0007 ~
'7 ~ II interpolator_O nterpolator
i
~ II Out_put PIO (parallel 110) clk_O Ox OOOO_ OOOO Ox OOOO OO Of
~ II pio_O PIO (parallel 110) clk_O
'" Ox OOOO 0000 Ox OOOO OOO f

Figure 3. Configuring hardware cnc-on-chip using the tool Qsys

11. BUILDING INTERPOLATION ALGORITHMS BASE ON length per IPO cycle time (Ti po) L1L, calculate axial
incremental value per IPO cycle time L1x, L1y, L1z.
HARDWARE OF THE Soc FPGA FOR CNC-ON-CHIP
The fundamental idea of this algorithm is a segment of
A. Linear Interpolation Algorithm Based on SoC FPGA the path by the interpolation time, Tipo. At each sampling
time the interpolated point can be defined as in (2) wherein
As we know, interpolated on hardware costs a lot of
the displacement of each axis is given by (3).
resources on the chip, and software interpolation on the
slow speed due to the sequential structure of the program
[9]. (1)
Fig. 4 is analyzed reference word algorithm linear
interpolation. In particular, the starting point A (xl, yl, zl)
and end point B (x2, y2, z2), calculate entire path length L
(1), the interpolation of point Pi to Pi+l, calculate path
(2)

244
 As shown in Eg. (3), the line segment ~L depends on accuracy [10]. From the study of interpolation was
velocity V. Velocity V is defmed by Eg. (4) When the implemented on FPGA gives pretty good results working
command velocity V o defined in apart program is speed due to parallel structure of FPGA [11]. These studies
compensated for by feed override. are mostly based on the theory or empirical FPGA circuit
board with extemal auxiliary complements the CNC.
L= V.Tipo Limitations of FPGA resources are few and limited
(3) libraries when building complex functions. SoC FPGA
have advantages in addition to integrated support HPS
complex handling, minimizing the waste of resources.
(4) That's why authors choose SoC FPGA to build a linear
where,
interpolation algorithm on hardware. Simulation
F: The feed override;
parameters set as follows: Use the counter a = 3 cycles
Va: The velocity is defined in the "offset".
(BLU = 3 pulses); starting point (xl, yl, zl) = (I, I, I) to
Synchronous pulse generator in the axis due to
end point (x2, y2, z2) = (10,6,8); the number ofpulses to
hardware configuration on SoC FPGA. Most CNC
move the axes X = 9, Y = 5, Z = 7. This paper format
machines are currently using software algorithms on the
values xl, yl, zl, x2, y2, z2, X, Y, Z format 32-bit and dX,
core processor or host PC is suitable for machining
dY, dZ format pulse.
complex contour curves, but limited in terms of speed and

clk JUL uu JUL

13
ruu- JULruu- UULruu- UULruu- UULruu- l-JUL uu JUL
11 12 13 10 h 2 13 10 11 12 3 10 h 12 13 0 h 12 13 10 1 12 13 10 h 2 I] 10 h 12 3 10 h 12 13 0 h 12

dX~ l I I Ih h I
11 12 13 4 IS 16 17 18 9 110

dY L - Il I I
11 12 13 4 IS 16

dZ L - Il I I Ih
11 12 13 4 Is 16 17 18
111 1111111 1 11111111 11 1111 111 111111111 11111 1111 111111111 111 111111 111111111 11 111111 1 1 11111111 111 111111 1 11111111 11 1111111 1111111 11 1 11111111 I I
Ops 10 ps 10 ps 30 ps 40 ps sops 60 ps 70 ps so ps 90 ps 100 ps 1l0 ps 120 ps 130 ps 140 ps 150 ps

Figure 4. The simulation results while building algorithm 3-axis simultaneously linear interpolation on SoC FPGA

The simulation results in Fig. 4 shows pulse dX, dY, dZ There:

axes, generated is independent, not dependent on each axis, Lmax : Maximum length ofthe axis;
that is due to the structural design of SoC the parallel N x , Ny, N z : Number of pulses corresponding steps
hardware. Therefore, the algorithm builds on SoC FPGA for each axis
allows faster than soft-core algorithms. k: Coefficient ofPulse BLU;
B. Construction Method Synchronization Time between X, Y,Z: length of the projection on the
Axes Based on High Clock Speed ofSoC FPGA corresponding asix x, y, z.
SoC FPGA give the parallel structures Pulse axes
simultaneously improve the speed of machine tools,
especially with multiple-axis machine. However, when the
points have the coordinates of the axes are not
simultaneously, then the pulse generator axes pulse number
at (Y axis is 5 pulses Fig. 4) will finish before the pulse
multiple axes (X-axis is 9 pulses). It leads to orbital motion
wi 11 be been error.
To remedy this, the authors used time synchronization
methods on the axis. This method finds values min and
max number pulses of the axes, which allocate the pulse of
min are scattered a along axis of time with axes max by Figure 5. The algorithm synchronization time between axes.
calculating the length Lmax (Xmax , Ymax. Zmax). Then count After combining the sync pulse method with linear
the number of steps reguired to the pulse generator axis N x, interpolation as above to synchronize time with Modelsim
Ny, N z as folIows: N x = k.Lmax/X; Ny = k.Lmax/Y; N z = simulation axes starting point (1,1,1); end point (10,6,8). In
k.LmaxlZ; Fig. 6 is the simulation results after using synchronized
time axes. The purpose of this method is to make the
duration of the pulses almost the same between axles

245
 --- - -
(number of pulses has not changed), to bring trajectory motion between the axis close to true trajectory.

jtst_countempjcJk JUUUlJ JUUUlJ JUUUU JUUlJ1f JUUlJ1f

I l
WU1IU WU1IU
n
wmI JUUUlJ JlMIU JUUUU
l
WUW
jtstcounterupjdXI JL
jtstcountempjdYI n h I Jl -
/tst counterupjdZI I h n J
/tst counterup{X \l 12 3 14 15 16 J7 B 19 110
/tst counterup/y 11 12 13 4 15 16
/tst counterup/Z[I 12 13 14 5 J6 J7 jB

Figure 6. Simulation results after using time synchronization between axes

As the results in Fig. 6 shows the number of pulses on the iterations are required and N, the number of iteration steps,
axis is not changed (9 X-axis, 5 Y-axis and 7 Z-axis). can be calculated using (6).
However, at this time of pulse generator axis with less
number of pulses (Y -axis) is stretched out nearly the time of N =Ixo -xfl+lyo -Yfl (6)
the pulse multiple axes (X-axis). That means that the There,
movement of the axis with alm ost the same time, avoid (X o, Y a) is the start point
running long axis, the axis have stopped making the (X f, Yf) is the end point
trajectory becomes "ziczac" error with true trajectory. However, an improved algorithm is proposed because the
C. Stairs Approximation Algorithm for Circle above mentioned algorithmhas some problems. In the
interpolation Based on SoC FPGA improved Stairs Approximation Algorithm, (5) is changed to
Fig. 7 shows how the Stairs Approximation Algorithm (7) by adding one more index.
for circle interpolator behaves in the case that the
commanded circular movement is in the clockwise direction
(7)
in the first quadrant with respect to the center ofthe circle. In
this algorithm, the variable Dk is calculated by (5).
In (7), i and j respectively denote the number of steps
along the X-axis and the Y-axis. When one step is added
along the X-axis, (8) is changed to (9)

D;+l,J = (X; + 1)2 + Y] - R 2

(8)
(Xf, Y i> = Di,j +2X; + 1 = Du +M;

Similarly, when the Y axis is reduced by 1 step, while the

pulse on the axis defined by (9) as folIows:

;:2
Figure 7. The behavior ofthe stairs approximation algorithm.

The direction of a step is determined based on Dk, the Mi+I: M

commanded circular direction, and the quadrant where { (9)
~X;+I -M; 2
movement is done.

(5) After performing building hardware with appropriate

+ Dk < 0: This case means that the position (Xk,Yk) is
located on the inside of a circle and, in this case, the step
moves in the positive direction ofX-axis.
+ Dk > 0: This case means that the position (Xk, Yk) is
located on the outside of a circle and, in this case, the step is
moved in the negative direction ofthe Y -axis.
+ Dk =0: One of the above rules can be arbitrarily
selected and applied.
After one step is completed by applying the above rules,
the position (Xk+)' Yk+ 1) is updated and the procedure
repeated until the tool reaches the position commanded,
(Xf,Y f). This algorithm requires a small amount of
computation and less memory space. However, numerous
parameters and running translation to create the
configuration file.sof to SoC FPGA (5CSEMA5F31).
Perform simulation with parameters as above parameter
interpolation results on SoC FPGA hardware. The initial
parameters x I = 0, yl = 10, x2 = 10, y2 = 0, use the counter
to the creation interpolation cycle.
Results Fig. 8 shows the stairs approximation algorithms
have trajectory close to trajectory motion carried the circle,
the maximum deviation 1 BLU trajectory, repeat score 21
points. The pulse X axis ofthe positions 1, 3,4, 5, 6, 8, 9, 11,
13, 16 and pulse generator axis Y at position 2, 7, 10, 12, 14,
15, 17, 18, 19, 20. This algorithm does not have a pulse
generator simultaneously in all axes makes deviation from
the trajectory largest real when multiple axis interpolation.

246
Also, increase the number of interpolation points,
interpolated time prolonged.

clk u ~~~~S ~~S S S I S S S S ~ W- S ~ ~

I1 2 3 4 5 I> 7 8 9 10 11 11 13 14 15 16 17 18 19 20 21
dX
lLlLlLI lLI I I I
dYL - h h I I L I lLIL L h
Xu 2 3 4 5 5 7 B 9 10 0
Y ~ I() 9 8 7 6 5 .4 3 2 1 0

111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 1111111111111111111
ops 60 ps so ps 100 ps 110 ps l4D ps 160 ps 180 ps 200 ps

Figure 8. Results perfonn Stairs Approximation Algorithm for on SoC FPGA.

D. The Circle Interpolation Base on SoC FPGA The third case is different from the Stairs Approximation
Considering the Smallest Deviations Trajectory Algorithm. The Di,j for each case is evaluated and the case
with the smallest absolute value is selected for movement.
One of the weaknesses of the stairs approximation Fig. 9 shows the flowchart of the Direct Search Algorithm
algorithm above is very much iteration. Because the motion for c10ckwise circular movement in the first quadrant.
concurrently of the axis and is not considered in the
algorithm, which it is very meaningful in SoC FPGA. Th e t raje ctory cons ide ri ng the sma ll est devi ations t rajector

Furthermore, the position error conditions is not considered :1 * (X.YI I

as dependent as interpolation.
SoC FPGA's strengths is the ability to configure . . ........:........ : ........ . . .
hardware, building the parallel structures on chip. Therefore 7 .............. ; ....... ; ........ !........ ~ ....... ~ ...... * ...... ;........!...... .
a solution is set for the building algorithms to search through
......
6 ....... : ....... : ....... : ........:........ : ....... : ....... : ................:...... .

all possible directions and find a path towards the smallest

deviations compared with true trajectory (Fig. 9)
i-------i--------:--------~ -------t- ----- -~ -------i--------*:-------
: : : : : : : : :
3 - - - -- - - ~ - - -- - - -
, , , , , , , , ,
2 , ~ i:;r, i -:-
1 ....... : ....... : ....... : ........:........ ; ....... : ....... c....... : ........:...... .

Externa l clock O~~-~-~--L-~5-~-~-~-~--~

10
Axis-x

0 1= IO + L'.XI Figure 10. The trajectory considering the smallest deviations trajectory.
0 2= 10 +L'.YI
OJ = 10 +L'.X + L'. YI The maximum deviation ofthis algorithm is 1/2 BLU and
accuracy of this algorithm is better than the stairs
_ O--<...Ol >
r -_ _ _N 0 2>_Y_e_s _ _-----,
approximation algorithm on, the number of iterations N is
less than 30% compared with the stack Stairs Approximately
Ye_s_.+~
0 1> DJ >-___ Aigorithm (Fig. 10).
From algorithm flowchart. Fig. 9 considering the
o , N~ optimum trajectory bias, the authors builds on SoC FPGA
hardware and simulation results Fig. 1l. At positions 4, 6, 7,
the smallest deviations trajectory 8, 9, 11 is the pulse generator between axes concurrently,
thanks to the characteristics tested according to the direction
of the errors smallest trajectory. Completion time
Figure 9. Direct search (the smallest deviations trajectory) flowchart.
interpolation after 15 cycles. The time is shortened, the
When clockwise circular movement in the first quadrant difference is reduced as the advantages of the method
is commanded, three cases should be considered: considered of errors smallest trajectory, thanks to a
Increasing 1BLU for the X-direction, concurrently pulse generator, and built algorithm on
Decreasing lBLUfor the Y-direction, and hardware of SoC FPGA.
Increasing 1 BLU for the X-direction and
simultaneously decreasing 1 BLU for the Y-direction.

247
 dk ~~
50
l--------J l--------J l--------J~ ~ ~ ~ ~ l--------J ~ ~ ~ ~
xl 0
yl 10
x2 10
y2 0
1 2 3
5 6 7 B 9 10 11 12 13
" 15

~ Cii= =Pe =R
dX ~~ ~~~ n
dy ~~~~~
0 1 2 3
5 6 7 B 9 10
y 10 9 B 7 6 5 3 2 1 0

Figure 11. Simulation results using circle algorithm considering the smallest deviations trajectory improvements on SoC FPGA.

111. CONCLUSION REFERENCES

The selection CSoC for the CNC-on-Chip is a suitable
solution, which builds configuration "hardware" to make
the foundation for the system "software" later. This
paper was contributed the following issues:
The CNC_on_chip proposed replace all control
system of the machine tool by a single chip, it is
performed base on SoC FPGA's strengths.
Compared to before, many authors propose
implementing an FPGA application supplement for
the CNC to improve the speed, or replace some
interpolation function or position control function,
PWM function ...
Building success ofthe CNC interpolation algorithm
based SoC FPGA is strides consistent with today's
technology base on advantages SoC FPGA.
The build linear and circle interpolation bring
advantages in speed and trajectory deviation and
speed feed thanl(s to parallel hardware
configurations SoC FPGA. The advantages SoC
FPGA showed conformity with the construction of
CNC functions including interpolation function. The
building on the SoC FPGA hardware algorithms
showed more speed, more accurate trajectories than
software algorithms, there by forming the future
CNC.
[1] Y. Hu, D. Yu, S. Du, X. Zhang, Y. Tao, and Z. Wang, "Design and
Implementation of Reconfigurable CNC System Based on Fieldbus"
Int. Conf. Inf. Autom., pp. 794-799,2008.
[2] Y. Chen, H. Wee, K. Sun, T. Wang, and Y. Zou, "System-on-Chip
Design for CNC System," no. ISIE, pp. 690-693,2009.
[3] H. Gilberto, T. Iv, and J. Carlos, "FPGA based on-Line Tool
Breakage Detection System for CNC Milling Machines," Elsevier,
vo!. 14, pp. 439-454, 2004.
[4] M. X. and S. L. Jian-guang SHEN, Tao TAO, Xue-song MEI, "An
improved Line-Drawing Aigorithm for Arbitrary Fractional
Frequency Divider Multiplier Based on FPGA," J. Eng. Sei. Technol.
Rev., vol. 6, no. I, pp. 25-32, 2013.
[5] J. J. De Santiago-Perez, O. Rios, R. 1. Romero-Troncoso, and L.
Morales-Velazquez, "FPGA-Based Hardware CNC lnterpolator of
Bezier, Splines, B-splines and NURBS Curves for Industrial
Applications," Comput. lnd. Eng., vo!. 66, no. 4, pp. 925-932, Dec.
2013.
[6] J. Fei, R. Deng, Z. Zhang, and M. Zhou, "Research on Embedded
CNC Device Based on ARM and FPGA," Procedia Eng., vol. 16, pp.
818-824, Jan. 2011.
[7] S. Liu, H. Lin, Y. Tao, Y. Zheng, and Y. Jin, "Design and Research
of SoC Communication in CNC System Based on Heterogeneous
Processor," 2012 IEEE 12 1h lnt. Conf. Comput. lnf. Techno!., pp. 994-
998, Oct. 2012.
[8] M. Gao, 1. Lou, 1. Ye, and Z. Wu, "FPGA-Based Implementation of
circular interpolation," vol. 6, no. 7, pp. 585-593,2014.
[9] H. C. S. H. Suh Seong, Kyoon Kang Dae, Theory and Design ofCNC
Systems, 2008.
[10] B. Bahr, X. Xiao, and K. Krishnan, "A real-time scheme of cubic
parametrie curve interpolations for CNC systems," vo!. 45, pp. 309-
317,2001.
[11] S. Chebiyyam, R. Maddasani, S. R. Gaddala, and S. Y. Pasha,
"Design of High Speed Serial Communication Protocol for FPGA
based SoC Applications," vol. 3, no. 2, pp. 1-4,2013 .

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