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HIP0061
60V, 3.5A, 3-Transistor Common Source
December 1997 ESD Protected Power MOSFET Array
Features Description
Three 3.5A Power MOS N-Channel Transistors The HIP0061 is a power MOSFET array that consists of
three matched N-Channel enhancement mode MOS transis-
Output Voltage to 60V
tors connected in a common source configuration. The
rDS(ON) . . . . . 0.225 Max Per Transistor at VGS = 10V advanced Intersil PASIC2 process technology used in this
product utilizes efficient geometries that provides outstand-
Pulsed Current . . . . . . . . . . . . . . . .10A Each Transistor ing device performance and ruggedness.
Avalanche Energy . . . . . . . . . . 100mJ Each Transistor The HIP0061 is designed to integrate three power devices in
Grounded Tab Eliminates Heat Sink Isolation one chip thus providing board layout area and heat sink sav-
ings for applications such as Motor Controls, Lamps,
Solenoids and Resistive Loads.
Applications
Automotive
Appliance Symbol
Industrial Control
DRAIN1 DRAIN2 DRAIN3
Robotics 2 5 7
TEMP. PKG.
PART NUMBER RANGE (oC) PACKAGE NO.
4
HIP0061AS1 -40 to 125 7 Ld Staggered Z7.05C SOURCE, TAB
Vertical SIP
Pinouts
HIP0061AS1 HIP0061AS2
(SIP - VERTICAL) (SIP - GULLWING)
TOP VIEW TOP VIEW
7 DRAIN3 7 DRAIN3
6 GATE3 6 GATE3
5 DRAIN2 5 DRAIN2
4 SOURCE 4 SOURCE
3 GATE2 3 GATE2
2 DRAIN1 2 DRAIN1
1 GATE 1 1 GATE 1
TAB
TAB
TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4 TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. FN3982.3
Copyright Intersil Americas Inc. 2002. All Rights Reserved
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HIP0061
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
Drain to Source On-State Voltage Range . . . . . . . . . . . . 5V to 10V
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Pulse width limited by maximum junction temperature.
2. Drain current limited by package construction.
3. VDD = 25V, Start TJ = 25oC, L = 15mH, RGS = 50, IPEAK = 3.5A. See Figures 1, 2, 12, and 13.
4. JA is measured with the component mounted on an evaluation PC board in free air.
TC = 25o C - 70 - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 1.8 2.3 2.7 V
Forward Gate Current, Drain Short IGSSF VDS = 0V, VGS = 20V - - 100 nA
Circuited to Source
Reverse Gate Current, Drain Short IGSSR VDS = 0V, VGS = -15V - - -100 nA
Circuited to Source
Drain to Source On Resistance (Note 5) rDS(ON) VGS = 10V, ID = 3.5A TC = 25oC - 0.215 0.265
Total Gate Charge (Note 6) Qg(TOT) VDS = 50V, VGS = 10V, ID = 2A - 8.0 9.5 nC
See Figures 16, 17
Gate-Source Charge (Note 6) Qgs - 0.7 1.0 nC
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HIP0061
10
10s 10
ID , DRAIN CURRENT (A)
10s
ID , DRAIN CURRENT (A)
100s
100s
1ms
10ms
100ms 100s
1
OPERATION IN THIS DC 1
1ms
AREA MAY BE OPERATION IN THIS
10ms
LIMITED BY rDS(ON) AREA MAY BE
100ms
LIMITED BY rDS(ON)
DC
TC = 25oC
TC = 105oC
TJ = MAX RATED
0.1 TJ = MAX RATED
1 10 100 0.1
1 10 100
VDS , DRAIN VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 1A. 25oC SAFE-OPERATING AREA CURVE FIGURE 1B. 105oC SAFE-OPERATING AREA CURVE
3
HIP0061
50
10
1
5
OPERATION IN THIS 100s
AREA MAY BE
1ms
LIMITED BY rDS(ON) 10ms
100ms
TC = 125oC DC
TJ = MAX RATED
0.1 1
1 10 100 0.001 0.01 0.1 1.0
VDS , DRAIN TO SOURCE VOLTAGE (V) tAV , TIME IN AVALANCHE (ms)
10.0 20
VGS = 10V
VDS = 15V 25oC
VGS = 8V -40oC
VGS = 6V VGS = 5V
125oC
ID, DRAIN CURRENT (A)
7.5 15
ID, DRAIN CURRENT (A)
5.0 10
VGS = 4V
2.5 5
2.5 1.2
rDS(ON), NORMALIZED ON RESISTANCE
2.0
1.1
NORMALIZED BVDSS
1.5
1.0
1.0
0.9
0.5
0 0.8
-75 -25 25 75 125 175
-75 -25 25 75 125 175
TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)
FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERA- FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE
TURE
4
HIP0061
2.0 12
VGS = VDS, ID = 250A
VDS = 50V
VDS = 20V
8
1.0
4
0.5
ID = 2.0A, TC = 25oC
0 0
-75 -25 25 75 125 175 0 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) Q, GATE CHARGE (nC)
FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION TEMPERA- FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
TURE
750 5
VGS = 0V, f = 1MHz, TC = 25oC
600 4
C, CAPACITANCE (pF)
450 3
VGS = 10V
VGS = 5V
CISS
300 2
COSS
CRSS
150 1
0 0
0 5 10 15 20 25 25 50 75 100 125 150
VDS, DRAIN TO SOURCE VOLTAGE (V) TC, CASE TEMPERATURE (oC)
FIGURE 9. TYPICAL CAPACITANCE vs VOLTAGE FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
5
HIP0061
10
ZJC, NORMALIZED THERMAL IMPEDANCE
TC = 25oC
1 D = 1.0
0.5
0.2
0.1
0.1 0.05
0.02
0.01 NOTES:
1. DUTY FACTOR, D = t1/t2
SINGLE PULSE 2. PEAK TJ = PDM x (ZJC) +TC
tP tAV
10 V
VDS
VGS 0
L IAS
RG +
DUT
VDD
VGS -
ID 0
BVDSS
tP
0V ID VDS
0.01
0
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
6
HIP0061
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VDS
VGS
0V
90%
RGS
50% 50%
VGS
PULSE WIDTH
10%
FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
+VDS
CURRENT Qg
REGULATOR SAME TYPE
10V
AS DUT
+ 0.2F 25k
10V
BATTERY
-
0.1F
Qgs Qgd
VG
DUT
IGS
0
CHARGE
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. BASIC GATE CHARGE WAVEFORM
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PSPICE Model Listing
Device Model Netlist for the HIP0061 Power MOSFET Array
NOTE: For further discussion of the PSPICE PowerFET macromodel consult Spicing-Up SPICE II Software for Power MOSFET Modeling,
Intersil Application Note AN8610.
8
HIP0061
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HIP0061
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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