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Faculty of
UTM
UNIVERSITI TEKNOLOGI MAUYSIA
E le c tric a l
E n g in e e rin g
SECTIONS 01 / 02 / 03 / 04 / 05 / 06 / 07 / 08
TIME 2 HOURS
100 Q
Rb Rc
Figure A2
6. In a P-type semiconductor, electrons are the carriers and holes are the
carriers.
9. Name one (1) basic op-amp circuit for a linear application and one (1) basic op-amp
circuit for a non-linear application.
Linear application:_______________________________________
Non-linear application:___________________________________
10. The N-channel E-MOSFET operates in the cut-off region when Vos i s ____ than
V g s (th ), and the saturation region when V gs i s ______ than V g s (th ) and V ds is
than V g s - V g s (th ).
11. Reversed biased ideal diode is equivalent to a / a n ___ circuit, whereas forward
biased ideal diode is equivalent to a/an ________ circuit.
14. A rectifier usually has a capacitor connected in parallel to the load resistor to
the rectified output voltage.
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Qi
(a) A simple voltage reference circuit that is used to drive two series loads Ri and R 2
in a control circuit is shown in Figure Q l(a). The reverse characteristic o f the
diode used in the circuit is depicted in Figure Q l(b), and R 2 = 50 Q, Assume that
R] = 3 R 2 and let the maximum power dissipated in the diode be denoted as Pzm
The supply voltage, Vg vary between 4.5 and 5.6 V, For regulation to remain
effective, find;
(i) Maximum value o f the resistor, R,
(ii) Maximum power dissipation, P zm
(10 marks)
Load
Vs -
(a) (b)
Figure Q l
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SKEU 2012
(b) Referring to full-wave bridge rectifier circuit in Figure Q l(c), all diodes are silicon
with V f = 0 .7 V.
(i) Draw and label the output (vo) waveform.
(ii) Calculate the Vo(ave).
(7 marks)
240V,
50Hz
Figure Q l(c)
(c) Figure Q l(d) is a DC power supply using a zener voltage regulator circuit that
provides a regulated dc output o f 7.5 V to a load resistance (R l) varying fi-om
120 Q to 450 2 with an average unregulated input voltage (Vj(ave)) o f 30V.
(i) Draw the internal circuit o f the voltage regulator using suitable zener diode
and source limiting resistor, Rs.
(ii) Determine the proper value o f Rs and the maximum current (Izmax) through
zener diode.
(8 marks)
D, D2
D3 D4
------ ------- M
Rl =
120Q - 4 5 0 0
Figure Ql(d)
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Q.2
(a) Refer to Figure Q2(a). The biasing point Q is at Ic;Q=5mA. Given that p = 350,
V.T = 26mV, and = oo;
(i) Draw the AC small signal equivalent circuit o f the amplifier.
(ii) Calculate g, and r^ o f the transistor.
(iii) Calculate the input impedance, Z;..
(iv) Calculate the output impedance, Zk>
(J7 marks)
V,o
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(b)
(i) For the fixed-bias circuit given in Figure Q2(b), determine the values for
Vcc, the resistor Ri, and the resistor R 2 , if we require Rj = 8 OR2 ,
Figure Q2(b)
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Q3
(a) The amplifier circuit in Figure Q3(a) has the following parameters: Id ss = 10 mA,
Vos(oii) = |Vp| = -3 .5 V
(i) Using the transfer characteristic curve in Figure Q3(b), graphically
determine the transistor operating points (Id q and V g sq )-
+
Va
Figure Q3(a)
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Figure Q3(b)
NOTE: Use this Figure Q3(b) for Question 3(a) part (i) and s'uhmit this graph along with
your answer book.
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Q.4
(a) Refer to Figure Q4(a).
(i) Show that Vo = - R f (V,/R, + V 2/R 2 ).
(ii) Given that Ri = 25 kQ, R 2 = 40 kQ and Rf = 100 kQ, sketch Vo when
V, = 0.5 sin (ot (V) and V 2 = 3V.
(8 marks)
Rf
-o V
lOkQ 30kQ
Figure Q4(b)
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(c) In Figure Q4(c), the operational amplifier has infinite open-loop gain, infinite input
impedance and negligible output impedance. What is the suitable range value for
Rx to obtain the total amplifier gain, |Av| in dB of 26 dB to 40 dB?
(8 marks)
-oV out
Figure Q4( g)
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Q5
(a) For the Schmitt Trigger circuit in Figure Q5(a);
(i) Determine the upper and lower threshold voltage, V tn rp and V ltp .
(7 marks)
VlN (V)
+9V
Figure Q5(a)
(ii) Analyze the comparator circuit by filling-up the status (ON or OFF) for each
o f the LED (LED l, LED2, and LED3) in Table Q5 for the three different
levels o f input voltage, Vm-
(10 marks)
Table Q5
1.5 V
2.5V ON
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+ 12V +12V
Figure Q5(b)
(c) Figure Q5(c) is a 555 timer circuit to generate a free running clock at frequency,
fo ~ Hz and duty cycle, D = 60%. Determine the suitable values for resistances
Ra and R b to achieve the desired clock specification? Use Capacitor Cj = 22 }jF.
(8 marks)
+9 V
: 8
RESET Vcc
OUT
DISCH ""V o
555
TIMER J lT U l
Rb
_6
THRESH
2 TRIG CONT
GND ^ C2
1 0 .0 1 nF
Figure Q5(c)
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h = Ic + h
Vavg = Vdc = -^ /c - / + Ic B O
t = R C ln l t = RCln3
Vd c 2yf3fRiC
r= _f}VT
Vdc 4Vs/fitC
rn = Icq
y VpT Vp
r = -^
9m AVgs
'D(on)
(ycs(on)-VcsiTH)^) Id K(ycs ^GS(rW))
- 2 lpss
I^GS(OFF,l g, - 2 K ( V - Vc,S(TH))