LOW-COST OFF-GRID SOLAR PANEL INVERTER

WITH MAXIMUM POWER-POINT TRACKING

By

Andrew OConnell
Jaroslaw Klosek

ECE 445, SENIOR DESIGN PROJECT

SPRING 2008
TA: Grant Pitel
27 April 2008
Project No. 1
 ABSTRACT

In recent years, the interest in solar energy has risen due to surging oil prices and environmental
concern. In many remote or underdeveloped areas, direct access to an electric grid is impossible and a
photovoltaic inverter system would make life much simpler and more convenient. With this in mind, this
project aims to design, build, and test a solar panel inverter. This inverter system could be used as back-
up power during outages, battery charging, or for typical household applications.

The key features of the system are a true 60Hz, 120Vrms sinusoidal voltage output, a wide input range,
and maximum power-point tracking (MPPT), and a power output of up to 500W. The overall goal is to
design this system while minimizing component costs. Although systems with similar features already
exist, many are prohibitively expensive for those people who stand to benefit the most. In addition,
inverters in the lower price range typically lack the features mentioned above.

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 TABLE OF CONTENTS

1. INTRODUCTION ....................................................................................................................1
1.1 Purpose ...............................................................................................................................1
1.2 Specifications......................................................................................................................1
1.3 Power Stages and Descriptions...........................................................................................1
1.3.1 Boost Converter ...............................................................................................................2
1.3.2 Buck Converter................................................................................................................2
1.3.3 Half-Bridge Inverter ........................................................................................................2
1.3.4 High-Frequency Transformer ..........................................................................................2
1.3.5 Bridge-Rectifier ...............................................................................................................2
1.3.6 H-Bridge Inverter.............................................................................................................2
1.3.7 Control and Logic Supply................................................................................................2

2. DESIGN PROCEDURE...........................................................................................................3
2.1 Design Procedure................................................................................................................3
2.1.1 MPPT Stage Design.........................................................................................................3
2.1.2 Boost Converter Design...................................................................................................4
2.1.3 Buck Converter Design....................................................................................................4
2.1.4 Battery Charge Controller Design ...................................................................................5
2.1.5 Half-Bridge Inverter Design ............................................................................................5
2.1.6 High-Frequency Transformer Design..............................................................................5
2.1.7 H-Bridge Inverter Design ................................................................................................5
2.2 Control and Logic Supply Module .....................................................................................5
2.2.1 Grounding Issues .............................................................................................................6
2.2.2 Gate Drive Voltage Levels ..............................................................................................6
2.2.3 Boost and Buck Control...................................................................................................6
2.2.4 Half-Bridge and H-Bridge Control..................................................................................6
2.3 Preliminary Baseline Simulations.......................................................................................7

3. DESIGN DETAILS ..................................................................................................................8

3.1 Boost Converter Diagram and Components .......................................................................8
3.2 Buck Converter Diagram and Components........................................................................9
3.3 Half-Bridge Inverter Diagram and Components ..............................................................10
3.4 Bridge-Rectifier and H-Bridge Diagram and Components ..............................................11
3.5 Control Board Diagram and Components ........................................................................11
3.6 PCB Design ......................................................................................................................12
3.7 Transformer Design ..........................................................................................................12

4. DESIGN VERIFICATION.....................................................................................................14
4.1 Boost Converter Testing: Results and Analysis ...............................................................14
4.2 Buck Converter Testing: Results and Analysis ................................................................15
4.3 Half-Bridge Inverter Testing: Results and Analysis.........................................................15
4.5 Bridge-Rectifier and H-Bridge Inverter Testing: Results and Analysis ...........................16

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5. COST ......................................................................................................................................17
5.1 Parts ..................................................................................................................................17
5.2 Labor.................................................................................................................................17

6. CONCLUSIONS ....................................................................................................................18

APPENDIX A Control Code ...............................................................................................19

APPENDIX B MATLAB Script, Equation Derivations and Simulation Results ...............22
APPENDIX C Schematics, Layouts, and Pictures ..............................................................28
APPENDIX D Data Results and Related Figures ...............................................................32
APPENDIX E Cost Summary .............................................................................................39
APPENDIX F MPPT Figures .............................................................................................42
REFERENCES .......................................................................................................................43

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 1. INTRODUCTION

The initial selection of this project was motivated by the increased interest in renewable energy
systems, which has been fueled by rising oil prices and environmental concern. It is our belief that the
marketplace needs a wider variety of products that will utilize such systems for household applications.
We also believe that the process of designing a solar panel interface will be greatly beneficial to a power
engineer in the rapidly expanding field of renewable energy applications.

1.1 Purpose

The main objective of this project is to design, build, and test a solar panel inverter. This inverter should
be low cost, as compared to other commercially available inverter system, flexible utilizing a wide
input voltage range for various photovoltaic panels as well as providing a charge control option, and
make optimal use out of any solar panels this is achieved by using a maximum power-point tracking
(MPPT) algorithm.

1.2 Specifications

The entire system will have the following technical specifications:

Wide input voltage range: 24-48V
Maximum output power of 500W
Maximum power-point tracking (MPPT) for most photovoltaic panels
True 120Vrms, 60Hz sine wave output

1.3 Power Stages

The entire inverter system consists of 6 stages of power converters linked in series as follows: boost
converter, buck converter, half-bridge inverter, high-frequency transformer, bridge rectifier, and H-
bridge inverter. Each of these stages plays an important role in the overall functionality of the inverter
system. In addition, a control and logic supply module is necessary to operate each power stage. Figure
1.1 shows a block diagram of the overall topology of the inverter and the proceeding sections briefly
describe the purpose and function of each stage; a more detailed design procedure is outlined in the
following design section.

Figure 1.1: Block diagram of the inverter system

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1.3.1 Boost Converter

This power converter serves as the input stage from the solar panel and also performs MPPT. It takes an
input voltage from 24-48V and steps up the output to a value determined by the MPPT operation. The
control utilizes voltage sensing in order to alter the perceived impedance of the circuit such that
maximum power is extracted from the photovoltaic panel.

1.3.2 Buck Converter

The buck converter takes the MPPT-determined output of the boost converter and outputs a highly
regulated 26Vdc. Feedback is employed to provide a steady output under varying input conditions. The
26Vdc is passed to the next stage and can be used for charging a 24V battery.

1.3.3 Half-Bridge Inverter

This power stage takes a 26Vdc bus from the buck converter/battery output and converts it into an AC
square wave of amplitude 13V and frequency 31.25kHz.

1.3.4 High-Frequency Transformer

The transformer is used to step up the square wave AC signal from the half-bridge inverter. It takes the
square wave as its input and outputs another square wave of the same frequency but with an amplitude
of approximately 175V.

1.3.5 Bridge Rectifier

The bridge rectifier simply takes the 175V square wave signal generated by the transformer and
performs a full-wave rectification into a 175Vdc bus.

1.3.6 H-Bridge Inverter

This final module takes a 175Vdc bus produced by the bridge rectifier and utilizes PWM control in
order to output a 60Hz sine wave.

1.3.7 Control and Logic Supply

This module provides the control signals as well as logic power to all the ICs found in the power stages.
The control is accomplished using programmable integrated circuits (PICs) and the C language. The
logic supply is implemented using voltage regulators as well as isolated power supply modules.

2
 2. DESIGN PROCEDURE

2.1 Design Procedure

The initial idea for the project consisted of an MPPT input stage followed by a single boost converter,
which would bring a nominally 12 V solar panel up to the necessary 170 V DC bus for the h-bridge
inverter. However, equation 3.1 shows that the duty ratio would have to be around 93%, which is not
acceptable. Using two boost converters in tandem was briefly considered but eventually discarded as
excessively difficult to control and inelegant.

The next iteration of design focused on the use of a transformer. Two options were immediately
obvious: a very large 60Hz transformer or a small high-frequency transformer could be used. In the case
of the former, the h-bridge bus voltage would be relatively low and the 60Hz PWM output would be
amplified through an appropriately sized transformer. With the latter, the low voltage signal would be
converted to a high-frequency square wave via a half-bridge inverter before being passed through the
transformer and rectified to feed the h-bridges DC bus. Because of the difficulty in procuring a 60Hz
transformer with the correct winding ratios, the high-speed DC link was selected. It was believed that
the high frequency transformer could be fabricated by hand.

After performing the initial analysis on the system, it was determined that a 12 V nominal input voltage
was not feasible since, at 500 W, this corresponds to a current of almost 42 A. Not only would this
converter have heavy losses but it would be very difficult to test with available laboratory equipment.
Thus, it was decided that the input voltage would be 24 V-48 V, 36 V nominally.

2.1.1 MPPT Stage Design

The concept of maximum power point tracking is best illustrated by way of the solar cell V-I
characteristic, as shown in Figure F.1 in Appendix F. The figure shows that photovoltaic cells are far
from ideal voltage sources and depend heavily on solar insolation. Because of this, there is an associated
current and voltage operating point in which maximum power is transferred from a cell under a given
illumination. This point is demonstrated for each curve in Figure F.1 by the rising blue line.

There are numerous control schemes that have been devised to maintain operation at the maximum
power transfer point, but all seek to change the perceived converter impedance to influence solar cell
voltage and current. The first MPPT method considered for use in the inverter was perturb and observe
(P&O). The control algorithm for P&O is shown in Figure F.2 in Appendix F. Briefly, the controller
samples both the solar panel input current and voltage and calculates the instantaneous power transfer. It
then either increases or decreases the MPPT voltage reference and recalculates the power. If the new
power value is higher than the old, the voltage reference is once again varied in the same direction. If
the old power value is higher, the voltage reference is varied in the opposite direction. Only when two
consecutive power readings are the same does the reference remain unchanged between iterations [2].
The net result is that the converter climbs the power characteristic to reach the maximum point.

Unfortunately, as mentioned, P&O requires both current and voltage sensing. Due to the already large
scale of the project, it was eventually decided that a simpler method was needed. This led to the
transition to constant voltage (CV) MPPT. The method requires only voltage sensing and is similar in
implementation to the proportional control already designed for the buck converter.

CV MPPT is based on the fact that, while the ratio of [the maximum power point voltage to the open
circuit voltage] depends on the solar cella commonly used value is 76% for maximum power point
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tracking []. That is, the voltage reference for the converter is set such that the solar cell operates at 76%
of its open circuit voltage. While an approximate method, this finds validation in Figure 2.1, where the
maximum power point line is maintained at about 0.4V (80%) throughout various illumination
conditions.

The original idea for the maximum power point tracking stage was a buck-boost converter that
connected directly to a charge controller and the half-bridge inverter. It was quickly realized that the
converter could not perform both MPPT and regulate the output voltage simultaneously. It was decided
that the MPPT stage would be a boost converter and it would be followed by a buck converter to
regulate the result.

2.1.2 Boost Converter Design

The boost converter topology was standard, but the control method was CV MPPT. Because the source
of the FET in a boost converter is grounded, a standard low-side gate driver was used (MIC4424). This
simplified things considerably, and lies in contrast to the dual high-low gate drivers used elsewhere.

Some issues did arise in the testing of the boost because voltage ratings were not heeded. The output of
the boost was designed to go up to about 70V, meaning that the FET and diode needed to be able to
block that voltage. In an effort to find inexpensive FETs and diodes with low on-state resistances and
forward voltages, respectively, the blocking voltage was not given enough thought. The result was
switches rated for 55V that ended up failing during testing. After this, all of the switches purchased
were rated considerably higher than what they theoretically needed to block. As it turns out, this was not
quite high enough to accommodate inductive voltage spikes, but that issue will be addressed later.

2.1.3 Buck Converter Design

As with the boost, the buck converter power stage design was fairly standard. The issue of underrating
the switches was even more of a problem in this, however. Because of this, a lossy turn-off snubber had
to be added to dampen the inductive voltage spikes across the FET.

In addition to FET damage, a grounding issue arose. Usually, the FET in a buck converter is moved to
the low side to allow for simple gate drive operation. As will be discussed in more detail later, however,
this configuration creates referencing issues on the control board. Should the FET be placed on the low
side, the half-bridge ground would have to be different than that of the buck and boost. This would
necessitate the use of an additional set of isolated power supplies to interface with the microcontroller
and gate driver of the half-bridge. This scenario was avoided by using a high-side gate driver (IR2117).

The high-side gate driver did, however, bring problems of its own. During testing, the FET would
inexplicably stop responding to the control signal as the input power and voltage increased. Upon
debugging the circuit, it was found that the boot-strapped capacitor (0.1F) was discharging far too
rapidly during operation and falling into an ambiguous state of around 7V. This situation was resolved
by switching to a polarized 47F tantalum capacitor.

Further complicating the above situation was the fact that, at high voltages, the gate driver would fail.
Several gate drivers later, it was realized that the diode used in with the gate driver was severely
underrated. A 1N5819 was being used but only had a voltage rating of 40V, but was being exposed to
voltages of up to 70V. The failure mode for this diode was to short-circuit, causing large amounts of
current to flow into both the gate driver and the control circuit. Once this was realized, the diodes were
quickly replaced with STPR820s, which can block up to 200V.

4
2.1.4 Battery Charge Controller Design

While a part of the proposal and design review, the battery charge controller scheme was eventually
dismissed altogether. The UC2906, a dedicated sealed lead-acid battery charger, seemed like an ideal
choice, with several charge-rate modes based on the batteries state of charge and a price of less that $4.
The underlying operation, however, turned out to be less than ideal. The control signal provided by the
chip drives an external BJT that is connected between the input source and the battery--essentially a
large variable resistor. Of course, the BJT would incur huge amounts of thermal dissipation at the power
levels of interest and would need an elaborate cooling system just to function, never mind the impact on
efficiency.

2.1.5 Half-Bridge Inverter Design

The half-bridge inverter did not undergo any major revisions, but had issues similar to those of the buck
converter. The high side gate driver capacitance had to be increased but, due to the low voltage of the
input voltage (24V), the 1N5819 diodes did not have any problems. Like the buck, the half-bridge
needed to implement turn-off snubbers to limit voltage spikes on the FETs, which were only rated to 55
V.

2.1.6 High-Frequency Transformer Design

Contrary to what was hoped, the high-frequency transformer could not be fabricated by hand. The high
primary current from the half-bridge required about 10 mm2 of copper for each turn to stay within a
reasonable 500A/cm2 current density. That realistically meant 4-5 parallel strands of 14 AWG wire. In
addition, the turns ratio required to take a 26 Vp-p square wave to 170 V was about 14, with each turn
requiring 2 parallel strands of 16 AWG wire.

This design was attempted on a powdered iron toroid of relative permeability 75, while maintaining
amp-turn and volt-second limits. 5 primary and 70 secondary turns were used. Testing this transformer
showed that the primary side was not coupled sufficiently to the core and was simply shorting the input
supply. Realistically, it makes much more sense to have a transformer with such tight requirements
manufactured.

2.1.7 H-Bridge Inverter Design

The H-bridge inverter design, like that of the half-bridge and buck converters, was complicated by high-
side gate capacitance and diode ratings. After resolving these issues with 47uF tantalum capacitors and
larger gate driver diodes, the issue of inductive voltage spikes came to the forefront. As the dc bus
voltage neared a certain threshold, both the FETs and diodes were damaged. Unfortunately, this was
discovered late in the design process and there was not sufficient time to replace the devices with more
appropriately rated switches.

2.2 The Control and Logic Supply Module

The control was implemented with three PIC18F2520 microcontrollers. These 28-pin devices were
selected because of their low cost and simple functionality. Each contained an analog-to-digital (A/D)
converter, an internal 8 MHz oscillator and two compare, capture, PWM (CCP) modules. The A/D
converters were necessary for implementing feedback in the buck and boost converters, while the CCP
modules made PWM adjustment very straightforward. The internal oscillator was useful in that it
circumvented the need for a costly external crystal oscillator. Note that all inputs and outputs were
protected against over-voltage damage with 5V zener diodes.
5
Due to its convenience, an MPLAB ICD 2 programmer was used in conjunction with the MCC18
compiler. The control code for each of the power stages is shown in Appendix A.

The logic supply was implemented using two sets of +5 V and +15 V supplies. Three comparators were
also used to increase the voltage of the control signals to proper levels in order for gate drive ICs to
function properly.

2.2.1 Grounding Issues

The half-bridge and buck converters are controlled by the same PIC, while the boost and h-bridge
converters each have a dedicated microcontroller. Because the buck, boost and half-bridge converters
share a common input ground, the control signals, and thus the PICs, could be referenced to the power
stage ground. For this reason, a simple 5 V linear regulator was used to power the boost PIC and a 15V
regulator to power the gate drivers. Because of the need for isolation after the transformer stage,
however, the h-bridge control needed an isolated supply. Thus, isolated 5 and 15 V supply modules were
used exclusively for the h-bridge.

2.2.2 Gate Driver Voltage Levels

As mentioned above, the control board provided both control signals and power to the various gate
drivers. The issue with this is that the PIC output is a 0-5 V signal, while the gate driver power is 15 V.
The boost and half-bridge gate drivers recognized the 5 V signal as high, while the buck and h-bridge
drivers did not. To solve this problem, three comparators were used to scale the h-bridge and buck
control signals to 0-15 V before being sent to their respective power stages.

2.2.3 Boost and Buck Control

As mentioned previously, the boost stage control was designed such that the input voltage was regulated
to 76% of its open-circuit value. Similarly, the buck stage control was designed to regulate the output
voltage at 26 V. In terms of the microcontroller, each converter required an A/D converter to process the
scaled voltage feedback signal and a CCP module to adjust the duty cycle. In order to reach the desired
31.25 kHz switching frequency, the PWM timer had to scale the original 8 MHz clock by 256. Briefly,
the code for both converters functions as follows:
The CCP and A/D modules and I/O pins are initialized.
The A/D module converts the scaled feedback signal and subtracts it from an internal reference.
The error signal is conditioned to determine an offset in the duty cycle from 50%.
The CCP module is updated with the new duty cycle.

2.2.4 Half-Bridge and H-Bridge Inverter Control

The control for the half-bridge inverter was designed to be simple: a single CCP module was used to
output a constant 50% duty cycle. That is, the converter was run open loop, without any feedback or the
need for an A/D converter. The reason for this was that the half-bridge needed to maintain an AC
output; varying the duty cycle would add a DC component that would quickly saturate the transformer.

Similarly, the h-bridge inverter was tested without feedback. Unlike the half-bridge, however, the reason
behind this choice was a reduction in complexity. Indeed, if the voltage from the buck converter is
regulated well enough, the h-bridge bus voltage should not vary significantly and, thus, the PWM sine

6
wave should stay within its specified tolerance. The h-bridge control utilized two CCP modules in order
to provide independent signals for each leg of the bridge. The PWM duty cycle values were pre-
determined by sampling half of a 60 Hz sine wave and the results were stored in an array. The maximum
value in the array corresponded to a duty cycle of 80%. The actual operation of the control code is
slightly more complicated than that of the boost and buck:
The CCP modules and I/O pins are initialized.
For half of a 60 Hz cycle, CCP module 1 (CCP1) is loaded sequentially with the array data while
CCP2 is held at 0%.
For the second half of the 60 Hz cycle, CCP1 is held at 0% and CCP2 is loaded with the array
data.
CCP1 and CCP2 each controlled one leg of the h-bridge and produced identical switching waveforms.
Note that, due to non-idealities in PIC processor performance and very little program memory, the
operating frequency had to be reduced to 20 kHz. While reducing switching losses, this also resulted in a
less precise sine wave.

2.3 Preliminary Baseline Simulation

The starting point for the design is a set of numerical simulations using a MATLAB script. Each power
stage was analyzed using basic circuit equations, as well as derived equations in order to provide basic
theoretical calculations for each power stage. In addition to the MATLAB script, the derivation of
pertinent equations and the resulting graphs are shown in Appendix B. They will be used as the basis for
comparison between theoretical and observed results in Section 4.

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 3. DESIGN DETAILS

Since the design procedure was explained in the previous section, this section will focus on the discrete
components chosen for each particular power stage. Finalized circuit schematics will be provided to
illustrate the topology of each power converter. A summary of all parts used in the project is shown in
Section 5: Cost.

3.1 Boost Converter Diagram and Components

Figure C.1, located in Appendix C, shows the circuit schematic for the boost converter with all
component names and values.

The key components of the circuit are the power switches, the inductor, capacitor, and gate drive IC.
The selection of each of these components depends highly on the input, output, and power
characteristics of the boost converter.

The input and output relation of a boost converter is given by the following equation:

Vin
Vout = (3.1)
1-D1

The duty ratio D1 represents the fraction of time that switch #1 is on during the switching period. Simple
analysis of this circuit reveals that switch #1, the power MOSFET, must be able to block the output
voltage. The same is true for switch #2, the power diode. Assuming, an overall target efficiency of 70%,
the input power should be approximately 715W. The current is a maximum at this power level when the
input voltage is the lowest, 24V; this corresponds to a current of approximately 30A. This current must
be carried by both the power MOSFET and diode under the maximum load. The power MOSFET
chosen for this purpose was IRF310Z, an n-channel device which can block 100V, carry a continuous
current of 59A, and has an Rds-on of 18m. The power diode is IR43CTQ100 which can block 100V and
carry 40A and has a forward drop of 0.67V.

Since, the PIC control chips can only source 25mA of current, this is not sufficient to achieve fast
switching times. Therefore, the MIC4424 low-side gate drive chip was used to achieve fast switching.

The inductor value is dependent on the switching frequency. The switching frequency was chose such
that: (1) it would not fall within the audible range, (2) be easy to implement with proposed control
methods, and (3) reduce the commutation loss in the switches. The switching frequency was chosen to
be 31.25kHz based on these requirements. The critical inductance in a boost converter is determined by
the following equation:
D (1-D1 ) 2 RT D1 (1-D1 ) 2 R
Lcrit = 1 = (3.2)
2 2f switch

For proper inductor design, the output power was set to a 25W minimum, which corresponds to a load
resistance of approximately 100. The duty ratio was limited to about 2/3. Substituting these values and
fswitch = 31.25kHz yields a critical inductance of 116H. To provide head room and increase the
operation range, a pre-constructed 300H was utilized. In order to carry the proposed 30A of current
under maximum load, under medium cooling conditions (5A/mm2), approximately 6.0 mm2 of copper
was necessary; 5 parallel windings of 16AWG wire gave the copper a cross-sectional area of 6.545 mm2,
a sufficient value.

8
The capacitor value determines the voltage ripple seen on the output waveform. Typical electrolytic
capacitors have high equivalent series resistance (ESR), which degrades the output by introducing a
significant voltage ripple. To combat this effect there are usually 2 options: (1) use low ESR capacitors,
which tend to be expensive or (2) use multiple capacitors in parallel to increase capacitance and decrease
the ESR. To achieve the low cost criterion, the latter option was chosen and the capacitor values were
determined by trial-and-error testing. These values were two 2200F electrolytic capacitors.

3.2 Buck Converter Diagram and Components

Figure C.2, located in Appendix C, shows the circuit schematic for the buck converter with all
component names and values.

Once again, the key components of this circuit are the power switches, the inductor, capacitor, and gate
drive IC. As with the boost converter, the selection of each of these components depends upon the input,
output, and power characteristics of the buck converter.

The buck converter input and output relation is given by the following equation:

Vout = D1Vin (3.3)

The duty ratio, D1, represents the fraction of time switch #1 is on. Simple analysis of the circuit reveals
that switch #1, the power MOSFET, must block the input voltage. The same is true for switch #2, the
power diode. Since the input of the buck converter is the same as the output of the boost converter,
identical power switching devices were used, IRF310Z and IR43CTQ100.

In order to maintain proper ground referencing, the high-side FET topology was used. This meant using
a high-side gate drive, IR2117, utilizing a 0.22F bootstrap capacitor and a STPR820 Schottky rectifier
to push the VGS switching signal 15V above the input voltage. The maximum high side offset voltage is
200V.

Using identical criterion as in the boost converter, the switching frequency was chosen to be 31.25kHz.
Selecting the proper inductor value is done by utilizing the following formula:

RT R
Lcrit = (1-D1 ) = (1-D1 ) (3.4)
2 2fswitch

The maximum input voltage was determined to be 72V, corresponding to a duty ratio of approximately
0.361. Placing the minimum output power at 25W yields a critical inductance of 236H. Once again, a
pre-constructed 300H inductor was available for use. The estimated output power at this stage was
calculated to be 577W through simulations available in Appendix B. With an output voltage of 26Vdc,
the current through the inductor windings would be approximately 22A at maximum load. With medium
cooling (5A/mm2), the cross-sectional copper requirement is 4.4mm2; 4 parallel windings of 16AWG
wire produce 5.24mm2 of copper, a sufficient value.

Capacitor selection was governed by the same design criteria as the boost stage. Multiple parallel
capacitors were implemented in order to reduce ESR and decrease the voltage ripple on the output.

This circuit experiences inductive voltage spike across the power MOSFET during turn-off. Therefore,
turn-off snubbers were implemented to protect the device. The snubber network is the combination of

9
C7, R7, and D7. Snubber design is based upon the selection of the optimal capacitor value determined
by the following formula.
3Ion t f
Copt = (3.5)
12 iVoff

Substituting some of the maximum values for Ion, tf, and Voff yields the optimal capacitance of 0.0146F,
the closes capacitor value is 0.01F. The selection of the resistor is such that the RC combination can
discharge during the time the switch is off. This balance is give by the following formula:

DT D
R< = (3.6)
2C 2 C f switch

Substituting the appropriate values for D, C, and fswitch gives R < 577. This resistor has to be able to
dissipate the power provided by the discharging capacitor, give by:

1
Pr = CVoff 2 f switch (3.7)
2

Substituting the appropriate values gives Pr = 1.563W. Based on availability of parts, a 63 3W resistor
was selected to provide extra head room for discharge time as well as power dissipation. A 1N5813
Schottky diode was used to control the current path between the switch and the snubber.

3.3 Half-Bridge Inverter Diagram and Components

Figure C.3, located in Appendix C, shows the circuit schematic for the half-bridge inverter with all
component names and values.

The key components of this circuit are the power MOSFET switches, dual high and low-side gate drive
IC, non-polarized film capacitors, as well as the snubber circuit across each switch.

This circuit simply takes a 26Vdc bus, and converts it into a 31.25kHz square wave with a 26Vp-p, 13V
amplitude. This is done by alternating the switches which charge and discharge capacitors C8 and C9.
Considering this, the switches must be able to block the full 26V. The current carrying requirement at
maximum input power of 577W, is approximately 44A. The devices chosen is the STP80NF55, an n-
channel device which can block a voltage of 55V, carry a continuous current of 80A, and has an Rds-on of
6.5m.

The switching signal has a duty ratio of 50% and comes from the control module into the IRS2003 IC, a
dual high and low-side gate drive capable of sourcing 290mA on the high side output and 600mA on the
low side output. The low and high-side inputs are inverted to provide alternating switching. This chip
also includes an internal dead time of 650ns to prevent shoot-through current due to supply shorting.
The high side switching is accomplished by providing a bootstrap capacitor of 1F capacitor and a
1N5819 Schottky diode. The high side offset voltage has a maximum rating of 200V.

The capacitors are also worth a special mention, since they provide the charge/discharge cycles that
produce the square wave signal. With alternating charging/discharging the capacitors cannot be
polarized and must have a high enough capacitance to maintain a constant voltage across the switching
interval. Due to availability, 100F film capacitors were chosen for this purpose.

10
Due to the high current through the power MOSFET devices, temperature was a concern. To help
alleviate this effect, a substantial heat sink with a large surface area was added to both devices. Another
feature to help reduce the power dissipated during turn-off is the use of a turn off snubber across each
power MOSFET. This is simply the network of R7, D7, C7 for the low-side switch and R6, D6, C6 for
the high side-switch, which moves the power dissipated during turn-off away from the switches.
Equation 3.5 can be applied, by substituting the appropriate values the optimal capacitance is found to
be 0.125uF, the closest capacitor value is 0.1F. The resistor can be selected according to Equation 3.6
and it is found to be R < 80. The power dissipated by this resistor is given by Equation 3.7:
Pr = 1.056W. Once again, based on availability of parts, a 63 3W resistor was selected to provide extra
head room for discharge time as well as power dissipation. A 1N5813 Schottky diode was also used to
control the current path between the switch and the snubber.

3.4 Bridge-Rectifier and H-Bridge Inverter Diagram and Components

Figure C.4, located in Appendix C, shows the circuit schematic for the bridge-rectifier and h-bridge
inverter with all component names and values.

The key components of this circuit are GBU4M, power MOSFET switches, dual high and low-side gate
drive ICs, as well as snubber circuitry. The bridge-rectifier is a single package component, GBU4M,
with an average forward voltage drop of 1V, with a forward current of 0-4A. It is able to block 1000V
and able to hand an RMS input voltage of 700V.

Inspection of the H-bridge circuit reveals that the switches must block the 170Vdc bus. For a 500W
load, the current through the switches is approximately 4.17A. The switch that was chosen was the
IRF640 n-channel device capable of blocking 200V, carrying 8A, and has an Rds-on of 0.18.

The switching signal is provided by the control module and it is varying duty ratio signal between 0-
80% at a switching frequency of 20kHz. The varying duty ratio allows the output voltage to track a
60Hz sinusoid. When each leg of the H-bridge is activated by the appropriate control signal, it either
introduces a positive or negative voltage on the load. The gate drive IC chosen for this purpose is
IR2010 dual high-low side gate drive. It features a peak current source of 3.0A, matching 15ns delays
between high and low-side outputs, as well as a high side offset voltage of 200V. The high side
switching is accomplished by using a 47F tantalum bootstrap capacitor as well as a STPR820 Schottky
diode.

The design of the snubbers, to lower temperature by moving the turn of losses away from the switch, is a
similar procedure to that of the half-bridge and buck converter. Using Equations 3.5, 3.6, and 3.7 yields
values of Copt = 560pF, R < 160, and Pr = 0.5W, respectively. The closest capacitor and resistor values
are 1000pF and a 63, 3W should provide extra protection for the switches. 1N5819 Schottky diodes
were used to guide the current between the snubber and the switches.

3.5 Control Board Diagrams and Components

The complete schematic of the control board with all component names and values is shown in Figures
C.5-C.7, located in Appendix C.

The control board, as mentioned previously, was powered by two sets of supplies due to the need for
isolation after the transformer stage. The buck, boost and half-bridge microcontrollers were powered by
a L7805ABV 5V linear regulator. In addition, these stages were provided with logic power by a
L7815CP 15V linear regulator. Both regulators have a maximum input voltage of 35V and a maximum
11
current of over 1A, while providing thermal overload and short circuit protection. The logic power
source was originally intended to be provided by the battery array (24V nominally), so there was no
issue with exceeding the 35V limits. While quite inefficient, these regulators were very inexpensive
(refer to Section 5 for cost analysis) and only needed to provide small amounts of power.

The h-bridge inverter PIC and gate drivers, on the other hand, had to utilize isolated dc-dc converters for
power. The PIC was supplied with 5V by an NME2405 and the gate driver with 15V by an NME2415.
Both supplies are rated to handle up to 1W while maintaining a load regulation of 10%, a line
regulation of 1.2% of the input voltage, and an efficiency of around 70-75%. In addition, they can
tolerate voltage fluctuations of up to 10% from the rated 24V source, or 2.4V. The major downside
of these converters was cost; each was over $10.

Since the h-bridge and buck converter gate drivers were not TTL logic-level compatible, these gate
control signals could not be taken directly from the PICs. For this, each of the three signals was taken to
a standard LM311 comparator, as can be seen in Figure C.6, located in APPENDIX C. The control
signals were taken directly into the positive input terminals and 15V was supplied to the positive rails.
The negative terminals were set somewhat arbitrarily to 2.5V through 100k and 20k resistive
dividers. The operation is as follows: when the control signal is greater then 2.5V (i.e. the positive input
terminal voltage is greater than that of the negative), the output is connected to the 15V rail through a
pull-up resistor; conversely, when the control signal is below 2.5V, the output is connected to ground.
Thus, the comparators effectively bring the control to a level that can be recognized by the gate drivers.

The control board external connections were provided via MTA connectors. The connections to the buck
and boost converters, which utilized feedback control, required both a 2- and 3-pin MTA connector. The
2-pin connector was provided for the incoming feedback signal and the 3-pin for the outgoing control
signal as well as logic power and ground. The reason for this separation was to reduce interference
between control and feedback signals. The open circuit converters (half- and h-bridge inverters) only
needed control signals and were thus only provided with a single 3-pin MTA connector.

To ensure that the PICs were adequately protected against over-voltage damage during operation, all
inputs and outputs were tied to ground through 1N4733 5.1V zener diodes.

3.6 PCB Design

Initial functional testing of the power converters was done on power breadboards. However, it was
quickly evident that reliability problems would persist due to uncertain factors associated with the power
breadboards. The decision was made to fabricate PCBs for each power converter to solve some issues
associated with breadboard testing. Figure C.8-C.1, located in Appendix C, contain layout diagrams as
well pictures of each power converter.

3.7 Transformer Design

As discussed previously, transformer fabrication was found to be particularly difficult. The transformer
fabricated consisted of the core and primary and secondary windings discussed in 2.1.6. These values
were determined to keep the current density under 10A/mm2 on each winding and to satisfy the amp-
turn and volt-second limits of equations 3.8-3.9. In these equations, N is the number of turns, i is the
peak transformer current, Bsat is the saturation flux density of the powdered iron core, is the core
permeability, Vdc is the 13V dc signal applied across the transformer, t is the time over which the DC
voltage is applied, and l and Acore are the flux path length and area, respectively, of the core.

12
 l
Ni < Bsat (3.8)

Vdc t < Bsat N Acore (3.9)

Even though carefully designed, the transformer, when fabricated, did not have enough coupling
between the primary side winding and the core. It was decided that, with such tight design constraints,
the transformer should be manufactured for adequate performance.

13
 4. DESIGN VERIFICATION: TESTING AND ANALYSIS

The following section will summarize the results and data gathered during testing of each power stage
individually. For power converters, the figures of merit are the input/output characteristics and
efficiency. Also included are oscilloscope plots showing relevant signal in each power converter. The
efficiency is simply given by Equation 4.1, below:
P Pout
Efficiency = = out = (4.1)
Pin Pout +Ploss

4.1 Boost Converter Testing: Results and Analysis

Testing of the boost converter was a straight-forward process. Various input voltages and loads were
applied and measurements were taken for input voltage, current, and power as well as output voltage,
current, power. The load and line regulation are not really significant in this case as the output is
somewhat arbitrary due to the nature of the MPPT control.

The solar panel was modeled by using a Magna Power supply capable of a DC input voltage of 0-400V
and providing a current up to 27A. The load was a HP 6060B DC electronic load capable of handling 3-
60V/0-60A with a peak maximum power of 300W.

The input voltage was varied for typical solar panel output voltages of 24V, 36V, and 48V. The output
voltage was taken at 2 points: the minimal output voltage of 26V and maximum voltage of 60V, due to
limitation of the electronic load. Another limitation of the testing was the output power, which was
limited to 300W by a single electronic load. Although it is possible to daisy-chain these devices to test
for larger loads, this proved to provide unreliable measurements and caused imbalance due to device
mismatches and wire runs. The results are tabulated in Table D.1 in Appendix D. Also included are the
results displayed in graphical form in Figures D.1-D4.

Figures D.1 and D.3 show the input/output voltage relationships as well as the associated duty ratio for
each of the operating conditions; the duty ratio represents the control signal via a feedback loop that was
provided by the control board.

Figures D.2 and D.4 display power output characteristics. For the operating range, the boost converter
exhibited and efficiency between 95-85%, very close to the theoretical simulation results displayed in
Figure B.1, which show theoretical efficiency values of 98-89%. The extra ~5% percent of loss can be
accounted for by taking into consideration core losses in the inductor as well as the effect of ESR on the
output capacitors. These effects are difficult to model during initial simulation, due to the uncertainty of
the exact specifications of the components being used (inductor and capacitor).

Also located in Appendix D are oscilloscope plots showing the relevant boost converter signals during
various operating points. These are shown in Figures D.5-D.8, where Ch.1 is the output waveform, Ch.2
is the switching signal, Ch.3 is the Vds across the switch, and Ch.4 is the inductor current.

4.2 Buck Converter Testing: Results and Analysis

Buck converter testing was carried out in a similar manner to the testing of the boost converter. The
same power supply was utilized as well as the HP electronic load; the same output power limitation of
300W was present.

14
The input voltage was varied between 30V and 72V, while varying the load as well. The output voltage
was held at 26V and associated input/output voltage levels and power measurements were taken.
Oscilloscope traces of the important signals were also taken.

Table D.2, located in Appendix D, displays the raw data for the buck converter. Figure D.9 displays the
output characteristics as well as the input in graphical manner. This plot shows the variation of the
output voltage on the input voltage as well as the associated duty ratio necessary to achieve proper
operation.

Figure D.10 displays the power characteristics of the buck converter. The plot shows the variation of
efficiency with respect to Vin and Pin; the achieved efficiency results fall in the range between 99-81%.
The theoretical simulation shown in Figure B.2, located in appendix B, gives results ranging between
98.5-93%. The resulting error between theoretical and observed efficiency values can be attributed to
core losses in the inductor as well the presence of high ESR on the output capacitance.

The output capacitors had trouble maintaining a steady-voltage on the output, which is shown in Table
D.2 under the ripple column. This can be linked to unknown values of ESR on the output capacitors, and
higher quality capacitors would be essential to alleviate this problem.

Also located in Appendix D are Figures D.11-D.14, which are oscilloscope plots of the relevant buck
converter signals during various operating conditions. The channels are exactly the same as the boost
converter plots. An important aspect of these plots, is the high ripple visible on the output waveform, as
well as the inductive spikes present on the Vds of the switch. For the several tested loads, these Vds
spikes are nearly 100V high, therefore, this was the decision was made not to test the circuit under larger
loads since increasing it any further would destroy the switches. Normally, these switches should be
replaced with ones that have higher ratings, but due to time concerns this was not accomplished.

4.3 Half-Bridge Testing: Results and Analysis

In order to test the half-bridge circuit, a constant 26Vdc input needed to be supplied over the range of
minimum and maximum load. Once again the source was the Magna Power supply. The output
waveform was monitored with an oscilloscope to ensure the proper 26Vp-p square wave signal was
present.

Reliable testing, however, proved to be difficult to achieve due to reference and power issues. Firstly,
the electronic load used in the previous tests can only be referenced to ground and since the half-bridge
output is +13V and -13V; the use of the electronic load essentially cut out half of the output waveform.
This meant that the only possible way to test the half-bridge was to use discrete power resistors, or an
isolated power supply. However, the isolated power supplies available could not provide enough current
(the Kenwood PD56-10AD can only supply a maximum current of 10A) to enable testing up to and
including a 500W load.

While using discrete power resistors is certainly feasible, in order to apply a 500W load, a power resistor
of 0.338 is necessary with that particular power rating. With wire runs of ~2m, larger loads provided
enough inductance and wire resistance to significantly reduce the performance of this power converter.
Therefore, only limited testing was performed due to the nature of the specialized testing equipment
necessary.

Figure D.15, located in Appendix D, displays a graph of the resulting output and power characteristics
of the half-bridge inverter. One axis shows the output voltage amplitude as a function of input power,
which remains constant throughout the load range. However, once a power of approximately 130W was
15
reached, the efficiency was significantly affected. At this power and voltage level, the current going into
the load would be approximately 10A. Unfortunately, the available wires were not able to handle this
amount of current and huge wire losses started to become evident when the temperature of the wires
increase by a significant margin. Due to safety reasons, the half-bridge inverter could only be tested up
to this operation point.

Appendix D also contains the oscilloscope plots that show the relevant half-bridge signals; this is shown
in Figures D.16-D.19 under a variety of operating conditions. The 4 oscilloscope signals are: Ch.1 is the
output waveform, Ch.2 is the switching signal, Ch.3 is the Vds on the high side switch, and Ch.4 is the
output current.

4.4 Bridge-Rectifier and H-Bridge Testing: Results and Analysis

Since the bridge-rectifier is a single package discrete component, its data sheet provides thorough
performance characteristics under a variety of conditions. Therefore, it will no be included in the
proceeding discussion.

The testing of the H-bridge proved to be a difficult task. Although all components were chosen
carefully, frequent failures occurred. The maximum DC bus voltage that was obtained was 120V. Even
at lower voltage levels, the h-bridge could only push a meager 12W of power into the load. After this
point, power switches and gate drives started malfunctioning and failing; with only a limited supply of
parts, only qualitative results are available in the form of oscilloscope plots, shown in Figures D.20-D23.

The important aspects of Figure D.20 are the output PWM voltage, displayed on Ch.3, the (inverted)
output current waveform on Ch.4 and a reference 60Hz sine wave on Ch.1. Note that frequency of the
PWM signals is exactly 60Hz and the switching operation is clearly visible. It should be noted that no
output filtering was used in this figure.

Figure D.21 shows the output voltage waveform on Ch.3 and a 60Hz reference on Ch.1 under a 12W
load and light inductive output filtering. The signals of Figure D.22 are the two h-bridge leg gate
signals, shown on Ch.1 and Ch.2, and the output voltage waveform on Ch.4. Note that shoot-through
was avoided by inserting dead time between the PWM gate signals of the two legs.

Finally, Figure D.23 shows the output voltage (Ch.3), drain-to-source voltage of a low-side FET (Ch.4)
and the input current (Ch.2) under the maximum bus voltage obtainable during testing, 120V. The
drain-to-source voltage is of special importance because it shows the inductive spikes that became
prominent at higher voltages. Beyond this level, the FETs were damaged and the inverter operation
broke down.

16
 5. COST ANALYSIS

One of the main points of this project was to minimize the parts cost, when compared to commercially
available system. For example, a simple web-search for solar inverter products reveals that a 600W
inverter costs about $460; however, it does not have MPPT and outputs a modified sine wave. The goal
was to bring the price of the parts to about $250. This, along with research and development costs and
economies of scale, could produce a product that could be available for approximately $300-350, a price
reduction of about 20-25% compared to its counterparts.

5.1 Parts

Tables E1-E5located in Appendix E summarize the parts used in each power stage and control/supply
module, along with their cost. The total parts cost from those table comes out to be $222.48, which
includes the transformer estimation.

5.2 Labor

Table E6 in Appendix E, shows the time spent by both engineers working on the project each month.
The total number of hours worked on design, fabrication, and testing totals 489 hours. With an
engineering dream salary of $50/hour, the total labor cost for research and development comes out to be
$24,450.

17
 6. CONCLUSIONS

Although the project was never fully integrated, the disparate elements showed promise. The boost
converter met the specifications up to 300W, while the buck converter did so up to about 175W. The
half-bridge was unable to be tested using conventional methods and available equipment above 125W,
but showed excellent performance up to that point. The h-bridge, although unable to provide high power
levels, displayed the proper PWM output at bus voltages up to 120V.

Among the stages, there was consistently an issue with inductive voltage spikes. This accounted for
many of the performance limitations seen. Another issue involved the printed circuit boards. The PCBs
used were not rated for the operating currents required and haphazard external routing schemes had to be
devised. Even if the devices were capable of handling the aforementioned inductive spikes, it is unlikely
that the PCBs could handle power levels as high as 500W.

Cost analysis reveals that the low-cost objective was met by using the components described in section
3. The inverter was found to be less expensive than comparable commercially available units, even
without the benefits of mass production.

Future work would likely solve the problems described above and lead to a reliable and commercially
viable design. This would include revised and higher quality PCBs as well as more appropriately rated
components. Additionally, sufficient funding would provide the option to manufacture a professionally-
designed transformer and purchase adequate testing equipment to verify the final design. Finally, the
MPPT feedback control could be perfected with additional research and development time.

18
 APPENDIX A CONTROL CODE
/***BUCK AND HALF-BRIDGE CONTROL***/

/***INCLUDES ***/

#include <p18f2520.h>
#include <p18cxxx.h>
#include <delays.h>
#include <pwm.h>
#include <adc.h>
#include <timers.h>
#pragma config OSC = INTIO7
#pragma config DEBUG = ON, LVP = OFF
#pragma config IESO = OFF, PWRT = OFF, WDT = OFF, MCLRE = ON
#pragma config CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF, CPB = OFF, CPD = OFF, WRT0 = OFF
#pragma config WRT1 = OFF, WRT2 = OFF, WRT3 = OFF, WRTB = OFF, WRTC = OFF, WRTD = OFF, EBTR0 = OFF
#pragma config EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF, EBTRB = OFF

/**** PROGRAM CODE ****/

#pragma code
void Init();
int result;
int ref;
int diff;
int diffscale;
int duty;

/***SET UP CCP AND A/D MODULES***/

void Init() {
OSCCON=0xF3;
T2CON=0x00000100; //7:N/A,6-3:Postscale,2:On/off,1-0:Prescale-->Timer 2 on, no pre/postscale
TRISAbits.TRISA1=0;
TRISAbits.TRISA0=1;
TRISCbits.TRISC2=0;
TRISCbits.TRISC1=0;
OpenADC( ADC_FOSC_2 & //set frequency to 500KHz/16=31.25kHz
ADC_RIGHT_JUST & //Result in least significant bits
ADC_2_TAD, //A/D acquisition time is selected as 2 TAD
ADC_CH0 & //RA0/AN0 is the input channel (Pin 2)
ADC_INT_ON & //Interupts enabled
ADC_REF_VDD_VSS, //Internal referencing
0 ); //All general I/O ports are analog (AN12-AN0)--0000=PCFG3:PCFG0

OpenPWM2(0x3F); //PWM period=[(period)+1]xTosc x TMR2 prescaler-->Set PWM frequency //to 31.25KHz

OpenPWM1(0x3F);
}

// Main: Read voltage feedback signal and compare it to an internal reference.

// Use the error between the two values to change the duty cycle about 50%

void main(void)
{
Init();
ref=0x0D90; //Set the internal Reference to about 2.5V
diff=0x0000; //Initialize variables to 0
diffscale=0x000;
result=0x0000;
duty=128; //Set the initial duty cycle to 50%
SetDCPWM1(duty); //PWM x Duty Cycle=(DCx<9:0>) x Tosc-->Set Half-bridge duty to 50%
SetDCPWM2(duty); //Initialize buck duty to 50%
while (1) {
ConvertADC(); //Start conversion
result=ReadADC(); //Returns 16-bit result of an A/D conversion of type int
diff=ref-result; //Error
diffscale=diff>>5; //Scale error by ignoring lower bits
duty=diffscale+128; //Vary duty cycle from 50% by magnitude of error
SetDCPWM2(duty); //Update buck duty cycle
}
}
//***H-BRIDGE CONTROL***//
/***INCLUDES ***/

#include <p18f2520.h>

19
#include <p18cxxx.h>
#include <pwm.h>
#include <timers.h>
#pragma config OSC = INTIO7
#pragma config DEBUG = ON, LVP = OFF
#pragma config IESO = OFF, PWRT = OFF, WDT = OFF, MCLRE = ON
#pragma config CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF, CPB = OFF, CPD = OFF, WRT0 = OFF
#pragma config WRT1 = OFF, WRT2 = OFF, WRT3 = OFF, WRTB = OFF, WRTC = OFF, WRTD = OFF, EBTR0 = OFF
#pragma config EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF, EBTRB = OFF
#pragma udata data1=0x300

//**PWM array sampled from 60Hz sine-->80% duty ratio maximum, 166 samples**//
unsigned char
abc[]={0,0,3,5,6,8,9,11,12,14,15,16,18,19,21,22,24,25,27,28,29,31,32,34,35,36,38,39,40,42,43,44,45,47,48,49,50,51,53,54,55,56,57,58,59,60,61,62,63,64,6
5,66,66,67,68,69,70,70,71,72,72,73,74,74,75,75,76,76,77,77,77,78,78,78,79,79,79,79,80,80,80,80,80,80,80,80,80,80,80,80,79,79,79,79,78,78,78,77,77,77,76
,76,75,75,74,73,73,72,72,71,70,69,69,68,67,66,65,64,64,63,62,61,60,59,58,57,55,54,53,52,51,50,49,47,46,45,44,42,41,40,39,37,36,35,33,32,30,29,28,26,25,
23,22,20,19,17,16,14,13,12,10,9,7,6,4,0,0};

short i; //Array index

static unsigned char val = 0; //Interrupt Flag

void lowisr(); //Interrupt Function

#pragma code low_vector=0x18 //Direct to lowisr() on interrupt

void interrupt_at_low_vector(void)
{
_asm GOTO lowisr _endasm
}

//Keep 'val' low until the PWM process has completed to avoid rewriting PWM register prematurely
#pragma code
#pragma interruptlow lowisr
void lowisr() {
if(PIR1bits.TMR2IF == 1) {
val=1;
PIR1bits.TMR2IF = 0;
} else {
while(1);
}
}

/**** PROGRAM CODE ****/

#pragma code
void Init();

void Init() {
OSCCON=0b11111111; //Initialize internal oscillator block
T2CON=0b00000100; //Timer 2 on, no pre/postscale
PIE1bits.TMR2IE = 1; //Enable interrupts on timer 2
INTCON |= 0xC0; //Initialize interrupt control register
TRISCbits.TRISC1=0; //Enable CCP outputs
TRISCbits.TRISC2=0;
OpenPWM1(0x63); //PWM period=[(period)+1]xTosc x TMR2 prescaler-->20kHz PWM
OpenPWM2(0x63);
}

//**Main: Step through array for each CCP output, using interrupts to ensure proper operation
//**SetDCPWMx function is very slow, so PWM registers are written to directly.
void main(void)
{
Init();
CCP1CONbits.DC1B1=0; //Allow CCP buffer register to be written
CCP1CONbits.DC1B0=0;
CCP2CONbits.DC2B1=0;
//***H-BRIDGE CONTROL CONTINUED***//
CCP2CONbits.DC2B0=0;

while(1) {
for (i=0;i<=165;i=i+1) {
CCPR2L=abc[i]; //Set CCP2 module to array values while
CCPR1L=0; //CCP1 module is held low
while(val!=1); //Wait until new duty value has been latched
val = 0; //Clear interrupt flag for next iteration
}
for (i=0;i<=165;i=i+1) {

20
 CCPR1L=abc[i];
CCPR2L=0;
while(val!=1);
val = 0;

}
}
}

/***BOOST CONTROL***/
/***INCLUDES ***/

#include <p18f2520.h>
#include <p18cxxx.h>
#include <delays.h>
#include <pwm.h>
#include <adc.h>
#include <timers.h>
#pragma config OSC = INTIO7
#pragma config DEBUG = ON, LVP = OFF
#pragma config IESO = OFF, PWRT = OFF, WDT = OFF, MCLRE = ON
#pragma config CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF, CPB = OFF, CPD = OFF, WRT0 = OFF
#pragma config WRT1 = OFF, WRT2 = OFF, WRT3 = OFF, WRTB = OFF, WRTC = OFF, WRTD = OFF, EBTR0 = OFF
#pragma config EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF, EBTRB = OFF

/**** PROGRAM CODE ****/

#pragma code
void Init();
int result;
int ref;
int diff;
int diffscale;
int duty;

/***SET UP CCP AND A/D MODULES***/

void Init() {
OSCCON=0xF3;
T2CON=0x00000100; //7:N/A,6-3:Postscale,2:On/off,1-0:Prescale-->Timer 2 on, no pre/postscale
TRISAbits.TRISA1=0;
TRISAbits.TRISA0=1;
TRISCbits.TRISC2=0;
TRISCbits.TRISC1=0;
OpenADC( ADC_FOSC_2 & //set frequency to 500KHz/16=31.25kHz
ADC_RIGHT_JUST & //Result in least significant bits
ADC_2_TAD, //A/D acquisition time is selected as 2 TAD
ADC_CH0 & //RA0/AN0 is the input channel (Pin 2)
ADC_INT_ON & //Interupts enabled
ADC_REF_VDD_VSS, //Internal referencing
0 ); //All general I/O ports are analog (AN12-AN0)--0000=PCFG3:PCFG0

OpenPWM2(0x3F); //PWM period=[(period)+1]xTosc x TMR2 prescaler-->Set PWM frequency to 31.25KHz

OpenPWM1(0x3F);
}

// Main: Read voltage feedback signal and compare it to an internal reference.

//Use the error between the two values to change the duty cycle about the 50% mark
void main(void)
{
Init();
ref=0x0D90; //Set the internal Reference to about 2.5V
diff=0x0000; //Initialize variables to 0
diffscale=0x000;
result=0x0000;
duty=128; /Set the initial duty cycle to 50%
SetDCPWM2(duty); //Initialize boost duty to 50%
while (1) {
ConvertADC(); //Start conversion
result=ReadADC(); //Returns 16-bit result of an A/D conversion of type int
diff=ref-result; //Error
diffscale=diff>>5; //Scale error by ignoring lower bits
duty=diffscale+128; //Vary duty cycle from 50% by magnitude of error
SetDCPWM2(duty); //Update boost duty cycle
}
}

21
 APPENDIX B MATLAB SCRIPT, EQUATION DERIVATON
AND SIMULATION RESULTS

B.1: Equations and Derivations

Non-idealities in power electronic switches can make converter modeling difficult. To deal with this,
some basic approximations are made in the analysis. First, static models are assumed for the FET, diode
and inductor. The FET is taken to have an on-state resistance, Rds(on), the diode to have a constant
forward voltage drop, Vd, and the inductor to have a constant series resistance, RL. It is also possible to
model the capacitors as having an equivalent series resistance (ESR), but this analysis does not include
it. The losses associated with these static models are described in B1-B3.

Pstatic = I 2 Rds ( on ) (B1)

Pstatic = IVd (B2)
Pstatic = I 2 RL (B3)

In addition to these so-called static models, the author shows in [1], that the switching losses
associated with the FET can be modeled by EQUATION, where Voff is the voltage that the switch must
block when off, Ion is the current that it must conduct, tswitch is the total switching time (which can be
found on manufacturers data sheets), fswitch is the switching frequency, and a is a parameter that
describes the switching trajectory. Typically a is taken to be 2.

Voff I on tswitch f switch

Pswitch = (B4)
a

All of the converter analysis was done using the MATLAB script of B.2. The analysis behind the half-
bridge, h-bridge and bridge rectifier is straightforward and does not require further elaboration.
However, the buck and boost converters require a more involved derivation and so are shown below.

Boost converter:
Looking at the capacitor, when:
switch #1 is on:
Pout
ic = I R = .
Vout
switch #2 is on:
Pout
ic = I L I R = I L .
Vout

Since the average capacitor current is zero,

P P
ic = 0 = D out + (1 D ) I L out .
Vout Vout
1 Pout
D = 1 (B5)
I L Vout
Power balance also reveals that:

Pout = Pin Pdiode PFET PL Pswitch ,

22
 f swVout I Ltsw
(1 D)Vout I L = Vin I L (1 D) I LVd DI L2 Rds ( on ) DI L2 RL ,
a
f swVout tsw
Vin Vout Vd I L RL
D= a . (B6)
I L Rds ( on ) Vd Vout

Note that B5 and B6 are functions of only IL and D; all other quantities are known. The two equations
can be used in an iterative process by varying IL and comparing the resulting duty ratios of each
equation with one another. When the two duty ratio values are sufficiently close, the system is solved
and all power, voltage and current values can be determined.

Buck Converter:

Because the inductor is connected directly to the output:

Pout
IL = (B7)
Vout
Power balance gives:
Pout = Pin Pdiode PFET Pswitch .
f swVout I Ltsw
Vout I L = DVin I L (1 D) I LVd DI L2 Rds ( on ) I L2 RL .
a
Reducing:
f swVout tsw
Vout + Vd + I L RL +
D= a (B8)
Vin I L Rds ( on ) + Vd

With D and IL known, all other quantities can be determined.

B.2: MATLAB Script

clc
clear all

a=2; %Assume rectangular commutation

%H-bridge Inverter

%FET parameters from datasheet

Rds_h=0.18;
tdon_h=30;
tr_h=25;
tdoff_h=100;
tf_h=40;
tsw_h=(tdon_h+tr_h+tdoff_h+tf_h)*10^-9; %Total switching time

f_h=20*10^3; %Switching frequency is 20kHz

%Because the control was implemented by sampling a sinusoid and scaling it

% so that the maximum corresponded to the maximum duty ratio, it can be
% shown that the average duty ratio during PWM operation is simply the
% average of the scaled sinusoid.

23
D_h_peak=0.8; %Maximum duty ratio is 80%
D_h_avg=(2/pi)*D_h_peak; %Average of rectified sinusoid is (2/pi)*peak

Pout_h=500; %System output power

Vout_h=170; %For a 120Vrms sinusoid, the peak voltage is

% 120*sqrt(2)=170V

I_h=Pout_h/(Vout_h*D_h_avg); %Instantaneous current depends on

Vbus_h=Vout_h+2*I_h*Rds_h;
Pstat_h=2*D_h_avg*Rds_h*I_h^2;
Pcom_h=2*f_h*Vout_h*I_h*tsw_h/a;
Pin_h=Pout_h+Pstat_h+Pcom_h;
Eta_h=Pout_h/Pin_h;
% average voltage and output power
%Bus voltage is higher by 2 resistive
% FET on-state drops
%Satic FET losses
%Commutation losses
%Output Power=Input Power-Losses
%H-bridge Efficiency

%Bridge Rectifier

Vd_rect=1; %Diode parameter from datasheet

Vout_rect=Vbus_h; %Output voltage is H-bridge input
Vin_rect=Vout_rect+2*Vd_rect; %Output is input less 2 diode drops
Pout_rect=Pin_h; %Output power is H-bridge input
I_rect=Pout_rect/Vout_rect;
Pstat_rect=2*I_rect*Vd_rect;
Pin_rect=Pout_rect+Pstat_rect;
Eta_rect=Pout_rect/Pin_rect;

%Tranformer
% Note that transformer efficiency is estimated to provide a better view
% of the whole system
Eta_trans=0.9;
Pout_trans=Pin_rect; %Output power is bridge rect input
Pin_trans=Pout_trans/Eta_trans; %Input power is estimated

%Half-Bridge Inverter

%FET parameters from datasheet

Rds_ha=0.0065;
tdon_ha=27;
tr_ha=155;
tdoff_ha=125;
tf_ha=65;
tsw_ha=(tdon_ha+tr_ha+tdoff_ha+tf_ha)*10^-9;

f_ha=31.25*10^3; %Switching frequency is 31.25kHz

Pout_ha=Pin_trans; %Output power is transformer input

Vout_ha=13; %Voltage regulated to a constant 13V
Iout_ha=Pout_ha/Vout_ha;
Vin_ha=2*(Vout_ha+Iout_ha*Rds_ha); %Input voltage is twice the output plus
% two resistive FET drops (~26V)
Pstat=Rds_ha*Iout_ha^2;
Pcom=f_ha*(Vin_ha/2)*Iout_ha*tsw_ha/a;
Pin_ha=Pout_ha+Pstat+Pcom;
Eta_ha=Pout_ha/Pin_ha;

24
%Buck Converter
%FET parameters from datasheet
Rds_bu=0.018;
tdon_bu=17;
tr_bu=77;
tdoff_bu=41;
tf_bu=56;
tsw_bu=(tdon_bu+tr_bu+tdoff_bu+tf_bu)*10^-9;

Vd_bu=0.67; %Diode forward drop from datasheet

Rl_bu=0.08; %Measured DC inductor resistance

f_bu=31.25*10^3;

Vout_bu=Vin_ha; %Buck output is halfbridge input

Vin_bu=72; %Buck input ranges from ~30V-70V and
% depends on boost MPPT operation
Pout_bu=Pin_ha;

%Derived equations from analysis in APPENDIX

IL_bu=Pout_bu/Vout_bu;

A=Vout_bu+Vd_bu+IL_bu*Rl_bu+f_bu*tsw_bu*Vin_bu/a; %Dummy variables for

B=Vin_bu-IL_bu*Rds_bu+Vd_bu; % clarity
D_bu=A/B; %Solve for duty ratio

Pin_bu=Vin_bu*IL_bu*D_bu; %Find input power

Eta_bu=Pout_bu/Pin_bu; % and then efficiency

%Boost Converter
Rds_bo=0.018;
tdon_bo=17;
tr_bo=77;
tdoff_bo=41;
tf_bo=56;
tsw_bo=(tdon_bo+tr_bo+tdoff_bo+tf_bo)*10^-9;

Rl_bo=0.08;
Vd_bo=0.67;

f_bo=31.25*10^3;

Vin_bo=48; %Input voltage varies from 24-48V

Vout_bo=Vin_bu; %Boost MPPT output is buck input
Pout_bo=Pin_bu;

IL_bo=0; %Initialize inductor current to 0 for

% iteration about IL
tol_bo=1; %Set tolerance to some high value

%While the duty ratios from the two derived equations of APPENDIX differ by
% more than 0.0005, increment the inductor current
while tol_bo>=0.0005
IL_bo=IL_bo+0.0001;
A=Vin_bo-Vout_bo-Vd_bo-IL_bo*Rl_bo-f_bo*Vout_bo*tsw_bo/a;
B=IL_bo*Rds_bo-Vd_bo-Vout_bo;
D1_bo=A/B;

25
 D2_bo=1-(Pout_bo/Vout_bo)/IL_bo;
tol_bo=abs(D1_bo-D2_bo);
end
%The duty ratios were successfully found--compute the power and efficiency
Pin_bo=Vin_bo*IL_bo;
Eta_bo=Pout_bo/Pin_bo;

%All system parameters are known--compute the overall efficiency

Eta_tot=Eta_h*Eta_rect*Eta_trans*Eta_ha*Eta_bu*Eta_bu*100

B.3 Simulation Results

Figure B.1: Boost Converter Efficiency Figure B.2: Buck Converter Efficiency

Figure B.3: Half-Bridge Efficiency Figure B.4: H-Bridge Efficiency

26
Figure B.5: Overall Inverter Efficiency

27
APPENDIX C SCHEMATICS, LAYOUTS, AND PICTURES

Figure C.1: Boost Converter Schematic

Figure C.2 Buck Converter Schematic

Figure C.3: Half-Bridge Inverter Schematic

28
 Figure C.4: Bridge-Rectifier and H-Bridge Schematic

Figure C.5: Control Board Schematic of PICs

Figure C.6: Comparator Interface between Gate Drive ICs and PICs

29
 Figure C.7: Input Output Connections of the Control Board

Figure C.8: PCB Layout of Boost-Buck Figure C.9: Actual picture of completed Boost/Buck

Figure C.10: PCB Layout of Half-Bridge Figure C.11: Actual picture of completed Half-Bridge

30
Figure C.12: PCB Layout of H-Bridge Figure C.13: Actual picture of completed H-Bridge

Figure C.14: PCB Layout of Control Board Figure C.15: Actual picture of completed Control
Board

Figure C.16: The entire inverter system shown together

31
 APPENDIX D DATA RESULTS AND RELATED FIGURES

Table D.1: Raw Data for Boost Converter Testing

Vin In Pin Duty Vout Load Pout Efficiency Ripple
[V] [A] [W] [V] [V] [Ohms] [W] [%] [V]
24.26 0.714 17.08 0.107 25.99 40 16.3 95.43325527 0.08
24.22 1.708 41.19 0.1202 26.02 17 39.3 95.41150765 0.12
24.12 3.49 84.08 0.1371 26 8.4818068 79.7 94.79067555 0.14
24.01 5.39 128.2 0.153 26 5.6569038 119.5 93.21372855 0.18
23.87 7.35 174.6 0.1775 26.02 4.23 159.5 91.35166094 0.23
23.79 9.35 221.8 0.1935 26 3.3833834 199.8 90.08115419 0.26
23.66 11.49 271.5 0.2127 26.07 2.82 240.8 88.69244936 0.29
23.56 13.61 320.6 0.2261 26 2.4142857 280 87.33624454 0.35
24.03 1.126 25.52 0.632 60.05 144.9 22.6 88.55799373 0.09
23.97 3.49 81.4 0.6466 60.19 48 73.9 90.78624079 0.15
23.83 5.86 138.2 0.6561 60.17 28.8 123.2 89.14616498 0.26
23.71 8.37 197.7 0.6644 60.15 20.58 174.2 88.11330298 0.34
23.55 11.1 260.9 0.6737 60.25 16 226 86.62322729 0.41
23.42 13.78 322.1 0.6801 60 13.1 272.9 84.72524061 0.5
36 0.793 24.97 0.43 60.04 144.93 22.6 90.50861033 0.028
35.93 2.227 78.3 0.4433 60.09 48.1 73.8 94.25287356 0.068
35.85 3.79 131.9 0.451 60.05 28.8 122.9 93.17664898 0.102
35.78 5.34 187.8 0.4576 60.15 20.62 174.2 92.75825346 0.128
35.7 6.89 243.6 0.4634 60.12 16 224.2 92.03612479 0.18
35.6 8.45 299.1 0.4687 60.09 13.11 274.3 91.70845871 0.192
47.89 0.576 24.17 0.231 59.97 144.93 22.6 93.50434423 0.04
47.88 1.631 76.9 0.243 60 48.1 72.7 94.53836151 0.052
47.9 2.75 129 0.2495 60.1 28.8 123 95.34883721 0.078
47.81 3.88 183 0.2532 60 20.58 172.8 94.42622951 0.101
47.77 5 237 0.258 60 16.085791 223.8 94.43037975 0.148
47.73 6.14 291 0.2629 60.09 13.1 274.2 94.22680412 0.16

Vin(24V), Vout(26V)
Vin(24V), Vout(60V)
Duty Ratio (Vout=26V)
Duty Ratio (Vout=60V)
0.8
60
0.7
50
0.6
40 0.5
Vout [V]

Duty Ratio

30 0.4

0.3
20
0.2
10
0.1

0 0
23.4 23.6 23.8 24 24.2 24.4
Vin [V]

Figure D.1: Output Characteristics (Vin=24V, Vout=26V & Vout=60V)

32
 Pin vs Pout (Vout=26V)
Pin vs Pout (Vout=60V)
Efficiency (Vout=26V)
Efficiency (Vout=60V) 100

98
260
96

210 94

92

160 90

88
110
86

84
60
82

10 80
0 50 100 150 200 250 300 350

P i n [ W]

Figure D.2: Power Characteristics (Vin=24V, Vout=26V & Vout=60V)

Vin(36V), Vout(60V)
Vin(48V), Vout(60V)
Duty Ratio (Vin-36V, Vout=60V)
Duty Ratio (Vin=48V, Vout=60V)
60 1
0.9
50
0.8
0.7
40

Duty Ratio
0.6
Vin [V]

30 0.5
0.4
20
0.3
0.2
10
0.1
0 0
59.96 59.98 60 60.02 60.04 60.06 60.08 60.1 60.12 60.14 60.16
Vout [V]

Figure D.3: Output Characteristics (Vin=36V & Vin=48V, Vout=60V)

Pout (Vin=36V, Vout=60V)
Pout (Vin=40V, Vout=60V)
Efficiency (Vin=36V, Vout=60V)
Efficiency (Vin=48V, Vout=60V)

300 100
98
250
96
94
200
Efficiency [%]

92
Pout [W]

150 90
88
100
86
84
50
82
0 80
0 50 100 150 200 250 300 350
Pin [W]

Figure D.4: Power Characteristics (Vin=36V & Vin=48V, Vout=60V)

33
 Figure D.5: Boost Signals Figure D.6: Boost Signals
(Vin=24, Vout=26, Pout=80W) (Vin=24, Vout=60, Pout=175W)

Figure D.7: Boost Signals Figure D.8: Boost Signals

(Vin=36, Vout=60V, Pout=225W) (Vin=48, Vout=60V, Pout=275W)

Table D.2: Raw Data for Buck Converter

Vout Load Pout Duty Vin In Pin Efficiency Ripple
[V] [Ohms] [W] [V] [A] [W] [%] [V]
26 27 24.5 0.06 29.92 0.975 24.76 98.94991922 0.25
26.02 9 74.9 0.05 29.85 2.653 77.5 96.64516129 0.708
26.02 5.41 124.4 0.058 29.75 4.65 131.1 94.88939741 1.46
26.05 3.86 175.4 0.063 29.59 6.9 195.3 89.81054788 2.76
26 27.027 21.35 0.5114 50 0.893 22.33 95.61128527 0.304
25.99 9.01 74.3 0.52 50.2 2.146 84.2 88.24228029 0.71
25.99 5.41 124.2 0.552 50.23 4.21 136 91.32352941 1.66
26.04 3.86 175.2 0.537 49.89 5.77 201 87.1641791 1.52
26.07 27 25.17 0.343 72.67 0.908 31 81.19354839 1.35
26.12 9.01 70.2 0.3596 72.83 1.732 74.1 94.73684211 2.76
26 5.41 95.3 0.3655 72.9 2.009 101.4 93.98422091 3.04

34
 Vin=30V
Vin=50V
Vin=72V
Duty Ratio (Vin=30V)
Duty Ratio (Vin=50V)
Duty Ratio (Vin=72V)

26.5 0.65

26.4
0.6
26.3

26.2 0.55

26.1
0.5
26
0.45
25.9

25.8 0.4

25.7
0.35
25.6

25.5 0.3
25 35 45 55 65 75
V in [ V ]

Figure D.9: Buck Output Characteristics

Efficiency (Vin=30V)
Efficiency (Vin=50V)
Efficiency (Vin=72V)
Pin (Vin=30V)
Pin (Vin=50V)
Pi (Vi 72V)
80 250

70
200
60

50
150

40

100
30

20
50
10

0 0
80 85 90 95 100
E f f i c i e nc y [ %]

Figure D.10 Buck Power Characteristics

35
Figure D.11: Buck Signals Figure D.12: Buck Signal
(Vin=30V, Pout=75W) (Vin=30V, Pout=175W)

Figure D.13: Buck Signals Figure D.14: Buck Signals

(Vin=50V, Pout=75W) (Vin= 50V, Pout=125W)

100 14.5

90
14
80

70
13.5
60

50 13
40
12.5
30
20
12
10
0 11.5
0 50 100 150 200
Pin [ W ]
Eff iciency
Pin vs Vout

Figure D.15: Half-Bridge Performance

36
 Figure D.16: Half-Bridge Signals (Pout=25W) Figure D.17: Half-Bridge Signals (Pout=50W)

Figure D.18: Half-Bridge Signals (Pout = 76W) Figure D.19: Half-Bridge Signals (Pout =100W)

Figure D.20: H-Bridge Signals (Vdc = 50V) Figure D.21: H-Bridge Signals (Filtering)

37
Figure D.22: H-Bridge Signals (Gate Signals) Figure D.23: H-Bridge Signals (Vdc=120V)

38
 APPENDIX E COST SUMMARY

The following appendix contains parts list for the final design as well as the labor cost throughout the
entire project.
Table E1 : Miscellaneous Parts Used
Part Name Price Quantity Subtotal
General Heat Sink 3.48 1 3.48
14 AWG magnet wire 12.95 1 12.95
Ferrite Core 20 1 20
Total 36.43

Table E2: Boost Converter Parts List

Part Name Price Quantity Subtotal
MIC4424 2.45 1 2.45
R=100 Ohms, 1/4W 0.12 1 0.12
100k trimpot 0.85 1 0.85
IRF3710 2.14 1 2.14
43CTQ100 2.66 1 2.66
.22uF Ceramic 0.077 1 0.077
2200 uF Electrolytic 10.09 2 20.18
1n5819 0.109 1 0.109
Test Points 0.309 6 1.854
Banana Stands 0.662 4 2.648
Powdered Iron Core 2.86 1 2.86
MTA 100, 3-pin female 0.173 1 0.173
MTA 100, 3-pin male 0.173 1 0.173
Total 36.294

Table E3: Buck Converter Parts List

Part Name Price Quantity Subtotal
IR2117 2.37 1 2.37
R=100 Ohms, 1/4W 0.12 1 0.12
1n5819 0.109 2 0.218
.22uF Ceramic 0.077 3 0.231
43CTQ100 2.66 1 2.66
IRF3710 2.14 1 2.14
STPR820 0.618 1 0.618
50k trimpot 0.85 1 0.85
R=63 Ohms, 3W 0.855 1 0.855
IRF3710 2.14 1 2.14
2200 uF Electrolytic 10.09 2 20.18
4700uF Electrolytic 4.18 2 8.36
Powdered Iron Core 2.86 1 2.86
Banana Stands 0.662 5 3.31
Test Points 0.309 6 1.854
MTA 100, 3-pin female 0.173 1 0.173
MTA 100, 3-pin male 0.173 1 0.173
Total 49.112

39
 Table E3: Half-Bridge Parts List
Part Name Price Quantity Subtotal
IRS2003 1.179 1 1.179
1uF Electrolytic 0.031 1 0.031
R=100 Ohms, 1/4W 0.12 1 0.12
R=63 Ohms, 3W 0.855 2 1.71
.22uF Ceramic 0.077 3 0.231
1n5819 0.109 5 0.545
STB80NF55 1.77 2 3.54
Banana Jacks 0.882 4 3.528
100uF Film 10.59 2 21.18
Test Points 0.309 6 1.854
MTA 100, 3-pin female 0.173 1 0.173
MTA 100, 3-pin male 0.173 1 0.173
Total 34.264

Table E4: Bridge-Rectifier and H-Bridge Parts List

Part Name Price Quantity Subtotal
IR2010 3.95 2 7.9
R=100 Ohms, 1/4W 0.12 4 0.48
1n5819 0.109 8 0.872
47uF tantalum 0.26 2 0.52
.22uF Ceramic 0.077 4 0.308
1000pF Ceramic 0.597 4 2.388
R=63 Ohms, 3W 0.855 4 3.42
STPR820 0.618 2 1.236
GBU4M 0.755 1 0.755
MTA 100, 3-pin female 0.173 2 0.346
MTA 100, 3-pin male 0.173 2 0.346
Test Points 0.309 9 2.781
Heat Sinks 0.634 4 2.536
Total 23.888

Table E5: Control/Logic Supply Parts List

Part Name Price Quantity Subtotal
PIC18F2520 3.98 3 11.94
.22uF Ceramic 0.077 21 1.617
1N4773 0.04 5 0.2
Banana Stands 0.662 2 1.324
L7805AB 0.638 1 0.638
L7815CP 0.529 1 0.529
NME2405 10.11 1 10.11
NME2415 10.11 1 10.11
LM311 0.72 3 2.16
R=1k Ohms, 1/4W 0.12 6 0.72
R=100k Ohms, 1/4W 0.12 3 0.36
R=20k Ohms, 1/4W 0.12 3 0.36
MTA 100, 3-pin female 0.173 5 0.865
MTA 100, 3-pin male 0.173 5 0.865
MTA 100, 2-pin female 0.173 2 0.346
MTA 100, 2-pin male 0.173 2 0.346
Total 42.49

40
Table E6: Engineering hours spent on project and cost
Month Total Engineering Hours
February 113.5
March 83.5
April 292.5
Total 489.5
Labor Cost
(assuming $50/hour $24,450
salary)

41
 APPENDIX F MPPT FIGURES

Figure F.1: Solar Cell I-V Characteristic

Source: http://upload.wikimedia.org/wikipedia/commons/d/d8/Solar-Cell-IV-curve-with-MPP.png

Figure 2.2: Perturb and Observe Algorithm Flowchart

Source: http://www.iet.aau.dk/~des/papers/PID253435-1_EPE-PEMC2006.pdf

42
 REFERENCES

[1] P. T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998.

[2] D. Sera, T. Kerekes, et al., Improved MPPT Algorithms for Rapidly Changing Environmental
Conditions,
Etching reactors, April 2008, http://www.iet.aau.dk/~des/papers/PID253435-1_EPE-
PEMC2006.pdf.

43