002-14796 CYW43438 Single-Chip IEEE 802.11ac B G N MAC Baseband Radio With Integrated Bluetooth 4.1 and FM Receiver

PRELIMINARY CYW43438
Single-Chip IEEE 802.11ac b/g/n MAC/Baseband/

Radio with Integrated Bluetooth 4.1 and FM Receiver
The Cypress CYW43438 is a highly integrated single-chip solution and offers the lowest RBOM in the industry for smartphones,
tablets, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio,
Bluetooth 4.1 support, and an FM receiver. In addition, it integrates a power amplifier (PA) that meets the output power requirements
of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF
switch, further reducing the overall solution cost and printed circuit board area.
The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in
4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth/FM host interface.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43438 is designed to address
the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit
that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while
maximizing battery life.
The CYW43438 implements the worlds most advanced Enhanced Collaborative Coexistence algorithms and hardware
mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence.
Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number Cypress Part Number
BCM43438 CYW43438
BCM43438KUBG CYW43438KUBG
Features
IEEE 802.11x Key Features Bluetooth and FM Key Features
Single-band 2.4 GHz IEEE 802.11b/g/n. Complies with Bluetooth Core Specification Version 4.1 with
provisions for supporting future specifications.
Support for 2.4 GHz Broadcom TurboQAM data rates (256-
QAM) and 20 MHz channel bandwidth. Bluetooth Class 1 or Class 2 transmitter operation.
Integrated iTR switch supports a single 2.4 GHz antenna Supports extended Synchronous Connections (eSCO), for
shared between WLAN and Bluetooth. enhanced voice quality by allowing for retransmission of
dropped packets.
Supports explicit IEEE 802.11n transmit beamforming.
Adaptive Frequency Hopping (AFH) for reducing radio fre-
Tx and Rx Low-density Parity Check (LDPC) support for quency interference.
improved range and power efficiency.
Interface support Host Controller Interface (HCI) using a
Supports standard SDIO v2.0 and gSPI host interfaces. high-speed UART interface and PCM for audio data.
Supports Space-Time Block Coding (STBC) in the receiver. FM receiver unit supports HCI for communication.
Integrated ARM Cortex-M3 processor and on-chip memory Low-power consumption improves battery life of handheld
for complete WLAN subsystem functionality, minimizing the devices.
need to wake up the applications processor for standard
WLAN functions. This allows for further minimization of FM receiver: 65 MHz to 108 MHz FM bands; supports the
power consumption, while maintaining the ability to field- European Radio Data Systems (RDS) and the North Ameri-
upgrade with future features. On-chip memory includes 512 can Radio Broadcast Data System (RBDS) standards.
KB SRAM and 640 KB ROM. Supports multiple simultaneous Advanced Audio Distribution
Profiles (A2DP) for stereo sound.
OneDriver software architecture for easy migration from
existing embedded WLAN and Bluetooth devices as well as Automatic frequency detection for standard crystal and
to future devices. TCXO values.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 002-14796 Rev. *K Revised May 11, 2017
General Features Security:

Supports a battery voltage range from 3.0V to 4.8V with an WPA and WPA2 (Personal) support for powerful encryption

internal switching regulator. and authentication.
Programmable dynamic power management. AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
4 Kbit One-Time Programmable (OTP) memory for storing Reference WLAN subsystem provides Cisco Compatible Ex-
board parameters. tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
Can be routed on low-cost 1 x 1 PCB stack-ups. Reference WLAN subsystem provides WiFi Protected Set-
up (WPS).
63-ball WLBGA package (4.87 mm 2.87 mm, 0.4 mm
Worldwide regulatory support: Global products supported
pitch).
with worldwide homologated design.
Figure 1. CYW43438 System Block Diagram
VDDIO VBAT
WL_REG_ON
WLAN
WL_IRQ
Host I/F
SDIO*/SPI
CLK_REQ 2.4 GHz WLAN +

Bluetooth TX/RX BPF
BT_REG_ON
CYW43438
PCM
Bluetooth BT_DEV_WAKE
Host I/F
BT_HOST_WAKE FM
RX
UART
FM RX
Host I/F Stereo Analog Out
Document No. Document Number: 002-14796 Rev. *K Page 2 of 101

Contents
1. Overview ............................................................ 5 9. Microprocessor and Memory Unit
1.1 Overview ............................................................. 5 for Bluetooth ................................................... 39
1.2 Features .............................................................. 6 9.1 RAM, ROM, and Patch Memory .........................39
1.3 Standards Compliance ........................................ 6 9.2 Reset ..................................................................39
2. Power Supplies and Power Management ....... 8 10. Bluetooth Peripheral Transport Unit............. 40
2.1 Power Supply Topology ...................................... 8 10.1 PCM Interface ....................................................40
2.2 CYW43438 PMU Features .................................. 8 10.2 UART Interface ..................................................46
2.3 WLAN Power Management ............................... 11 11. FM Receiver Subsystem ................................ 48
2.4 PMU Sequencing .............................................. 11 11.1 FM Radio ............................................................48
2.5 Power-Off Shutdown ......................................... 12 11.2 Digital FM Audio Interfaces ................................48
2.6 Power-Up/Power-Down/Reset Circuits ............. 12 11.3 Analog FM Audio Interfaces ...............................48
3. Frequency References ................................... 13 11.4 FM Over Bluetooth .............................................48
3.1 Crystal Interface and Clock Generation ............ 13 11.5 eSCO .................................................................48
3.2 TCXO ................................................................ 13 11.6 Wideband Speech Link ......................................48
3.3 External 32.768 kHz Low-Power Oscillator ....... 15 11.7 A2DP ..................................................................48
11.8 Autotune and Search Algorithms .......................48
4. WLAN System Interfaces ............................... 16
11.9 Audio Features ...................................................49
4.1 SDIO v2.0 .......................................................... 16
4.1.1 SDIO Pin Descriptions ........................... 16 11.10RDS/RBDS ........................................................51
4.2 Generic SPI Mode ............................................. 17 12. CPU and Global Functions ............................ 52
5. Wireless LAN MAC and PHY.......................... 25 12.1 WLAN CPU and Memory Subsystem ................52
5.1 MAC Features ................................................... 25 12.2 One-Time Programmable Memory .....................52
5.1.1 MAC Description .................................... 25 12.3 GPIO Interface ...................................................52
5.2 PHY Description ................................................ 27 12.4 External Coexistence Interface ..........................53
5.2.1 PHY Features ........................................ 28 12.5 JTAG Interface ...................................................53
6. WLAN Radio Subsystem ................................ 29 12.6 UART Interface ..................................................53
6.1 Receive Path ..................................................... 30 13. WLAN Software Architecture......................... 54
6.2 Transmit Path .................................................... 30 13.1 Host Software Architecture ................................54
6.3 Calibration ......................................................... 30 13.2 Device Software Architecture .............................54
7. Bluetooth + FM Subsystem Overview........... 31 13.2.1 Remote Downloader ...............................54
7.1 Features ............................................................ 31 13.3 Wireless Configuration Utility .............................54
7.2 Bluetooth Radio ................................................. 32 14. Pinout and Signal Descriptions..................... 55

8. Bluetooth Baseband Core.............................. 34 14.1 Ball Map .............................................................55
8.1 Bluetooth 4.1 Features ...................................... 34 14.2 WLBGA Ball List in Ball Number
Order with X-Y Coordinates ..............................56
8.2 Link Control Layer ............................................. 34
14.3 WLBGA Ball List Ordered By Ball Name ............58
8.3 Test Mode Support ............................................ 35
14.4 Signal Descriptions ............................................59
8.4 Bluetooth Power Management Unit .................. 35
14.5 WLAN GPIO Signals and Strapping Options .....62
8.5 Adaptive Frequency Hopping ............................ 38
14.6 Chip Debug Options ...........................................62
8.6 Advanced Bluetooth/WLAN Coexistence .......... 38
14.7 I/O States ...........................................................63
8.7 Fast Connection
(Interlaced Page and Inquiry Scans) ................. 38 15. DC Characteristics.......................................... 65
15.1 Absolute Maximum Ratings ...............................65
15.2 Environmental Ratings .......................................65
Document Number: 002-14796 Rev. *K Page 3 of 101

15.3 Electrostatic Discharge Specifications .............. 65 21. Interface Timing and AC Characteristics ..... 90
15.4 Recommended Operating Conditions 21.1 SDIO Default Mode Timing ................................90
and DC Characteristics ..................................... 66 21.2 SDIO High-Speed Mode Timing .........................91
16. WLAN RF Specifications ................................ 68 21.3 gSPI Signal Timing .............................................92
16.1 2.4 GHz Band General RF Specifications ......... 68 21.4 JTAG Timing ......................................................92
16.2 WLAN 2.4 GHz Receiver Performance 22. Power-Up Sequence and Timing ................... 93
Specifications .................................................... 69
22.1 Sequencing of Reset and Regulator
16.3 WLAN 2.4 GHz Transmitter Performance Control Signals ..................................................93
Specifications .................................................... 72
16.4 General Spurious Emissions Specifications ...... 73 23. Package Information ...................................... 96
23.1 Package Thermal Characteristics ......................96
17. Bluetooth RF Specifications .......................... 74
24. Mechanical Information.................................. 97
18. FM Receiver Specifications ........................... 80
25. Ordering Information...................................... 99
19. Internal Regulator Electrical
Specifications .................................................. 84 26. Additional Information ................................... 99
19.1 Core Buck Switching Regulator ........................ 84 26.1 Acronyms and Abbreviations .............................99
19.2 3.3V LDO (LDO3P3) ......................................... 85 26.2 IoT Resources ....................................................99
19.3 CLDO ................................................................ 86 Document History......................................................... 100
19.4 LNLDO .............................................................. 87 Sales, Solutions, and Legal Information .................... 101
Worldwide Sales and Design Support ............................101
20. System Power Consumption ......................... 88 Products .........................................................................101
20.1 WLAN Current Consumption ............................. 88 PSoC Solutions ............................................................101
20.1.1 2.4 GHz Mode ....................................... 88 Cypress Developer Community ......................................101
20.2 Bluetooth and FM Current Consumption ........... 89 Technical Support ...........................................................101

1. Overview
1.1 Overview
The Cypress CYW43438 provides the highest level of integration for a mobile or handheld wireless system, with integrated
IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes
and allows for handheld device flexibility in size, form, and function. The CYW43438 is designed to address the needs of highly mobile
devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnection of all the major physical blocks in the CYW43438 and their associated external interfaces, which
are described in greater detail in subsequent sections.
Figure 2. CYW43438 Block Diagram
JTAG*
Cortex
ETM
SDP
Debug
M3
FMRX AHB
FMRF FMDigital
AHBtoAPB
AHBBusMatrix
ADC
FM
FMDemod. Bridge RAM
I/F
FM_RX LNA MDXRDS APB ROM
Decode
ADC
WDTimer Patch
InterCtrl
SWTimer DMA
LO Control
RSSI DPLL BusArb
Gen. GPIO
Ctrl ARMIP
JTAGsupportedoverSDIOorBTPCM
SDIOorgSPI
SWREG Power
BPL
UART
Commonand
LDOx2 Supply
RadioDigital
Buffer SDIO PMU

Modem RF LPO SleepCLK
Control
Digital XTALOSC. XTAL
APU gSPI
Debug Demod. POR WL_REG_ON
UART BTClock/ &Bit
Hopper Sync
JTAG*
ARM
Digital WDT
BlueRF PA CM3
I/O Interface OTP
PCM Digital
Mod. GPIO GPIO
I/OPortControl
LCU
Backplane
UART UART
RAM
RX/TX JTAG* SupportedoverSDIOorBTPCM
ROM
GPIO
Buffer
IF
BTPHY PLL
IEEE802.11a/b/g/n
Wake/ BTWLAN
BTFMClockControl
ECI
LNPPHY
WiMaxCoex
SleepCtrl 2.4GHz
Radio
MAC
Sleep PA
Clock PMU
time PMU
2.4GHz
Management Ctrl
Keeping SharedLNA
BPF
WiMax
Coex. XO
LPO POR
Buffer
PTU WLAN
VBAT
XTAL
BT_REG_ON
VREGs
*ViaGPIOconfiguration,JTAGissupportedoverSDIOorBTPCM

1.2 Features
The CYW43438 supports the following WLAN, Bluetooth, and FM features:
IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch
Bluetooth v4.1 with integrated Class 1 PA
Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation
On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
Simultaneous BT/WLAN reception with a single antenna
WLAN host interface options:
SDIO v2.0, including default and high-speed timing.
gSPIup to a 50 MHz clock rate
BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces.
ECIenhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions.
PCM for FM/BT audio, HCI for FM block control
HCI high-speed UART (H4 and H5) transport support
Wideband speech support (16 bits, 16 kHz sampling PCM, through PCM interfaces)
Bluetooth SmartAudio technology improves voice and music quality to headsets.
Bluetooth low power inquiry and page scan
Bluetooth Low Energy (BLE) support
Bluetooth Packet Loss Concealment (PLC)
FM advanced internal antenna support
FM auto searching/tuning functions
FM multiple audio routing options: PCM, eSCO, and A2DP
FM mono-stereo blending and switching, and soft mute support
FM audio pause detection support
Multiple simultaneous A2DP audio streams
FM over Bluetooth operation and on-chip stereo headset emulation
1.3 Standards Compliance

The CYW43438 supports the following standards:
Bluetooth 2.1 + EDR
Bluetooth 3.0
Bluetooth 4.1 (Bluetooth Low Energy)
65 MHz to 108 MHz FM bands (US, Europe, and Japan)
IEEE 802.11nHandheld Device Class (Section 11)
IEEE 802.11b
IEEE 802.11g
IEEE 802.11d
IEEE 802.11h
IEEE 802.11i
The CYW43438 will support the following future drafts/standards:
IEEE 802.11r Fast Roaming (between APs)

IEEE 802.11k Resource Management

IEEE 802.11w Secure Management Frames
IEEE 802.11 Extensions:
IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)
IEEE 802.11i MAC Enhancements
IEEE 802.11r Fast Roaming Support
IEEE 802.11k Radio Resource Measurement
The CYW43438 supports the following security features and proprietary protocols:
Security:
WEP

WPA Personal

WPA2 Personal
WMM
WMM-PS (U-APSD)
WMM-SA
WAPI
AES (Hardware Accelerator)
TKIP (host-computed)
CKIP (SW Support)
Proprietary Protocols:
CCXv2
CCXv3
CCXv4
CCXv5
IEEE 802.15.2 Coexistence Compliance on silicon solution compliant with IEEE 3-wire requirements.

2. Power Supplies and Power Management

2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43438. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth, WLAN, and FM functions in embedded
designs.
A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW43438.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out
of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down
only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the
dynamic demands of the digital baseband.
The CYW43438 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 provides the CYW43438 with all required voltage, further reducing leakage currents.
Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.
Note: VDDIO should be connected to the WCC_VDDIO pin of the device.
2.2 CYW43438 PMU Features

The PMU supports the following:
VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator
VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3
1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep
Additional internal LDOs (not externally accessible)
PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
Figure 3 and Figure 4 show the typical power topology of the CYW43438.

Figure 3. Typical Power Topology (1 of 2)
SR_VDDBAT5V
VBAT WLRFTXMixerandPA
(notallversions)
MiniPMU
CYW43438 InternalVCOLDO 1.2V WLRFLOGEN
1.2V 80mA(NMOS)
InternalRXLDO 1.2V WLRFRXLNA

VBAT: 10mA(NMOS)
Operational: 3.04.8V VDD1P35 InternalADCLDO
Performance: 3.04.8V 10mA(NMOS) 1.2V WLRFADCREF
AbsoluteMaximum: 5.5V
VDDIO InternalTXLDO
80mA(PMOS) 1.2V WLRFTX
Operational: 1.83.3V 1.35V
InternalAFELDO
80mA(NMOS) 1.2V WLRFAFEandTIA
CoreBuck 10mAaverage,
SR_VLX MiniPMUisplaced
Int_SR_VBAT Regulator >10mAatstartup
inWLradio WLRFRFPLLPFDandMMD
Peak:370mA WLRF_XTAL_
(320mA) Avg:170mA 2.2uH 600@ VDD1P2
SW1 0603 100MHz WLRFXTAL
LDO_VDD_1P5 1.2V
SR_VBAT5V LNLDO FM_RF_VDD 4.6mA
VBAT 4.7uF (100mA) VOUT_LNLDO FMLNA,Mixer,TIA,VCO
0402 0.1uF
SR_PVSS 0201
2.2uF
0402 BTFM_PLL_VDD 6.4mA
GND PMU_VSS FMPLL,LOGEN,AudioDAC/BTPLL
BT_VCO_VDD
BTLNA,Mixer,VCO
BT_IF_VDD
BTADC,Filter
WCC_VDDIO
WCC_VDDIO (40mA) LPLDO1 1.1V
(5mA)
WLAN/BT/CLB/Top,AlwaysOn
VDDC1
1.3V,1.2V,
CLLDO or0.95V WLOTP
Peak:200mA (AVS) VDDC2
Avg:80mA
(Bypassindeep VOUT_CLDO 2.2uF
sleep) 0402 WLDigitalandPHY
WL_REG_ON o_wl_resetb
BT_REG_ON o_bt_resetb
WLVDDM(SROMs&AOS)
Supplyball Supplybump/pad Powerswitch

BTVDDM
Groundball Groundbump/pad Nopowerswitch
BT/WLANreset Nodedicatedpowerswitch,butinternalpower
balls Externaltochip downmodesandblockspecificpowerswitches
BTDigital

Figure 4. Typical Power Topology (2 of 2)
CYW43438 6.4mA
1.8V,2.5V,and3.3V WLBBPLL/DFLL
WLOTP3.3V
LDO3P3with
VBAT BackPower VOUT_3P3 WLRF_PA_VDD 480to800mA
Protection WLRFPA(2.4GHz)
LDO_ (Peak450800mA 4.7uF 1uF
VDDBAT5V
200mAAverage) 3.3V 0402 0201
2.5VCapless 6.4mA
LNLDO WLRFADC,AFE,LOGEN,
LNA,NMOSMiniPMULDOs
22 (10mA)
ohm
PlacedinsideWLRadio
Peak:70mA
BT_PAVDD Average:15mA
BTClass1PA
1uF
0201
Powerswitch
Externaltochip
Nopowerswitch
Supplyball
Nodedicatedpowerswitch,butinternalpower
downmodesandblockspecificpowerswitches

2.3 WLAN Power Management

The CYW43438 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize
power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43438 integrated RAM is a high
volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43438 includes an advanced
WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43438 into various power management states
appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and
other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable
them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/
turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever
possible.
The CYW43438 WLAN power states are described as follows:
Active mode All WLAN blocks in the CYW43438 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required
regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
Doze modeThe radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43438 remains powered up in an IDLE state. All
main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This
condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leak-
age current.
Deep-sleep modeMost of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved
and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the
digital core are restored to their pre-deep-sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the
PMU timers.
Power-down modeThe CYW43438 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-
enabling the internal regulators.
2.4 PMU Sequencing

The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and
a table that describes the relationship between resources and the time required to enable and disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by
any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks.
Each resource is in one of the following four states:
enabled
disabled
transition_on
transition_off

The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on
or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements
on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If
the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that
the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either
the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
Computes the required resource set based on requests and the resource dependency table.
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
Compares the request with the current resource status and determines which resources must be enabled or disabled.
Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Power-Off Shutdown

The CYW43438 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW43438 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW43438 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43438, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43438 to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW43438 is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits

The CYW43438 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks,
allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see
Section 22.: Power-Up Sequence and Timing .
Table 2. Power-Up/Power-Down/Reset Control Signals

Signal Description
This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the
BT_REG_ON input to control the internal CYW43438 regulators. When this pin is high, the regulators are enabled
WL_REG_ON and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and
WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that
is enabled by default. It can be disabled through programming.
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal
BT_REG_ON CYW43438 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has
an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming.

3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to
differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation

The CYW43438 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,
including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
WLRF_XTAL_XOP
12 27 pF
WLRF_XTAL_XON
R
12 27 pF
Note: Resistor value determined by crystal drive level.

See reference schematics for details.
The CYW43438 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate
using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced
directly to the CYW43438.
The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase
noise requirements listed in Table 3.
If the TCXO is dedicated to driving the CYW43438, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor
with value ranges from 200 pF to 1000 pF as shown in Figure 6.
Figure 6. Recommended Circuit to Use with an External Dedicated TCXO
200 pF 1000 pF
TCXO WLRF_XTAL_XOP
NC WLRF_XTAL_XON

Table 3. Crystal Oscillator and External Clock Requirements and Performance

External Frequency Ref-
Crystal
Parameter Conditions/Notes erence
Min. Typ. Max. Min. Typ. Max. Units
1
Frequency 37.4 MHz
Crystal load capacitance 12 pF
ESR 60
External crystal must be able to
Drive level 200 W
tolerate this drive level.
Input Impedance (WLRF_X- Resistive 10k 100k
TAL_XOP) Capacitive 7 pF
2
WLRF_XTAL_XOP input voltage AC-coupled analog signal 400 1260 mVp-p
WLRF_XTAL_XOP input low
DC-coupled digital signal 0 0.2 V
level
WLRF_XTAL_XOP input high
DC-coupled digital signal 1.0 1.26 V
level
Frequency tolerance
20 20 20 20 ppm
Initial + over temperature
Duty cycle 37.4 MHz clock 40 50 60 %
Phase Noise3, 4, 5 37.4 MHz clock at 10 kHz offset 129 dBc/Hz
(IEEE 802.11 b/g) 37.4 MHz clock at 100 kHz offset 136 dBc/Hz
Phase Noise 3, 4, 5 37.4 MHz clock at 10 kHz offset 134 dBc/Hz
(IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 100 kHz offset 141 dBc/Hz
Phase Noise3, 4, 5 37.4 MHz clock at 10 kHz offset 140 dBc/Hz
(256-QAM) 37.4 MHz clock at 100 kHz offset 147 dBc/Hz
1. The frequency step size is approximately 80 Hz. The CYW43438 does not auto-detect the reference clock frequency; the frequency is
specified in the software and/or NVRAM file.
2. To use 256-QAM, a 800 mV minimum voltage is required.
3. For a clock reference other than 37.4 MHz, 20 log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in
MHz.
4. Phase noise is assumed flat above 100 kHz.
5. The CYW43438 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.

3.3 External 32.768 kHz Low-Power Oscillator

The CYW43438 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 4.
Note: The CYW43438 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.
To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Table 4. External 32.768 kHz Sleep-Clock Specifications

Parameter LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy 200 ppm
Duty cycle 3070 %
Input signal amplitude 2003300 mV, p-p
Signal type Square wave or sine wave
>100 k
Input impedance1
<5 pF
Clock jitter <10,000 ppm
1. When power is applied or switched off.

4. WLAN System Interfaces

4.1 SDIO v2.0
The CYW43438 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed
4-bit mode (50 MHz clocks200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal
notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within
the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 18 for details.
Three functions are supported:
Function 0 standard SDIO function. The maximum block size is 32 bytes.
Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.
Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode SD 1-Bit Mode gSPI Mode

DATA0 Data line 0 DATA Data line DO Data output
DATA1 Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt
DATA2 Data line 2 NC Not used NC Not used
DATA3 Data line 3 NC Not used CS Card select
CLK Clock CLK Clock SCLK Clock
CMD Command line CMD Command line DI Data input
Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
CMD
SDHost CYW43438
DAT[3:0]
Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
SDHost CYW43438
DATA
IRQ

4.2 Generic SPI Mode

In addition to the full SDIO mode, the CYW43438 includes the option of using the simplified generic SPI (gSPI) interface/protocol.
Characteristics of the gSPI mode include:
Up to 50 MHz operation
Fixed delays for responses and data from the device
Alignment to host gSPI frames (16 or 32 bits)
Up to 2 KB frame size per transfer
Little-endian and big-endian configurations
A configurable active edge for shifting
Packet transfer through DMA for WLAN
gSPI mode is enabled using the strapping option pins. See Table 18 for details.
Figure 9. Signal Connections to SDIO Host (gSPI Mode)
SCLK
DI
DO
SDHost CYW43438
IRQ
CS

4.2.1 SPI Protocol

The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 10 and Figure
11 show the basic write and write/read commands.
Figure 10. gSPI Write Protocol
Figure 11. gSPI Read Protocol

Command Structure
The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 12.
Figure 12. gSPI Command Structure
_SPID
CYW_ I Command Structure
r
31 30 29 28 27 11 10 0
C A F1 F0 Address 17 bits Packet length - 11bits *
* 11h0 = 2048 bytes
ction No: 00 Func 0:

Function 0 All SPI-specific registers
1 Registers and memories belonging to other blocks in the chip (64 bytes max)
01 Func 1:
2 DMA channel 1. WLAN packets up to 2048 bytes.
10 Func 2:
11 Func 3
3: DMA channel 2 (optional). Packets up to 2048 bytes.
Access : 0 Fixed address

1 Incremental address
Command : 0 Read
1 Write
Write
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following
bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.
Write/Read
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge
of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows
data to be ready for the first clock edge without relying on asynchronous delays.
Read
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read
command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval
between the command/address is not fixed.

Status
The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information
about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of
interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus
timing for read/write transactions with and without status notification are as shown in Figure 13 below and Figure 14. See Table 6 for
information on status-field details.
Figure 13. gSPI Signal Timing Without Status
Write CS
SCLK
MOSI C31
C31 C30
C30 C1
C1 C0
C0 D31
D31 D30
D30 D1
D1 D0
D0
Command 32 bits Write Data 16*n bits
Write-Read CS
SCLK
MOSI C31
C31 C30
C30 C0
C0
MISO D31
D31 D30
D30 D1
D1 D0
D0
Response
Command Read Data 16*n bits
32 bits Delay
Read CS
SCLK
MOSI C31
C31 C30
C30 C0
C0
MISO D31
D31 D30
D30 D0
D0
Command Response Read Data
32 bits Delay 16*n bits

Figure 14. gSPI Signal Timing with Status (Response Delay = 0)
W r it e CS
SCLK
MOSI CC3311 CC11 CC00 DD3311 DD11 DD00
M IS O SS3311 SS11 SS00
C o m m a n d 3 2 b its W rite D a ta 1 6 * n b its S ta tu s 3 2 b its
W r it e - R e a d CS
SCLK
MOSI CC3311 CC00
M IS O DD3311 DD11 DD00 SS3311 SS00
C o m m a n d 3 2 b its R e a d D a ta 1 6 * n b its S ta tu s 3 2 b its
R ead CS
SC LK
MOSI CC3311 CC00
M IS O DD3311 DD11 DD00 SS3311 SS00
C o m m a n d 3 2 b its R e a d D a ta 1 6 * n b its S ta tu s 3 2 b its
Table 6. gSPI Status Field Details

Bit Name Description
0 Data not available The requested read data is not available.
1 Underflow FIFO underflow occurred due to current (F2, F3) read command.
2 Overflow FIFO overflow occurred due to current (F1, F2, F3) write command.
3 F2 interrupt F2 channel interrupt.
5 F2 RX ready F2 FIFO is ready to receive data (FIFO empty).
7 Reserved
8 F2 packet available Packet is available/ready in F2 TX FIFO.
9:19 F2 packet length Length of packet available in F2 FIFO
4.2.2 gSPI Host-Device Handshake

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN
register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43438 is ready for data transfer. The
device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for
waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to
pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the
interrupt and then take necessary actions.

4.2.3 Boot-Up Sequence

After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command
to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register
content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg
0x00 bit 7). Wake-up WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal
frequency.
For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available,
the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive
interrupt is issued to the host. This indicates device awake/ready status. See Table 7 for information on gSPI registers.
In Table 7, the following notation is used for register access:
R: Readable from host and CPU
W: Writable from host
U: Writable from CPU
Table 7. gSPI Registers

Address Register Bit Access Default Description
0: 16-bit word length
Word length 0 R/W/U 0
1: 32-bit word length
0: Little endian
Endianess 1 R/W/U 0
1: Big endian
0: Normal mode. Sample on SPICLK rising edge, output
on falling edge.
High-speed mode 4 R/W/U 1
x0000 1: High-speed mode. Sample and output on rising edge
of SPICLK (default).
0: Interrupt active polarity is low.
Interrupt polarity 5 R/W/U 1
1: Interrupt active polarity is high (default).
A write of 1 denotes a wake-up command from host to
Wake-up 7 R/W 0 device. This will be followed by an F2 interrupt from the
gSPI device to host, indicating device awake status.
0: No status sent to host after a read/write.
Status enable 0 R/W 1
1: Status sent to host after a read/write.
x0002
0: Do not interrupt if status is sent.
Interrupt with status 1 R/W 0
1: Interrupt host even if status is sent.
x0003 Reserved
Requested data not available. Cleared by writing a 1 to
0 R/W 0
this location.
1 R 0 F2/F3 FIFO underflow from the last read.
x0004 Interrupt register 2 R 0 F2/F3 FIFO overflow from the last write.
5 R 0 F2 packet available
6 R 0 F3 packet available
7 R 0 F1 overflow from the last write.
5 R 0 F1 Interrupt
x0005 Interrupt register 6 R 0 F2 Interrupt
7 R 0 F3 Interrupt
Interrupt enable Particular interrupt is enabled if a corresponding bit is
x0006, x0007 15:0 R/W/U 16'hE0E7
register set.
x0008 to x000B Status register 31:0 R 32'h0000 Same as status bit definitions

Table 7. gSPI Registers (Cont.)

Address Register Bit Access Default Description
0 R 1 F1 enabled
x000C, x000D F1 info. register 1 R 0 F1 ready for data transfer
13:2 R/U 12'h40 F1 maximum packet size
0 R/U 1 F2 enabled
x000E, x000F F2 info. register 1 R 0 F2 ready for data transfer
15:2 R/U 14'h800 F2 maximum packet size
This register contains a predefined pattern, which the
Test-Read only 32'hFEEDB
x0014 to x0017 31:0 R host can read to determine if the gSPI interface is
register EAD
working properly.
This is a dummy register where the host can write some
32'h000000
x0018 to x001B TestR/W register 31:0 R/W/U pattern and read it back to determine if the gSPI interface
00
is working properly.
Individual response delays for F0, F1, F2, and F3. The
0x1D = 4,
Response delay value of the registers is the number of byte delays that
x001C to x001F 7:0 R/W other
registers are introduced before data is shifted out of the gSPI
registers = 0
interface during host reads.
Figure 15 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-on reset (POR)
evoked by the WL_REG_ON signal. After initial power-up, the WL_REG_ON signal can be held low to disable the CYW43438 or
pulsed low to induce a subsequent reset.
Note: The CYW43438 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after
VDDC and VDDIO have both passed the 0.6V threshold.

Figure 15. WLAN Boot-Up Sequence
VBAT Ramptimefrom0Vto4.3V>40s
0.6V
VDDIO
>2SleepClockcycles
WL_REG_ON
<1.5ms
VDDC
(frominternalPMU) <3ms
InternalPOR
AfterafixeddelayfollowinginternalPORgoinghigh ,
<50ms
thedevicerespondstohostF0(address0x14)reads.
Devicerequestsareferenceclock.
1
15 ms 1
After15ms thereferenceclock
isassumedtobeup.Accessto
PLLregistersispossible.
SPIHostInteraction:
HostpollsF0(address0x14)untilitreads
apredefinedpattern.
Hostsetswakeupwlanbit
1
andwaits15ms ,the
1
maximumtimefor After15 ms,thehost
referenceclockavailability. programsthePLLregistersto
setthecrystalfrequency.
WL_IRQ ChipactiveinterruptisassertedafterthePLLlocks.
Hostdownloads
code.
1
Thiswaittimeisprogrammableinsleepclockincrementsfrom1to255(30usto15ms).

5. Wireless LAN MAC and PHY

5.1 MAC Features
The CYW43438 WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The
salient features are listed below:
Transmission and reception of aggregated MPDUs (A-MPDU).
Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP
operation.
Support for immediate ACK and Block-ACK policies.
Interframe space timing support, including RIFS.
Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.
Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.
Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.
Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.
Support for coexistence with Bluetooth and other external radios.
Programmable independent basic service set (IBSS) or infrastructure basic service set functionality
Statistics counters for MIB support.
5.1.1 MAC Description

The CYW43438 WLAN MAC is designed to support high throughput operation with low-power consumption. It does so without
compromising on Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several
power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing
synchronization. The architecture diagram of the MAC is shown in Figure 16.
Figure 16. WLAN MAC Architecture
EmbeddedCPUInterface
HostRegisters,DMAEngines
PMQ TXFIFO RXFIFO PSM

32KB 10KB PSM
UCODE
Memory
IFS
Backoff,BTCX
WEP
TSF WEP,TKIP,AES
SHM
BUS
IHR
NAV BUS
SharedMemory
TXE RXE 6KB
EXT IHR
TXAMPDU RXAMPDU
MAC PHYInterface

The following sections provide an overview of the important modules in the MAC.
PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to
implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predom-
inant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which
allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving
IEEE 802.11 specifications.
The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data
store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad
memory (similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal,
or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as
well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP,
and WPA2 AES-CCMP.
Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies
the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and
compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also
supported.
TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames
in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the
appropriate time determined by the channel access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic
streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule
a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a
precise timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames
from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The
decrypted data is stored in the RX FIFO.
The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria
such as receiver address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.

IFS
The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple
back-off engines required to support prioritized access to the medium as specified by WMM.
The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).
The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission.
In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-
saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized
by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer
expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the
TSF is synchronized to the network.
The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon trans-
mission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon
and probe response frames in order to maintain synchronization with the network.
The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration
field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.
MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming
interface, which can be controlled either by the host or the PSM to configure and control the PHY.
5.2 PHY Description

The CYW43438 WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity
supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.
The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments.
It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed
to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition
and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY
carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks with Bluetooth coexistence.

5.2.1 PHY Features

Supports the IEEE 802.11b/g/n single-stream standards.
Explicit IEEE 802.11n transmit beamforming.
Supports optional Greenfield mode in TX and RX.
Tx and Rx LDPC for improved range and power efficiency.
Supports IEEE 802.11h/d for worldwide operation.
Algorithms achieving low power, enhanced sensitivity, range, and reliability.
Algorithms to maximize throughput performance in the presence of Bluetooth signals.
Automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications.
Closed-loop transmit power control.
Designed to meet FCC and other regulatory requirements.
Support for 2.4 GHz Broadcom TurboQAM data rates and 20 MHz channel bandwidth.
Figure 17. WLAN PHY Block Diagram
CCK/DSSS
Filters Demodulate
Frequency
and
andTiming Descramble
Radio
Synch OFDM Viterbi and
Comp
Demodulate Decoder Deframe
CarrierSense,
AGC,andRx
Radio FSM Buffers FFT/IFFT MAC
Control Interface
AFE
Block
and
Radio
Modulation
TxFSM andCoding
Frameand
Scramble
Filtersand Modulate/
PAComp
RadioComp Spread
COEX
The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the PHY performs a full
calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate
for any temperature related drift, thus maintaining high-performance over time. A closed-loop transmit control algorithm maintains the
output power at its required level and can control TX power on a per-packet basis.

6. WLAN Radio Subsystem

The CYW43438 includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It
is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements
to the radio design include shared TX/RX baseband filters and high immunity to supply noise.
Figure 18 shows the radio functional block diagram.
Figure 18. Radio Functional Block Diagram
WLDAC
WLTXLPF
WLPA WLPGA WLDAC
WLTXGMixer WLTXLPF
Voltage
WLANBB
Regulators
WLRF_2G_RF
4~6nH
Recommend
Q=40
10pF WLADC
WLRXLPF
WLRF_2G_eLG
SLNA WLGLNA12 WLADC
WLRXGMixer WLRXLPF
Gm WLATX CLB
WLARX WLLOGEN WLPLL
BTLNAGM WLGTX
WLGRX
SharedXO
BTRX BTLOGEN BTPLL

BTTX
LPO/ExtLPO/RCAL
BTADC
BTRXLPF
BTLNALoad BTADC
BTRXMixer BTRXLPF BTBB BTFM

BTPA
BTDAC
BTDAC
BTTXMixer BTTXLPF

6.1 Receive Path

The CYW43438 has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure
reliable operation in the noisy 2.4 GHz ISM band.
6.2 Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable
of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PA is supplied
by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power
control is integrated.
6.3 Calibration
The CYW43438 features dynamic on-chip calibration, eliminating process variation across components. This enables the CYW43438
to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration
routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter calibration
for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R calibration,
and VCO calibration are performed on-chip.

7. Bluetooth + FM Subsystem Overview

The Broadcom CYW43438 is a Bluetooth 4.1-compliant, baseband processor and 2.4 GHz transceiver with an integrated FM/RDS/
RBDS receiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint,
power consumption, and system cost of a Bluetooth plus FM radio solution.
The CYW43438 is the optimal solution for any Bluetooth voice and/or data application that also requires an FM radio receiver. The
Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed UART and PCM interface for audio. The
FM subsystem supports the HCI control interface as well as PCMand stereo analog interfaces. The CYW43438 incorporates all
Bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume.
The CYW43438 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone
temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the
standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, NFC, and cellular radios.
The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.
7.1 Features
Major Bluetooth features of the CYW43438 include:

Supports key features of upcoming Bluetooth standards
Fully supports Bluetooth Core Specification version 4.1 plus enhanced data rate (EDR) features:
Adaptive Frequency Hopping (AFH)
Quality of Service (QoS)
Extended Synchronous Connections (eSCO)voice connections
Fast connect (interlaced page and inquiry scans)
Secure Simple Pairing (SSP)
Sniff Subrating (SSR)
Encryption Pause Resume (EPR)
Extended Inquiry Response (EIR)
Link Supervision Timeout (LST)
UART baud rates up to 4 Mbps

Supports all Bluetooth 4.1 packet types
Supports maximum Bluetooth data rates over HCI UART
Multipoint operation with up to seven active slaves
Maximum of seven simultaneous active ACL links
Maximum of three simultaneous active SCO and eSCO connections with scatternet support
Trigger Beacon fast connect (TBFC)

Narrowband and wideband packet loss concealment
Scatternet operation with up to four active piconets with background scan and support for scatter mode
High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see Host
Controller Power Management )
Channel-quality driven data rate and packet type selection
Standard Bluetooth test modes
Extended radio and production test mode features
Full support for power savings modes
Bluetooth clock request
Bluetooth standard sniff
Deep-sleep modes and software regulator shutdown
TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used
during power save mode for better timing accuracy.

Major FM Radio features include:

65 MHz to 108 MHz FM bands supported (US, Europe, and Japan)
FM subsystem control using the Bluetooth HCI interface
FM subsystem operates from reference clock inputs.
Improved audio interface capabilities with full-featured bidirectional PCM and stereo analog output.
FM Receiver-Specific Features Include:

Excellent FM radio performance with 1 V sensitivity for 26 dB (S+N)/N
Signal-dependent stereo/mono blending
Signal dependent soft mute
Auto search and tuning modes
Audio silence detection
RSSI and IF frequency status indicators
RDS and RBDS demodulator and decoder with filter and buffering functions
Automatic frequency jump
7.2 Bluetooth Radio

The CYW43438 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the
requirements to provide the highest communication link quality of service.
7.2.1 Transmit
The CYW43438 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block
and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path has signal filters, an I/Q upconverter, an output
power amplifier, and RF filters. The transmitter path also incorporates /4DQPSK for 2 Mbps and 8DPSK for 3 Mbps to support
EDR. The transmitter section is compatible with the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted
to provide Bluetooth Class 1 or Class 2 operation.
7.2.2 Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4DQPSK, and 8DPSK signal. The fully
digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much
more stable than direct VCO modulation schemes.
7.2.3 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-
synchronization algorithm.
7.2.4 Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides
greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external
filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-
cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near-thermal noise levels
for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)
block to keep the absolute output power variation within a tight range across process, voltage, and temperature.
7.2.5 Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation
enables the CYW43438 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the
Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.

7.2.6 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
7.2.7 Receiver Signal Strength Indicator

The radio portion of the CYW43438 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller
can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
7.2.8 Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43438 uses an
internal RF and IF loop filter.
7.2.9 Calibration
The CYW43438 radio transceiver features an automated calibration scheme that is self contained in the radio. No user interaction is
required during normal operation or during manufacturing to optimize performance. Calibration optimizes the performance of all the
major blocks within the radio to within 2% of optimal conditions, including filter gain and phase characteristics, matching between key
components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transpar-
ently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and
heats during normal operation in its environment.

8. Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages
data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these
functions, it independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase the reliability and security of data
before sending and receiving it over the air:
Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),
data decryption, and data dewhitening in the receiver.
Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
8.1 Bluetooth 4.1 Features

The BBC supports all Bluetooth 4.1 features, with the following benefits:
Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation.
Low energy physical layer
Low energy link layer
Enhancements to HCI for low energy
Low energy direct test mode
128 AES-CCM secure connection for both BT and BLE
Note: The CYW43438 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power
consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate
devices, such as sensors and remote controls.
8.2 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer contains the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth link
controller.
Major states:
Standby
Connection
Substates:
Page
Page Scan
Inquiry
Inquiry Scan
Sniff
BLE Adv
BLE Scan/Initiation

8.3 Test Mode Support

The CYW43438 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0.
This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW43438 also supports enhanced testing features to simplify RF debugging
and qualification as well as type-approval testing. These features include:
Fixed f8requency carrier-wave (unmodulated) transmission
Simplifies some type-approval measurements (Japan)
Aids in transmitter performance analysis
Fixed frequency constant receiver mode

Receiver output directed to an I/O pin
Allows for direct BER measurements using standard RF test equipment
Facilitates spurious emissions testing for receive mode
Fixed frequency constant transmission

Eight-bit fixed pattern or PRBS-9
Enables modulated signal measurements with standard RF test equipment
8.4 Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through
power management registers or packet handling in the baseband core. The power management functions provided by the CYW43438
are:
RF Power Management
Host Controller Power Management
BBC Power Management
FM Power Management
8.4.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver. The transceiver then processes the power-down functions accordingly.
8.4.2 Host Controller Power Management

When running in UART mode, the CYW43438 can be configured so that dedicated signals are used for power management
handshaking between the CYW43438 and the host. The basic power saving functions supported by those handshaking signals include
the standard Bluetooth defined power savings modes and standby modes of operation.
Table 8 describes the power-control handshake signals used with the UART interface.
Table 8. Power Control Pin Description
Signal Type Description
Bluetooth device wake-up signal: Signal from the host to the CYW43438 indicating that the host
requires attention.
BT_DEV_WAKE I Asserted: The Bluetooth device must wake up or remain awake.
Deasserted: The Bluetooth device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
Host wake-up signal. Signal from the CYW43438 to the host indicating that the CYW43438
requires attention.
BT_HOST_WAKE O Asserted: Host device must wake up or remain awake.
Deasserted: Host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
The CYW43438 asserts CLK_REQ when Bluetooth or WLAN directs the host to turn on the
reference clock. The CLK_REQ polarity is active-high. Add an external 100 k pull-down resistor
CLK_REQ O
to ensure the signal is deasserted when the CYW43438 powers up or resets when VDDIO is
present.
Note: Pad function Control Register is set to 0 for these pins.

Figure 19. Startup Signaling Sequence
LPO
VDDIO HostIOsunconfigured
HostIOsconfigured
HostResetX T1
BT_GPIO_0
(BT_DEV_WAKE)
T2
BTHIOsunconfigured BTHIOsconfigured
BT_REG_ON
BT_GPIO_1
(BT_HOST_WAKE) T3
Hostsidedrives
BT_UART_CTS_N thislinelow
BTHdevicedrivesthis
BT_UART_RTS_N T4 linelowindicating
transportisready
CLK_REQ_OUT T5 Driven
Notes: Pulled
T1isthetimeforhosttosettleitsIOsafterareset.
T2isthetimeforhosttodriveBT_REG_ONhighaftertheHostIOsareconfigured.
T3isthetimeforBTH(Bluetooth)devicetosettleitsIOsafteraresetandreferenceclocksettlingtimehas
elapsed.
T4isthetimeforBTHdevicetodriveBT_UART_RTS_NlowafterthehostdrivesBT_UART_CTS_Nlow.This
assumestheBTHdevicehasalreadycompletedinitialization.
T5isthetimeforBTHdevicetodriveCLK_REQ_OUThighafterBT_REG_ONgoeshigh.Notethispinisusedfor
designsthatuseanexternalreferenceclocksourcefromtheHost.ThispinisirrelevantforCrystalreference
clockbaseddesignswheretheBTHdevicegeneratesitsownreferenceclockfromanexternalcrystalconnected
toitsoscillatorcircuit.
TimingdiagramassumesVBATispresent.

8.4.3 BBC Power Management

The following are low-power operations for the BBC:
Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.
Bluetooth-specified low-power connection modes: sniff and hold. While in these modes, the CYW43438 runs on the low-power
oscillator and wakes up after a predefined time period.
A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational.
When the CYW43438 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This
allows the CYW43438 to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/
O-connected devices.
During the low-power shut-down state, provided VDDIO remains applied to the CYW43438, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on digital signals in the system and enables the CYW43438 to be fully integrated in an embedded device to take full
advantage of the lowest power-saving modes.
Two CYW43438 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not
have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the
CYW43438 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about
its state from the time before it was powered down.
8.4.4 FM Power Management

The CYW43438 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The FM
subsystem power management scheme operates in conjunction with the Bluetooth RF and BBC subsystems. The FM block does not
have a low power state, it is either on or off.
8.4.5 Wideband Speech

The CYW43438 provides support for wideband speech (WBS) technology. The CYW43438 can perform subband-codec (SBC), as
well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus.
8.4.6 Packet Loss Concealment

Packet Loss Concealment (PLC) improves the apparent audio quality for systems with marginal link performance. Bluetooth messages
are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several
ways:
Fill in zeros.
Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).
Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat).
These techniques cause distortion and popping in the audio stream. The CYW43438 uses a proprietary waveform extension algorithm
to provide dramatic improvement in the audio quality. Figure 20 and Figure 21 show audio waveforms with and without Packet Loss
Concealment. Broadcom PLC/BEC algorithms also support wideband speech.
Figure 20. CVSD Decoder Output Waveform Without PLC
Packet losses causes ramp-down

Figure 21. CVSD Decoder Output Waveform After Applying PLC
8.4.7 Codec Encoding

The CYW43438 can support SBC and mSBC encoding and decoding for wideband speech.
8.4.8 Multiple Simultaneous A2DP Audio Streams

The CYW43438 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a
user to share his or her music (or any audio stream) with a friend.
8.4.9 FM Over Bluetooth

FM Over Bluetooth enables the CYW43438 to stream data from FM over Bluetooth without requiring the host to be awake. This can
significantly extend battery life for usage cases where someone is listening to FM radio on a Bluetooth headset.
8.5 Adaptive Frequency Hopping

The CYW43438 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map
selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop
map.
8.6 Advanced Bluetooth/WLAN Coexistence

The CYW43438 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution.
These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including appli-
cations such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo.
Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also
supported. The CYW43438 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna
applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior performance versus
implementations that need to arbitrate between Bluetooth and WLAN reception.
The CYW43438 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexis-
tence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement.
The CYW43438 also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual
interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with
Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate
detection and elimination of interferers (including non-WLAN 2.4 GHz interference).
The Bluetooth AFH classification is also enhanced by the WLAN cores channel information.
8.7 Fast Connection (Interlaced Page and Inquiry Scans)

The CYW43438 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection
times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures.

9. Microprocessor and Memory Unit for Bluetooth

The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG
interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI).
The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM
for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same
device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches
may be downloaded from the host to the CYW43438 through the UART transports.
9.1 RAM, ROM, and Patch Memory

The CYW43438 Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and
patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory
is used for bug fixes and feature additions to ROM memory code.
9.2 Reset
The CYW43438 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out
of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.

10. Bluetooth Peripheral Transport Unit

10.1 PCM Interface
The CYW43438 supports two independent PCM interfaces. The PCM interface on the CYW43438 can connect to linear PCM codec
devices in master or slave mode. In master mode, the CYW43438 generates the PCM_CLK and PCM_SYNC signals, and in slave
mode, these signals are provided by another master on the PCM interface and are inputs to the CYW43438. The configuration of the
PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.
10.1.1 Slot Mapping

The CYW43438 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or
1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
10.1.2 Frame Synchronization

The CYW43438 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization
mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
10.1.3 Data Formatting

The CYW43438 may be configured to generate and accept several different data formats. For conventional narrowband speech mode,
the CYW43438 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various
data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a
programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first.
10.1.4 Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM
bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-
bit samples, resulting in a 64 kbps bit rate. The CYW43438 also supports slave transparent mode using a proprietary rate-matching
scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.

10.1.5 Multiplexed Bluetooth and FM over PCM

In this mode of operation, the CYW43438 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing
the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The data stream format
contains three channels: a Bluetooth channel followed by two FM channels (audio left and right). In this mode of operation, the bus
data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. To accomplish this, the Bluetooth data is
repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the
beginning of the frame.
To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This
mode of operation is only supported when the Bluetooth host is the master. Figure 22 shows the operation of the multiplexed transport
with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To
change between modes of operation, the transport must be halted and restarted in the new configuration.
Figure 22. Functional Multiplex Data Diagram
1Frame
BTSCO1RX BTSCO2RX BTSCO3RX
PCM_OUT FMright FMleft
BTSCO1TX BTSCO2TX BTSCO3TX
PCM_IN FMright FMleft
PCM_SYNC
CLK
PCM_CLK
16bitsperSCOframe 16bitsperframe 16bitsperframe
EachSCOchannelduplicatesthedata6times.
EachWBSframeduplicatesthedata3timesperframe.

10.1.6 PCM Interface Timing

Short Frame Sync, Master Mode
Figure 23. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2 3
PCM_BCLK
PCM_SYNC
PCM_OUT HighImpedance
5
6 7
PCM_IN
Table 9. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No. Characteristics Minimum Typical Maximum Unit
1 PCM bit clock frequency 12 MHz
2 PCM bit clock low 41 ns
3 PCM bit clock high 41 ns
4 PCM_SYNC delay 0 25 ns
5 PCM_OUT delay 0 25 ns
6 PCM_IN setup 8 ns
7 PCM_IN hold 8 ns
Delay from rising edge of PCM_BCLK during last bit period to
8 0 25 ns
PCM_OUT becoming high impedance

Short Frame Sync, Slave Mode

Figure 24. PCM Timing Diagram (Short Frame Sync, Slave Mode)
1
2 3
PCM_BCLK
4
5
PCM_SYNC
PCM_OUT HighImpedance
6
7 8
PCM_IN
Table 10. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
4 PCM_SYNC setup 8 ns
5 PCM_SYNC hold 8 ns
7 PCM_IN setup 8 ns
8 PCM_IN hold 8 ns
9 0 25 ns

Long Frame Sync, Master Mode

Figure 25. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2 3
PCM_BCLK
PCM_SYNC
PCM_OUT Bit0 Bit1 HighImpedance

5
6 7
PCM_IN Bit0 Bit1
Table 11. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
4 PCM_SYNC delay 0 25 ns
6 PCM_IN setup 8 ns
7 PCM_IN hold 8 ns
8 0 25 ns

Long Frame Sync, Slave Mode

Figure 26. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
2 3
PCM_BCLK
4
5
PCM_SYNC
PCM_OUT Bit0 HIGHIMPEDANCE

Bit1
6
7 8
PCM_IN Bit0 Bit1
Table 12. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
4 PCM_SYNC setup 8 ns
5 PCM_SYNC hold 8 ns
7 PCM_IN setup 8 ns
8 PCM_IN hold 8 ns
9 0 25 ns

10.2 UART Interface

The CYW43438 shares a single UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with
adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a
baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.
The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through
the Advanced High Performance Bus (AHB) interface through either DMA or the CPU. The UART supports the Bluetooth 4.1 UART
HCI specification: H4 and H5. The default baud rate is 115.2 Kbaud.
The UART supports the 3-wire H5 UART transport as described in the Bluetooth specification (Three-wire UART Transport Layer).
Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals.
The CYW43438 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP).
It can also perform a wake-on activity function. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.
Normally, the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection, and
the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included
through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43438 UARTs
operate correctly with the host UART as long as the combined baud rate error of the two devices is within 2% (see Table 13).
Table 13. Example of Common Baud Rates

Desired Rate Actual Rate Error (%)
4000000 4000000 0.00
3692000 3692308 0.01
3000000 3000000 0.00
2000000 2000000 0.00
1500000 1500000 0.00
1444444 1454544 0.70
921600 923077 0.16
460800 461538 0.16
230400 230796 0.17
115200 115385 0.16
57600 57692 0.16
38400 38400 0.00
28800 28846 0.16
19200 19200 0.00
14400 14423 0.16
9600 9600 0.00
UART timing is defined in Figure 27 and Table 14.

Figure 27. UART Timing
UART_CTS_N
1 2
UART_TXD
MidpointofSTOPbit MidpointofSTOPbit
UART_RXD
3
UART_RTS_N
Table 14. UART Timing Specifications

1 Delay time, UART_CTS_N low to UART_TXD valid 1.5 Bit periods
Setup time, UART_CTS_N high before midpoint
2 0.5 Bit periods
of stop bit
3 Delay time, midpoint of stop bit to UART_RTS_N high 0.5 Bit periods

11. FM Receiver Subsystem

11.1 FM Radio
The CYW43438 includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from 65 MHz to 108 MHz.
The receiver is controlled through commands on the HCI. FM received audio is available as a stereo analog output or in digital form
through PCM. The FM radio operates from the external clock reference.
11.2 Digital FM Audio Interfaces

The FM audio can be transmitted via the PCM pins, and the sampling rate is programmable. The CYW43438 supports a three-wire
PCM interface in either a master or slave configuration. The master or slave configuration is selected using vendor specific commands
over the HCI interface. In addition, multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master
mode, the clock rate is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
In slave mode, clock rates up to 3.072 MHz are supported.
11.3 Analog FM Audio Interfaces

The demodulated FM audio signal is available as line-level analog stereo output, generated by twin internal high SNR audio DACs.
11.4 FM Over Bluetooth

The CYW43438 can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS, or A2DP. For all link
types, after a link has been established, the host processor can enter sleep mode while the CYW43438 streams FM audio to the
remote Bluetooth device, thus minimizing system current consumption.
11.5 eSCO
In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is sent through the Bluetooth eSCO link
to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo.
11.6 Wideband Speech Link

In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is sent through the Bluetooth wideband
speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo.
11.7 A2DP
In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a remote Bluetooth
device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP lite stack is implemented in the
CYW43438 to support this use case, which eliminates the need to route the SBC-encoded audio back to the host to create the A2DP
packets.
11.8 Autotune and Search Algorithms

The CYW43438 supports a number of FM search and tune functions, allowing the host to implement many convenient user functions
by accessing the Broadcom FM stack.
Tune to PlayAllows the FM receiver to be programmed to a specific frequency.
Search for SNR > ThresholdChecks the power level of the available channel and the estimated SNR of the channel to help
achieve precise control of the expected sound quality for the selected FM channel. Specifically, the host can adjust its SNR require-
ments to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels.
Alternate Frequency JumpAllows the FM receiver to automatically jump to an alternate FM channel that carries the same infor-
mation, but has a better SNR. For example, when traveling, a user may pass through a region where a number of channels carry
the same station. When the user passes from one area to the next, the FM receiver can automatically switch to another channel
with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station.

11.9 Audio Features

A number of features are implemented in the CYW43438 to provide the best possible audio experience for the user.
Mono/Stereo Blend or SwitchThe CYW43438 provides automatic control of the stereo or mono settings based on the FM signal
carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio SNR based on the FM channel condition. Two
modes of operation are supported:
Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a wide range of input C/N. The
amount of separation is fully programmable. In Figure 28, the separation is programmed to maintain a minimum 50 dB SNR across
the blend range.
Switch: In this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality.
The stereo-to-mono switch point and the mono-to-stereo switch points are fully programmable to provide the desired amount of
audio SNR. In Figure 29, the switch point is programmed to switch to mono to maintain a 40 dB SNR.
Figure 28. Blending and Switching Usage
AudioSNR(dB)
In p u tC / N (d B )
Figure 29. Blending and Switching Separation

ChannelSeparation(dB)
InputC/N(dB)

Soft MuteImproves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents
a blast of static to the user. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An
example mute characteristic is shown in Figure 30.
Figure 30. Soft Muting Characteristic
AudioGain(dB)
InputC/N(dB)
High CutA programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output
audio signal. Like the soft mute circuit, it is fully programmable to provide any amount of high cut based on the FM signal C/N.
Audio Pause DetectThe FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when
the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide
alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the
audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection.
Automatic Antenna TuningThe CYW43438 has an on-chip automatic antenna tuning network. When used with a single off-chip
inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength
for the desired frequency. The high-Q nature of this matching network simultaneously provides out-of-band blocking protection as
well as a reduction of radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external
wire antennas.

11.10 RDS/RBDS
The CYW43438 integrates a RDS/RBDS modem, the decoder includes programmable filtering and buffering functions. The RDS/
RBDS data can be read out through the HCI interface.
In addition, the RDS/RBDS receive functionality supports the following:
Block decoding, error correction, and synchronization
A flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible
to set up the CYW43438 such that synchronization is achieved when a minimum of two good blocks (error free) are decoded in
sequence. The number of good blocks required for sync is programmable.)
Storage capability up to 126 blocks of RDS data
Full or partial block-B match detection with host interruption
Audio pause detection with programmable parameters
Program Identification (PI) code detection with host interruption
Automatic frequency jumping
Block-E filtering
Soft muting
Signal dependent mono/stereo blending

12. CPU and Global Functions

12.1 WLAN CPU and Memory Subsystem
The CYW43438 includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a
low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the
Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI.
At 0.19 W/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/W. It supports integrated sleep modes.
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced
silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-
M3 supports extensive debug features including real-time tracing of program execution.
On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.
12.2 One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is
read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC
address, can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package. Documentation on the OTP development process is available on the Broadcom customer
support portal (http://www.broadcom.com/support).
12.3 GPIO Interface

Five general purpose I/O (GPIO) pins are available on the CYW43438 that can be used to connect to various external devices.
GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.
They can also be programmed to have internal pull-up or pull-down resistors.
GPIO_0 is normally used as a WL_HOST_WAKE signal.
The CYW43438 supports a 2-wire coexistence configuration using GPIO_1 and GPIO_2.

12.4 External Coexistence Interface

The CYW43438 supports a 2-wire coexistence interface to enable signaling between the device and an external colocated wireless
device in order to manage wireless medium sharing for optimal performance. The external colocated device can be any of the following
ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration.
Figure 31 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:
GPIO_1: WLAN_SECI_TX output to an LTE IC.
GPIO_2: WLAN_SECI_RX input from an LTE IC.
Figure 31. 2-Wire Coexistence Interface to an LTE IC
GPIO_1 WLAN_SECI_TX
UART_IN
WLAN GPIO_2 WLAN_SECI_RX
UART_OUT
Coexistence
Interface
BT/FM
CYW43438 LTE/IC
Notes:
ORingtogenerateISM_RX_PRIORITYforERCX_TXCONForBT_RX_PRIORITYisachievedby
settingtheGPIOmaskregistersappropriately.
WLAN_SECI_OUTandWLAN_SECI_INaremultiplexedontheGPIOs.
See Figure 27 and Table 14: UART Timing Specifications for UART timing.
12.5 JTAG Interface

The CYW43438 supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB
assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary
debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins
by means of test points or a header on all PCB designs.
12.6 UART Interface

One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI
pin, and UART_TX is available on the JTAG_TDO pin.
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the
CYW43438 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It
is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 8 in each direction.

13. WLAN Software Architecture

13.1 Host Software Architecture
The host driver (DHD) provides a transparent connection between the host operating system and the CYW43438 media (for example,
WLAN) by presenting a network driver interface to the host operating system and communicating with the CYW43438 over an
interface-specific bus (SPI, SDIO, and so on) to:
Forward transmit and receive frames between the host network stack and the CYW43438 device.
Pass control requests from the host to the CYW43438 device, returning the CYW43438 device responses.
The driver communicates with the CYW43438 over the bus using a control channel and a data channel to pass control messages and
data messages. The actual message format is based on the BDC protocol.
13.2 Device Software Architecture

The wireless device, protocol, and bus drivers are run on the embedded ARM processor using a Broadcom-defined operating system
called HNDRTE, which transfers data over a propriety Broadcom format over the SDIO/SPI interface between the host and device
(BDC/LMAC). The data portion of the format consists of IEEE 802.11 frames wrapped in a Broadcom encapsulation. The host archi-
tecture provides all missing functionality between a network device and the Broadcom device interface. The host can also be
customized to provide functionality between the Broadcom device interface and a full network device interface.
This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus
each host-initiated bus operation contains an explicit device target addressand does not natively support a higher-level data frame
concept. Broadcom has implemented a hardware/software message encapsulation scheme that ignores the bus operation code
address and prefixes each frame with a 4-byte length tag for framing. The device presents a packet-level interface over which data,
control, and asynchronous event (from the device) packets are supported.
The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver.
If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet
received from the device medium follows the same path in the reverse direction. If the packets are control packets, the protocol header
is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTL API of the wireless driver is called to configure
the wireless device. The microcode running in the D11 core processes all time-critical tasks.
13.2.1 Remote Downloader

When the CYW43438 powers up, the DHD initializes and downloads the firmware to run in the device.
Figure 32. WLAN Software Architecture
DHD Host Driver
SPI/SDIO
BDC/LMAC Protocol
Wireless Device Driver
D11 Core
13.3 Wireless Configuration Utility

The device driver that supports the Broadcom IEEE 802.11 family of wireless solutions provides an input/output control (IOCTL)
interface for making advanced configuration settings. The IOCTL interface makes it possible to make settings that are normally not
possible when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The utility uses IOCTLs to
query or set a number of different driver/chip operating properties.

14. Pinout and Signal Descriptions

14.1 Ball Map
Figure 33 shows the 63-ball WLBGA ball map.
Figure 33. 63-Ball WLBGA Ball Map (Bottom View)
A B C D E F G H J K L M
B T_UA RT_ B T_ D E V _ B T_HOS T_ B T_V C O_ B T_ IF _ W L RF _ W LRF _ W LRF _

1 F M _ RF _IN B T_P A V D D 1
RX D WAKE WAKE VDD VDD 2 G_eLG 2G_RF P A _V D D
W LRF _ W L RF _ V D
B T_ UA RT_ B T_ UA RT_ F M _RF _ B TF M _ B TF M _ W L RF _ W LRF _P A _
2 F M _OUT1 F M _ OUT2 B T_ IF _V S S GE NE RA L_ D_ 2
TX D C TS _N VDD P L L_ V D D P LL _V S S L NA _GND GND
GND 1P 35
B T_UA RT_ F M _RF _ V S B T_ V C O_ V W LRF _GP I W L RF _V C W LRF _ X TA

3 VDDC 3
RTS _N S SS O O_ GND L_V D D 1P 2
B T_P C M _ B T_P C M _I W LRF _ A F E W LRF _ X TA W LRF _ X TA

4 VSSC VDDC 4
OUT N _ GND L_ GND L_ X OP
B T_ P C M _ B T_P C M _ W LRF _ X TA
5 L P O_IN VSSC GP IO_2 5
C LK S YNC L_ X ON
P M U_A V S V OUT_C LD V OUT_L NL B T_ RE G_ O W C C _V D D I W L_ RE G_ S D IO_

6 S R_V LX GP IO_1 GP IO_0 S D IO_C M D C LK _RE Q 6
S O DO N O ON D A TA _0
S R_ LD O_V D D 1 L D O_ S D IO_ S D IO_ S D IO_

7 S R_P V S S V OUT_3 P 3 S D IO_C LK 7
V D D B A T5V P5 V D D B A T5 V D A TA _1 D A TA _3 D A TA _ 2
A B C D E F G H J K L M

14.2 WLBGA Ball List in Ball Number Order with X-Y Coordinates
Table 15 provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0)
center.
Table 15. CYW43438 WLBGA Ball List Ordered By Ball Number

Ball Number Ball Name X Coordinate Y Coordinate
A1 BT_UART_RXD 1200.006 2199.996
A2 BT_UART_TXD 799.992 2199.996
A5 BT_PCM_CLK or BT_I2S_CLK 399.996 2199.996
A6 SR_VLX 799.992 2199.978
A7 SR_PVSS 1199.988 2199.978
B1 BT_DEV_WAKE 1200.006 1800
B2 BT_UART_CTS_N 799.992 1800
B4 BT_PCM_OUT or BT_I2S_DO 0 1800
B5 BT_PCM_SYNC or BT_I2S_WS 399.996 1800
B6 PMU_AVSS 799.992 1799.982
B7 SR_VBAT5V 1199.988 1799.982
C1 BT_HOST_WAKE 1200.006 1399.995
C2 FM_OUT1 799.992 1399.986
C3 BT_UART_RTS_N 399.996 1399.995
C4 BT_PCM_IN or BT_I2S_DI 0 1399.995
C6 VOUT_CLDO 799.992 1399.986
C7 LDO_VDD15V 1199.988 1399.986
D2 FM_OUT2 799.992 999.99
D3 VDDC 399.996 999.999
D4 VSSC 0 999.999
D6 VOUT_LNLDO 799.992 999.99
E1 FM_RF_IN 1199.988 599.994
E2 FM_RF_VDD 799.992 599.994
E3 FM_RF_VSS 399.996 599.994
E6 BT_REG_ON 799.992 599.994
E7 VOUT_3P3 1199.988 599.994
F1 BT_VCO_VDD 1199.988 199.998
F2 BTFM_PLL_VDD 799.992 199.998
F5 LPO_IN 399.996 199.998
F6 WCC_VDDIO 800.001 199.998
F7 LDO_VBAT5V 1199.988 199.998
G1 BT_IF_VDD 1199.988 199.998
G2 BTFM_PLL_VSS 799.992 199.998
G4 VDDC 0 199.998
G6 WL_REG_ON 800.001 199.998

Table 15. CYW43438 WLBGA Ball List Ordered By Ball Number (Cont.)
Ball Number Ball Name X Coordinate Y Coordinate
H1 BT_PAVDD 1199.988 599.994
H2 BT_IF_VSS 799.992 599.994
H3 BT_VCO_VSS 399.996 599.994
H4 WLRF_AFE_GND 0 599.994
H6 GPIO_1 800.001 599.994
H7 SDIO_DATA_1 1200.006 599.994
J1 WLRF_2G_eLG 1199.988 999.99
J2 WLRF_LNA_GND 799.992 999.99
J3 WLRF_GPIO 399.996 999.99
J5 VSSC 399.996 999.999
J6 GPIO_0 800.001 999.999
J7 SDIO_DATA_3 1200.006 999.999
K1 WLRF_2G_RF 1199.988 1399.986
K2 WLRF_GENERAL_GND 799.992 1399.986
K6 SDIO_DATA_0 800.001 1399.995
L2 WLRF_PA_GND 799.992 1799.982
L3 WLRF_VCO_GND 399.996 1799.982
L4 WLRF_XTAL_GND 0 1799.982
L5 GPIO_2 399.996 1799.991
L6 SDIO_CMD 800.001 1799.991
L7 SDIO_DATA_2 1200.006 1799.991
M1 WLRF_PA_VDD 1199.988 2199.978
M2 WLRF_VDD_1P35 799.992 2199.978
M3 WLRF_XTAL_VDD1P2 399.996 2199.978
M4 WLRF_XTAL_XOP 0 2199.978
M5 WLRF_XTAL_XON 399.996 2199.978
M6 CLK_REQ 800.001 2199.996
M7 SDIO_CLK 1200.006 2199.996

14.3 WLBGA Ball List Ordered By Ball Name

Table 16 provides the ball numbers and names in ball name order.
Table 16. CYW43438 WLBGA Ball List Ordered By Ball Name
Ball Name Ball Number Ball Name Ball Number
BT_DEV_WAKE B1 SDIO_CMD L6
BT_HOST_WAKE C1 SDIO_DATA_0 K6
BT_IF_VDD G1 SDIO_DATA_1 H7
BT_IF_VSS H2 SDIO_DATA_2 L7
BT_PAVDD H1 SDIO_DATA_3 J7
BT_PCM_CLK or BT_I2S_CLK A5 SR_PVSS A7
BT_PCM_IN or BT_I2S_DI C4 SR_VDDBAT5V B7
BT_PCM_OUT or BT_I2S_DO B4 SR_VLX A6
BT_PCM_SYNC or BT_I2S_WS B5 VDDC D3
BT_REG_ON E6 VDDC G4
BT_UART_CTS_N B2 VOUT_3P3 E7
BT_UART_RTS_N C3 VOUT_CLDO C6
BT_UART_RXD A1 VOUT_LNLDO D6
BT_UART_TXD A2 VSSC D4
BT_VCO_VDD F1 VSSC J5
BT_VCO_VSS H3 WCC_VDDIO F6
BTFM_PLL_VDD F2 WL_REG_ON G6
BTFM_PLL_VSS G2 WLRF_2G_eLG J1
CLK_REQ M6 WLRF_2G_RF K1
FM_OUT1 C2 WLRF_AFE_GND H4
FM_OUT2 D2 WLRF_GENERAL_GND K2
FM_RF_IN E1 WLRF_GPIO J3
FM_RF_VDD E2 WLRF_LNA_GND J2
FM_RF_VSS E3 WLRF_PA_GND L2
GPIO_0 J6 WLRF_PA_VDD M1
GPIO_1 H6 WLRF_VCO_GND L3
GPIO_2 L5 WLRF_VDD_1P35 M2
LDO_VDD1P5 C7 WLRF_XTAL_GND L4
LDO_VDDBAT5V F7 WLRF_XTAL_VDD1P2 M3
LPO_IN F5 WLRF_XTAL_XON M5
PMU_AVSS B6 WLRF_XTAL_XOP M4
SDIO_CLK M7

14.4 Signal Descriptions

Table 17 provides the WLBGA package signal descriptions.
Table 17. WLBGA Signal Descriptions

WLBGA Type
Signal Name Description
Ball
RF Signal Interface
WLRF_2G_RF K1 O 2.4 GHz BT and WLAN RF output port
SDIO Bus Interface
SDIO_CLK M7 I SDIO clock input
SDIO_CMD L6 I/O SDIO command line
SDIO_DATA_0 K6 I/O SDIO data line 0
SDIO_DATA_1 H7 I/O SDIO data line 1.
SDIO_DATA_2 L7 I/O SDIO data line 2. Also used as a strapping option (see Table 20).
SDIO_DATA_3 J7 I/O SDIO data line 3
Note: Per Section 6 of the SDIO specification, 10 to 100 k pull-ups are required on the four DATA lines and the CMD line. This
requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host
pull-ups.
WLAN GPIO Interface
WLRF_GPIO J3 I/O Test pin. Not connected in normal operation.
Clocks
WLRF_XTAL_XON M5 O XTAL oscillator output
WLRF_XTAL_XOP M4 I XTAL oscillator input
External system clock requestUsed when the system clock is not provided
CLK_REQ M6 O by a dedicated crystal (for example, when a shared TCXO is used). Asserted
to indicate to the host that the clock is required. Shared by BT, and WLAN.
External sleep clock input (32.768 kHz). If an external 32.768 kHz clock
LPO_IN F5 I cannot be provided, pull this pin low. However, BLE will be always on and
cannot go to deep sleep.
FM Receiver
FM_OUT1 C2 O FM analog output 1
FM_OUT2 D2 O FM analog output 2
FM_RF_IN E1 I FM radio antenna port
FM_RF_VDD E2 I FM power supply
Bluetooth PCM
BT_PCM_CLK or BT_I2S_CLK A5 I/O PCM or I2S clock; can be master (output) or slave (input)
BT_PCM_IN or BT_I2S_DI C4 I PCM or I2S data input sensing
BT_PCM_OUT or BT_I2S_DO B4 O PCM or I2S data output
BT_PCM_SYNC or BT_I2S_WS B5 I/O PCM SYNC or I2S_WS; can be master (output) or slave (input)

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Type
Ball
Bluetooth UART and Wake
UART clear-to-send. Active-low clear-to-send signal for the HCI UART
BT_UART_CTS_N B2 I
interface.
UART request-to-send. Active-low request-to-send signal for the HCI UART
BT_UART_RTS_N C3 O
interface.
BT_UART_RXD A1 I UART serial input. Serial data input for the HCI UART interface.
BT_UART_TXD A2 O UART serial output. Serial data output for the HCI UART interface.
BT_DEV_WAKE B1 I/O DEV_WAKE or general-purpose I/O signal.
BT_HOST_WAKE C1 I/O HOST_WAKE or general-purpose I/O signal.
Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality.
Through software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows:
PCM_CLK on the UART_RTS_N pin
PCM_OUT on the UART_CTS_N pin
PCM_SYNC on the BT_HOST_WAKE pin
PCM_IN on the BT_DEV_WAKE pin
In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire
UART Transport.
Miscellaneous
Used by PMU to power up or power down the internal regulators used by the
WLAN section. Also, when deasserted, this pin holds the WLAN section in
WL_REG_ON G6 I
reset. This pin has an internal 200 k pull-down resistor that is enabled by
default. It can be disabled through programming.
Used by PMU to power up or power down the internal regulators used by the
Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/
BT_REG_ON E6 I
FM section in reset. This pin has an internal 200 k pull-down resistor that
is enabled by default. It can be disabled through programming.
Programmable GPIO pins. This pin becomes an output pin when it is used
GPIO_0 J6 I/O
as WLAN_HOST_WAKE/out-of-band signal.
GPIO_1 H6 I/O Programmable GPIO pins
GPIO_2 L5 I/O Programmable GPIO pins
WLRF_2G_eLG J1 I Connect to an external inductor. See the reference schematic for details.
Integrated Voltage Regulators
SR_VDDBAT5V B7 I SR VBAT input power supply
CBUCK switching regulator output. See Table 36 for details of the inductor
SR_VLX A6 O
and capacitor required on this output.
LDO_VDDBAT5V F7 I LDO VBAT
LDO_VDD1P5 C7 I LNLDO input
VOUT_LNLDO D6 O Output of low-noise LNLDO
VOUT_CLDO C6 O Output of core LDO
Bluetooth Power Supplies
BT_PAVDD H1 I Bluetooth PA power supply
BT_IF_VDD G1 I Bluetooth IF block power supply
BTFM_PLL_VDD F2 I Bluetooth RF PLL power supply
BT_VCO_VDD F1 I Bluetooth RF power supply

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Type
Ball
Power Supplies
WLRF_XTAL_VDD1P2 M3 I XTAL oscillator supply
WLRF_PA_VDD M1 I Power amplifier supply
WCC_VDDIO F6 I VDDIO input supply. Connect to VDDIO.
WLRF_VDD_1P35 M2 I LNLDO input supply
VDDC D3, G4 I Core supply for WLAN and BT.
VOUT_3P3 E7 O 3.3V output supply. See the reference schematic for details.
Ground
BT_IF_VSS H2 I 1.2V Bluetooth IF block ground
BTFM_PLL_VSS G2 I Bluetooth/FM RF PLL ground
BT_VCO_VSS H3 I 1.2V Bluetooth RF ground
FM_RF_VSS E3 I FM RF ground
PMU_AVSS B6 I Quiet ground
SR_PVSS A7 I Switcher-power ground
VSSC D4, J5 I Core ground for WLAN and BT
WLRF_AFE_GND H4 I AFE ground
WLRF_LNA_GND J2 I 2.4 GHz internal LNA ground
WLRF_GENERAL_GND K2 I Miscellaneous RF ground
WLRF_PA_GND L2 I 2.4 GHz PA ground
WLRF_VCO_GND L3 I VCO/LO generator ground
WLRF_XTAL_GND L4 I XTAL ground

14.5 WLAN GPIO Signals and Strapping Options

The pins listed in Table 18 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using
a 10 k resistor or less.
Note: Refer to the reference board schematics for more information.
Table 18. GPIO Functions and Strapping Options

Pin Name WLBGA Pin # Default Function Description
WLAN host interface This pin selects the WLAN host interface mode. The
SDIO_DATA_2 L7 1
select default is SDIO. For gSPI, pull this pin low.
14.6 Chip Debug Options

The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and
SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2.
Table 19 shows the debug options of the device.
Table 19. Chip Debug Options

JTAG_SEL GPIO_2 GPIO_1 Function SDIO I/O Pad Function BT PCM I/O Pad Function
0 0 0 Normal mode SDIO BT PCM
0 0 1 JTAG over SDIO JTAG BT PCM
0 1 0 JTAG over BT PCM SDIO JTAG
0 1 1 SWD over GPIO_1/GPIO_2 SDIO BT PCM

14.7 I/O States

The following notations are used in Table 20:
I: Input signal
O: Output signal
I/O: Input/Output signal
PU = Pulled up
PD = Pulled down
NoPull = Neither pulled up nor pulled down
Table 20. I/O States1

(WL_REG_ON
Out-of-Reset; =1 Out-of-Reset;
Power-Down3 (WL_REG_ON = 1; BT_REG_ON = (WL_REG_ON = 0
Keeper Low Power State/Sleep WL_REG_ON = 0 BT_REG_ON = 0) VDDIOs BT_REG_ON = 1)
2
Name I/O Active Mode (All Power Present) BT_REG_ON = 0 Do Not Care) Present VDDIOs Present Power Rail
WL_REG_ON I N Input; PD (pull-down Input; PD (pull-down can Input; PD (of 200K) Input; PD (200k) Input; PD
can be disabled) be disabled) (200k)
BT_REG_ON I N Input; PD (pull down Input; PD (pull down can Input; PD (of 200K) Input; PD (200k) Input; PD Input; PD (200k)
can be disabled) be disabled) (200k)
CLK_REQ I/O Y Open drain or push-pull Open drain or push-pull PD Open drain, active Open drain, Open drain, WCC_VDDIO
(programmable). Active (programmable). Active high. active high. active high.
high. high
BT_HOST_ I/O Y I/O; PU, PD, NoPull I/O; PU, PD, NoPull High-Z, NoPull Input, PD Output, Drive low WCC_VDDIO
WAKE (programmable) (programmable)
BT_DEV_WAKE I/O Y I/O; PU, PD, NoPull Input; PU, PD, NoPull High-Z, NoPull Input, PD Input, PD WCC_VDDIO
(programmable) (programmable)
BT_UART_CTS I Y Input; NoPull Input; NoPull High-Z, NoPull Input; PU Input, NoPull WCC_VDDIO
BT_UART_RTS O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Output, NoPull WCC_VDDIO
BT_UART_RXD I Y Input; PU Input; NoPull High-Z, NoPull Input; PU Input, NoPull WCC_VDDIO
BT_UART_TXD O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Output, NoPull WCC_VDDIO
SDIO_DATA_0 I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> SDIO MODE -> PU SDIO MODE -> Input; PU WCC_VDDIO
NoPull NoPull
NoPull NoPull
NoPull NoPull

Table 20. I/O States1 (Cont.)

(WL_REG_ON
Out-of-Reset; =1 Out-of-Reset;
3
Power-Down (WL_REG_ON = 1; BT_REG_ON = (WL_REG_ON = 0
Keeper Low Power State/Sleep WL_REG_ON = 0 BT_REG_ON = 0) VDDIOs BT_REG_ON = 1)
2
Name I/O Active Mode (All Power Present) BT_REG_ON = 0 Do Not Care) Present VDDIOs Present Power Rail
NoPull NoPull
SDIO_CMD I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> SDIO MODE -> PU SDIO MODE -> Input; PU WCC_VDDIO
NoPull NoPull
SDIO_CLK I N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> SDIO MODE -> SDIO MODE -> Input WCC_VDDIO
NoPull NoPull NoPull
BT_PCM_CLK I/O Y Input; NoPull4 Input; NoPull4 High-Z, NoPull Input, PD Input, PD WCC_VDDIO
BT_PCM_IN I/O Y Input; NoPull4 Input; NoPull4 High-Z, NoPull Input, PD Input, PD WCC_VDDIO
BT_PCM_OUT I/O Y Input; NoPull4 Input; NoPull4 High-Z, NoPull Input, PD Input, PD WCC_VDDIO
BT_PCM_SYNC I/O Y Input; NoPull4 Input; NoPull4 High-Z, NoPull Input, PD Input, PD WCC_VDDIO
JTAG_SEL I Y PD PD High-Z, NoPull Input, PD PD Input, PD WCC_VDDIO

GPIO_0 I/O Y TBD Active mode High-Z, NoPull5 Input, SDIO OOB Int, Active mode Input, NoPull WCC_VDDIO
NoPull
GPIO_1 I/O Y TBD Active mode High-Z, NoPull5 Input, PD Active mode Input, Strap, PD WCC_VDDIO
GPIO_2 I/O Y TBD Active mode High-Z, NoPull5 Input, GCI GPIO[7], Active mode Input, Strap, NoPull WCC_VDDIO
NoPull
1. PU = pulled up, PD = pulled down.
2. N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in the power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should
be driven to prevent leakage due to floating pad, for example, SDIO_CLK.
3. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied.
4. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input.
5. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down.

15. DC Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
15.1 Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 21 indicate levels where permanent damage to the device can occur, even if these
limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT,
operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 21. Absolute Maximum Ratings

Rating Symbol Value Unit
1
DC supply for VBAT and PA driver supply VBAT 0.5 to +6.0 V
DC supply voltage for digital I/O VDDIO 0.5 to 3.9 V
DC supply voltage for RF switch I/Os VDDIO_RF 0.5 to 3.9 V
DC input supply voltage for CLDO and LNLDO 0.5 to 1.575 V
DC supply voltage for RF analog VDDRF 0.5 to 1.32 V
DC supply voltage for core VDDC 0.5 to 1.32 V
Maximum undershoot voltage for I/O2 Vundershoot 0.5 V
2
Maximum overshoot voltage for I/O Vovershoot VDDIO + 0.5 V
Maximum junction temperature Tj 125 C
1. Continuous operation at 6.0V is supported.
2. Duration not to exceed 25% of the duty cycle.
15.2 Environmental Ratings

The environmental ratings are shown in Table 22.
Table 22. Environmental Ratings
Characteristic Value Units Conditions/Comments
1
Ambient temperature (TA) 30 to +70C C Operation
Storage temperature 40 to +125C C
Less than 60 % Storage
Relative humidity
Less than 85 % Operation
1. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details).
15.3 Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 23. ESD Specifications

Pin Type Symbol Condition ESD Rating Unit
ESD, Handling Reference:
Human Body Model Contact Discharge per
NQY00083, Section 3.4, ESD_HAND_HBM 1000 V
JEDEC EID/JESD22-A114
Group D9, Table B
Machine Model (MM) ESD_HAND_MM Machine Model Contact 30 V
Charged Device Model Contact Discharge per
CDM ESD_HAND_CDM 300 V
JEDEC EIA/JESD22-C101

15.4 Recommended Operating Conditions and DC Characteristics

Functional operation is not guaranteed outside the limits shown in Table 24, and operation outside these limits for extended periods
can adversely affect long-term reliability of the device.
Table 24. Recommended Operating Conditions and DC Characteristics
Value
Element Symbol Unit
Minimum Typical Maximum
DC supply voltage for VBAT VBAT 3.01 4.82 V
DC supply voltage for core VDD 1.14 1.2 1.26 V
DC supply voltage for RF blocks in chip VDDRF 1.14 1.2 1.26 V
VDDIO,
DC supply voltage for digital I/O 1.71 3.63 V
VDDIO_SD
DC supply voltage for RF switch I/Os VDDIO_RF 3.13 3.3 3.46 V
External TSSI input TSSI 0.15 0.95 V
Internal POR threshold Vth_POR 0.4 0.7 V
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage VIH 1.27 V
Input low voltage VIL 0.58 V
Output high voltage @ 2 mA VOH 1.40 V
Output low voltage @ 2 mA VOL 0.45 V
For VDDIO_SD = 3.3V:
Input high voltage VIH 0.625 VDDIO V
0.25
Input low voltage VIL V
VDDIO
Output high voltage @ 2 mA VOH 0.75 VDDIO V
0.125
Output low voltage @ 2 mA VOL V
VDDIO
Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage VIH 0.65 VDDIO V
0.35
Input low voltage VIL V
VDDIO
Output high voltage @ 2 mA VOH VDDIO 0.45 V
For VDDIO = 3.3V:
Input high voltage VIH 2.00 V
Input low voltage VIL 0.80 V
Output low Voltage @ 2 mA VOL 0.40 V

Table 24. Recommended Operating Conditions and DC Characteristics (Cont.)
Value
Element Symbol Unit
Minimum Typical Maximum
RF Switch Control Output Pins3
For VDDIO_RF = 3.3V:
Input capacitance CIN 5 pF
1. The CYW43438 is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only
for 3.2V < VBAT < 4.8V.
2. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed.
3. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

16. WLAN RF Specifications

The CYW43438 includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF
characteristics of the 2.4 GHz radio.
Note: Values in this data sheet are design goals and may change based on device characterization results.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in
Table 22: Environmental Ratings and Table 24: Recommended Operating Conditions and DC Characteristics . Functional
operation outside these limits is not guaranteed.
Typical values apply for the following conditions:
VBAT = 3.6V.
Ambient temperature +25C.
Figure 34. RF Port Location
Chip
C2
Port
TX Filter
10 pF Antenna
CYW43438
C1 Port
L1
RX
4.7 nH
10 pF
Note: All specifications apply at the chip port unless otherwise specified.
16.1 2.4 GHz Band General RF Specifications
Table 25. 2.4 GHz Band General RF Specifications

Item Condition Minimum Typical Maximum Unit
TX/RX switch time Including TX ramp down 5 s
RX/TX switch time Including TX ramp up 2 s

16.2 WLAN 2.4 GHz Receiver Performance Specifications

Note: Unless otherwise specified, the specifications in Table 26 are measured at the chip port (for the location of the chip port, see
Figure 34
Table 26. WLAN 2.4 GHz Receiver Performance Specifications
Parameter Condition/Notes Minimum Typical Maximum Unit

Frequency range 2400 2500 MHz
1 Mbps DSSS 97.5 99.5 dBm
RX sensitivity (8% PER for 1024 2 Mbps DSSS 93.5 95.5 dBm
octet PSDU) 1 5.5 Mbps DSSS 91.5 93.5 dBm
11 Mbps DSSS 88.5 90.5 dBm
6 Mbps OFDM 91.5 93.5 dBm
RX sensitivity (10% PER for 18 Mbps OFDM 85.5 87.5 dBm
1000 octet PSDU) at WLAN RF
port 1 24 Mbps OFDM 82.5 84.5 dBm
20 MHz channel spacing for all MCS rates (Mixed mode)
256-QAM, R = 5/6 67.5 69.5 dBm
256-QAM, R = 3/4 69.5 71.5 dBm
MCS7 71.5 73.5 dBm
RX sensitivity MCS6 73.5 75.5 dBm
(10% PER for 4096 octet PSDU).
MCS5 74.5 76.5 dBm
Defined for default parameters:
Mixed mode, 800 ns GI. MCS4 79.5 81.5 dBm
MCS3 82.5 84.5 dBm
MCS2 84.5 86.5 dBm
MCS1 86.5 88.5 dBm
MCS0 90.5 92.5 dBm

Table 26. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

704716 MHz LTE 13 dBm
776794 MHz CDMA2000 13.5 dBm
815830 MHz LTE 12.5 dBm
816824 MHz CDMA2000 13.5 dBm
816849 MHz LTE 11.5 dBm
824849 MHz WCDMA 11.5 dBm
824849 MHz CDMA2000 12.5 dBm
824849 MHz LTE 11.5 dBm
824849 MHz GSM850 8 dBm
830845 MHz LTE 11.5 dBm
832862 MHz LTE 11.5 dBm
880915 MHz WCDMA 10 dBm
880915 MHz E-GSM 9 dBm
Blocking level for 3 dB RX sensi-
tivity degradation (without 17101755 MHz LTE 14.5 dBm
external filtering).2
17101755 MHz CDMA2000 14.5 dBm
17101785 MHz LTE 14.5 dBm
17101785 MHz GSM1800 12.5 dBm
18501910 MHz GSM1900 11.5 dBm
18501910 MHz CDMA2000 16 dBm
18501910 MHz LTE 16 dBm
18501915 MHz LTE 17 dBm
19201980 MHz CDMA2000 19.5 dBm
19201980 MHz LTE 19.5 dBm
23002400 MHz LTE 44 dBm
25002570 MHz LTE 43 dBm
25702620 MHz LTE 34 dBm
5G WLAN >4 dBm
@ 1, 2 Mbps (8% PER, 1024 octets) 6 dBm
Maximum receive level
@ 5.5, 11 Mbps (8% PER, 1024 octets) 12 dBm
@ 2.4 GHz
@ 654 Mbps (10% PER, 1000 octets) 15.5 dBm

Table 26. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Adjacent channel rejection-
DSSS.
(Difference between interfering
and desired signal [25 MHz 11 Mbps DSSS 70 dBm 35 dB
apart] at 8% PER for 1024 octet
PSDU with desired signal level
as specified in Condition/Notes.)
6 Mbps OFDM 79 dBm 16 dB
Adjacent channel rejection-
OFDM.
(Difference between interfering 18 Mbps OFDM 74 dBm 11 dB
and desired signal (25 MHz
apart) at 10% PER for 10003
octet PSDU with desired signal 36 Mbps OFDM 67 dBm 4 dB
level as specified in Condition/
Notes.)
Range 98 dBm to 75 dBm 3 3 dB
RCPI accuracy4
Range above 75 dBm 5 5 dB
Return loss Zo = 50 across the dynamic range. 10 dB
1. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between 10C and 55C.
2. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose
of this test. It is not intended to indicate any specific usage of each band in any specific country.
3. For 65 Mbps, the size is 4096.
4. The minimum and maximum values shown have a 95% confidence level.

16.3 WLAN 2.4 GHz Transmitter Performance Specifications

Note: Unless otherwise specified, the specifications in Table 26 are measured at the chip port (for the location of the chip port, see
Figure 34).
Table 27. WLAN 2.4 GHz Transmitter Performance Specifications

Frequency range MHz
776794 MHz CDMA2000 167.5 dBm/Hz
869960 MHz CDMAOne, GSM850 163.5 dBm/Hz
14501495 MHz DAB 154.5 dBm/Hz
15701580 MHz GPS 152.5 dBm/Hz
15921610 MHz GLONASS 149.5 dBm/Hz
17101800 MHz DSC-1800-Uplink 145.5 dBm/Hz
18051880 MHz GSM1800 143.5 dBm/Hz
18501910 MHz GSM1900 140.5 dBm/Hz
Transmitted power in cellular and 19101930 MHz TDSCDMA, LTE 138.5 dBm/Hz
WLAN 5G bands (at 21 dBm, 90% duty GSM1900, CDMAOne,
cycle, 1 Mbps CCK).1 19301990 MHz 139 dBm/Hz
WCDMA
20102075 MHz TDSCDMA 127.5 dBm/Hz
21102170 MHz WCDMA 124.5 dBm/Hz
23052370 MHz LTE Band 40 104.5 dBm/Hz
50005900 MHz WLAN 5G 109.5
dBm/
4.85.0 GHz 2nd harmonic 26.5
MHz
Harmonic level (at 21 dBm with 90% dBm/
7.27.5 GHz 3rd harmonic 23.5
duty cycle, 1 Mbps CCK) MHz
dBm/
9.610 GHz 4th harmonic 32.5
MHz
EVM Does Not Exceed
IEEE 802.11b
9 dB 21 dBm
(DSSS/CCK)
OFDM, BPSK 8 dB 20.5 dBm
TX power at the chip port for the OFDM, QPSK 13 dB 20.5 dBm
highest power level setting at 25C, OFDM, 16-QAM 19 dB 20.5 dBm
VBA = 3.6V, and spectral mask and
EVM compliance2, 3 OFDM, 64-QAM
25 dB 18 dBm
(R = 3/4)
OFDM, 64-QAM
27 dB 17.5 dBm
(R = 5/6)
OFDM, 256-QAM
32 dB 15 dBm
(R = 5/6)

Table 27. WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)

TX power control
9 dB
dynamic range
Across full temperature and voltage range.
Closed loop TX power variation at
Applies across 5 to 21 dBm output power 1.5 dB
highest power level setting
range.
Carrier suppression 15 dBc
Gain control step 0.25 dB
Return loss Zo = 50 4 6 dB
EVM degradation 3.5 dB
Output power variation 2 dB
VSWR = 2:1.
ACPR-compliant power
Load pull variation for output power, 15 dBm
level
EVM, and Adjacent Channel Power
Ratio (ACPR) EVM degradation 4 dB
Output power variation 3 dB
VSWR = 3:1.
ACPR-compliant power
15 dBm
level
1. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those
bands.
2. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance.
3. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between 10C and 55C.
16.4 General Spurious Emissions Specifications
Table 28. General Spurious Emissions Specifications

General Spurious Emissions
30 MHz < f < 1 GHz RBW = 100 kHz 99 96 dBm
1 GHz < f < 12.75 GHz RBW = 1 MHz 44 41 dBm
TX emissions
1.8 GHz < f < 1.9 GHz RBW = 1 MHz 68 65 dBm
30 MHz < f < 1 GHz RBW = 100 kHz 99 96 dBm
RX/standby 1 GHz < f < 12.75 GHz RBW = 1 MHz 54 51 dBm
emissions 1.8 GHz < f < 1.9 GHz RBW = 1 MHz 88 85 dBm
Note: The specifications in this table apply at the chip port.

17. Bluetooth RF Specifications

Unless otherwise stated, limit values apply for the conditions specified in Table 22: Environmental Ratings and
Table 24: Recommended Operating Conditions and DC Characteristics . Typical values apply for the following conditions:
VBAT = 3.6V.
Note: All Bluetooth specifications apply at the chip port. For the location of the chip port, see Figure 34: RF Port Location, on page 68
Table 29. Bluetooth Receiver RF Specifications

Parameter Conditions Minimum Typical Maximum Unit
Note: The specifications in this table are measured at the chip output port unless otherwise specified.
General
GFSK, 0.1% BER, 1 Mbps 94 dBm
RX sensitivity /4DQPSK, 0.01% BER, 2 Mbps 96 dBm
8DPSK, 0.01% BER, 3 Mbps 90 dBm
Input IP3 16 dBm
Maximum input at antenna 20 dBm
Interference Performance1
C/I co-channel GFSK, 0.1% BER 11 dB
C/I 1 MHz adjacent channel GFSK, 0.1% BER 0.0 dB
C/I 2 MHz adjacent channel GFSK, 0.1% BER 30 dB
C/I 3 MHz adjacent channel GFSK, 0.1% BER 40 dB
C/I image channel GFSK, 0.1% BER 9 dB
C/I 1 MHz adjacent to image channel GFSK, 0.1% BER 20 dB
C/I co-channel /4DQPSK, 0.1% BER 13 dB
C/I 1 MHz adjacent channel /4DQPSK, 0.1% BER 0.0 dB
C/I 2 MHz adjacent channel /4DQPSK, 0.1% BER 30 dB
C/I 3 MHz adjacent channel /4DQPSK, 0.1% BER 40 dB
C/I image channel /4DQPSK, 0.1% BER 7 dB
C/I 1 MHz adjacent to image channel /4DQPSK, 0.1% BER 20 dB
C/I co-channel 8DPSK, 0.1% BER 21 dB
C/I 1 MHz adjacent channel 8DPSK, 0.1% BER 5.0 dB
C/I 2 MHz adjacent channel 8DPSK, 0.1% BER 25 dB
C/I 3 MHz adjacent channel 8DPSK, 0.1% BER 33 dB
C/I Image channel 8DPSK, 0.1% BER 0.0 dB
C/I 1 MHz adjacent to image channel 8DPSK, 0.1% BER 13 dB
Out-of-Band Blocking Performance (CW)
302000 MHz 0.1% BER 10.0 dBm
20002399 MHz 0.1% BER 27 dBm
24983000 MHz 0.1% BER 27 dBm
3000 MHz12.75 GHz 0.1% BER 10.0 dBm

Table 29. Bluetooth Receiver RF Specifications (Cont.)

Out-of-Band Blocking Performance, Modulated Interferer (LTE)
GFSK (1 Mbps)
2310 MHz LTE band40 TDD 20M BW 20 dBm
2510 MHz LTE band7 FDD 20M BW 24 dBm
/4 DPSK (2 Mbps)
8DPSK (3 Mbps)
Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE)
GFSK (1 Mbps)1
824849 MHz GSM850 12 dBm
17101785 MHz GSM1800 15 dBm
18501910 MHz GSM1900 20 dBm


18801920 MHz TD-SCDMA 18 dBm
20102025 MHz TDSCDMA 18 dBm
/4 DPSK (2 Mbps)1
824849 MHz GSM850 9 dBm
17101785 MHz GSM1800 14 dBm
18501910 MHz GSM1900 15 dBm
1
8DPSK (3 Mbps)
824849 MHz GSM850 11 dBm
17101785 MHz GSM1800 16 dBm
18501910 MHz GSM1900 17 dBm
RX LO Leakage
2.4 GHz band 90.0 80.0 dBm


Spurious Emissions
30 MHz1 GHz 95 62 dBm
112.75 GHz 70 47 dBm
869894 MHz 147 dBm/Hz
925960 MHz 147 dBm/Hz
18051880 MHz 147 dBm/Hz
19301990 MHz 147 dBm/Hz
21102170 MHz 147 dBm/Hz
1. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level.
Table 30. LTE Specifications for Spurious Emissions

Parameter Conditions Typical Unit
25002570 MHz Band 7 147 dBm/Hz
23002400 MHz Band 40 147 dBm/Hz
25702620 MHz Band 38 147 dBm/Hz
25452575 MHz XGP Band 147 dBm/Hz
Table 31. Bluetooth Transmitter RF Specifications1

General
Basic rate (GFSK) TX power at Bluetooth 12.0 dBm
QPSK TX power at Bluetooth 8.0 dBm
8PSK TX power at Bluetooth 8.0 dBm
Power control step 2 4 8 dB
GFSK In-Band Spurious Emissions
20 dBc BW 0.93 1 MHz
EDR In-Band Spurious Emissions
1.0 MHz < |M N| < 1.5 MHz M N = the frequency range for which 38 26.0 dBc
the spurious emission is measured
1.5 MHz < |M N| < 2.5 MHz 31 20.0 dBm
relative to the transmit center
|M N| 2.5 MHz 2
frequency. 43 40.0 dBm
Out-of-Band Spurious Emissions
30 MHz to 1 GHz 36.0 3,4 dBm
4,5,6
1 GHz to 12.75 GHz 30.0 dBm
1.8 GHz to 1.9 GHz 47.0 dBm
5.15 GHz to 5.3 GHz 47.0 dBm
GPS Band Spurious Emissions
Spurious emissions 103 dBm

Table 31. Bluetooth Transmitter RF Specifications1 (Cont.)

Out-of-Band Noise Floor7
65108 MHz FM RX 147 dBm/Hz
776794 MHz CDMA2000 146 dBm/Hz
869960 MHz cdmaOne, GSM850 146 dBm/Hz
925960 MHz E-GSM 146 dBm/Hz
15701580 MHz GPS 146 dBm/Hz
18051880 MHz GSM1800 144 dBm/Hz
19301990 MHz GSM1900, cdmaOne, WCDMA 143 dBm/Hz
21102170 MHz WCDMA 137 dBm/Hz
1. Unless otherwise specified, the specifications in this table apply at the chip output port, and output power specifications are with the
temperature correction algorithm and TSSI enabled.
2. Typically measured at an offset of 3 MHz.
3. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.
4. The spurious emissions during Idle mode are the same as specified in Table 31.
5. Specified at the Bluetooth antenna port.
6. Meets this specification using a front-end band-pass filter.
7. Transmitted power in cellular and FM bands at the Bluetooth antenna port. See Figure 34 for location of the port.
Table 32. LTE Specifications for Out-of-Band Noise Floor

Parameter Conditions Typical Unit
25002570 MHz Band 7 130 dBm/Hz
23002400 MHz Band 40 130 dBm/Hz
25702620 MHz Band 38 130 dBm/Hz
25452575 MHz XGP Band 130 dBm/Hz
Table 33. Local Oscillator Performance

Parameter Minimum Typical Maximum Unit
LO Performance
Lock time 72 s
Initial carrier frequency tolerance 25 75 kHz
Frequency Drift
DH1 packet 8 25 kHz
DH3 packet 8 40 kHz
DH5 packet 8 40 kHz
Drift rate 5 20 kHz/50 s
Frequency Deviation
1
00001111 sequence in payload 140 155 175 kHz
10101010 sequence in payload2 115 140 kHz
Channel spacing 1 MHz
1. This pattern represents an average deviation in payload.
2. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

Table 34. BLE RF Specifications

1
RX sense GFSK, 0.1% BER, 1 Mbps 97 dBm
TX power2 8.5 dBm
Mod Char: delta f1 average 225 255 275 kHz
3
Mod Char: delta f2 max 99.9 %
Mod Char: ratio 0.8 0.95 %
1. The Bluetooth tester is set so that Dirty TX is on.
2. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm.
The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit.
3. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz.

18. FM Receiver Specifications

Unless otherwise stated, limit values apply for the conditions specified inTable 22: Environmental Ratings and
Table 24: Recommended Operating Conditions and DC Characteristics . Typical values apply for the following conditions:
VBAT = 3.6V.
Table 35. FM Receiver Specifications

Parameter Conditions1 Minimum Typical Maximum Units
RF Parameters
2
Operating frequency Frequencies inclusive 65 108 MHz
1 dBV EMF
Sensitivity3 FM only, SNR 26 dB 1.1 V EMF
5 dBV
Measured for 30 dB SNR at audio output.
Signal of interest: 23 dBV EMF (14.1 V EMF).
Receiver adjacent channel
selectivity 3,4 At 200 kHz. 51 dB
At 400 kHz. 62 dB
Intermediate signal-plus-
noise to noise ratio (S + N)/ Vin = 20 dBV (10 V EMF). 45 53 dB
N, stereo3
Blocker level increased until desired at
30 dB SNR.
Intermodulation perfor- Wanted signal: 33 dBV EMF (45 V EMF)
55 dBc
mance3,4 Modulated interferer: At fWanted + 400 kHz and +
4 MHz.
CW interferer: At fWanted + 800 kHz and + 8 MHz.
Vin = 23 dBV EMF (14.1 V EMF).
AM suppression, mono3 AM at 400 Hz with m = 0.3. 40 dB
No A-weighted or any other filtering applied.
RDS
17 dBV EMF
RDS deviation = 1.2 kHz. 7.1 V EMF
RDS sensitivity5,6 11 dBV
13 dBV EMF
RDS deviation = 2 kHz. 4.4 V EMF
7 dBV
Wanted Signal: 33 dBV EMF (45 V EMF),
2 kHz RDS deviation.
Interferer: f = 40 kHz, fmod = 1 kHz.
RDS selectivity6 200 kHz 49 dB
300 kHz 52 dB
400 kHz 52 dB
RF Input
RF input impedance 1.5 k
Antenna tuning cap 2.5 30 pF

Table 35. FM Receiver Specifications (Cont.)

113 dBV EMF
Maximum input
SNR > 26 dB. 446 mV EMF
level3
107 dBV
Local oscillator breakthrough measured on the
55 dBm
reference port.
RF conducted emissions
869894 MHz, 925960 MHz,
90 dBm
18051880 MHz, and 19301990 MHz. GPS.
GSM850, E-GSM (standard); BW = 0.2 MHz.
824849 MHz, 7 dBm
880915 MHz.
GSM 850, E-GSM (edge); BW = 0.2 MHz.
824849 MHz, 0 dBm
880915 MHz.
GSM DCS 1800, PCS 1900 (standard, edge);
BW = 0.2 MHz.
12 dBm
17101785 MHz,
18501910 MHz.
WCDMA: II (I), III (IV,X); BW = 5 MHz.
17101785 MHz (17101755 MHz,
12 dBm
17101770 MHz),
18501980 MHz (19201980 MHz).
WCDMA: V (VI), VIII, XII, XIII, XIV;
RF blocking levels at the BW = 5 MHz.
5 dBm
FM antenna input with a 40 824849 MHz (830840 MHz),
dB SNR (assumes a 50 880915 MHz.
input and excludes spurs)
CDMA2000, CDMA One; BW = 1.25 MHz.
776794 MHz,
0 dBm
824849 MHz,
887925 MHz.
CDMA2000, CDMA One; BW= 1.25 MHz.
17501780 MHz,
12 dBm
18501910 MHz,
19201980 MHz.
Bluetooth; BW = 1 MHz.
11 dBm
24022480 MHz.
LTE, Band 38, Band 40, XGP Band 11 dBm
WLAN-g/b; BW = 20 MHz.
11 dBm
24002483.5 MHz.
WLAN-a; BW = 20 MHz.
6 dBm
49155825 MHz.
Tuning
Frequency step 10 kHz
Single frequency switch in any direction
to a frequency within the 88108 MHz or
Settling time 150 s
7690 MHz bands. Time measured to within 5
kHz of the final frequency.
Total time for an automatic search to
sweep from 88108 MHz or 7690 MHz
Search time 8 sec
(or in the reverse direction) assuming no
channels are found.


General Audio
Audio output level7 14.5 12.5 dBFS
Maximum audio output
0 dBFS
level8
Conditions:
Vin = 66 dBV EMF (2 mV EMF),
DAC audio output level 72 88 mV RMS
f = 22.5 kHz, fmod = 1 kHz,
f Pilot = 6.75 kHz
Maximum DAC audio
333 mV RMS
output level8
Audio DAC output level
1 1 dB
difference9
Left and right AC mute FM input signal fully muted with DAC enabled 60 dB
Left and right hard mute FM input signal fully muted with DAC disabled 80 dB
Soft mute attenuation and Muting is performed dynamically, proportional to the desired FM input signal C/N. The muting charac-
start level teristic is fully programmable. See Audio Features .
Maximum signal plus
noise-to-noise ratio 69 dB
(S + N)/N, mono9
Maximum signal plus
noise-to-noise ratio 64 dB
(S + N)/N, stereo7
Vin = 66 dBV EMF(2 mV EMF):
f = 75 kHz, fmod = 400 Hz. 0.8 %
Total harmonic distortion,
f = 75 kHz, fmod = 1 kHz. 0.8 %
mono
f = 75 kHz, fmod = 3 kHz. 0.8 %
f = 100 kHz, fmod = 1 kHz. 1.0 %
Total harmonic distortion,
f = 67.5 kHz, fmod = 1 kHz, 1.5 %
stereo
f pilot = 6.75 kHz, L = R
Range from 300 Hz to 15 kHz
Audio spurious products9 60 dBc
with respect to a 1 kHz tone.
Audio bandwidth, upper (
15 kHz
3 dB point) Vin = 66 dBV EMF (2 mV EMF)
Audio bandwidth, lower ( f = 8 kHz, for 50 s
20 Hz
3 dB point)
100 Hz to 13 kHz,
Audio in-band ripple Vin = 66 dBV EMF (2 mV EMF), 0.5 0.5 dB
f = 8 kHz, for 50 s.
Deemphasis time constant
With respect to 50 and 75 s. 5 %
tolerance
3 83 dBV EMF
With 1 dB resolution and 5 dB accuracy
RSSI range
at room temperature. 1.41 1.41E+4 V EMF
3 77 dBV


Stereo Decoder
Forced Stereo mode
Stereo channel separation f = 67.5 kHz, fmod = 1 kHz, 44 dB
f Pilot = 6.75 kHz,
R = 0, L = 1
Mono stereo blend and Dynamically proportional to the desired FM input signal C/N. The blending and switching characteristics
switching are fully programmable. See Audio Features .
Pilot suppression 46 dB
f = 75 kHz, fmod = 1 kHz.
Pause Detection
Audio level at which Relative to 1-kHz tone, f = 22.5 kHz.
a pause is detected 4 values in 3 dB steps 21 12 dB
Audio pause
4 values 20 40 ms
duration
1. The following conditions are applied to all relevant tests unless otherwise indicated: Preemphasis and deemphasis of 50 s, R = L for mono,
BAF = 300 Hz to 15 kHz, A-weighted filtering applied.
2. Contact your Broadcom representative for applications operating between 6576 MHz.
3. Signal of interest: f = 22.5 kHz, fmod = 1 kHz.
4. Interferer: f = 22.5 kHz, fmod = 1 kHz.
5. RDS sensitivity numbers are for 87.5108 MHz only.
6. Vin = f = 32 kHz, fmod = 1 kHz, f pilot = 7.5 kHz, and with an interferer for 95% of blocks decoded with no errors after correction, over
a sample of 5000 blocks.
7. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz, f pilot = 6.75 kHz.
8. Vin = 66 dBV EMF (2 mV EMF), f = 100 kHz, fmod = 1 kHz, f pilot = 6.75 kHz.
9. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz.

19. Internal Regulator Electrical Specifications

Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Functional operation is not guaranteed outside of the specification limits provided in this section.
19.1 Core Buck Switching Regulator
Table 36. Core Buck Switching Regulator (CBUCK) Specifications

Specification Notes Min. Typ. Max. Units
1
Input supply voltage (DC) DC voltage range inclusive of disturbances. 2.4 3.6 4.8 V
PWM mode switching frequency CCM, load > 100 mA VBAT = 3.6V. 4 MHz
PWM output current 370 mA
Output current limit 1400 mA
Programmable, 30 mV steps.
Output voltage range 1.2 1.35 1.5 V
Default = 1.35V.
PWM output voltage Includes load and line regulation.
4 4 %
DC accuracy Forced PWM mode.
Measure with 20 MHz bandwidth limit.
Static load, max. ripple based on VBAT = 3.6V,
Vout = 1.35V,
PWM ripple voltage, static 7 20 mVpp
Fsw = 4 MHz, 2.2 H inductor L > 1.05 H, Cap
+ Board total-ESR < 20 m,
Cout > 1.9 F, ESL<200 pH
Peak efficiency at 200 mA load, inductor DCR
PWM mode peak efficiency 85 %
= 200 m, VBAT = 3.6V, VOUT = 1.35V
10 mA load current, inductor DCR = 200 m,
PFM mode efficiency 77 %
VBAT = 3.6V, VOUT = 1.35V
VDDIO already ON and steady.
Start-up time from
Time from REG_ON rising edge to CLDO 400 500 s
power down
reaching 1.2V
0603 size, 2.2 H 20%,
External inductor 2.2 H
DCR = 0.2 25%
Ceramic, X5R, 0402,
External output capacitor 2.02 4.7 103 F
ESR <30 m at 4 MHz, 4.7 F 20%, 10V
For SR_VDDBATP5V pin,
External input capacitor ceramic, X5R, 0603, 0.672 4.7 F
ESR < 30 m at 4 MHz, 4.7 F 20%, 10V
Input supply voltage ramp-up time 0 to 4.3V 40 s
1. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
2. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
3. Total capacitance includes those connected at the far end of the active load.

19.2 3.3V LDO (LDO3P3)
Table 37. LDO3P3 Specifications

Min. = Vo + 0.2V = 3.5V dropout voltage
Input supply voltage, Vin requirement must be met under maximum 3.1 3.6 4.81 V
load for performance specifications.
Output current 0.001 450 mA
Nominal output voltage, Vo Default = 3.3V. 3.3 V
Dropout voltage At max. load. 200 mV
Output voltage DC accuracy Includes line/load regulation. 5 +5 %
Quiescent current No load 66 85 A
Line regulation Vin from (Vo + 0.2V) to 4.8V, max. load 3.5 mV/V
Load regulation load from 1 mA to 450 mA 0.3 mV/mA
Vin Vo + 0.2V,
PSRR Vo = 3.3V, Co = 4.7 F, 20 dB
Max. load, 100 Hz to 100 kHz
LDO turn-on time Chip already powered up. 160 250 s
Ceramic, X5R, 0402,
External output capacitor, Co 1.02 4.7 5.64 F
(ESR: 5 m240 m), 10%, 10V
For SR_VDDBATA5V pin (shared with band
gap) Ceramic, X5R, 0402,
External input capacitor (ESR: 30m-200 m), 10%, 10V. 4.7 F
Not needed if sharing VBAT capacitor 4.7 F
with SR_VDDBATP5V.
1. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
aging.

19.3 CLDO
Table 38. CLDO Specifications

Min. = 1.2 + 0.15V = 1.35V dropout voltage
Input supply voltage, Vin 1.3 1.35 1.5 V
requirement must be met under maximum load.
Output voltage, Vo Programmable in 10 mV steps. Default = 1.2.V 0.95 1.2 1.26 V
Dropout voltage At max. load 150 mV
Output voltage DC accuracy Includes line/load regulation 4 +4 %
No load 13 A
Quiescent current
200 mA load 1.24 mA
Line regulation Vin from (Vo + 0.15V) to 1.5V, maximum load 5 mV/V
Load regulation Load from 1 mA to 300 mA 0.02 0.05 mV/mA
Power down 5 20 A
Leakage current
Bypass mode 1 3 A
PSRR @1 kHz, Vin 1.35V, Co = 4.7 F 20 dB
VDDIO up and steady. Time from the REG_ON rising
Start-up time of PMU edge to the CLDO 700 s
reaching 1.2V.
LDO turn-on time LDO turn-on time when rest of the chip is up. 140 180 s
External output capacitor, Co Total ESR: 5 m240 m 1.11 2.2 F
Only use an external input capacitor at the VDD_LDO
External input capacitor 1 2.2 F
pin if it is not supplied from CBUCK output.
aging.

19.4 LNLDO
Table 39. LNLDO Specifications

Min. VIN = VO + 0.15V = 1.35V
Input supply voltage, Vin (where VO = 1.2V) dropout voltage requirement must be 1.3 1.35 1.5 V
met under maximum load.
Output voltage, Vo Programmable in 25 mV steps.Default = 1.2V 1.1 1.2 1.275 V
Dropout voltage At maximum load 150 mV
Output voltage DC accuracy Includes line/load regulation 4 +4 %
No load 10 12 A
Quiescent current
Max. load 970 990 A
Line regulation Vin from (Vo + 0.15V) to 1.5V, 200 mA load 5 mV/V
Load from 1 mA to 200 mA:
Load regulation 0.025 0.045 mV/mA
Vin (Vo + 0.12V)
Leakage current Power-down, junction temp. = 85C 5 20 A
@30 kHz, 60150 mA load Co = 2.2 F 60
Output noise nV/ Hz
@100 kHz, 60150 mA load Co = 2.2 F 35
PSRR @1 kHz, Vin (Vo + 0.15V), Co = 4.7 F 20 dB
LDO turn-on time LDO turn-on time when rest of chip is up 140 180 s
External output capacitor, Co Total ESR (trace/capacitor): 5 m240 m 0.51 2.2 4.7 F
Only use an external input capacitor at the VDD_LDO pin
External input capacitor if it is not supplied from CBUCK output. Total ESR (trace/ 1 2.2 F
capacitor): 30 m200 m
aging.

20. System Power Consumption

Note: The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise
stated, these values apply for the conditions specified in Table 24: Recommended Operating Conditions and DC Characteristics .
20.1 WLAN Current Consumption

Table 40 shows typical currents consumed by the CYW43438s WLAN section. All values shown are with the Bluetooth core in Reset
mode with Bluetooth and FM off.
20.1.1 2.4 GHz Mode
Table 40. 2.4 GHz Mode WLAN Power Consumption
VBAT = 3.6V, VDDIO = 1.8V, TA 25C

Mode Rate
VBAT (mA) Vio (A)
Sleep Modes
Leakage (OFF) N/A 0.0035 0.08
1
Sleep (idle, unassociated) N/A 0.0058 80
2
Sleep (idle, associated, inter-beacons) Rate 1 0.0058 80
3
IEEE Power Save PM1 DTIM1 (Avg.) Rate 1 1.05 74
IEEE Power Save PM1 DTIM3 (Avg.) 4 Rate 1 0.35 86
3
4
Active Modes
Rx Listen Mode 5 N/A 37 12
Rate 1 39 12
Rate 11 40 12
Rx Active (at 50dBm RSSI) 6
Rate 54 40 12
Rate MCS7 41 12
Rate 1 @ 20 dBm 320 15
Rate 11 @ 18 dBm 290 15
Tx 6
Rate 54 @ 15 dBm 260 15
Rate MCS7 @ 15 dBm 260 15
1. Device is initialized in Sleep mode, but not associated.
2. Device is associated, and then enters Power Save mode (idle between beacons).
3. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).
4. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).
5. Carrier sense (CCA) when no carrier present.
6. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet Engine mode (pseudo-random
data)

20.2 Bluetooth and FM Current Consumption

The Bluetooth, BLE, and FM current consumption measurements are shown in Table 41.
Note:
The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 41.
For FM measurements, the Bluetooth core is in Sleep mode.
The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.
Table 41. Bluetooth BLE and FM Current Consumption

VBAT (VBAT = 3.6V) VDDIO (VDDIO = 1.8V)
Operating Mode Units
Typical Typical
Sleep 6 150 A
Standard 1.28s Inquiry Scan 193 162 A
500 ms Sniff Master 305 172 A
DM1/DH1 Master 23.3 mA
3DH5/3DH5 Master 25.1 mA
SCO HV3 Master 11.8 mA
1
FMRX Analog Audio only 8.6 mA
FMRX Analog Audio + RDS1 8.6 mA
2
BLE Scan 187 164 A
BLE Adv. Unconnectable 1.00 sec 93 163 A
BLE Connected 1 sec 71 163 A
1. In Mono/Stereo blend mode.
2. No devices present. A 1.28 second interval with a scan window of 11.25 ms.

21. Interface Timing and AC Characteristics

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table
22 and Table 24. Functional operation outside of these limits is not guaranteed.
21.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 35 and Table 42.
Figure 35. SDIO Bus Timing (Default Mode)
fP P
tW L tW H
S D IO _ C L K
tTH L tT LH
t IS U t IH
In p u t
O u tp u t
tO D LY tO D LY
(m a x ) (m in )
Table 42. SDIO Bus Timing 1 Parameters (Default Mode)

Parameter Symbol Minimum Typical Maximum Unit
SDIO CLK (All values are referred to minimum VIH and maximum VIL2)
FrequencyData Transfer mode fPP 0 25 MHz
FrequencyIdentification mode fOD 0 400 kHz
Clock low time tWL 10 ns
Clock high time tWH 10 ns
Clock rise time tTLH 10 ns
Clock fall time tTHL 10 ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time tISU 5 ns
Input hold time tIH 5 ns
Outputs: CMD, DAT (referenced to CLK)
Output delay timeData Transfer mode tODLY 0 14 ns
Output delay timeIdentification mode tODLY 0 50 ns
1. Timing is based on CL 40 pF load on command and data.
2. min(Vih) = 0.7 VDDIO and max(Vil) = 0.2 VDDIO.

21.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 36 and Table 43.
Figure 36. SDIO Bus Timing (High-Speed Mode)
fPP
tWL tWH
50% VDD
SDIO_CLK
tTHL tTLH
tISU tIH
Input
Output
tODLY tOH
Table 43. SDIO Bus Timing 1 Parameters (High-Speed Mode)

Parameter Symbol Minimum Typical Maximum Unit
SDIO CLK (all values are referred to minimum VIH and maximum VIL2)
Frequency Data Transfer Mode fPP 0 50 MHz
Frequency Identification Mode fOD 0 400 kHz
Clock low time tWL 7 ns
Clock high time tWH 7 ns
Clock rise time tTLH 3 ns
Clock fall time tTHL 3 ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time tISU 6 ns
Input hold time tIH 2 ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time Data Transfer Mode tODLY 14 ns
Output hold time tOH 2.5 ns
Total system capacitance (each line) CL 40 pF
1. Timing is based on CL 40 pF load on command and data.
2. min(Vih) = 0.7 VDDIO and max(Vil) = 0.2 VDDIO.

21.3 gSPI Signal Timing

The gSPI device always samples data on the rising edge of the clock.
Figure 37. gSPI Timing
T1
T2
T4 T5
T3
SPI_CLK
T6 T7
SPI_DIN
T8 T9
SPI_DOUT
(fallingedge)
Table 44. gSPI Timing Parameters

Parameter Symbol Minimum Maximum Units Note
Clock period T1 20.8 ns Fmax = 50 MHz
Clock high/low T2/T3 (0.45 T1) T4 (0.55 T1) T4 ns
Clock rise/fall time T4/T5 2.5 ns
Setup time, SIMO valid to SPI_CLK active
Input setup time T6 5.0 ns
edge
Hold time, SPI_CLK active edge to SIMO
Input hold time T7 5.0 ns
invalid
Setup time, SOMI valid before SPI_CLK
Output setup time T8 5.0 ns
rising
Hold time, SPI_CLK active edge to SOMI
Output hold time T9 5.0 ns
invalid
CSX to clock1 7.86 ns CSX fall to 1st rising edge
Clock to CSXc ns Last falling edge to CSX high
1. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction)
21.4 JTAG Timing
Table 45. JTAG Timing Characteristics

Output Output
Signal Name Period Setup Hold
Maximum Minimum
TCK 125 ns
TDI 20 ns 0 ns
TMS 20 ns 0 ns
TDO 100 ns 0 ns
JTAG_TRST 250 ns

22. Power-Up Sequence and Timing

22.1 Sequencing of Reset and Regulator Control Signals
The CYW43438 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and
internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the
signals for various operational states (see Figure 38 through Figure 41). The timing values indicated are minimum required values;
longer delays are also acceptable.
Note:
The WL_REG_ON and BT_REG_ON signals are ORed in the CYW43438. The diagrams show both signals going high at the same
time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used
(one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW43438
regulators.
The reset requirements for the Bluetooth core are also applicable for the FM core. In other words, if FM is to be used, then the
Bluetooth core must be enabled.
The CYW43438 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC
and VDDIO have both passed the POR threshold (see Table 24: Recommended Operating Conditions and DC Characteristics ).
Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses.
VBAT and VDDIO should not rise faster than 40 s. VBAT should be up before or at the same time as VDDIO. VDDIO should not
be present first or be held high before VBAT is high.
22.1.1 Description of Control Signals

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the
internal CYW43438 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW43438 regulators. If both the
BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT
section is in reset.
Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles
(where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed,
then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start.

22.1.2 Control Signal Timing Diagrams

Figure 38. WLAN = ON, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT 90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
Figure 39. WLAN = OFF, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT
VDDIO
WL_REG_ON
BT_REG_ON

Figure 40. WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
VBAT 90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
Figure 41. WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
VBAT 90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON

23. Package Information

23.1 Package Thermal Characteristics
Table 46. Package Thermal Characteristics1

Characteristic Value in Still Air
JA (C/W) 54.75
JB (C/W) 15.38
JC (C/W) 7.16
JT (C/W) 0.04
JB (C/W) 14.21
Maximum Junction Temperature Tj (C)2 125
Maximum Power Dissipation (W) 1.2
1. No heat sink, TA = 70C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD517
(101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous dissipation.
2. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting.
23.1.1 Junction Temperature Estimation and PSI Versus Thetajc

Package thermal characterization parameter PSI-JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for this is JC assumes that all the power is dissipated
through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of
the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating
the device junction temperature is as follows:
TJ = TT + P JT
Where:
TJ = junction temperature at steady-state condition, C
TT = package case top center temperature at steady-state condition, C
P = device power dissipation, Watts

JT = package thermal characteristics (no airflow), C/W

24. Mechanical Information

Figure 42 shows the mechanical drawing for the CYW43438 WLBGA package.
Figure 42. 63-Ball WLBGA Mechanical Information

Figure 43. WLBGA Package Keep-Out AreasTop View with the Bumps Facing Down

25. Ordering Information
Table 47. Part Ordering Information

Operating Ambi-
Part Number 1 Package Description ent Temperature
63-ball WLBGA halogen-free package 2.4 GHz single-band WLAN
CYW43438KUBG 30C to +70C
(4.87 mm x 2.87 mm, 0.40 pitch) IEEE 802.11n + BT 4.1 + FMRX
1. Add T to the end of the part number to specify Tape and Reel.
26. Additional Information

26.1 Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used
in Cypress documents, go to: http://www.cypress.com/glossary.
26.2 IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).

Document History
Document Title: CYW43438 Single-Chip IEEE 802.11ac b/g/n MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM
Receiver
Document Number: 002-14796
Orig. of Submission
Revision ECN Description of Change
Change Date
43438-DS100-R
** - - 3/18/2014
Initial release
43438-DS101-R
*A - - 4/07/2014
Refer to the earlier release for detailed revision history.
43438-DS102-R
*B - - 4/18/2014
43438-DS103-R
*C - - 6/09/2014
43438-DS104-R
*D - - 09/05/2014
43438-DS105-R
*E - - 10/03/2014
43438-DS106-R
*F - - 01/12/2015
43438-DS107-R
Updated:
Table 20, I/O States .
Table 23, ESD Specifications .
*G - - 07/01/2015
Table 26, WLAN 2.4 GHz Receiver Performance Specifications .
Table 27, WLAN 2.4 GHz Transmitter Performance Specifications .
Table 35, FM Receiver Specifications .
Table 40, 2.4 GHz Mode WLAN Power Consumption .
43438-DS108-R
Updated:
Figure 3: Typical Power Topology (1 of 2), on page 9 (43438) on page 16
and
*H - - 08/24/2015
Figure 4: Typical Power Topology (2 of 2), on page 10 (43438) on page 16.
Table 3, Crystal Oscillator and External Clock Requirements and
Performance .
Table 20, I/O States .
Added Cypress Part Numbering Scheme and Mapping Table on Page 1.
*I 5451420 UTSV 10/04/2016
Updated to Cypress template.
*J 5600128 YUCA 01/24/2017 Updated Figure 3
*K 5734075 RUPA 05/11/2017 Updated Cypress logo and Copyright information.

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101
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Document Number: 002-14796 Rev. *K Revised May 11, 2017 Page 101 of 101

002-14796 CYW43438 Single-Chip IEEE 802.11ac B G N MAC Baseband Radio With Integrated Bluetooth 4.1 and FM Receiver

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002-14796 CYW43438 Single-Chip IEEE 802.11ac B G N MAC Baseband Radio With Integrated Bluetooth 4.1 and FM Receiver

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PRELIMINARY CYW43438

Single-Chip IEEE 802.11ac b/g/n MAC/Baseband/

Cypress Part Numbering Scheme

Broadcom Part Number Cypress Part Number

General Features Security:

Figure 1. CYW43438 System Block Diagram

CLK_REQ 2.4 GHz WLAN +

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7.1 Features ............................................................ 31 13.3 Wireless Configuration Utility .............................54

7.2 Bluetooth Radio ................................................. 32 14. Pinout and Signal Descriptions..................... 55

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Buffer SDIO PMU

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1.3 Standards Compliance

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IEEE 802.11k Resource Management

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2. Power Supplies and Power Management

2.2 CYW43438 PMU Features

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Figure 3. Typical Power Topology (1 of 2)

InternalRXLDO 1.2V WLRFRXLNA

Supplyball Supplybump/pad Powerswitch

Groundball Groundbump/pad Nopowerswitch

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Figure 4. Typical Power Topology (2 of 2)

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2.3 WLAN Power Management

2.4 PMU Sequencing

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2.5 Power-Off Shutdown

2.6 Power-Up/Power-Down/Reset Circuits

Table 2. Power-Up/Power-Down/Reset Control Signals

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3.1 Crystal Interface and Clock Generation

Note: Resistor value determined by crystal drive level.

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Table 3. Crystal Oscillator and External Clock Requirements and Performance

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3.3 External 32.768 kHz Low-Power Oscillator

Table 4. External 32.768 kHz Sleep-Clock Specifications

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4. WLAN System Interfaces

4.1.1 SDIO Pin Descriptions

Table 5. SDIO Pin Descriptions

SD 4-Bit Mode SD 1-Bit Mode gSPI Mode

Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)

Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)

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4.2 Generic SPI Mode

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4.2.1 SPI Protocol

Figure 11. gSPI Read Protocol

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C A F1 F0 Address 17 bits Packet length - 11bits *

* 11h0 = 2048 bytes

ction No: 00 Func 0:

Access : 0 Fixed address

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Command 32 bits Write Data 16*n bits

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Figure 14. gSPI Signal Timing with Status (Response Delay = 0)