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Lecture 7:
Power
= C V ( t )dV = 12 CVC2
0
7: Power CMOS VLSI Design 4th Ed. 3 7: Power CMOS VLSI Design 4th Ed. 4
1
Charging a Capacitor Switching Waveforms
When the gate output rises Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
Energy stored in capacitor is
EC = 12 CLVDD
2
= CLVDD dV = C V
2
L DD
0
7: Power CMOS VLSI Design 4th Ed. 5 7: Power CMOS VLSI Design 4th Ed. 6
= CVDD 2 f sw
C
7: Power CMOS VLSI Design 4th Ed. 7 7: Power CMOS VLSI Design 4th Ed. 8
2
Short Circuit Current Power Dissipation Sources
When transistors switch, both nMOS and pMOS Ptotal = Pdynamic + Pstatic
networks may y be momentarilyy ON at once Dynamic power: Pdynamic = Pswitching + Pshortcircuit
Leads to a blip of short circuit current. Switching load capacitances
< 10% of dynamic power if rise/fall times are Short-circuit current
comparable for input and output Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
We will generally ignore this component Subthreshold leakage
Gate leakage
Junction leakage
Contention current
7: Power CMOS VLSI Design 4th Ed. 9 7: Power CMOS VLSI Design 4th Ed. 10
7: Power CMOS VLSI Design 4th Ed. 11 7: Power CMOS VLSI Design 4th Ed. 12
3
Dynamic Power Reduction Activity Factor Estimation
Let Pi = Prob(node i = 1)
Pswitchingg = CVDD f
2
Pi = 11-P
Pi
Try to minimize: i = Pi * Pi
Activity factor Completely random data has P = 0.5 and = 0.25
Capacitance Data is often not completely random
Supply voltage e.g. upper bits of 64-bit words representing bank
Frequency account balances are usually 0
Data propagating through ANDs and ORs has lower
activity factor
Depends on design, but typically 0.1
7: Power CMOS VLSI Design 4th Ed. 13 7: Power CMOS VLSI Design 4th Ed. 14
7: Power CMOS VLSI Design 4th Ed. 15 7: Power CMOS VLSI Design 4th Ed. 16
4
Clock Gating Capacitance
The best way to reduce the activity is to turn off the Gate capacitance
clock to registers
g in unused blocks Fewer stages of logic
Saves clock activity ( = 1) Small gate sizes
Eliminates all switching activity in the block Wire capacitance
Requires determining if block will be used Good floorplanning to keep communicating
blocks close to each other
Drive long wires with inverters or buffers rather
than
h complex l gates
7: Power CMOS VLSI Design 4th Ed. 17 7: Power CMOS VLSI Design 4th Ed. 18
7: Power CMOS VLSI Design 4th Ed. 19 7: Power CMOS VLSI Design 4th Ed. 20
5
Static Power Example Solution
Revisit power estimation for 1 billion transistor chip
Wnormal-Vt = ( 50 106 ) (12 )( 0.025 m / )( 0.05 ) = 0.75 106 m
Estimate static power consumption
Whigh-Vt = ( 50 106 ) (12 )( 0.95 ) + ( 950 106 ) ( 4 ) ( 0.025 m / ) = 109.25 106 m
Subthreshold leakage
I sub = Wnormal-Vt 100 nA/ m+Whigh-Vt 10 nA/ m / 2 = 584 mA
Normal Vt: 100 nA/m
High Vt: 10 nA/m (
)
I gate = Wnormal-Vt + Whigh-Vt 5 nA/ m / 2 = 275 mA
Pstatic = ( 584 mA + 275 mA )(1.0 V ) = 859 mW
High Vt used in all memories and in 95% of
logic gates
Gate leakage 5 nA/m
Junction leakage negligible
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7: Power CMOS VLSI Design 4th Ed. 23 7: Power CMOS VLSI Design 4th Ed. 24
6
Leakage Control Gate Leakage
Leakage and delay trade off Extremely strong function of tox and Vgs
Aim for low leakage
g in sleep p and low delay
y in Negligible for older processes
active mode
Approaches subthreshold leakage at 65 nm and
To reduce leakage: below in some processes
Increase Vt: multiple Vt
An order of magnitude less for pMOS than nMOS
Use low Vt only in critical circuits
Control leakage in the process using tox > 10.5
Increase Vs: stack effect
Input
put vector
ecto co t o in s
control sleep
eep High-k gate dielectrics help
Decrease Vb Some processes provide multiple tox
Reverse body bias in sleep e.g. thicker oxide for 3.3 V I/O transistors
Or forward body bias in active mode Control leakage in circuits by limiting VDD
7: Power CMOS VLSI Design 4th Ed. 25 7: Power CMOS VLSI Design 4th Ed. 26
Power Gating
Turn OFF power to blocks when they are idle to
save leakage
Use virtual VDD (VDDV)
Gate outputs to prevent
invalid logic levels to next block