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1, JANUARY 2000

Experimental Testing of a Neural Network Based

Digital Differential Relay for Synchronous Generators
A. I. Megahed, Member, IEEE, and O. P. Malik, Fellow, IEEE

AbstractThis paper describes the laboratory implementation late the parallel distributed nature of NNs. The simulation re-
and real-time test results of a new neural network (NN) based dig- sults presented may be said to be close to the expected in a phys-
ital differential relay used for detecting faults and classifying in- ical system as the generator model represents fairly closely the
ternal faults in the stator winding of synchronous generators. De-
tails of the software written to enable the operation of the relay are physical system [6] and the sequential algorithm can obtain the
described. Behavior of the NN based relay is observed and the ex- same output of a dedicated NN hardware, except for a longer
perimental results are presented. computation time [7].
Index TermsDigital differential protection, generators, micro- Computer simulation is still different from the real physical
processor based instrument, neural networks. system since the operating environment of the physical system
is not ideal, due to the existence of noise, current transformer
(CT) mismatches and CT saturation. Therefore, after theoret-
ical development and computer simulation, the next desirable

S YNCHRONOUS generators are an essential part of

the power system. Loss of even a single unit seriously
jeopardizes the operation of the power system to which it is
step is to evaluate the relay performance on a physical model. As
it is necessary to implement a NN based relay in hardware and
make sure that the calculation time is less than the intersampling
connected. The collective function of all forms of protection period, very few laboratory implementations of NN based re-
applied to generators is, therefore, to reduce the outage pe- lays are reported in the literature. A feedforward neural network
riod to a minimum by rapid discriminative clearance of all (FNN) based technique, that distinguishes between magnetizing
fault conditions associated with it. All faults associated with inrush and internal fault currents of a power transformer, has
synchronous generators may be classified as either insulation been implemented in a laboratory environment in [8]. In trans-
failures or abnormal running conditions [1], [2]. An insulation mission line protection, a FNN has been implemented on a trans-
failure in the stator winding will result in either an interturn puter system as a part of a single pole autoreclosure technique
fault, a phase fault or a ground fault, but most commonly [9]. For the purpose of detecting electric arcs in power system
the latter since most insulation failures eventually bring the devices a NN has been implemented in [10].
winding into direct contact with the core [1]. Differential The implementation in a laboratory environment of a NN
relays, in particular the digital ones, are used to detect stator based relay, used for detecting faults and classifying internal
faults of generators. faults in the stator winding of synchronous generators, is
In a previous paper, [3], the problems associated with existing reported in this paper. The important modules needed for the
conventional differential relays were demonstrated. Also, a new proposed relay are presented and described in this paper. The
neural network (NN) based digital differential relay, used for de- physical model, used to implement the NN based relay and test
tecting faults and classifying internal faults in the stator winding it, is also described. Effectiveness of the relay, in response to
of synchronous generators, has been suggested. The main ad- different operating conditions and various types of faults, is
vantage of the NN method over the conventional method is the demonstrated through the real-time test results.
nonalgorithmic parallel distributed architecture for information
processing that allows it to learn any complex input/output map-
ping [4]. Subsequently, researchers have applied NNs to solve
relaying problems in a number of different areas [5]. The NN based digital differential relay has two FNNs: one
The results presented in [3] have shown that the NN based FNN is used by the fault detector module and the other by the
relay exhibits very good performance. Like most other neural fault classifier module. The FNN based fault detector module
network based research, the results in [3] are based on computer is used to discriminate between three generator states, namely
simulations. In these simulations, the generator states were sim- the normal operation state, external fault state and internal fault
ulated using a set of simultaneous differential equations, and state. In the event of an internal fault the trip logic module issues
NNs were simulated by using a sequential algorithm to simu- a trip signal and activates the FNN based fault classifier module,
which identifies the faulted phase(s). In the case of an external
Manuscript received September 22, 1998. fault the relay acts as a backup relay for the main protection
A. I. Megahed is with the Department of EE, Alexandria University, Alexan- against external faults. The NN based relay uses current sam-
dria, Egypt. ples from the line-side ( , , ) and the neutral-end
O. P. Malik is with the Department of ECE, University of Calgary, Calgary,
Alberta, Canada T2N 1N4. ( , , ) of the generator in addition to samples from the
Publisher Item Identifier S 0885-8977(00)00571-9. field current ( ). Fundamental and/or second harmonic present
08858977/00$10.00 2000 IEEE

in the field current during a fault help the FNN, used for fault of two parts. The first part is a FNN that classifies the phases
detection, to differentiate between the three generator states. as faulty or healthy. The second part is a simple fault classifier
Details of the structure and method of training of the proposed confirmation logic that averages the FNN output.
NN based differential relay has been described in [3]. In this The inputs to the FNN are the line-side ( , , )
section a brief description of the function and structure of the and the neutral-end ( , , ) currents, each current being
important modules is given. represented by four consecutive samples making a total of 24
inputs to the FNN. Samples of the field current are not used in
A. Fault Detector Module this module as they do not help in classifying the phases. The
The FNN based fault detector module is the main part of the FNN has three layers, with 14 tan-sigmoid neurons in the first
differential protection scheme. Its function is to differentiate be- hidden layer, 7 tan-sigmoid neurons in the second hidden layer
tween three generator states, namely the normal operation state and 3 log-sigmoid neurons in the output layer. Each neuron in
(NOS), external fault state (EFS), and internal fault state (IFS). the output layer is responsible for a fault in one of the phases. As
The inputs to the FNN are 7 currents, each current being rep- an example, suppose there is an internal fault in phase , then
resented by five consecutive samples, making a total of 35 in- the output of phase neuron will be mapped to a value greater
puts (the sampling rate is 20 samples/cycle, 1200 Hz). The FNN than 0.95, indicating that this phase is faulty, while the outputs
has three layers, with 18 tan-sigmoid neurons in the first hidden of the two other neurons will be less than 0.1, indicating that
layer, 10 tan-sigmoid neurons in the second hidden layer and these two phases are healthy.
3 log-sigmoid neurons in the output layer. Each neuron in the The fault classifier logic does not indicate that a certain phase
output layer is responsible for one fault type, except the first is faulty except after confirming the output of the FNN fault
one that signals the normal state. Therefore depending on the classifier. The classifier confirms the presence of an internal
state of the generator one output is mapped to a value greater fault in one of the phases by averaging five consecutive outputs
than 0.9 while the two others are less than 0.1. The FNN was of each of the three output neurons. So, for the fault classifier
trained in a static manner using the back propagation algorithm logic to indicate that there is an internal fault in phase , the
[4]. conditions specified in (4) should exist for 3 consecutive sam-
ples. For a two phase fault, for example in phases and , the
B. Trip Logic Module relay would not indicate that these two phases are faulty unless
the boundary conditions of (5) exist for 3 consecutive samples
The trip logic module issues a trip signal only when it con-
firms that the output of the fault detector module is either an and and (4)
internal fault or a prolonged external fault that may affect the
generator. In order to confirm the presence of a certain state
(normal, external or internal), the fault logic module averages
six consecutive outputs of each of the three output neurons. The and and (5)
generator is considered to be operating at its normal state if (1)
where , , and are the averaged outputs
is valid. A trip decision is taken in the case of an internal fault
of phase , phase , and phase neurons.
if the conditions specified in (2) exist for 3 consecutive samples


A. Neural Network Weights
The FNNs used in the relay operate in a static manner. In
and and (2) other words, they were trained off-line using a computer simu-
lation program [6], [11], and once the desired performance was
where , , and are the averaged outputs of achieved the weights and biases of the FNNs were frozen. So,
normal state, external fault, and internal fault neurons, respec- the main objective of the experimental work is to verify that the
tively. When the trip logic module issues a trip signal based on previously trained FNNs can perform well when exposed to ac-
the detection of an internal fault it also activates the fault clas- tual current patterns. For that reason the weights and biases of
sifier module. In the event of an external fault, this relay is used the FNNs used in the relay implementation are the same ones
as a back-up relay. A trip decision is taken in the case of an ex- obtained from the off-line training process described in [3].
ternal fault if the conditions specified in (3) are sustained for a
prespecified number of cycles, , and the responsible relay has B. Power System Model
not tripped Fig. 1 shows the single line diagram of the power system
model implemented in the laboratory of the University of Cal-
and and (3) gary. It consists of a synchronous generator connected to an in-
finite bus (city power system) through a short , represented
by a resistance and an inductance . Both the generator
C. Fault Classifier Module and the infinite bus neutrals are grounded through resistances
The fault classifier module is activated by the trip logic and , respectively, in order to limit the short circuit
module only in the event of an internal fault. It is composed currents. The generator is rated at 5 kVA, 208 V, 1800 RPM.

The synchronous machine is driven by a 4.5 kW, 250 ma-

chine. The armature winding of the generator consists of two
paths per phase. The two paths of each phase are connected in
series during all states, i.e., during NOS, EFS, and IFS.
A 3-phase contactor (normally open) with a timer inserted in
its control circuit (timer dial, 0.050.2 s) is used in this labora-
tory setup. So, during different states of the generator the power
system model, Fig. 1, is not changed but the location and type Fig. 1. Single line diagram of the power system model implemented in the
of fault are changed by changing the connection of the 3-phase laboratory.

C. Hardware Structure
Current transformers, having turns ratio of 50/5 A, are used
in this laboratory setup with current shunts (5 A/100 mV) con-
nected to their secondaries, Fig. 2. An additional current shunt (2
A/100 mV) is connected in the field circuit, to enable recording
the field current. As the produced voltage signals are in the milli-
volt range, it is essential to amplify the signals before converting
them to digital form. A 7-channel amplifier is used for amplifi-
cation purposes. To avoid aliasing problems, an antialiasing low
pass filter, with a cut-off frequency of 600 Hz, is installed.
A data acquisition system (DAS) is connected to the low pass
filter output as shown in Fig. 2. The DAS is connected to a dig-
ital signal processing (DSP) board via two links. One link is for
the multiplexing command and the other for the analog voltage
signals to pass on to the analog to digital converter (A/D) of
the DSP board. The DSP board contains a Texas Instruments
TMS320C30 DSP chip. The board is mounted inside an 80 486
PC which is equipped with corresponding development and de-
bugging tools. Fig. 2. Hardware structure.

D. Software Structure
The relay software, running on DSP, is developed in C lan-
guage. In addition, a communication routine, running on PC, is
also developed to further facilitate the implementation process.
The PC communication routine functions as a man machine in-
terface. It first initializes vectors and flags for DSP-PC com-
munication. Then, it loads the DSP code into the chip. It then
reads the FNNs weights and biases and sends them to the DSP
chip through a dual access RAM (DARAM). After the incep-
tion of the main relay loop by the DSP, the PC communication
routine reads the outputs of the fault detector module and trip
logic module. It should be noted that once the relay detects an
internal fault, it activates the fault classifier module, and sub-
sequently the communication routine reads the outputs of the
fault classifier module. Once the DSP program is stopped, as
explained below, the output data is saved in a file.
The DSP program first initializes the vectors and flags for
DSP-PC communication then it reads the FNNs parameters
from DARAM, reset all counters and set all the scales. The set- Fig. 3. Flow chart of the main relay loop of the DSP program.
ting of the scales is very important as all inputs should have
a value between 1, so they can be processed by the FNNs. input signal is done at the beginning of each intersampling pe-
After initializing the DAS and the sampling time counter, the riod. The DAS program is executed in about 0.12 ms. Following
DSP program enters the main relay loop. The relay then waits that, the main relay loop proceeds in the manner shown in Fig. 3.
for the DAS program to be executed. The DAS program is a very The DSP program is stopped if an internal fault is detected and
small program, which is also performed by the DSP board. In classified or if an external fault is detected, as indicated in Fig. 3.
this program multiplexing, A/D conversion and scaling of each The main relay loop, including the DAS program, is executed

Fig. 4. NOS, P = 0:5 pu and pf = 0:8 lag.

Fig. 6. EFS, ppg phases a and c, at end of T L, FI = 4.

Fig. 5. EFS, pg phase c, at machine terminals, FI = 25.

in 0.76 ms. This time is well within the available intersampling Fig. 7. EFS, 3 phase at machine terminals with CT saturation, FI = 10.
time of 0.833 ms.


A. NOS Results
Fig. 4 shows the real-time test results of the fault detector
module and trip logic module during normal operation. The term
in Fig. 4 indicates the power delivered by the generator in
per-unit and the term pf is for the power factor. It is noticed that
the EFS and IFS output neurons have slightly higher values than
in the simulation results shown in [3]. This may be attributed to
CT mismatches and noisy current patterns. However, the FNN
based fault detector module is still able to accurately identify the
state of the generator, Fig. 4(a). Also, the averaging scheme of
the trip logic module smooths the outputs of all three neurons,
Fig. 4(b). Finally the NOS condition specified in (1) enables the
relay to identify a NOS even in the presence of noisy signals and
CT mismatches.

B. EFS Results
The DSP program, Fig. 3, allows for an external fault to per-
sist for 30 samples after its detection before it is stopped. In
other words, if the DSP board is connected to a circuit breaker,
which is not the case, a trip signal will be issued after 30 sam-
ples based on the detection of a prolonged external fault. All the
results presented in this section are up to the sample the DSP Fig. 8. IFS, pg at 100% of phase b, FI = 32.

Fig. 9. IFS, pg at 50% of phase a, FI = 51. Fig. 10. IFS, pp at 100% of phase a and 100% of phase b, FI = 25.

program is stopped. In the figures presented in this paper the The results shown in Fig. 8 are for an internal single phase
term pg indicates a single phase to ground fault, ppg indicates a to ground fault at 100% of phase , and those in Fig. 9 are for
two phase to ground fault, pp means a phase to phase fault and a similar fault at 50% of phase . The relay tripping time is
FI is the fault inception time in samples. 89 samples (less than one half cycle) after fault inception and
The results shown in Fig. 5 are for an external single phase to classification takes 7 samples. The relay also clearly detected
ground fault occurring at the machine terminals. The NN based and classified internal phase to phase faults, as shown in Fig. 10.
relay clearly indicated the existence of an EFS. Current trans-
former mismatches are more appreciable during external faults V. CONCLUSIONS
involving more than one phase. The response of the NN based
relay to a phase to phase fault is shown in Fig. 6. It is shown that Implementation of the NN based relay in a laboratory envi-
the relay is not affected by CT mismatches, which can cause a ronment and real-time test results on a physical model power
conventional digital differential relay to maloperate. system are presented in this paper. The relay is implemented in
In this laboratory setup it has been found that a terminal 3 a real-time digital environment by means of a DSP board. The
phase fault causes CTs to saturate. Current transformer satu- real-time test results done indicate that the relay is always suc-
ration presents a problem to differential relays in general. The cessful in detecting any of the generator three states. The relay
response of the relay to a 3 phase fault at the machine terminals also performs very well in the presence of CT mismatches and
is shown in Fig. 7. The relay clearly indicated the existence of saturation. The FNN based modules are able to detect and clas-
an EFS. The only effect of saturation may be the fluctuations sify internal faults they have not been exposed to during training.
occurring, in the EFS and IFS neurons, for a couple of samples. Finally, the relay tripping time is half a cycle or less (8 to 10
However, the averaging scheme diminished these fluctuations samples) and classification time is also within half a cycle (7 to
and the tripping speed of the relay has also not been affected, 10 samples).
Fig. 7(b).
C. IFS Results [1] Protective Relays Applications Guide, The English Electric Company
Limited, Relay Division, Stafford, 1975.
For internal faults, the DSP program, Fig. 3, detects an in- [2] C. J. Mozina, IEEE Tutorial on the Protection of Synchronous Gener-
ternal fault and then activates the fault classifier module to iden- ators, IEEE Tutorial Course, IEEE Power Engineering Society Special
Publ., no. 95 TP102, 1995.
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the classification is done. For each internal fault presented in digital differential protection scheme for synchronous generator stator
this section the results of the fault detector module, trip logic winding protection, IEEE Trans. on Power Delivery, 1997, to be pub-
module, FNN fault classifier and fault classifier confirmation [4] S. Haykin, Neural Networks: A Comprehensive Foundation. New
logic are shown. York, NY: Macmillan College Publishing Company, 1994.

[5] M. S. Sachdev, Advancements in Microprocessor Based Protection and [11] P. Subramaniam and O. P. Malik, Digital simulation of a synchronous
Communication, IEEE Tutorial Course, IEEE Power Engineering So- generator in direct-phase quantities, Proc. IEE, vol. 118, no. 1, pp.
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[7] H. Demuth and M. Beale, Neural Network Toolbox: For Use with
Matlab: The Math Works, Inc., 1993. A. I. Megahed obtained the B.Sc. and M.Sc. degrees in electrical engineering
[8] M. R. Zaman and M. A. Rahman, Experimental testing of the artificial from Alexandria University in 1991 and 1994, and the Ph.D. degree from the
neural network based protection of power transformers, presented at the University of Calgary in 1998. He is currently a Lecturer at Alexandria Univer-
IEEE Winter Meeting, New York, Feb. 1997, no. PE-045-PWRD-0-11- sity, Egypt.
[9] D. S. Fitton, R. W. Dunn, R. K. Aggarwal, A. T. Johns, and A. Bennett,
Design and implementation of an adaptive single pole autoreclosure
technique for transmission lines using artificial neural networks, IEEE
Trans. on Power Delivery, vol. 11, no. 2, pp. 748756, Apr. 1996. O. P. Malik graduated in electrical engineering in 1952, obtained the M.E. de-
[10] T. S. Sidhu, G. Singh, and M. S. Sachdev, Microprocessor based in- gree in 1962 and the Ph.D. and D.I.C. degrees from London University in 1965.
strument for detecting and locating electric arcs, presented at the IEEE From 1952 to 1961, he worked with electrical utilities in India. He is currently
Winter Meeting, Tampa, FL, Feb. 1998, no. PE-331-PWRD-0-11-1997. a Professor Emeritus at the University of Calgary, Canada.