Technique for synchronizing a single-phase

inverter to the mains

Samir Cabello Romero

Facultad de Ingeniera de la Universidad
Autnoma de Quertaro
Queretaro, Mexico
Samir.cabello74@gmail.com

Abstract The injection of energy into the grid by investors is a
recent and attractive issue due to the new energy reforms that
have been made in recent years, which is why it is necessary to
use, research and develop Systems interconnected to the electric
grid with a control scheme such as the one proposed in this work
Due to the dynamics in the mathematical model of the inverter,
there are constant variations in the parameters of the plant,
therefore, to apply a control scheme that works robustly requires
a control with a system able to adapt to these variations in the
time. It is therefore necessary to use two types of control
primarily in the design of an inverter, one in charge of
maintaining good voltage regulation at the output and another, a
control loop that is able to follow the frequency and phase of the
low network Conditions of distortion in the wave.
For correct operation of inverter control, it is necessary that the
inverter is properly synchronized with the mains. This is
achievable by using a PLL. A PLL scheme used in three-phase
systems is based on the use of a synchronous frame of reference
(SRF). For single-phase systems, the direct application of an
SRF, It is possible, but it is possible to generate a quadrature
component with the voltage sign and to be able to apply the
inverse Park transform. One way of producing quadrature
components is implementing a delay, which is responsible for
introducing a phase shift of 90 with respect to the fundamental
frequency of the Input signal.
I. INTRODUCTION
In the design of an inverter connected to the grid to inject
energy, it is crucial to design a control loop[1] that made me
measure the frequency and phase of the electric grid to make
the inverter follow this instruction.
The latter, a control loop called the PLL phase tracking loop,
is responsible for executing this task.
Phase, amplitude and frequency of the utility voltage are
critical information for the operation of the grid-connected
systems. The grid voltage monitoring is used to ensure that the
performance of a grid-connected system comply with the
standard requirements for operation under comon utility
distortions In such applications, an accurate and fast detection
of the phase angle of the utility voltage is essential to assure
the correct generation of the reference signals. Thus,
phaselocked loop topologies must handle distorted utility
voltages if they are intented to applications that required the
tracking of the utility voltage vector. The Phase-Locked Loop
(PLL) structure is a feedback control system that
automatically adjusts the phase of a locally generated signal to
match the phase of an input signal.
With the increasing demands for high-quality power sources, a
pulse-width modulated (PWM) inverter has been used as a key
element for a high-performance power conversion system for
critical loads such as computers, medical equipment and
communication systems. A single-phase PWM inverter is
generally used in low-power applications. To obtain a high-
quality output, the PWM inverter should provide tight output
voltage regulation, low total harmonic distortion (THD) and
low output impedance against load variations. Moreover, an
accurate reference tracking capability is also important
because modern power conversion systems are connected to
the utility and are operated in parallel for increasing usability
and reliability
II. PLLCONCEPTS BASICS
The PLL circuit is a feedback system whose purpose Principal
principle in the generation of an output signal with fixed
amplitude and frequency coincident with that of Input, within
a certain range

The PLL technique has been used as a common way of

recovering the phase and frequency information in electrical
systems. In the area of power electronics, the PLL technique
has been adopted for the speed control of electric motors. This
is also available for generating the current references
synchronised with the utility voltages in the power conversion
system[2]. A simple method of obtaining the phase
information is to detect the zero crossing points of the utility
voltages. However, since the zero crossing points can be Fig. 2. Frequency band.
detected only at every half-cycle of the utility frequency (i.e.
120 times per second), the phase tracking action is impossible
between the detecting points, and fast tracking performance (1)
cannot be achieved. Another method is the technique using the
quadrature of the input waveform shifted by 90 degrees[3].

An electronic inverter or DC / AC converter as its name (2)

indicates a circuit where a direct current voltage is input to the
input and an alternating current voltage of variable magnitude
and frequency.

It consists primarily of electronic power devices, which act as

cut-and-saturation switches operating in an appropriate
sequence to obtain three symmetrical and balanced output
voltages. The controller is another fundamental component in
the constitution of the converter, it is the one that generates the
signals of on and off of the semiconductor devices and
guarantees its good behavior. Any type of inverter (single
phase and three phase) or controlled activation and
deactivation devices (BJT, MOSFET, IGBT, MCT, SIT,
GTO) or forced switching thyristors, according to the
application as we can see in the figure 1.
Fig. 3. Phase locked loop.

When there is no signal applied to the system input, the

Fig. 1 Basic circuit of an inverter.
Maintaining the Integrity of the Specifications
When the PLL is out of sync, a very high or very low input
signal frequency, the output voltage adopts the center pulse
(co)[4]. There is a frequency band (locking range, lock range)
between which the PLL is in the tuning, characterized by i =
0, and another between which the circuit is capable of tuning
(C capture range, range Of the catch). The catch margin is
always lower than the catch margin and both are centered with
respect to the central push.
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voltage Vd (t) controlling the VCO has a value of zero. The
VCO oscillates at a frequency, f0 (or what is equivalent in Wo
radians) which is known as free oscillation frequency. When a
signal is applied to the system input, the phase detector
compares the phase and frequency of that signal with the VCO
frequency and generates an error voltage Ve (t) which is
proportional to the phase and frequency difference between
The two of signals[1]. This error voltage is then filtered,
extended, and applied to the control input of the VCO. In this
way, the control voltage Vd (t) forces the oscillation frequency
of the VCO to vary so as to reduce the frequency difference
between f0 and the input signal fi. If the input frequency fi is
sufficiently close to that of f0, the nature of the PLL feedback
causes the VCO oscillator to synchronize and engage the
incoming signal. Once hooked up, the VCO frequency is
identical to that of the input signal except for a finite phase
difference.
Is the phase difference needed to generate the correcting error
voltage Vd to achieve the free frequency offset of the VCO to
match the frequency fi of the input signal and thus keep the
PLL engaged[5]. This system autocorrection capability also
allows the PLL to "route" the frequency changes with the
input signal once it has been engaged. The range of
frequencies on which the PLL can maintain the engagement
with an input signal is defined as the "clutch range" of the
system[1]. The band frequencies on which the PLL can hook
with an input signal known as the "capture range" of the
system and is never greater than the range of hooking.

Another means of describing the operation of the PLL is in

observing that the phase comparator is actually a multiplier
circuit that mixes the input signal with the VCO signal[6].
This mix produces a range of frequencies which are sums and
frequency differences
(3)
When the loop is hooked
Fig. 4. Basic model for a PLL.
The basic blocks of the PLL are the Error Detector
(composed of a phase frequency detector and a charge pump),
Loop Filter, VCO, and a Feedback Divider. Negative feedback
forces the error signal, e(s), to approach zero at which point the
feedback divider output and the reference frequency are in
phase and frequency lock, and FO = NFREF.

Referring to Figure 4, a system for using a PLL to generate

(4)
Hence, at the output of the phase comparator we only have a
DC component. The lowpass filter overrides the frequency
component sum by being (fi + fo) out of its bandwidth but lets
pass the DC that is then amplified and attacks the VCO[7].
Note that when the loop is engaged, the frequency difference
component is always DC, such that the engagement range is
independent of the flank of the low pass filter bandwidth
higher frequencies than the input, the VCO oscillates at an
angular frequency of O. A portion of this signal is fed back to
the error detector, via a frequency divider with a ratio 1/N. This
divided down frequency is fed to one input of the error
detector. The other input in this example is a fixed reference
signal. The error detector compares the signals at both inputs.
When the two signal inputs are equal in phase and frequency,
the error will be constant and the loop is said to be in a
locked condition.
A. Phase frequency detector (PFD)

III. PLL COMPENSATOR Figure 5 shows a popular implementation of a Phase

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Frequency Detector (PFD), basically consisting of two D-type
flip flops. One Q output enables a positive current source; and
the other Q output enables a negative current source. Assuming
that, in this design, the D-type flip flop is positive-edge
triggered, the possible states are shown in the logic table.

A phase-locked loop is a feedback system combining a

voltage controlled oscillator (VCO) and a phase comparator so
connected that the oscillator maintains a constant phase angle
relative to a reference signal. Phase-locked loops can be used,
for example, to generate stable output high frequency signals
from a fixed low-frequency signal.

Figure 4A shows the basic model for a PLL. The PLL can
be analyzed as a negative feedback system using Laplace
Transform theory with a forward gain term, G(s), and a
feedback term, H(s), as shown in Figure 4B. The usual Fig. 5. Popular implementation of a Phase Frequency Detector (PFD).
equations for a negative feedback system apply.
 Consider now how the circuit behaves if the system is out
of lock and the frequency at +IN is much higher than the
frequency at IN, as shown in Figure 5A. Since the frequency
at +IN is much higher than that at IN, the UP output spends
most of its time in the high state. The first rising edge on +IN
sends the output high and this is maintained until the first rising
edge occurs on IN. In a practical system this means that the
output, and thus the input to the VCO, is driven higher,
resulting in an increase in frequency at IN. This is exactly
what is desired. If the frequency on +IN were much lower than
on IN, the opposite effect would occur. The output at OUT
would spend most of its time in the low condition. This would
have the effect of driving the VCO in the negative direction
and again bring the frequency at IN much closer to that at
+IN, to approach the locked condition.
Figure 5B shows the waveforms when the inputs are
frequency-locked and close to phase-lock. Since +IN is leading
IN, the output is a series of positive current pulses. These
pulses will tend to drive the VCO so that the IN signal
become phase-aligned with that on +IN. When this occurs, if
there were no delay element between U3 and the CLR inputs of
U1 and U2, it would be possible for the output to be in high-
impedance mode, producing neither positive nor negative
current pulses. This would not be a good situation.
The VCO would drift until a significant phase error
developed and started producing either positive or negative
current pulses once again. Over a relatively long period of
time, the effect of this cycling would be for the output of the
charge pump to be modulated by a signal that is a subharmonic
of the PFD input reference frequency[8]. Since this could be a
low frequency signal, it would not be attenuated by the loop
filter and would result in very significant spurs in the VCO
output spectrum, a phenomenon known as the "backlash" or
"dead zone" effect. The delay element between the output of
U3 and the CLR inputs of U1 and U2 ensures that it does not
happen. With the delay element, even when the +IN and IN
are perfectly phasealigned, there will still be a current pulse
generated at the charge pump output as shown in Figure 5C.
The duration of this delay is equal to the delay inserted at the
output of U3 and is known as the anti-backlash pulse width.
Note that if the +IN frequency is lower than the IN frequency
and/or the +IN phase lags the IN phase, then the output of the
charge pump will be a series of negative current pulsesthe
reverse of the condition shown in (A) and (B) in Figure 5.
B. Preescalers
state the units for each quantity that you use in an equation.
In the classical Integer-N synthesizer, the resolution of the
output frequency is determined by the reference frequency
applied to the phase detector. So, for example, if 200 kHz
spacing is required (as in GSM phones), then the reference
frequency must be 200 kHz. However, getting a stable 200
kHz frequency source is not easy. A sensible approach is to
take a good crystal-based high frequency source and divide
it down. For example, the desired frequency spacing could
be achieved by starting with a 10 MHz frequency reference
and dividing it down by 50.
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