16-Bit, 130 MSPS IF Sampling ADC

AD9461
FEATURES FUNCTIONAL BLOCK DIAGRAM
130 MSPS guaranteed sampling rate AGND AVDD1 AVDD2 DRGND DRVDD
78.7 dBFS SNR/90 dBc SFDR with 10 MHz input DFS
(3.4 V p-p input, 130 MSPS) AD9461
DCS MODE
77.7 dBFS SNR with 170.3 MHz input BUFFER
OUTPUT MODE
VIN+ 16
(4.0 V p-p input, 130 MSPS) PIPELINE 2
T/H CMOS OR
VIN ADC OR
77.0 dBFS SNR/84 dBc SFDR with 170 MHz input LVDS 32
OUTPUT D15 TO D0
(3.4 V p-p input, 130 MSPS) STAGING
76.3 dBFS SNR/86 dBc SFDR with 225 MHz input CLK+ CLOCK
2
DCO
(3.4 V p-p input, 125 MSPS) AND TIMING
REF
CLK MANAGEMENT
89 dBFS two-tone SFDR with 169 MHz and 170 MHz
(130 MSPS)

06011-001
60 fsec rms jitter VREF SENSE REFT REFB

Excellent linearity Figure 1.

DNL = 0.6 LSB typical
INL = 5.0 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available

APPLICATIONS
MRI receivers
Optional features allow users to implement various selectable
Multicarrier, multimode, cellular receivers
operating conditions, including input range, data format select,
Antenna array positioning
and output data mode.
Power amplifier linearization
Broadband wireless The AD9461 is available in a Pb-free, 100-lead, surface-mount,
Radar plastic package (100-lead TQFP_EP) specified over the industrial
Infrared imaging temperature range 40C to +85C.
Communications instrumentation
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION 1. True 16-bit linearity.
The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital 2. High performance: outstanding SNR performance for
converter (ADC) with an on-chip track-and-hold circuit. It is baseband IFs in data acquisition, instrumentation,
optimized for performance, small size, and ease of use. The magnetic resonance imaging, and radar receivers.
AD9461 operates up to 130 MSPS, providing a superior signal-
to-noise ratio (SNR) for instrumentation, medical imaging, and 3. Ease of use: on-chip reference and high input impedance
radar receivers using baseband (<100 MHz) and IF frequencies. track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
The ADC requires 3.3 V and 5.0 V power supplies and a low 4. Packaged in a Pb-free, 100-lead TQFP_EP.
voltage differential input clock for full performance operation.
No external reference or driver components are required for 5. Clock duty cycle stabilizer (DCS) maintains overall ADC
many applications. Data outputs are CMOS or LVDS compatible performance over a wide range of clock pulse widths.
(ANSI-644 compatible) and include the means to reduce the 6. Out-of-range (OR) outputs indicate when the signal is
overall current needed for short trace distances. beyond the selected input range.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved.
AD9461

TABLE OF CONTENTS
Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8

Functional Block Diagram .............................................................. 1 Equivalent Circuits......................................................................... 12

Applications....................................................................................... 1 Typical Performance Characteristics ........................................... 13

General Description ......................................................................... 1 Terminology .................................................................................... 16

Product Highlights ........................................................................... 1 Theory of Operation ...................................................................... 17

Revision History ............................................................................... 2 Analog Input and Reference Overview ................................... 17

Specifications..................................................................................... 3 Clock Input Considerations...................................................... 18

DC Specifications ......................................................................... 3 Power Considerations................................................................ 19

AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 20

Digital Specifications ................................................................... 5 Timing ......................................................................................... 20

Switching Specifications .............................................................. 5 Operational Mode Selection ..................................................... 20

Timing Diagrams.......................................................................... 6 Evaluation Board ............................................................................ 21

Absolute Maximum Ratings............................................................ 7 Outline Dimensions ....................................................................... 28

Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 28

ESD Caution.................................................................................. 7

REVISION HISTORY
4/06Revision 0: Initial Version

Rev. 0 | Page 2 of 28
 AD9461

SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = 1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 1.
AD9461BSVZ
Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full 4.2 0.1 +4.2 mV
Gain Error 25C 3 0.5 +3 % FSR
Full 3.4 +3.4 % FSR
Differential Nonlinearity (DNL) 1 25C 1.0 0.6 +1.0 LSB
Full 1.0 +1.3 LSB
Integral Nonlinearity (INL)1 25C 7 5.0 +7 LSB
VOLTAGE REFERENCE
Output Voltage VREF = 1.7 V Full +1.7 V
Load Regulation @ 1.0 mA Full 2 mV
Reference Input Current (External VREF = 1.7 V) Full 350 A
INPUT REFERRED NOISE 25C 2.6 LSB rms
ANALOG INPUT
Input Span
VREF = 1.7 V Full 3.4 V p-p
VREF = 1.0 V Full 2.0 V p-p
Internal Input Common-Mode Voltage Full 3.5 V
External Input Common-Mode Voltage Full 3.2 3.9 V
Input Resistance 2 Full 1 k
Input Capacitance2 Full 6 pF
POWER SUPPLIES
Supply Voltage
AVDD1 Full 3.14 3.3 3.46 V
AVDD2 Full 4.75 5.0 5.25 V
DRVDDLVDS Outputs Full 3.0 3.6 V
DRVDDCMOS Outputs Full 3.0 3.3 3.6 V
Supply Current1
AVDD1 Full 405 426 mA
AVDD21, 3 Full 131 143 mA
IDRVDD1LVDS Outputs Full 72 81 mA
IDRVDD1CMOS Outputs Full 14 mA
PSRR
Offset Full 1 mV/V
Gain Full 0.2 %/V
POWER CONSUMPTION
LVDS Outputs Full 2.2 2.4 W
CMOS Outputs (DC Input) Full 2.0 W
1
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For SFDR = AVDD1, IAVDD2 decreases by ~8 mA, decreasing power dissipation.

Rev. 0 | Page 3 of 28
AD9461
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal
trimmed reference (1.7 V mode), AIN = 1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 2.
AD9461BSVZ
Parameter Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz 25C 76.3 77.7 dB
Full 76.0 dB
fIN = 170 MHz 1 25C 74.2 76.0 dB
Full 73.8 dB
fIN = 225 MHz 25C 74.4 dB
fIN = 225 MHz @125 MSPS 25C 75.3 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz 25C 74.0 76.7 dB
Full 74.0 dB
fIN = 170 MHz1 25C 71.9 75.1 dB
Full 68.3 dB
fIN = 225 MHz 25C 73.5 dB
fIN = 225 MHz @125 MSPS 25C 74.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 25C 12.5 Bits
fIN = 170 MHz1 25C 12.2 Bits
fIN = 225 MHz 25C 11.9 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC)
fIN = 10 MHz 25C 82 90 dBc
Full 80 dBc
fIN = 170 MHz1 25C 77 84 dBc
Full 71 dBc
fIN = 225 MHz 25C 82 dBc
fIN = 225 MHz @125 MSPS 25C 86 dBc
WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS
fIN = 10 MHz 25C 88 96 dBc
Full 86 dBc
fIN = 170 MHz1 25C 89 95 dBc
Full 85 dBc
fIN = 225 MHz 25C 91 dBc
fIN = 225 MHz @ 125 MSPS 25C 93 dBc
TWO-TONE SFDR
fIN = 169.6 MHz @ 7 dBFS, 170.6 MHz @ 7 dBFS 25C 89 dBFS
ANALOG BANDWIDTH Full 615 MHz
1
SFDR = high (AVDD1). See the Operational Mode Selection section.

Rev. 0 | Page 4 of 28
 AD9461
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 k, unless otherwise noted.
Table 3.
AD9461BSVZ
Parameter Temp Min Typ Max Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage Full 2.0 V
Low Level Input Voltage Full 0.8 V
High Level Input Current Full 200 A
Low Level Input Current Full 10 +10 A
Input Capacitance Full 2 pF
DIGITAL OUTPUT BITSCMOS MODE (D0 to D15, OTR) 1
High Level Output Voltage Full 3.25 V
Low Level Output Voltage Full 0.2 V
DIGITAL OUTPUT BITSLVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage 2 Full 247 545 mV
VOS Output Offset Voltage Full 1.125 1.375 V
CLOCK INPUTS (CLK+, CLK)
Differential Input Voltage Full 0.2 V
Common-Mode Voltage Full 1.3 1.5 1.6 V
Input Resistance Full 1.1 1.4 1.7 k
Input Capacitance Full 2 pF
1
Output voltage levels measured with 5 pF load on each output.
2
LVDS RTERM = 100 .

SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9461BSVZ
Parameter Temp Min Typ Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full 130 MSPS
Minimum Conversion Rate Full 1 MSPS
CLK Period Full 7.7 ns
CLK Pulse Width High 1 (tCLKH) Full 3.1 ns
CLK Pulse Width Low1 (tCLKL) Full 3.1 ns
DATA OUTPUT PARAMETERS
Output Propagation DelayCMOS (tPD) 2 (Dx, DCO+) Full 3.35 ns
Output Propagation DelayLVDS (tPD) 3 (Dx+), (tCPD)3 (DCO+) Full 2.3 3.6 4.8 ns
Pipeline Delay (Latency) Full 13 Cycles
Aperture Uncertainty (Jitter, tJ) Full 60 fsec rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

Rev. 0 | Page 5 of 28
AD9461
TIMING DIAGRAMS
N1 N + 15
N
N + 14
AIN N+1
N + 13

tCLKL
tCLKH
1/fS
CLK+

CLK

tPD

DATA OUT N 13 N 12 N N+1

13 CLOCK CYCLES
DCO+

DCO

06011-002
tCPD

Figure 2. LVDS Mode Timing Diagram

N
N1

N+1
VIN N+2
tCLKL
tCLKH
CLK

CLK+

tPD
13 CLOCK CYCLES

DX N 13 N 12 N1 N

DCO+

06011-003
DCO

Figure 3. CMOS Timing Diagram

Rev. 0 | Page 6 of 28
 AD9461

ABSOLUTE MAXIMUM RATINGS

Table 5. THERMAL RESISTANCE
Parameter Rating
The heat sink of the AD9461 package must be soldered to
ELECTRICAL
ground.
AVDD1 to AGND 0.3 V to +4 V
AVDD2 to AGND 0.3 V to +6 V Airflow increases heat dissipation, effectively reducing JA. Also,
DRVDD to DGND 0.3 V to +4 V more metal directly in contact with the package leads from
AGND to DGND 0.3 V to +0.3 V metal traces through holes, ground, and power planes reduces
AVDD1 to DRVDD 4 V to +4 V the JA. It is required that the exposed heat sink be soldered to
AVDD2 to DRVDD 4 V to +6 V the ground plane.
AVDD2 to AVDD 4 V to +6 V
Table 6.
D0 through D15 to DGND 0.3 V to DRVDD + 0.3 V
Package Type JA 1 JB 2 JC 3 Unit
CLK+/CLK to AGND 0.3 V to AVDD1 + 0.3 V
100-Lead TQFP_EP 19.8 8.3 2 C/W
OUTPUT MODE, DCS MODE, and 0.3 V to AVDD1 + 0.3 V
DFS to AGND 1
Typical JA = 19.8C/W (heat sink soldered) for multilayer board in still air.
VIN+, VIN to AGND 0.3 V to AVDD2 + 0.3 V 2
Typical JB = 8.3C/W (heat sink soldered) for multilayer board in still air.
3
Typical JC = 2C/W (junction to exposed heat sink) represents the thermal
VREF to AGND 0.3 V to AVDD1 + 0.3 V
resistance through heat sink path.
SENSE to AGND 0.3 V to AVDD1 + 0.3 V
REFT, REFB to AGND 0.3 V to AVDD1 + 0.3 V
ENVIRONMENTAL
Storage Temperature Range 65C to +125C
Operating Temperature Range 40C to +85C
Lead Temperature (Soldering 10 sec) 300C
Junction Temperature 150C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 28
AD9461

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D15+ (MSB)
DRGND
DRVDD

DRVDD
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND

AGND
SFDR

D14+

D13+

D12+

D11+
D15

D14

D13

D12

D11
OR+
OR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

DCS MODE 1 75 DRGND

PIN 1
DNC 2 74 D10+
OUTPUT MODE 3 73 D10
DFS 4 72 D9+
LVDS_BIAS 5 71 D9
AVDD1 6 70 D8+
SENSE 7 69 D8
VREF 8 68 DCO+
AD9461
AGND 9 67 DCO
LVDS MODE
REFT 10 TOP VIEW 66 D7+
REFB 11 (Not to Scale) 65 D7
AVDD2 12 64 DRVDD
AVDD2 13 63 DRGND
AVDD2 14 62 D6+
AVDD2 15 61 D6
AVDD2 16 60 D5+
AVDD2 17 59 D5
AVDD1 18 58 D4+
AVDD1 19 57 D4
AVDD1 20 56 D3+
AGND 21 55 D3
VIN+ 22 54 D2+
VIN 23 53 D2
AGND 24 52 D1+
AVDD2 25 51 D1

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
CLK+
AGND

AGND

AGND
CLK

DRGND

D0 (LSB)
D0+
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1

AVDD1
AVDD1
AVDD1

DRVDD

06011-004

Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode

Table 7. Pin Function Descriptions100-Lead TQFP_EP in LVDS Mode

Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2 DNC Do Not Connect. This pin should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, AVDD1 3.3 V (5%) Analog Supply.
38, 43 to 45, 92 to 97
7 SENSE Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
8 VREF 1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 F and 10 F capacitors.
9, 21, 24, 39, 42, 46, 91, 98, AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to
99, Exposed Heat Sink AGND.
Rev. 0 | Page 8 of 28
 AD9461
Pin No. Mnemonic Description
10 REFT Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB
(Pin 11) with 0.1 F and 10 F capacitors.
11 REFB Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT
(Pin 10) with 0.1 F and 10 F capacitors.
12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (5%).
22 VIN+ Analog InputTrue.
23 VIN Analog InputComplement.
40 CLK+ Clock InputTrue.
41 CLK Clock InputComplement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
49 D0 (LSB) D0 Complement Output Bit (LVDS Levels).
50 D0+ D0 True Output Bit.
51 D1 D1 Complement Output Bit.
52 D1+ D1 True Output Bit.
53 D2 D2 Complement Output Bit.
54 D2+ D2 True Output Bit.
55 D3 D3 Complement Output Bit.
56 D3+ D3 True Output Bit.
57 D4 D4 Complement Output Bit.
58 D4+ D4 True Output Bit.
59 D5 D5 Complement Output Bit.
60 D5+ D5 True Output Bit.
61 D6 D6 Complement Output Bit.
62 D6+ D6 True Output Bit.
65 D7 D7 Complement Output Bit.
66 D7+ D7 True Output Bit.
67 DCO Data Clock OutputComplement.
68 DCO+ Data Clock OutputTrue.
69 D8 D8 Complement Output Bit.
70 D8+ D8 True Output Bit.
71 D9 D9 Complement Output Bit.
72 D9+ D9 True Output Bit.
73 D10 D10 Complement Output Bit.
74 D10+ D10 True Output Bit.
77 D11 D11 Complement Output Bit.
78 D11+ D11 True Output Bit.
79 D12 D12 Complement Output Bit.
80 D12+ D12 True Output Bit.
81 D13 D13 Complement Output Bit.
82 D13+ D13 True Output Bit.
83 D14 D14 Complement Output Bit.
84 D14+ D14 True Output Bit.
85 D15 D15 Complement Output Bit.
86 D15+ (MSB) D15 True Output Bit.
89 OR Out-of-Range Complement Output Bit.
90 OR+ Out-of-Range True Output Bit.
100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz. For applications with
analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR
performance; power dissipation from AVDD2 decreases by ~40 mW.

Rev. 0 | Page 9 of 28
AD9461

D15+ (MSB)

DRGND
DRVDD

DRVDD
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND

AGND
SFDR

D14+
D13+
D12+
D11+
D10+
OR+

D9+
D8+
D7+
D6+
D5+
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

DCS MODE 1 75 DRGND

PIN 1
DNC 2 74 D4+
OUTPUT MODE 3 73 D3+
DFS 4 72 D2+
LVDS_BIAS 5 71 D1+
AVDD1 6 70 D0+ (LSB)
SENSE 7 69 DNC
VREF 8 68 DCO+
AD9461
AGND 9 67 DCO
CMOS MODE
REFT 10 TOP VIEW 66 DNC
REFB 11 (Not to Scale) 65 DNC
AVDD2 12 64 DRVDD
AVDD2 13 63 DRGND
AVDD2 14 62 DNC
AVDD2 15 61 DNC
AVDD2 16 60 DNC
AVDD2 17 59 DNC
AVDD1 18 58 DNC
AVDD1 19 57 DNC
AVDD1 20 56 DNC
AGND 21 55 DNC
VIN+ 22 54 DNC
VIN 23 53 DNC
AGND 24 52 DNC
AVDD2 25 51 DNC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
CLK
CLK+
AGND

AGND

AGND
DRGND

DNC
DNC
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1

AVDD1
AVDD1
AVDD1

DRVDD

06011-005
Figure 5. 100-Lead TQFP_EP, Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions100-Lead TQFP_EP in CMOS Mode

Pin No. Mnemonic Description
1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float.
3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement.
DFS = low (ground) for offset binary format.
5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, AVDD1 3.3 V (5%) Analog Supply.
38, 43 to 45, 92 to 97
7 SENSE Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
8 VREF 1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming
resistors. Decouple to ground with 0.1 F and 10 F capacitors.
9, 21, 24, 39, 42, 46, 91, 98, AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to
99, Exposed Heat Sink AGND.
10 REFT Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB
(Pin 11) with 0.1 F and 10 F capacitors.

Rev. 0 | Page 10 of 28
 AD9461
Pin No. Mnemonic Description
11 REFB Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT
(Pin 10) with 0.1 F and 10 F capacitors.
12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (5%).
22 VIN+ Analog InputTrue.
23 VIN Analog InputComplement.
40 CLK+ Clock InputTrue.
41 CLK Clock InputComplement.
47, 63, 75, 87 DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
67 DCO Data Clock OutputComplement.
68 DCO+ Data Clock OutputTrue.
70 D0+ (LSB) D0 True Output Bit (CMOS Levels).
71 D1+ D1 True Output Bit.
72 D2+ D2 True Output Bit.
73 D3+ D3 True Output Bit.
74 D4+ D4 True Output Bit.
77 D5+ D5 True Output Bit.
78 D6+ D6 True Output Bit.
79 D7+ D7 True Output Bit.
80 D8+ D8 True Output Bit.
81 D9+ D9 True Output Bit.
82 D10+ D10 True Output Bit.
83 D11+ D11 True Output Bit.
84 D12+ D12 True Output Bit.
85 D13+ D13 True Output Bit.
86 D14+ D14 True Output Bit.
89 D15+ (MSB) D15 True Output Bit.
90 OR+ Out-of-Range True Output Bit.
100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the
AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz. For applications with
analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR
performance; power dissipation from AVDD2 decreases by ~40 mW.

Rev. 0 | Page 11 of 28
AD9461

EQUIVALENT CIRCUITS
AVDD2

VIN+
6pF 1k

DRVDD

3.5V X1 T/H

AVDD2 1k DX

VIN

06011-006
6pF

06011-009
Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent CMOS Digital Output Circuit

VDD

DRVDD DRVDD

K DCS MODE,
1.2V OUTPUT MODE,
DFS
LVDSBIAS 30k
06011-007

3.74k

06011-010
ILVDSOUT

Figure 7. Equivalent LVDS_BIAS Circuit Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE

AVDD1

DRVDD

3k 3k

CLK+ CLK
V V

DX DX+
2.5k 2.5k
V V
06011-008

06011-011

Figure 8. Equivalent LVDS Digital Output Circuit Figure 11. Equivalent Sample Clock Input Circuit

Rev. 0 | Page 12 of 28
 AD9461

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25C, 3.4 V p-p differential
input, AIN = 1 dBFS, internal trimmed reference (nominal VREF = 1.7 V), unless otherwise noted.
0 5
130MSPS
10 10.3MHz @ 1.0dBFS 4
20 SNR = 77.7dB
ENOB = 12.6 BITS 3
30 SFDR = 90dBc
40 2
AMPLITUDE (dBFS)

50 1

INL (LSB)
60
0
70
80 1

90 2
100
3
110

06011-012

06011-017
4
120
130 5
0 16.25 32.50 48.75 65.00 0 8192 16384 24576 32768 40960 49152 57344 65536
FREQUENCY (MHz) OUTPUT CODE

Figure 12. 130 MSPS, 64k Point Single-Tone FFT, 10.3 MHz Figure 15. 130 MSPS, INL Error vs. Output Code, 10.3 MHz

0 95
130MSPS
10 170.3MHz @ 1.0dBFS
20 SNR = 75.4dB SFDR = +85C
ENOB = 12.3 BITS 90
30 SFDR = 86dBc
40
AMPLITUDE (dBFS)

50 85
60 SFDR = +25C
(dB)

70
SFDR = 40C
80 80
SNR = 40C
90
100
75
110 SNR = +25C SNR = +85C
06011-015

06011-018
120
130 70
0 16.25 32.50 48.75 65.00 0 50 100 150 200
FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)

Figure 13. 130 MSPS, 64k Point Single-Tone FFT,170.3 MHz Figure 16. 130 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p

0.6 95

SFDR = +85C
0.4
90

0.2
85
DNL (LSB)

SFDR = +25C
(dB)

0
SFDR = 40C
80
0.2 SNR = 40C

75
0.4
06011-016

06011-019

SNR = +85C
SNR = +25C
0.6 70
0 8192 16384 24576 32768 40960 49152 57344 65536 0 50 100 150 200
OUTPUT CODE ANALOG INPUT FREQUENCY (MHz)

Figure 14. 130 MSPS, DNL Error vs. Output Code, 10.3 MHz Figure 17. 130 MSPS, SNR/SFDR vs. Analog Input Frequency,
3.4 V p-p, CMOS Output Mode

Rev. 0 | Page 13 of 28
AD9461
120 0
SFDR dBFS 10

100 20
SFDR dBc
30
SFDR dBc 40

SFDR AND IMD3 (dB)

80
50
WORST IMD3 dBc
60
(dB)

60
70
SNR dBFS 80
40 SFDR dBFS
90
100
20 110

06011-020

06011-025
SNR dB 120
WORST IMD3 dBFS
0 130
90 80 70 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0
ANALOG INPUT AMPLITUDE (dB) ANALOG INPUT AMPLITUDE (dB)

Figure 18. 130 MSPS,170.3 MHz SNR/SFDR vs. Analog Input Amplitude Figure 21. 130 MSPS, Two-Tone SFDR vs. Analog Input Amplitude,
169.6 MHz, 170.6 MHz

95 6000

SFDR = +25C 5000

90

FREQUENCY 4000
85
(dB)

SFDR = 40C 3000

SFDR = +85C
80
SNR = 40C
2000

75
1000
SNR = +85C

06011-028
06011-021

SNR = +25C

70 0

N+0
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N9
N8
N7
N6
N5
N4
N3
N2
N1

N+10
N+11
N11
N10

0 50 100 150 200

ANALOG INPUT FREQUENCY (MHz)
BIN
Figure 19. 125 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p Figure 22. 130 MSPS, Grounded Input Histogram

120 0
105MSPS
170.6MHz @ 7.0dBFS
SFDR dBFS 20 169.6MHz @ 7.0dBFS
100 SFDR = 89dBFS

40
SNR dBFS
AMPLITUDE (dBFS)

80
60
(dB)

60
80
SFDR dBc
40
100

20 120
06011-029
06011-023

SNR dB

0 140
90 80 70 60 50 40 30 20 10 0 0 15.625 31.250 46.875 62.500
ANALOG INPUT AMPLITUDE (dB) FREQUENCY (MHz)

Figure 20. 130 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Amplitude, Figure 23. 130 MSPS, 64k Point Two-Tone FFT, 169.6 MHz, 170.6 MHz
CMOS Output Mode

Rev. 0 | Page 14 of 28
 AD9461
0.6 90

SFDR dBc
0.5
85
0.4
GAIN ERROR (%FS)

0.3
80
SNR dB

(dB)
0.2

75
0.1

0
70
0.1

06011-030

06011-046
0.2 65
40 20 0 20 40 60 80 2.9 3.1 3.3 3.5 3.7 3.9 4.1
TEMPERATURE (C) ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 24. 130 MSPS, Gain vs. Temperature Figure 27. 130 MSPS, SNR/SFDR vs. Analog Input Common Mode

97 90

170.3MHz SFDR dBc SFDR dBc

92 85

87 80
(dBc)

(dB) SNR dB

82 75

170.3MHz SNR dBFS

77 70
06011-047

06011-035
72 65
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 45 65 85 105 125 145
ANALOG INPUT RANGE (V p-p) SAMPLE RATE (MSPS)

Figure 25. 130 MSPS, SNR, SFDR vs. Analog Input Range Figure 28. Single-Tone SNR/SFDR vs. Sample Rate 170.3 MHz

1.734

1.732

1.730

1.728
VREF (V)

1.726

1.724

1.722

1.720
06011-032

1.718

1.716
40 20 0 20 40 60 80
TEMPERATURE (C)

Figure 26. 130 MSPS, VREF vs. Temperature

Rev. 0 | Page 15 of 28
AD9461
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all operating ranges.
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs LSB before the first code
transition. Positive full scale is defined as a level 1 LSB beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms input signal amplitude to the rms
value of the sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral component. The peak spurious
component may be a harmonic. SFDR can be reported in dBc (that
is, degrades as signal level is lowered) or dBFS (always related back
to converter full scale).
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Rev. 0 | Page 16 of 28
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
(SINAD 1.76 )
ENOB =
6.02
Gain Error
The first code transition should occur at an analog value of
LSB above negative full scale. The last transition should occur
at an analog value of 1 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value of
LSB below VIN+ = VIN. Offset error is defined as the
deviation of the actual transition from that point.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25C) value to the value
at TMIN or TMAX.
 AD9461

THEORY OF OPERATION
The AD9461 architecture is optimized for high speed and ease ranges <2 V p-p. However, reducing the range can improve SFDR
of use. The analog inputs drive an integrated, high bandwidth performance in some applications. Likewise, increasing the
track-and-hold circuit that samples the signal prior to quantization range up to 3.4 V p-p can improve SNR. Users are cautioned
by the 16-bit pipeline ADC core. The device includes an on-board that the differential nonlinearity of the ADC varies with the
reference and input logic that accepts TTL, CMOS, or LVPECL reference voltage. Configurations that use <2.0 V p-p can
levels. The digital output logic levels are user selectable as standard exhibit missing codes and, therefore, degraded noise and
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT distortion performance.
MODE pin.
VIN+
ANALOG INPUT AND REFERENCE OVERVIEW VIN
REFT
A stable and accurate 0.5 V band gap voltage reference is built
0.1F
into the AD9461. The input range can be adjusted by varying ADC +
CORE 0.1F 10F
the reference voltage applied to the AD9461, using either the
REFB
internal reference or an externally applied reference voltage.
0.1F
The input span of the ADC tracks reference voltage changes VREF
linearly. 10F
+
0.1F
SELECT
Internal Reference Connection LOGIC

SENSE
A comparator within the AD9461 detects the potential at the
SENSE pin and configures the reference into three possible states,
0.5V
summarized in Table 9. If SENSE is grounded, the reference
amplifier switch is connected to the internal resistor divider (see

06011-036
AD9461
Figure 29), setting VREF to ~1.7 V. If a resistor divider is
connected as shown in Figure 30, the switch again sets to the Figure 29. Internal Reference Configuration
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as

VREF = 0.5 V 1 +
R2 VIN+
VIN
R1 REFT

0.1F
In all reference configurations, REFT and REFB drive the ADC
0.1F
+
10F
CORE
analog-to-digital conversion core and establish its input span. REFB
The input range of the ADC always equals twice the voltage at 0.1F
VREF
the reference pin for either an internal or an external reference.
+
10F 0.1F
SELECT
Internal Reference Trim R2 LOGIC
SENSE
The internal reference voltage is trimmed during the production
test; therefore, there is little advantage to the user supplying an
R1 0.5V
external voltage reference to the AD9461. The gain trim is
performed with the AD9461 input range set to 3.4 V p-p
AD9461 06011-037

nominal (SENSE connected to AGND). Because of this trim,

and the maximum ac performance provided by the 3.4 V p-p Figure 30. Programmable Reference Configuration
analog input range, there is little benefit to using analog input

Rev. 0 | Page 17 of 28
AD9461
Table 9. Reference Configuration Summary
Selected Mode SENSE Voltage
External Reference AVDD
Programmable Reference 0.2 V to VREF
Programmable Reference 0.2 V to VREF
(Set for 2 V p-p)
Internal Fixed Reference AGND to 0.2 V
External Reference Operation
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer continues to generate the positive
and negative full-scale references, REFT and REFB, for the
ADC core. The input span is always twice the value of the
reference voltage; therefore, the external reference must be
limited to a maximum of 2.0 V. See Figure 24 for gain variation vs.
temperature.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9461 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9461 cannot be realized with a single-ended analog input;
therefore, such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support single-
ended analog input configurations.
With the 1.7 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9461 analog input is nominally 3.4 V p-p or 1.7 V p-p on
each input (VIN+ or VIN).
VIN+
1.7V p-p
VIN
DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s
Figure 31. Differential Analog Input Range for VREF = 1.7 V
Resulting VREF (V) Resulting Differential Span (V p-p)
N/A 2 external reference
2 VREF
0.5 1 +
R2 , (See Figure 30)
R1
2.0
0.5 1 +
R2 , R1 = R2 = 1 k
R1
1.7 3.4
The AD9461 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 k resistor to
the 3.5 V bias voltage and to the input of a differential buffer. The
internal bias network on the input properly biases the buffer for
maximum linearity and range (see the Equivalent Circuits section).
Therefore, the analog source driving the AD9461 should be ac-
coupled to the input pins. The recommended method for driving
the analog input of the AD9461 is to use an RF transformer to
convert single-ended signals to differential (see Figure 32). Series
resistors between the output of the transformer and the AD9461
analog inputs help isolate the analog input source from switching
transients caused by the internal sample-and-hold circuit. The
series resistors, along with the 1 k resisters connected to the
internal 3.5 V bias, must be considered in impedance matching
the transformer input. For example, if RT is set to 51 , RS is set
to 33 and there is a 1:1 impedance ratio transformer, the input
matches a 50 source with a full-scale drive of 16.0 dBm. The
50 impedance matching can also be incorporated on the
secondary side of the transformer, as shown in the evaluation
board schematic (see Figure 35).
ANALOG ADT11WT RS
INPUT VIN+
SIGNAL R
T
RS
AD9461
VIN
06011-039
0.1F
Figure 32. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock combines with the desired signal at the analog-to-
digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9461, and the user is
advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
3.5V variety of internal timing signals and, as a result, can be sensitive
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9461 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
06011-038
signal with a nominal ~50% duty cycle. Noise and distortion per-
formance are nearly flat for a 30% to 70% duty cycle with the DCS
Rev. 0 | Page 18 of 28

formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 s to 5 s after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it can be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9461 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of per-
formance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
by 3 dB to 4 dB with 70 MHz analog input signals when using a
high jitter clock source. (See the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance for more
information.) For optimum performance, the AD9461 must be
clocked differentially. The sample clock inputs are internally
biased to ~1.5 V, and the input signal is usually ac-coupled into
the CLK+ and CLK pins via a transformer or capacitors.
Figure 33 shows one preferred method for clocking the
AD9461. The clock source (low jitter) is converted from single-
ended to differential using an RF transformer. The back-to-back
Schottky diodes across the secondary of the transformer limit
clock excursions into the AD9461 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9461 and
limits the noise presented to the sample clock inputs.
If a low jitter clock is available, it helps to band-pass filter the
clock reference before driving the ADC clock inputs. Another
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in Figure 34.
CRYSTAL ADT11WT
SINE CLK+
SOURCE 0.1F
AD9461
CLK
06011-040
HSMS2812
DIODES
Figure 33. Crystal Clock Oscillator, Differential Encode
Rev. 0 | Page 19 of 28
AD9461
VT
0.1F
ENCODE
ECL/
PECL AD9461
0.1F
ENCODE
06011-041
VT
Figure 34. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation:
SNR = 20 log[2fINPUT tJ]
In the equation, the rms aperture jitter represents the root-mean-
square of all jitter sources including the clock input, analog input
signal, and ADC aperture jitter specification. IF undersampling
applications are particularly sensitive to jitter
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the AD9461.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that can be received by the
AD9461. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 F chip capacitors.
The AD9461 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best per-
formance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9461 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,
the DRVDD supply can be connected from 2.5 V to 3.6 V for
compatibility with the receiving logic.
AD9461
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 k RSET
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, maximizes when
using the AD9461 in LVDS mode; designers are encouraged to
take advantage of this mode. The AD9461 outputs include
complementary LVDS outputs for each data bit (Dx+/Dx), the
overrange output (OR+/OR), and the output data clock output
(DCO+/DCO). The RSET resistor current is multiplied on-chip,
setting the output current at each output equal to a nominal
3.5 mA (11 IRSET). A 100 differential termination resistor
placed at the LVDS receiver inputs results in a nominal 350 mV
swing at the receiver. LVDS mode facilitates interfacing with
LVDS receivers in custom ASICs and FPGAs that have LVDS
capability for superior switching performance in noisy
environments. Single point-to-point net topologies are
recommended, with a 100 termination resistor located as
close to the receiver as possible. It is recommended to keep the
trace length less than two inches and to keep differential output
trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9461 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 ) to
minimize switching transients caused by the capacitive loading.
Table 10. Digital Output Coding
VIN+ VIN VIN+ VIN
Code Input Span = 3.4 V p-p (V) Input Span = 2 V p-p (V)
65,536 +1.700 +1.000
32,768 0 0
32,767 0.000058 0.0000305
0 1.70 1.00
Rev. 0 | Page 20 of 28
TIMING
The AD9461 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9461 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS-
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9461 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9461 outputs are LVDS compatible, and
the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
SFDR Enhancement
Under certain conditions, the SFDR performance of the AD9461
improves by decreasing the power of the core of the ADC. The
SFDR control pin (Pin 100) is a CMOS-compatible control pin
to optimize the configuration of the AD9461 analog front end.
Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz.
For applications with analog inputs from 40 MHz to 215 MHz,
connect this to AVDD1 for optimum SFDR performance; power
dissipation from AVDD2 decreases by ~40 mW.
Digital Output Digital Output
Offset Binary (D15D0) Twos Complement (D15D0)
1111 1111 1111 1111 0111 1111 1111 1111
1000 0000 0000 0000 0000 0000 0000 0000
0111 1111 1111 1111 1111 1111 1111 1111
0000 0000 0000 0000 1000 0000 0000 0000

EVALUATION BOARD
Evaluation boards are offered to configure the AD9461 in either
CMOS mode or LVDS mode only. This design represents a
recommended configuration for using the device over a wide
range of sampling rates and analog input frequencies. These
evaluation boards provide all the support circuitry required to
operate the ADC in its various modes and configurations.
Complete schematics are shown in Figure 35 through Figure 38.
Gerber files are available from engineering applications
demonstrating the proper routing and grounding techniques
that should be applied at the system level.
It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) are used to realize the ultimate
performance of the converter. Proper filtering of the input
signal to remove harmonics and lower the integrated noise at
the input is also necessary to achieve the specified noise
performance.
The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9461 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see Figure 35).
Rev. 0 | Page 21 of 28
AD9461
The LVDS mode evaluation boards include an LVDS-to-CMOS
translator, making them compatible with the high speed ADC
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9461 and many other
high speed ADCs.
Behavioral modeling of the AD9461 is also available at
www.analog.com/ADIsimADC. The ADIsimADC software
supports virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between the
AD9461 and other high speed ADCs with or without hardware
evaluation boards.
The user can choose to remove the translator and terminations
to access the LVDS outputs directly.
 P22 P21

GND
PTMICRO4 PTMICRO4
AD9461

DRGND
P4
P3
P2
P1
P4
P3
P2
P1

4
3
2
1
4
3
2
1

H2
MTHOLE6
H1
MTHOLE6
H3
MTHOLE6
H4
MTHOLE6
5V
GND
GND
VCC
DRGND
DRVDD
EXTREF
XTALPWR

VCC E19
E36
GND E18

VCC E4
E6

GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
DOR_T/DOR_Y
DOR_C
DRGND
(MSB) D15_T/D15_Y
D15_C/D14_Y
D14_T/D13_Y
D14_C/D12_Y
D13_T/D11_Y
D13_C/D10_Y
D12_T/D9_Y
D12_C/D8_Y
D11_T/D7_Y
D11_C/D6_Y
DRVDD

DRVDD
GND E5
GND

VCC E10

101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

E1
GND E9

EPAD
OR_T

SFDR
OR_C

AGND
AGND
AGND
D15_T
D14_T
D13_T
D12_T
D11_T

D15_C
D14_C
D13_C
D12_C
D11_C

AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
DRVDD
DRVDD

DRGND
VCC E3
E14 SCLK 1 75 DRGND
DCS MODE DRGND
GND E2 R11 2 74 D10_T/D5_Y
1k GND DNC D10_T
3 73
VCC OUTPUT MODE D10_C D10_C/D4_Y
4 72 D9_T/D3_Y
DFS D9_T
5 71 D9_C/D2_Y
LVDSBIAS D9_C
GND 6 70
VCC AVDD1 D8_T D8_T/D1_Y
GND E26 C86 7 69
VCC SENSE D8_C D8_C/D0_Y
E25 0.1F 8 68
VREF DCO DR
E41 E27 GND 9 67 DRB
AGND DCOB
R1 E24 10 66
R3 DNP EXTREF GND REFT D7_T D7_T
3.74k C3 11 65

Rev. 0 | Page 22 of 28
GND REFB AD9461 D7_C D7_C
0.1F 12 64

+
5V AVDD2 DRVDD DRVDD
GND C40 C51 C2 13 63
R2 10F 0.1F 5V AVDD2 DRGND DRGND
GND DNP C39 0.1F
C9 14 AVDD2 D6_T 62 D6_T
10F 5V
0.1F 61

Figure 35. Evaluation Board Schematic

5V 15 AVDD2 D6_C D6_C
GND 16 D5_T 60
5V AVDD2 D5_T
C98 17 59
DNP GND 5V AVDD2 D5_C D5_C
18 AVDD1 58
VCC D4_T D4_T
19 57
VCC AVDD1 D4_C D4_C
GND 20 56
R5 T1 VCC AVDD1 D3_T D3_T
ETC1-1-13 21 D3_C 55
DNP GND AGND D3_C
1 5 TOUT 22 54
J4 L1 GND VIN+ D2_T D2_T
SMBMST CT R28 23 53
10nH 2 GND C7 VIN D2_C D2_C
GND 33 24 52
C12 0.1F GND AGND D1_T D1_T
TINB 3 4 R4 25 51
C5 0.1F 5V AVDD2 D1_C D1_C
0.1F PRI SEC T2 25
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AGND
ENC
ENCB
AGND
AVDD1
AVDD1
AVDD1
AGND
DRGND
DRVDD
D0_C
D0_T

3 1

PRI
TOUTB
ANALOG
R9 C13
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

4 5 DNP DNP

ETC1-1-13
2

SEC
E15 R6 OPTIONAL
25
T5

C91
0.1F
ADT1-1WT
5V
5V

GND TOUT
VCC

VCC
VCC
VCC
VCC
VCC
ENC
VCC
VCC
GND

6
GND
GND

1 GND
D0_T

GND
ENCB

5 2
DRVDD

5V
DRGND

NC CT
3 4
D0_C (LSB)

TINB TOUTB C8 R35

PRI SEC 0.1F 33

DNP = DO NOT POPULATE

06011-042
 GND
ENCODE OPTIONAL ENCODE CIRCUITS
GND
R7 VXTAL
DNP CR2 TO MAKE LAYOUT AND PARASITIC
R39 LOADING SYMMETRICAL
0 E31 5V + C1 C41
ENC VXTAL 10F 0.1F
J5 E30 DNP DNP
SMBMST 3 1 2 E20 XTALPWR
T3 + C44 GND
C36 ADT1-1WT 10F
DNP CR2 DNP
1 6 DNP CR1
J1 NC 5 2 GND U2
SMBMST ECLOSC
3 4 C42
0.1F 2 1 3
PRI SEC GND 8
R8 C26 VXTAL 14
0.1F ENCB VCC OUT XTALINPUT
50 1
GND 7
VEE ~OUT

GND
XTALINPUT L5
FERRITE
DRVDD DRVDDX
L4
FERRITE
VCC VCCX
L3 L2
FERRITE 0
POWER OPTIONS 5V 5VX GND DRGND

Rev. 0 | Page 23 of 28
ADP3338-5 ADP3338-3.3 ADP3338-3.3
P4 U14 U7 U3

PJ-002A 5V 3.3V 3.3V

2 1 1 1
2 GND GND GND GND GND GND DRGND
3 4 2 4 2 4 2
3 5VX OUT OUT1 5VX VCCX OUT OUT1 VCCX DRVDDX OUT OUT1 DRVDDX
1 3 3 3
1 VIN IN VIN IN VIN IN VIN

+ C33 + C34 + C6 + C4
10F 10F 10F 10F
+ C89 + C87 + C88

Figure 36. Evaluation Board Schematic, Encode, Optional Encode, and Power Options
10F 10F 10F

GND GND GND DRGND

GND GND DRGND

DNP = DO NOT POPULATE
06011-043
AD9461
AD9461
BYPASS CAPACITORS

VCC
+ C64 C43 C35 C32 C30 C28 C27 C90 C50 C60 C10 C61 C75
10F 0.1F 0.1F 0.1F 0.01F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F DNP DNP
GND

VCC
C11 C14 C17 C16 C15 C31 C38 C29 C19
0.1F DNP DNP DNP 0.1F DNP 0.1F DNP DNP
GND

DRVDD DRVDD
+ C65 C47 C23 C21 C20 C69 C70 C45 C49
10F 0.1F 0.1F 0.1F 0.1F DNP DNP DNP DNP
DRGND DRGND

5V EXTREF
+ C56 C85 C53 C52 C58 C37 C48 C18 + C55
10F 0.1F 0.1F 0.1F 0.01F DNP 0.1F 0.1F 10F
DNP
GND GND

5V
C72 C73 C108 C109 C110
DNP DNP DNP DNP DNP
GND

5V
C94 C95 C22 C59 C93 C96 C97 C84 C46
0.1F 0.1F 0.1F 0.1F DNP 0.1F 0.1F 0.1F 0.1F
GND

06011-044
DNP = DO NOT POPULATE

Figure 37. Evaluation Board Schematic, Bypass Capacitors

Rev. 0 | Page 24 of 28
 U15
SN75LVDT390
1 16
DR 1A EN_1_2 DRVDD
2 15
DRB 1B 1Y DRO
3 14 R19
2A 2Y
4 13 0
2B VCC DRVDD
5 12
3A GND DRGND R10
6 11
3B 3Y 0
7 10
DRO_T/DOR_Y 4A 4Y ORO
8 9
DOR_C 4B EN_3_4 DRVDD

U8
SN75LVDT386
1 64
D15_T/D14_Y A1A GND DRGND
2 63 RZ5 220
D15_C/D14_Y A1B VCC1 DRVDD RSO16ISO
40 3 62 40
DRGND P40 P39 39 DRGND D14_T/D13_Y A2A VCC2 DRVDD DRGND P40 P39 39 DRGND
4 61 R1
38 D14_C/D12_Y A2B GND1 DRGND 1 16 D15O 38
DOR_T/DOR_Y P38 P37 37 DOR_C 5 60 ORO P38 P37 37 DRO
D13_T/D11_Y A3A ENA DRVDD R2
36 D13_C/D10_Y 6 59 2 15 D14O 36
D15_T/D15_Y P36 P35 35 D15_C/D14_Y A3B A1Y P36 P35 35 GND
7 58 R3
34 D12_T/D9_Y A4A A2Y 3 14 34
D14_T/D13_Y P33 33 D14_C/D12_Y 8 57 D13O P33 33 D15O
P34 D12_C/D8_Y A4B A3Y P34
9 56 R4
32 D11_T/D7_Y B1A A4Y 4 13 D12O 32
D13_T/D11_Y P32 P31 31 D13_C/D10_Y 10 55 P32 P31 31 D14O
D11_C/D6_Y B1B ENB DRVDD 5 R5 12
D12_T/D9_Y 30 P29 29 D10_T/D5_Y 11 54 D11O 30 P29 29
P30 D12_C/D8_Y B2A B1Y P30 D13O
12 53 R6
28 D10_C/D4_Y B2B B2Y 6 11 D10O 28
D11_T/D7_Y P28 P27 27 D11_C/D6_Y 13 52 P28 P27 27 D12O
D9_T/D3_Y B3A B3Y R7
26 14 51 7 10 D9O 26
D10_T/D5_Y P26 P25 25 D10_C/D4_Y D9_C/D2_Y B3B B4Y P26 P25 25 D11O
15 50 R8
24 D8_T/D1_Y B4A GND2 DRGND 8 9 D8O 24
D9_T/D3_Y P24 P23 23 D9_C/D2_Y 16 49 P24 P23 23 D10O
D8_C/D0_Y B4B VCC3 DRVDD
22 17 48 22
D8_T/D1_Y P22 P21 21 D8_C/DO_Y D7_T C1A VCC4 DRVDD 220 P22 P21 21 D9O

Rev. 0 | Page 25 of 28
18 47
20 D7_C C1B GND3 DRGND RSO16ISO 20
DR P20 P19 19 DRB 19 46 P20 P19 19 D8O
D6_T C2A C1Y
20 45 1 R1 16
18 P17 17 D6_C C2B C2Y D7O 18 P17 17
D7_T P18 D7_C 21 44 P18 D7O
D5_T C3A C3Y R2

Figure 38. Evaluation Board Schematic

16 22 43 2 15 D6O 16
D6_T P16 P15 15 D6_C D5_C C3B C4Y P16 P15 15 D6O
23 42 3 R3 14
14 D4_T C4A ENC DRVDD D5O 14
D5_T P14 P13 13 D5_C 24 41 P14 P13 13 D5O
D4_C C4B D1Y R4
12 25 40 4 13 D4O 12
D4_T P12 P11 11 D4_C D3_T D1A D2Y P12 P11 11 D4O
26 39 R5
10 D3_C D1B D3Y 5 12 10
D3_T P9 9 D3_C 27 38 D3O P9 9 D3O
P10 D2_T D2A D4Y P10
28 37 6 R6 11
8 P7 7 D2_C D2B END DRVDD D2O 8 P7 7
D2_T P8 D2_C 29 36 P8 D2O
D1_T D3A GND4 DRGND 7 R7 10
6 P5 5 30 35 D1O 6 P5 5
D1_T P6 D1_C D1_C D3B VCC5 DRVDD P6 D1O
31 34 8 R8 9
4 P3 3 D0_T D4A VCC6 DRVDD D0O 4 P3 3
D0_T P4 D0_C 32 33 P4 D0O
D0_C D4B GND5 DRGND
DRGND 2 P1 1 RZ4 2 P1 1
P2 DRGND DRGND P2 DRGND

P6 P7
C40MS C40MS
GND
C76 C82 C77 C78
0.1F 0.1F 0.1F 0.1F
GND
06011-045
AD9461
AD9461
Table 11. AD9461 Customer Evaluation Board Bill of Material
Item Qty. Reference Designator Description Package Value 1 Manufacturer Mfg. Part No.
1 7 C4, C6, C33, C34, C87, C88, C89 Capacitor TAJD 10 F Digi-Key 478-1699-2
Corporation
2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, Capacitor 402 0.1 F Digi-Key PCC2146CT-ND
C15, C20, C21, C22, C23, C26, C27, Corporation
C28, C32, C35, C38, C40, C42, C43,
C46, C47, C48, C50, C52, C53, C59,
C60, C76, C77, C78, C82, C84, C85,
C86, C90, C91, C94, C95, C96, C97
3 2 C30, C58 Capacitor 201 0.01 F Digi-Key 445-1796-1-ND
Corporation
4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key 478-1699-2
Corporation
5 1 C51 Capacitor 805 10 F Digi-Key 490-1717-1-ND
Corporation
6 1 CR1 Diode SOT23M5 Digi-Key MA3X71600LCT-
Corporation ND
7 1 CR21 Diode SOT23M5 DNP Digi-Key MA3X71600LCT-
Corporation ND
8 20 E1, E2, E3, E4, E5, E6, E9, E10, E14, E18, Header EHOLE Mouser 517-6111TG
E19, E20, E24, E25, E26, E27, E30, E31, Electronics
E36, E41
9 2 J1, J4 SMA SMA Digi-Key ARFX1231-ND
Corporation
10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-
10NXGBU
11 3 L3, L4, L5 EMIFIL 1206MIL Mouser 81-BLM31P500S
BLM31PG500SN1L Electronics
12 1 P4 Power jack PJ-002A Digi-Key CP-002A-ND
Corporation
13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-
D-RA
14 1 R3 Resistor 402 3.74 k Digi-Key P3.74KLCT-ND
Corporation
15 1 R8 Resistor 402 50 Digi-Key P49.9LCT-ND
Corporation
16 4 R10, R19, R39, L2 Resistor 402 0 Digi-Key P0.0JCT-ND
Corporation
17 1 R11 BRES402 402 1 k Digi-Key P1.0KLCT-ND
Corporation
18 2 R28, R35 Resistor 402 33 Digi-Key P33JCT-ND
Corporation
19 2 RZ4, RZ5 Resistor array 16-pin 22 Digi-Key 742C163220JCT-
Corporation ND
20 1 T3 Transformer ADT1-1WT Mini-Circuits ADT1-1WT
21 1 U1 AD9461BSVZ-105/130 SV-100-3 Analog AD9461BSVZ
Devices, Inc.
22 1 U14 ADP3338-5 SOT-223HS Analog ADP3338-5
Devices, Inc.
23 2 U3, U7 ADP3338-3.3 SOT-223HS Analog ADP3338-3.3
Devices, Inc.
24 1 U8 SN75LVDT386 TSSOP64 Arrow SN75LVDT386
Electronics,
Inc.
25 1 U15 SN75LVDT390 SOIC16PW Arrow SN75LVDT390
Electronics,
Inc.
26 2 R4, R6 Resistor 402 25 Digi-Key P36JCT-ND
Corporation
Rev. 0 | Page 26 of 28
 AD9461
Item Qty. Reference Designator Description Package Value 1 Manufacturer Mfg. Part No.
27 2 C1, C44, C551 Capacitor TAJD 10 F, Digi-Key 478-1699-2
DNP Corporation
28 23 C13, C14, C16, C17, C18, C19, C29, CAP402 402 DNP
C31, C36, C37, C41, C45, C49, C61,
C69, C70, C72, C73, C75, C93, C108,
C109, C1101
29 1 C981 Capacitor 805 DNP Digi-Key 490-1717-1-ND
Corporation
30 E151 Header EHOLE DNP Mouser 517-6111TG
Electronics
31 J51 SMA SMA DNP Digi-Key ARFX1231-ND
Corporation
32 P61 Header C40MS DNP Samtec, Inc. TSW-120-08-L-
D-RA
33 2 R1, R21 BRES402 402 DNP
34 3 R5, R7, R91 BRES402 402 DNP
35 1 U21 ECLOSC DIP4(14) DNP
36 4 H1, H2, H3, H41 MTHOLE6 MTHOLE6 DNP
37 2 T1, T21 Balun transformer SM-22 DNP M/A-COM ETC1-1-13
38 1 T51 Transformer ADT1-1WT DNP Mini-Circuits ADT1-WT
39 2 P21, P221 Term strip PTMICRO4 DNP Newark
Electronics
1
DNP = do not populate. All items listed in this category are not populated.

Rev. 0 | Page 27 of 28
AD9461

OUTLINE DIMENSIONS
0.75 1.20 16.00 BSC SQ
MAX
0.60 14.00 BSC SQ
0.45 100 76 76 100
1 75 75 1
PIN 1

TOP VIEW EXPOSED 9.50 SQ

(PINS DOWN) PAD

1.05 0 MIN
0.20 BOTTOM VIEW
1.00 0.09 (PINS UP)
25 51 51 25
0.95 7 26 50 50 26
3.5
0.15 0 VIEW A 0.50 BSC 0.27
SEATING LEAD PITCH
0.05 PLANE 0.08 MAX 0.22
COPLANARITY 0.17

VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

040506-A
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 39. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9461BSVZ 1 40C to +85C 100-Lead TQFP_EP SV-100-3
AD9461-LVDS/PCB AD9461-100 LVDS Mode Evaluation Board
1
Z = Pb-free part.

2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D0601104/06(0)

Rev. 0 | Page 28 of 28