Finger Print Based Electronic Voting Mac

Finger print based electronic voting machine
FROM:
Engr Rana Muhammad Shakeel
Engnr.shakeel@gmail.com
https://www.facebook.com/EngnrShakeel
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FINGER PRINT BASED ELECTRONIC VOTING MACHINE

Chapter 1
INTRODUCTION
This project examines policy regarding the electronic approaches and

developments towards electronic data storage and transmission. Finger print
devices for Voting machines and other existing identity documents are
discussed and implemented in this project.
JNTUA CE , pulivendula Page 1

The user has to show his voter ID card whenever he goes to the polling
booth to poll his vote. This is a time consuming process as the person has to
check the voter ID card with the list he has, confirm it as an authorized card
and then allow the person to poll his vote. Thus, to avoid this kind of problems,
we have designed a finger print based voting machine where the person no
need to carry his ID which contains his entire details.
The person at the polling booth has to show his Finger. This Finger print
reader reads the details from the tag. This data is passed to the controlling unit
for the verification. The controller reads the data from the reader and compares
this data with the already existing data. If the data matches with the already
stored information, the person is allowed to poll his vote. If not, a message is
displayed on LCD and the person is not allowed to poll his vote. The polling
mechanism carries out manually using the switches. LCD is used to display
the related messages.
1.1 Objective of the project

The project demands the user to submit his Finger print at the polling
booth. The project uses the Finger print technology and Embedded Systems to
design this application. The main objective of this project is to design a system
that asks the user to show his Finger print as an identity proof. The system
reads the data from the Finger print and verifies this data with the already
stored data in its database. If the details present in the data base it matches
with the stored data, the system allows the person to enter into and poll his
vote. If the details of the Finger do not match with the stored data, the system
immediately activates the display and the security authorities can come and
take the further action.
This project is a device that collects data from the tag and codes the data
into a format that can be understood by the controlling section. This system

also collects information from the master device and implements commands
that are directed by the master.
The objective of the project is to develop a microcontroller based security
and alert system. It consists of a Finger print reader, microcontroller, the
interfacing unit to allow the communication between the microcontroller and
Finger print module, and the LCD.
1.2 Background of the Project

The software application and the hardware implementation help the
microcontroller read the data from the Finger print verify the data with the
already stored data and take the next action. The system is totally designed
using Finger print module and embedded systems technology.
The Controlling unit has an application program to allow the
microcontroller interface with the Finger print module, the reader reads the
data from the tag, passes the data to the microcontroller and the controller
verifies this data with the already existing data in the controllers memory and
then implement the commands directed by the controller section. The
performance of the design is maintained by controlling unit.
1.3 Organization of the Thesis

In view of the proposed thesis work explanation of theoretical aspects
and algorithms used in this work are presented as per the sequence described
below.
Chapter 1 describes a brief review of the objectives and goals of the work.
Chapter 2 discusses the existing technologies and the study of various
technologies in detail.
Chapter 3 describes the Block diagram, Circuit diagram of the project and its
description. The construction and description of various modules used for the
application are described in detail.
Chapter 4 description of Lpc2148

Chapter 5 description of Finger Print module

Chapter 6 description of LCD switches
Chapter 7 explains the Software tools required for the project, the Code
developed for the design.
Chapter 8 presents the results, overall conclusions of the study
Chapter 9 proposes possible improvements and directions of future research
work.
Chapter 10 presents references.
Chapter 2
OVERVIEW OF THE TECHNOLOGIES USED
Embedded Systems:
An embedded system can be defined as a computing device that does a
specific focused job. Appliances such as the air-conditioner, VCD player, DVD
player, printer, fax machine, mobile phone etc. are examples of embedded
systems. Each of these appliances will have a processor and special hardware
to meet the specific requirement of the application along with the embedded
software that is executed by the processor for meeting that specific
requirement.

The embedded software is also called firm ware. The desktop/laptop

computer is a general purpose computer. You can use it for a variety of
applications such as playing games, word processing, accounting, software
development and soon.
In contrast, the software in the embedded systems is always fixed listed below:
Embedded systems do a very specific task, they cannot be programmed
to do different things. Embedded systems have very limited resources,
particularly the memory. Generally, they do not have secondary storage devices
such as the CDROM or the floppy disk. Embedded systems have to work
against some deadlines. A specific job has to be completed within a specific
time. In some embedded systems, called real-time systems, the deadlines are
stringent. Missing a deadline may cause a catastrophe-loss of life or damage to
property. Embedded systems are constrained for power. As many embedded
systems operate through a battery, the power consumption has to be very low.
Some embedded systems have to operate in extreme environmental conditions
such as very high temperatures and humidity.
Following are the advantages of Embedded Systems:
1. They are designed to do a specific task and have real time performance
constraints which must be met.
2. They allow the system hardware to be simplified so costs are reduced.
3. They are usually in the form of small computerized parts in larger
devices which serve a general purpose.
4. The program instructions for embedded systems run with limited
computer hardware resources, little memory and small or even non-
existent keyboard or screen.

Chapter 3
Hardware Implementation of the Project
This chapter briefly explains about the Hardware Implementation of the
project. It discusses the design and working of the design with the help of block
diagram and circuit diagram and explanation of circuit diagram in detail. It
explains the features, timer programming, serial communication, interrupts of
Lpc 2148 microcontroller. It also explains the various modules used in this
project.
3.1 Project Design

The implementation of the project design can be divided in two parts.

Hardware implementation
Firmware implementation
Hardware implementation deals in drawing the schematic on the plane

paper according to the application, testing the schematic design over the
breadboard using the various ICs to find if the design meets the objective,
carrying out the PCB layout of the schematic tested on breadboard, finally
preparing the board and testing the designed hardware.
The firmware part deals in programming the microcontroller so that it

can control the operation of the ICs used in the implementation. In the present
work, we have used the Orcad design software for PCB circuit design, the Keil
v3 software development tool to write and compile the source code, which has
been written in the C language. The Flash maic programmer has been used to
write this compile code into the microcontroller. The firmware implementation
is explained in the next chapter.
The project design and principle are explained in this chapter using the
block diagram and circuit diagram. The block diagram discusses about the
required components of the design and working condition is explained using
circuit diagram and system wiring diagram.
Power
Supply
Finger
Print
3.2 Block Diagram of the Project and its Description
Module
The block diagram of the project is as shown in the figure 3.1
16 X 2 LCD
MAX 232 ARM 7TDMI

EEPROM
LPC2148

Crystal
Oscillator Switches
Fig 3.1 : block diagram

Brief explanation of functioning of each block of the system is given
below the detailed is given in next chapters
3.2 Power Supply:

The input to the circuit is applied from the regulated power supply. The
a.c. input i.e., 230V from the mains supply is step down by the transformer to
12V and is fed to a rectifier. The output obtained from the rectifier is a
pulsating d.c voltage. So in order to get a pure d.c voltage, the output voltage
from the rectifier is fed to a filter to remove any a.c components present even
after rectification. Now, this voltage is given to a voltage regulator to obtain a
pure constant dc voltage. The block diagram of regulated power supply is
shown in the figure 3.2

Fig 3.2 components of power supply

Transformer:
Usually, DC voltages are required to operate various electronic
equipment and these voltages are 5V, 9V or 12V. But these voltages cannot be
obtained directly. Thus the a.c input available at the mains supply i.e., 230V is
to be brought down to the required voltage level. This is done by a transformer.
Thus, a step down transformer is employed to decrease the voltage to a
required level.
Rectifier:
The output from the transformer is fed to the rectifier. It converts A.C.
into pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In
this project, a bridge rectifier is used because of its merits like good stability
and full wave rectification.
Filter:
Capacitive filter is used in this project. It removes the ripples from the
output of rectifier and smoothens the D.C. Output received from this filter is
constant until the mains voltage and load is maintained constant. However, if
either of the two is varied, D.C. voltage received at this point changes.
Therefore a regulator is applied at the output stage.

Voltage regulator:
As the name itself implies, it regulates the input applied to it. A voltage
regulator is an electrical regulator designed to automatically maintain a
constant voltage level. In this project, power supply of 5V and 12V are required.
In order to obtain these voltage levels, 7805 and 7812 voltage regulators are to
be used. The first number 78 represents positive supply and the numbers 05,
12 represent the required output voltage levels
LPC2148:
LPC2148 arm processor is used for controlling. ARM processor is used
because of its extra features when compared to microcontroller. It controls LCD
and finger print module. It receives input commands from switches and control
finger print module when to receive the data, performs comparison , gives
command to LCD to display messages to direct the users to use it properly and
also displays the results.
Finger Print Module :

Finger print module is an input device used for Fingerprint processing
which includes two parts: fingerprint enrollment and fingerprint matching (the
matching can be 1:1 or 1:N). When enrolling, user needs to enter the finger two
times. The system will process the two time finger images, generate a template
of the finger based on processing results and store the template. When
matching, user enters the finger through optical sensor and system will
generate a template of the finger and compare it with templates of the finger
library. For 1:1 matching, system will compare the live finger with specific
template designated in the Module; for 1:N matching, or searching, system will
search the whole finger library for the matching finger. In both circumstances,
system will return the matching result, success or failure.

LCD display and Switches:

Switches here function as inputs that gives command to the controller
what to do and LCD display as output that directs the users how to use the
module and also to display the final results.
The firmware programmed in LPC2148 is designed to communicate with

Finger print and operates according the commands received from the Switches.
Therefore, after Receiving the Data from Finger print and processing and
validating, It takes the data from switches and comparing with the data base
and updating the data base and display the command and display the result
with respect to the switch operations.
The switches are used to activate the controller for registration during
enrollment, for comparisons to the database while identifying the user, for
selecting the party while casting the vote, finally for display of results.
LCD screen functions as interface between the user and microcontroller,
which displays messages that facilitates the user to know when to register and
when to vote, and also whether their vote is valid are not.
It displays welcome messages initially and enrolling message during
enrollment, identifying message when controller is comparing the data base
whether the user is valid are not, if valid displays please vote message, if not
displays no access message, and finally displays the result with party name
with their respective number of votes.

3.3.System wiring diagram and working procedure:

Wiring diagram of the project is as shown in the figure 3.3 below

Fig 3.3: wiring diagram

Working procedure:
Voting machine using Finger print is basically an embedded system that
makes the things easy in the polling booths during the time of elections. The

project Finger print technology and Embedded systems to implement the

application.
The user, who wants to poll his vote, has to submit the identity proof at
the counter at the polling booth. In this project, the necessary and, upto an
extent, the sufficient material, the user no need to carry with him is the Voter
card.
Voter card is nothing but an Finger Print which stores the details of the
person like the name of the user, location of place, mobile number for contact
etc. When the user is asked to show his Finger print. The Finger print module
reads the data present.
The working of our EVM an be explained in three modes

1.Enrolling mode
2.Identification and vote casting mode
3. Results
When the power of Ballot unit is turned on, the ballot unit awaits a
READY SIGNAL from controller. After getting READY SIGNAL, ballot unit
displays its welcome to EVM message on LCD indicating that the machine is ready
and waits for user input. The mode of operation depends on command given by
the user from the switches.
Enrolling Mode
If enrolling mode command is given, the controller waits for input and
activates the scanner to accept the finger print, displaying Enrollingon the
LCD display . The candidates finger print is scanned and generates a unique
characters code. During the character code generation, GENRATING
CHARACTER CODE is displayed on LCD. This unique code is stored in the
EEPROM memory of the controller for the future reference. After all
enrollments the system is ready for vote cast.

Identification and vote casting mode
Before casting the vote the candidate has to check for validity .so after
user pressing the identify button the controller displays identifying ..
message. During this mode the fingerprint of the candidate casting the vote is
compared with the finger prints already enrolled in the memory. If it is
matched a message PLEASE VOTE will be displayed on LCD. Once the
voter presses the button corresponding to the candidate of her/his choice, a
four-bit code is generated and sent to the control unit. Once the casting is
over message is displayed to whom they voted for.No ACCESS.. message will
be displayed if the same user tries to cast again. The machine returns to the
identifying mode and starts all over again for next voting.
RESULTS MODE
The contestant name and the secured votes will be displayed on the LCD
when the controller receives results instruction through the switches.
Chapter 4
Microcontroller
4.1.Definition of a Microcontroller
Microcontroller, as the name suggests, are small controllers. They are
like single chip computers that are often embedded into other systems to

function as processing/controlling unit. For example, the remote control you

are using probably has microcontrollers inside that do decoding and other
controlling functions. They are also used in automobiles, washing machines,
microwave ovens, toys ... etc, where automation is needed.
The key features of microcontrollers include:
High Integration of Functionality

Microcontrollers sometimes are called single-chip computers because
they have on-chip memory and I/O circuitry and other circuitries that
enable them to function as small standalone computers without other
supporting circuitry.
Field Programmability, Flexibility
Microcontrollers often use EEPROM or EPROM as their storage device to

allow field programmability so they are flexible to use. Once the program
is tested to be correct then large quantities of microcontrollers can be
programmed to be used in embedded systems.
Easy to Use
Assembly language is often used in microcontrollers and since they

usually follow RISC architecture, the instruction set is small. The
development package of microcontrollers often includes an assembler, a
simulator, a programmer to "burn" the chip and a demonstration board.
Some packages include a high level language compiler such as a C compiler
and more sophisticated libraries.
Most microcontrollers will also combine other devices such as:
A Timer module to allow the microcontroller to perform tasks for certain

time periods.

A serial I/O port to allow data to flow between the microcontroller and
other devices such as a PC or another microcontroller.
An ADC to allow the microcontroller to accept analogue input data for

processing.
Figure 4.1 a typical microcontroller device and its different subunits
The heart of the microcontroller is the CPU core. In the past this has
traditionally been based on an 8-bit microprocessor unit. Figure 4.1 above
Shows a typical microcontroller device and its different subunits
4.2.Microcontrollers versus Microprocessors
Microcontroller differs from a microprocessor in many ways. First and

the most important is its functionality. In order for a microprocessor to be
used, other components such as memory, or components for receiving and
sending data must be added to it. In short that means that microprocessor is
the very heart of the computer. On the other hand, microcontroller is designed

to be all of that in one. No other external components are needed for its
application because all necessary peripherals are already built into it. Thus, we
save the time and space needed to construct devices.
4.3 LPC214x
The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-

bit ARM7TDMI-S CPU with real-time emulation and embedded trace support,
that combine microcontroller with embedded high speed flash memory ranging
from 32 kB to 512 kB. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock
rate. For critical code size applications, the alternative 16-bit Thumb mode
reduces code by more than 30 % with minimal performance penalty. Due to
their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal
for applications where miniaturization is a key requirement, such as access
control and point-of-sale. Serial communications interfaces ranging from a
USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip
SRAM of 8 kB up to 40 kB, make these devices very well suited for
communication gateways and protocol converters, soft modems, voice
recognition and low end imaging, providing both large buffer size and high
processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit
DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level
sensitive external interrupt pins make these microcontrollers suitable for
industrial control and medical systems
4.3.1Key features
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip
flash memory.
128-bit wide interface/accelerator enables high-speed 60 MHz operation.
In-System Programming/In-Application Programming (ISP/IAP) via on-

chip boot loader software. Single flash sector or full chip erase in 400 ms
and programming of 256 bytes in 1 ms.
Embedded ICE RT and Embedded Trace interfaces offer real-time
debugging with the on-chip Real Monitor software and high-speed tracing
of instruction execution.
USB 2.0 Full-speed compliant device controller with 2 KB of endpoint
RAM. In addition, the LPC2146/48 provides 8 kB of on-chip RAM
accessible to USB by DMA.
One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a
total of 6/14 analog inputs, with conversion times as low as 2.44 s per
channel.
Single 10-bit DAC provides variable analog output (LPC2142/44/46/48
only).
Two 32-bit timers/external event counters (with four capture and four
compare channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz
clock input Multiple serial interfaces including two UARTs (16C550), two
Fast I2C-bus (400 Kbit/s),SPI and SSP with buffering and variable data
length capabilities.
Vectored Interrupt Controller (VIC) with configurable priorities and vector
addresses.
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64
package.
Up to 21 external interrupt pins available.
60 MHz maximum CPU clock available from programmable on-chip PLL
with settling time of 100 s.
On-chip integrated oscillator operates with an external crystal from 1
MHz to 25 MHz
Power saving modes include Idle and Power-down.

Individual enable/disable of peripheral functions as well as peripheral

clock scaling for additional power optimization.
Processor wake-up from Power-down mode via external interrupt or
BOD.
Single power supply chip with POR and BOD circuits: CPU operating
voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

The block diagram of LPC2148 is shown in figure 4.2 below
Fig : 4.2Block diagram

1) Pins shared with GPIO
2) LPC2144/46/48 only
3) USB DMA controller with 8KBof Ram accessible as general purpose
RAmand/or DMA available in LPC2146/48 only.
4) LPC21422/44/46/48 only

The pin description of the controller is shown in the figure 4.3
Fig 4.2: pin diagram

pin description is given in the following table4.2 below




Table 4.2 pin description

4.3.2. Functional description
Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which

offers high performance and very low power consumption. The ARM
architecture is based on Reduced Instruction Set Computer (RISC) principles,
and the instruction set and related decode mechanism are much simpler than
those of micro programmed Complex Instruction Set Computers (CISC). This
simplicity results in a high instruction throughput and impressive real-time

interrupt response from a small and cost-effective processor core. Pipeline

techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being
executed, its successor is being decoded, and a third instruction is being
fetched from memory. The ARM7TDMI-S processor also employs a unique
architectural strategy known as Thumb, which makes it ideally suited to high-
volume applications with memory restrictions, or applications where code
density is an issue.The key idea behind Thumb is that of a super-reduced
instruction set. Essentially, the ARM7TDMI-S processor has two instruction
sets:
The standard 32-bit ARM set.
A 16-bit Thumb set.
The Thumb sets 16-bit instruction length allows it to approach twice the
density of standard ARM code while retaining most of the ARMs performance
advantage over a traditional 16-bit processor using 16-bit registers. This is
possible because Thumb code operates on the same 32-bit register set as ARM
code. Thumb code is able to provide up to 65 % of the code size of ARM, and
160 % of the performance of an equivalent ARM processor connected to a 16-
bit memory system.The particular flash implementation in the
LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is
recommended to program performance critical and short code sections (such as
interrupt service routines and DSP algorithms) in ARM mode. The impact on
the overall code size will be minimal but the speed can be increased by 30%
over Thumb mode.
On-chip flash program memory
The LPC2148 incorporate a 512 kB flash memory system respectively.
This memory may be used for both code and data storage. Programming of the
flash memory may be accomplished in several ways. It may be programmed In
System via the serial port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of

flexibility for data storage field firmware upgrades, etc. Due to the architectural
solution chosen for an on-chip boot loader, flash memory available for users
code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB
respectively. The LPC2141/42/44/46/48 flash memory provides a minimum of
100,000 erase/write cycles and 20 years of data-retention.
On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The
SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44
and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In
case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly
by the USB can also be used as a general purpose RAM for data storage and
code storage and execution.
Memory map
The LPC2141/42/44/46/48 memory map incorporates several distinct
regions, as shown in Figure In addition, the CPU interrupt vectors may be
remapped to allow them to reside in either flash memory (the default) or on-
chip static RAM. Memory mapping table is shown in the table 4.1

Table 4.2: memory map table

Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt
request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored
Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable
settings. The programmable assignment scheme means that priorities of
interrupts from the various peripherals can be dynamically assigned and
adjusted. Fast interrupt request (FIQ) has the highest priority. If more than one
request is assigned to FIQ, the VIC combines the requests to produce the FIQ
signal to the ARM processor. The fastest possible FIQ latency is achieved when
only one request is classified as FIQ, because then the FIQ service routine does
not need to branch into the interrupt service routine but can run from the

interrupt vector location. If more than one request is assigned to the FIQ class,
the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt. Vectored IRQs have the middle
priority. Sixteen of the interrupt requests can be assigned to this category. Any
of the interrupt requests can be assigned to any of the 16 vectored IRQ slots,
among which slot 0 has the highest priority and slot 15 has the lowest. Non-
vectored IRQs have the lowest priority. The VIC combines the requests from all
the vectored and non-vectored IRQs to produce the IRQ signal to the ARM
processor. The IRQ service routine can start by reading a register from the VIC
and jumping there. If any of the vectored IRQs are pending, the VIC provides
the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are
active.
Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored
Interrupt Controller, but may have several internal interrupt flags. Individual
interrupt flags may also represent more than one interrupt source.
Fast general purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are
controlled by the GPIO registers. Pins may be dynamically configured as inputs
or outputs. Separate registers allow setting or clearing any number of outputs
simultaneously. The value of the output register may be read back, as well as
the current state of the port pins. LPC2141/42/44/46/48 introduce
accelerated GPIO functions over prior LPC2000 devices:
GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing.

Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte addressable.
Entire port value can be written in one instruction.
Features
Bit-level set and clear registers allow a single instruction set or clear of any
number of bits in one port.
Direction control of individual bits.
Separate control of output set and clear.
All I/O default to inputs after reset.
10-bit ADC
The LPC2141/42 contain one and the LPC2144/46/48 contain two

analog to digital converters. These converters are single 10-bit successive
approximation analog to digital converters. While ADC0 has six channels,
ADC1 has eight channels. Therefore, total number of available ADC inputs for
LPC2141/42 is 6 and for LPC2144/46/48 is 14.
Features
Measurement range of 0 V to VREF (2.0 V VREF VDDA).
Each converter capable of performing more than 400,000 10-bit samples per
second.
Every analog input has a dedicated result register to reduce interrupt
overhead.
Burst conversion mode for single or multiple inputs.
10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable

analog output. The maximum DAC output voltage is the VREF voltage.
Features
10-bit DAC.
Buffered output.
Power-down mode available.
Selectable speed versus power.
USB 2.0 device controller
The USB is a 4-wire serial bus that supports communication between a

host and a number (127 max) of peripherals. The host controller allocates the
USB bandwidth to attached devices through a token based protocol. The bus
supports hot plugging, unplugging, and dynamic configuration of the devices.
All transactions are initiated by the host controller. The
LPC2141/42/44/46/48 is equipped with a USB device controller that enables
12 Mbit/s data exchange with a USB host controller. It consists of a register
interface, serial interface engine, endpoint buffer memory and DMA controller.
The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer
or error condition is indicated via status registers. An interrupt is also
generated if enabled. A DMA controller (available in LPC2146/48 only) can
transfer data between an endpoint buffer and the USB RAM.
Features
Fully compliant with USB 2.0 Full-speed specification.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization of endpoints at run time.

Endpoint maximum packet size selection (up to USB maximum specification)

by software at run time.
RAM message buffer size based on endpoint realization and maximum packet
size.
Supports SoftConnect and GoodLink LED indicator. These two functions are
sharing one pin.
Supports bus-powered capability with low suspend current.
Supports DMA transfer on all non-control endpoints (LPC2146/48 only).
One duplex DMA channel serves all endpoints (LPC2146/48 only).
Allows dynamic switching between CPU controlled and DMA modes (only in
LPC2146/48).
Double buffer implementation for bulk and isochronous endpoints.
I2C-bus serial I/O controller

The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The
I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock
line (SCL), and a serial data line (SDA). Each device is recognized by a unique
address and can operate as either a receiver-only device (e.g., an LCD driver or
a transmitter with the capability to both receive and send information (such as
memory)). Transmitters and/or receivers can operate in either master or slave
mode, depending on whether the chip has to initiate a data transfer or is only
addressed. The I2C-bus is a multi-master bus, it can be controlled by more
than one bus master connected to it. The I2C-bus implemented in
LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).
Features
Compliant with standard I2C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.

Multi-master bus (no central master).

Arbitration between simultaneously transmitting masters without corruption
of serial data on the bus.
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a
full duplex serial interface, designed to handle multiple masters and slaves
connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data
transfer the master always sends a byte of data to the slave, and the slave
always sends a byte of data to the master.
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
SSP serial I/O controller

The LPC2141/42/44/46/48 each contain one SSP. The SSP controller is
capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. However, only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP
supports full duplex transfers, with data frames of 4 bits to 16 bits of data

flowing from the master to the slave and from the slave to the master. Often
only one of these data flows carries meaningful data.
Features
Compatible with Motorolas SPI, TIs 4-wire SSI and National Semiconductors
Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four bits to 16 bits per frame.
General purpose timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock
(PCLK) or an externally supplied clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers.
It also includes four capture inputs to trap the timer value when an input
signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an
application with or and and, as well as broadcast functions among them.
The LPC2141/42/44/46/48 can count external events on one of the capture
inputs if the minimum external pulse is equal or longer than a period of the
PCLK. In this configuration, unused capture lines can be selected as regular
timer capture inputs, or used as external interrupts.
Features
A 32-bit timer/counter with a programmable 32-bit prescaler.
External event counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot of
the timer value when an input signal transitions. A capture event may also
optionally generate an interrupt.
Four 32-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers,
with the following capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
Watchdog timer:
The purpose of the watchdog is to reset the microcontroller within a
reasonable amount of time if it enters an erroneous state. When enabled, the
watchdog will generate a system reset if the user program fails to feed (or
reload) the watchdog within a predetermined amount of time.
Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog
reset/interrupt to be disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (TPCLK 256 4) to (TPCLK 232 4) in
multiples of TPCLK 4.
Real-time clock
The RTC is designed to provide a set of counters to measure time when
normal or idle operating mode is selected. The RTC has been designed to use
little power, making it suitable for battery powered systems where the CPU is
not running continuously (Idle mode).

Features
Measures the passage of time to maintain a calendar and clock.
Ultra-low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week,
and Day of Year.
Can use either the RTC dedicated 32 kHz oscillator input or clock derived
from the external crystal/oscillator input at XTAL1. Programmable reference
clock divider allows fine adjustment of the RTC.
Dedicated power supply pin can be connected to a battery or the main 3.3 V.
Pulse width modulator

The PWM is based on the standard timer block and inherits all of its
features, although only the PWM function is pinned out on the
LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral
clock (PCLK) and optionally generate interrupts or perform other actions when
specified timer values occur, based on seven match registers. The PWM
function is also based on match register events. The ability to separately
control rising and falling edge locations allows the PWM to be used for more
applications.
System control
Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1
MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM
processor clock frequency is referred to as CCLK for purposes of rate

equations, etc. fosc and CCLK are the same value unless the PLL is running
and connected.
PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25
MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz
with a Current Controlled Oscillator (CCO). The multiplier can be an integer
value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on
this family of microcontrollers due to the upper frequency limit of the CPU).
The CCO operates in the range of 156 MHz to 320 MHz, so there is an
additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be
set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum
output divider value is 2, it is insured that the PLL output has a 50 % duty
cycle. The PLL is turned off and bypassed following a chip reset and may be
enabled by software. The program must configure and activate the PLL, wait for
the PLL to Lock, then connect to the PLL as a clock source. The PLL settling
time is 100 s.
Reset and wake-up timer
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin
and watchdog reset. The RESET pin is a Schmitt trigger input pin with an
additional glitch filter. Assertion of chip reset by any source starts the Wake-up
Timer (see Wake-up Timer description below), causing the internal chip reset to
remain asserted until the external reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the on-chip flash controller
has completed its initialization. When the internal reset is removed, the
processor begins executing at address 0, which is the reset vector. At that
point, all of the processor and peripheral registers have been
initialized to predetermined values. The Wake-up Timer ensures that the
oscillator and other analog functions required for chip operation are fully
functional before the processor is allowed to execute instructions. This is

important at power on, all types of reset, and whenever any of the
aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of
checking whether it is safe to begin code execution. When power is applied to
the chip, or some event caused the chip to exit Power-down mode, some time is
required for the oscillator to produce a signal of sufficient amplitude to drive
the clock logic. The amount of time depends on many factors, including the
rate of VDD ramp (in the case of power on), the type of crystal and its electrical
characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under
the existing ambient conditions.
Brownout detector
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on
the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt
signal to the VIC. This signal can be enabled for interrupt; if not, software can
monitor the signal by reading dedicated register. The second stage of low
voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when
the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of
the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal
operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a
regularly-executed event loop to sense the condition.
Code security
This feature of the LPC2141/42/44/46/48 allow an application to
control whether it can be debugged or protected from observation. If after reset
on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321

from address 0x1FC in flash, debugging will be disabled and thus the code in
flash will be protected from observation. Once debugging is disabled, it can be
enabled only by performing a full chip erase using the ISP.
External interrupt inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive
External Interrupt Inputs as selectable pin functions. When the pins are
combined, external events can be processed as four independent interrupt
signals. The External Interrupt Inputs can optionally be used to wake-up the
processor from Power-down mode. Additionally capture input pins can also be
used as external interrupts without the option to wake the device up from
Power-down mode.
Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors
that appear beginning at address 0x0000 0000. Vectors may be mapped to the
bottom of the on-chip flash memory, or to the on-chip static RAM. This allows
code running in different memory spaces to have control of the interrupts
Power control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle
mode and Power-down mode. In Idle mode, execution of instructions is
suspended until either a reset or interrupt occurs. Peripheral functions
continue operation during Idle mode and may generate interrupts to cause the
processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no
internal clocks. The processor state and registers, peripheral registers, and
internal SRAM values are preserved throughout Power-down mode and the
logic levels of chip output pins remain static. The Power-down mode can be
terminated and normal operation resumed by either a reset or certain specific
interrupts that are able to function without clocks. Since all dynamic operation

of the chip is suspended, Power-down mode reduces chip power consumption

to nearly zero.
VPB bus
The VPB divider determines the relationship between the processor clock
(CCLK) and the clock used by peripheral devices (PCLK). The VPB divider
serves two purposes. The first is to provide peripherals with the desired PCLK
via VPB bus so that they can operate at the speed chosen for the ARM
processor. In order to achieve this, the VPB bus may be slowed down to 12 to
14 of the processor clock rate. Because the VPB bus must work properly at
power-up (and its timing cannot be altered if it does not work since the VPB
divider control registers reside on the VPB bus), the default condition at reset is
for the VPB bus to run at 14 of the processor clock rate. The second purpose of
the VPB divider is to allow power savings when an application does not require
any peripherals to run at the full processor rate. Because the VPB divider is
connected to the PLL output, the PLL remains active (if it was running) during
Idle mode.
Emulation and debugging

The LPC2141/42/44/46/48 support emulation and debugging via a
JTAG serial port. A trace port allows tracing program execution. Debugging and
trace functions are multiplexed only with GPIOs on Port 1. This means that all
communication, timer and interface peripherals residing on Port 0 are available
during the development and debugging phase as they are when the application
is run in the embedded system itself.
EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The
debugging of the target system requires a host computer running the debugger
software and an EmbeddedICE protocol convertor. EmbeddedICE protocol

convertor converts the remote debug protocol commands to the JTAG data
needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) function

built-in. The DCC allows a program running on the target to communicate with
the host debugger or another separate host without stopping the program flow
or even entering the debug state. The DCC is accessed as a co-processor 14 by
the program running on the ARM7TDMI-S core. The DCC allows the JTAG port
to be used for sending and receiving data without affecting the normal program
flow. The DCC data and control registers are mapped in to addresses in the
EmbeddedICE logic.
Real Monitor
Real Monitor is a configurable software module, developed by ARM Inc.,
which enables real-time debug. It is a lightweight debug monitor that runs in
the background while users debug their foreground application. It
communicates with the host using the DCC, which is present in the Embedded
ICE logic. The LPC2141/42/44/46/48 contains a specific configuration of Real
Monitor software programmed into the on-chip flash memory.
UARTs
The LPC2141/42/44/46/48 each contain two UARTs. In addition to
standard transmit and receive data lines, the LPC2144/46/48 UART1 also
provide a full modem control handshake interface. Compared to previous
LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a
fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 with any crystal frequency
above 2 MHz In addition, auto-CTS/RTS flow-control functions are fully
implemented in hardware (UART1 in LPC2144/46/48 only).

Features
16 byte Receive and Transmit FIFOs.
Register locations conform to 550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in fractional baud rate generator covering wide range of baud rates
without a need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF)
flow control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interface signals.
This module also provides full support for hardware flow control (auto-CTS/RTS).
Universal Asynchronous Receiver/Transmitter 0 (UART0)

Features
16 byte Receive and Transmit FIFOs
Register locations conform to 550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in fractional baud rate generator with autobauding capabilities.
Mechanism that enables software and hardware flow control implementation.
Table 4.3 gives UART Pin description in controller
Table 4.3 pin description of UART in controller
Register description
UART0 contains registers organized as shown in Table 4.4. The Divisor
Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the
Divisor Latches.

table 4.3: register organization of UART0
UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when DLAB = 0,

Read Only)
The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx
FIFO contains the oldest character received and can be read via the bus
interface. The LSB (bit 0) represents the oldest received data bit. If the
character received is less than 8 bits, the unused MSBs are padded with
zeroes. The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to
access the U0RBR. The U0RBR is always Read Only. Since PE, FE and BI bits
correspond to the byte sitting on the top of the RBR FIFO (i.e. the one that will
be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the
U0LSR register, and then to read a byte from the U0RBR.
UART0 Receiver Buffer Register (U0RBR - address 0xE000 C000, when
DLAB = 0, Read Only) bit description

UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB =

0, Write Only) The U0THR is the top byte of the UART0 TX FIFO. The top byte
is the newest character in the TX FIFO and can be written via the bus
interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access
the U0THR. The U0THR is always Write Only.
UART0 Transmit Holding Register (U0THR - address 0xE000 C000, when
DLAB = 0, Write Only) bit description
UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM

-C004, when DLAB = 1)
The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate
Generator and holds the value used to divide the clock supplied by the
fractional prescaler in order to produce the baud rate clock, which must be 16x
the desired baud rate (Equation 1). The U0DLL and U0DLM registers together
form a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor and
U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.
Baudrates available when using 20 MHz peripheral clock (PCLK = 20 MHz)

UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0)

The U0IER is used to enable UART0 interrupt sources.
UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when
DLAB = 0) bit description

UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)

The U0IIR provides a status code that denotes the priority and source of
a pending interrupt. The interrupts are frozen during an U0IIR access. If an
interrupt occurs during an U0IIR access, the interrupt is recorded for the next
U0IIR access.

Interrupts are handled as described in Table 105. Given the status of

U0IIR[3:0], an interrupt handler routine can determine the cause of the
interrupt and how to clear the active interrupt. The U0IIR must be read in
order to clear the interrupt prior to exiting the Interrupt Service Routine. The
UART0 RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is
set whenever any one of four error conditions occur on the UART0 Rx input:
overrun error (OE), parity error (PE), framing error (FE) and break interrupt
(BI). The UART0 Rx error condition that set the interrupt can be observed via
U0LSR[4:1]. The interrupt is cleared upon an U0LSR read. The UART0 RDA
interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U0IIR[3:1] = 110).
The RDA is activated when the UART0 Rx FIFO reaches the trigger level
defined in U0FCR[7:6] and is reset when the UART0 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block
of data defined by the trigger level. The CTI interrupt (U0IIR[3:1] = 110) is a
second level interrupt and is set when the UART0 Rx FIFO contains at least
one character and no UART0 Rx FIFO activity has occurred in 3.5 to 4.5
character times. Any UART0 Rx FIFO activity (read or write of UART0 RSR) will
clear the interrupt. This interrupt is intended to flush the UART0 RBR after a
message has been received that is not a multiple of the trigger level size. For
example, if a peripheral wished to send a 105 character message and the
trigger level was 10 characters, the CPU would receive 10 RDA interrupts
resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending
on the service routine) resulting in the transfer of the remaining 5 characters.
The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt

and is activated when the UART0 THR FIFO is empty provided certain
initialization conditions have been met. These initialization conditions are
intended to give the UART0 THR FIFO a chance to fill up with data to eliminate
many THRE interrupts from occurring at system start-up. The initialization
conditions implement a one character delay minus the stop bit whenever
THRE=1 and there have not been at least two characters in the U0THR at one
time since the last THRE = 1 event. This delay is provided to give the CPU time
to write data to U0THR without a THRE interrupt to decode and service. A
THRE interrupt is set immediately if the UART0 THR FIFO has held two or
more characters at one time and currently, the U0THR is empty. The THRE

interrupt is reset when a U0THR write occurs or a read of the U0IIR occurs and
the THRE is the highest interrupt (U0IIR[3:1] = 001).
UART0 Transmit Enable Register (U0TER - 0xE000 C030)

LPC2141/2/4/6/8s U0TER enables implementation of software flow
control. When TXEn=1, UART0 transmitter will keep sending data as long as
they are available. As soon as TXEn becomes 0, UART0 transmission will
stop.Table describes how to use TXEn bit in order to achieve software flow
control.
UART0 Transmit Enable Register (U0TER - address 0xE000 C030) bit
description
Architecture
The architecture of the UART0 is shown below in the block diagram 4.3.
The VPB interface provides a communications link between the CPU or host
and the UART0. The UART0 receiver block, U0RX, monitors the serial input
line, RXD0, for valid input. The UART0 RX Shift Register (U0RSR) accepts valid
characters via RXD0. After a valid character is assembled in the U0RSR, it is
passed to the UART0 RX Buffer Register FIFO to await access by the CPU or
host via the generic host interface. The UART0 transmitter block, U0TX,
accepts data written by the CPU or host and buffers the data in the UART0 TX
Holding Register FIFO (U0THR). The UART0 TX Shift Register (U0TSR) reads

the data stored in the U0THR and assembles the data to transmit via the serial
output pin, TXD0. The UART0 Baud Rate Generator block, U0BRG, generates
the timing enables used by the UART0 TX block. The U0BRG clock input
source is the VPB clock (PCLK). The main clock is divided down per the divisor
specified in the U0DLL and U0DLM registers. This divided down clock is a 16x
oversample clock, NBAUDOUT. The interrupt interface contains registers
U0IER and U0IIR. The interrupt interface receives several one clock wide
enables from the U0TX and U0RX blocks. Status information from the U0TX
and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX
is stored in the U0LCR.
Fig 4.3: Architecture of UART

Chapter-5
R303A Series Fingerprint Identification Module

Fig 5.1: photograph of finger print module

Fingerprint modules processing , shown in figure 5.2 includes two
parts: fingerprint enrollment and fingerprint matching (the matching can be
1:1 or 1:N). When enrolling, user needs to enter the finger two times. The
system will process the two time finger images, generate a template of the
finger based on processing results and store the template. When matching,
user enters the finger through optical sensor and system will generate a
template of the finger and compare it with templates of the finger library. For
1:1 matching, system will compare the live finger with specific template
designated in the Module; for 1:N matching, or searching, system will search
the whole finger library for the matching finger. In both circumstances, system
will return the matching result, success or failure.
The following table 5.1 gives the specifications of finger print module R303a

Table 5.1 Specifications of fingerprint module

5.1 Serial Communication(P1)
When the FP module communicates with user device, definition of J1 is
as shown in the table 5.2:
Table 5.2: pin description of FP

5.2 Hardware connection and features
Via serial interface, the Module may communicate with MCU of 3.3V or
5V power: TD (pin 2 of P1) connects with RXD (receiving pin of MCU), RD (pin 3
of P1) connects with TXD (transferring pin of MCU). Should the upper
computer (PC) be in RS-232 mode, please add level converting circuit, like
MAX232, between the Module and PC. Serial communication protocol The

mode is semi duplex asynchronies serial communication. And the default baud
rate is 57600bps. User may set the baud rate in 9600 115200bps
Transferring frame format is 10 bit: the low-level starting bit, 8-bit data with
the LSB first, and an ending bit. There is no check bit.
Reset time
At power on, it takes about 500ms for initialization. During this period,
the Module cant accept commands for upper computer. Electrical parameter
(All electrical level takes GND as reference)
Power supply
The logic levels and their corresponding voltage levels are given in the
table 5.3 below

Table 5.3: logic levels and power supply specifications
IV System Resources
To address demands of different customer, Module system provides
abundant resources at users use.
Notepad
The system sets aside a 512-bytes memory (16 pages* 32 bytes) for
users notepad, where data requiring power-off protection can be stored. The
host can access the page by instructions of PS_WriteNotepad and PS_Read
Notepad.
Note: when write on one page of the pad, the entire 32 bytes will be
written in wholly covering the original contents.
Buffer
There are an image buffer and two 512-byte-character-file buffer within
the RAM space of the module. Users can read & write any of the buffers by
instructions.
Note: Contents of the above buffers will be lost at power-off.

Image buffer
Image Buffer serves for image storage and the image format is 256*288
pixels. When transferring through UART, to quicken speed, only the upper 4
bits of the pixel is transferred (that is 16 grey degrees). And two adjacent pixels
of the same row will form a byte before the transferring. When uploaded to PC,
the 16-grey-degree image will be extended to 256-grey-degree format. Thats 8-
bit BMP format. When transferring through USB, the image is 8-bit pixel, thats
256 grey degrees.
Character file buffer
Character file buffer, CharBuffer1, CharBuffer2, can be used to store
both character file and template file.
5.3 Fingerprint Library

System sets aside a certain space within Flash for fingerprint template
storage, thats fingerprint library. Contents of the library remain at power off.
Capacity of the library changes with the capacity of Flash, system will
recognize the latter automatically. Fingerprint templates storage in Flash is in
sequential order. Assume the fingerprint capacity N, then the serial number of
template in library is 0, 1, 2, 3 N. User can only access library by template
number. System Configuration Parameter To facilitate users developing,
Module opens part system parameters for use. And the basic instructions are
SetSysPara & ReadSysPara. Both instructions take Parameter Number as
parameter. When upper computer sends command to modify parameter,
Module first responses with original configurations, then performs the
parameter modification and writes configuration record into Flash. At the next
startup, system will run with the new configurations.
Baud rate control (Parameter Number: 4)

The Parameter controls the UART communication speed of the Module.

Its value is an integer N, N= [1, 12]. Corresponding baud rate is 9600*N bps
Security Level (Parameter Number: 5)
The Parameter controls the matching threshold value of fingerprint
searching and matching. Security level is divided into 5 grades, and
corresponding value is 1, 2, 3, 4, 5. At level 1, FAR is the highest and FRR is
the lowest; however at level 5, FAR is the lowest and FRR is the highest.
Data package length (Parameter Number: 6)
The parameter decides the max length of the transferring data package
when communicating with upper computer. Its value is 0, 1, 2, 3,
corresponding to 32 bytes, 64 bytes, 128 bytes, 256 bytes respectively.
System status register
System status register indicates the current operation status of the
Module. Its length is 1 word, and can be read via instruction ReadSysPara.
Definition of the register is as follows:
Note:
Busy1 bit. 1: system is executing commands; 0: system is free;
Pass1 bit. 1: find the matching finger; 0: wrong finger;
PWD1 bit. 1: Verified devices handshaking password.
ImgBufStat1 bit. 1: image buffer contains valid image.
Module password
At power-on reset, system first checks whether the handshaking
password has been modified. If not, system deems upper computer has no
requirement of verifying password and will enter into normal operation mode.
Thats, when Module password remains the default, verifying process can be
jumped. The password length is 4 bytes, and its default factory value is 0FFH,
0FFH, 0FFH, 0FFH. Should the password have be modified, refer to instruction
SetPwd, then Module (or device) handshaking password must be verified before
the system enter into normal operation mode. Or else, system will refuse to
execute and command. The new modified password is stored in Flash and
remains at power off.
Module address:
Each module has an identifying address. When communicating with
upper computer, each instruction/data is transferred in data package form,
which contains the address item. Module system only responds to data
package whose address item value is the same with its identifying address. The
address length is 4 bytes, and its default factory value is 0xFFFFFFFF. User
may modify the address via instruction SetAdder. The new modified address
remains at power off.
Random number generator Module integrates a hardware 32-bit random
number generator (RNG) (without seed). Via instruction GetRandomCode,
system will generate a random number and upload it.
Communication Protocol
The protocol defines the data exchanging format when ZFM-20 series
communicates with upper computer. The protocol and instruction sets apples
for both UART and USB communication mode. For PC, USB interface is
strongly recommended to improve the exchanging speed, especially in
fingerprint scanning device.
Data package format
When communicating, the transferring and receiving of
command/data/result are all wrapped in data package format.

The new modified password is stored in Flash and remains at power off.
Module address
Each module has an identifying address. When communicating with
upper computer, each instruction/data is transferred in data package form,
which contains the address item. Module system only responds to data
package whose address item value is the same with its identifying address. The
address length is 4 bytes, and its default factory value is 0xFFFFFFFF. User
may modify the address via instruction SetAdder. The new modified address
remains at power off. Random number generator Module integrates a hardware
32-bit random number generator (RNG) (without seed). Via instruction
GetRandomCode, system will generate a random number and upload it.
Module Instruction System
R303A series provide 23 instructions. Through combination of different
instructions, application program may realize muti finger authentication
functions. All commands/data are transferred in package format.

Chapter-6
Switches and Pushbuttons and LCD display
6.1Switches and Pushbuttons
This is the simplest way of controlling appearance of some voltage on

microcontrollers input pin. There is also no need for additional explanation of
how these components operate.
Fig 6.1 switch bounce patterns
This is about something commonly unnoticeable when using these

components in everyday life. It is about contact bounce, a common problem
with mechanical switches as shown in figure 6.1. If contact switching does not
happen so quickly, several consecutive bounces can be noticed prior to
maintain stable state. The reasons for this are: vibrations, slight rough spots
and dirt. Anyway, this whole process does not last long (a few micro- or
milliseconds), but long enough to be registered by the microcontroller.
Concerning the pulse counter, error occurs in almost 100% of cases.

Fig 6.2 Switch interfacing with microcontroller
The simplest solution is to connect simple RC circuit as shown in figure

6.2 which will suppress each quick voltage change. Since the bouncing time is
not defined, the values of elements are not strictly determined. In the most
cases, the values shown on figure are sufficient.
If complete safety is needed, radical measures should be taken. The

circuit (RS flip-flop) changes logic state on its output with the first pulse
triggered by contact bounce. Even though this is more expensive solution
(SPDT switch), the problem is definitely resolved. Besides, since the
condensator is not used, very short pulses can be also registered in this way.
In addition to these hardware solutions, a simple software solution is also
commonly applied. When a program tests the state of some input pin and finds
changes, the check should be done one more time after certain time delay. If
the change is confirmed, it means that switch (or pushbutton) has changed its
position. The advantages of such solution are: it is free of charge, effects of
disturbances are eliminated and it can be adjusted to the worst-quality
contacts.
6.2 LIQUID CRYSTAL DISPLAY:

LCD stands for Liquid Crystal Display. LCD is finding wide spread use
replacing LEDs (seven segment LEDs or other multi segment LEDs) because of
the following reasons:
1. The declining prices of LCDs.
2. The ability to display numbers, characters and graphics. This is in
contrast to LEDs, which are limited to numbers and a few characters.
3. Incorporation of a refreshing controller into the LCD, thereby relieving
the CPU of the task of refreshing the LCD. In contrast, the LED must be
refreshed by the CPU to keep displaying the data.
4. Ease of programming for characters and graphics.
These components are specialized for being used with the

microcontrollers, which means that they cannot be activated by standard IC
circuits. They are used for writing different messages on a miniature LCD.
Fig 6.3 LCD display

A model as shown in figure 6.3 here is for its low price and great
possibilities most frequently used in practice. It is based on the HD44780
microcontroller (Hitachi) and can display messages in two lines with 16
characters each. It displays all the alphabets, Greek letters, punctuation
marks, mathematical symbols etc. In addition, it is possible to display symbols
that user makes up on its own. Automatic shifting message on display (shift
left and right), appearance of the pointer, backlight etc. are considered as
useful characteristics.

Pins Functions
There are pins along one side of the small printed board used for
connection to the microcontroller. There are total of 14 pins marked with
numbers (16 in case the background light is built in). Their function is
described in the table 6.1 below:
Pin Logic
Function Name Description
Number State
Ground 1 Vss - 0V
Power supply 2 Vdd - +5V
Contrast 3 Vee - 0 Vdd
D0 D7 are interpreted as
0 commands
4 RS
1 D0 D7 are interpreted as
data
Write data (from controller
Control of 0 to LCD)
5 R/W
operating 1 Read data (from LCD to
controller)
0 Access to LCD disabled
1 Normal operating
6 E
From 1 Data/commands are
to 0 transferred to LCD
7 D0 0/1 Bit 0 LSB
8 D1 0/1 Bit 1
9 D2 0/1 Bit 2
Data / 10 D3 0/1 Bit 3
commands 11 D4 0/1 Bit 4
12 D5 0/1 Bit 5
13 D6 0/1 Bit 6
14 D7 0/1 Bit 7 MSB
Table 6.1 pin description of LCD
LCD screen:
LCD screen consists of two lines with 16 characters each. Each character
consists of 5x7 dot matrix. Contrast on display depends on the power supply
voltage and whether messages are displayed in one or two lines. For that
reason, variable voltage 0-Vdd is applied on pin marked as Vee. Trimmer
potentiometer is usually used for that purpose the connections are as shown in
figure 6.4. Some versions of displays have built in backlight (blue or green
diodes). When used during operating, a resistor for current limitation should be
used (like with any LE diode).
Fig 6.4:power supply connection to LCD

LCD Basic Commands
All data transferred to LCD through outputs D0-D7 will be interpreted as
commands or as data, which depends on logic state on pin RS:
RS = 1 - Bits D0 - D7 are addresses of characters that should be
displayed. Built in processor addresses built in map of characters and
displays corresponding symbols. Displaying position is determined by
DDRAM address. This address is either previously defined or the address
of previously transferred character is automatically incremented.
RS = 0 - Bits D0 - D7 are commands which determine display mode. List
of commands which LCD recognizes are given in the table 6.2 below:

Execution
Command RS RW D7 D6 D5 D4 D3 D2 D1 D0
Time
Clear display 0 0 0 0 0 0 0 0 0 1 1.64mS
Cursor home 0 0 0 0 0 0 0 0 1 x 1.64mS
Entry mode set 0 0 0 0 0 0 0 1 I/D S 40uS
Display on/off control 0 0 0 0 0 0 1 D U B 40uS
Cursor/Display Shift 0 0 0 0 0 1 D/C R/L X x 40uS
Function set 0 0 0 0 1 DL N F X x 40uS
Set CGRAM address 0 0 0 1 CGRAM address 40uS
Set DDRAM address 0 0 1 DDRAM address 40uS
Read BUSY flag (BF) 0 1 BF DDRAM address -
Write to CGRAM or DDRAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 40uS
Read from CGRAM or
1 1 D7 D6 D5 D4 D3 D2 D1 D0 40uS
DDRAM
Function Value Operation

I/D 1 Increment by 1
0 Decrement by 1
S 1 Display shift on
0 Display shift off
D 1 Display on
0 Display off
U 1 Cursor on
0 Cursor off
B 1 Cursor blink on
0 Cursor blink off
R/L 1 Shift right
0 Shift left
DL 1 8-bit interface
0 4-bit interface
N 1 Display in two
lines
0 Display in one
line
F 1 Character format
5x10 dots
0 Character format
5x7 dots
D/C 1 Display shift
0 Cursor shift
Table 6.2: LCD command description

LCD Connection
Depending on how many lines are used for connection to the
microcontroller, there are 8-bit and 4-bit LCD modes. The appropriate mode is
determined at the beginning of the process in a phase called initialization. In
the first case, the data are transferred through outputs D0-D7 as it has been
already explained. In case of 4-bit LED mode, for the sake of saving valuable
I/O pins of the microcontroller, there are only 4 higher bits (D4-D7) used for
communication, while other may be left unconnected.
Consequently, each data is sent to LCD in two steps: four higher bits are
sent first (that normally would be sent through lines D4-D7), four lower bits
are sent afterwards. With the help of initialization, LCD will correctly connect
and interpret each data received. Besides, with regards to the fact that data are
rarely read from LCD (data mainly are transferred from microcontroller to LCD)
one more I/O pin may be saved by simple connecting R/W pin to the Ground.
Even though message displaying will be normally performed, it will not be
possible to read from busy flag since it is not possible to read from display.
LCD Initialization
Once the power supply is turned on, LCD is automatically cleared. This
process lasts for approximately 15mS. After that, display is ready to operate.
The mode of operating is set by default. This means that:
1. Display is cleared
2. Mode
DL = 1 Communication through 8-bit interface
N = 0 Messages are displayed in one line
F = 0 Character font 5 x 8 dots
3. Display/Cursor on/off
D = 0 Display off
U = 0 Cursor off

B = 0 Cursor blink off

4. Character entry
ID = 1 Addresses on display are automatically incremented by 1
S = 0 Display shift off
Automatic reset is mainly performed without any problems. If for any

reason power supply voltage does not reach full value in the course of 10mS,
display will start perform completely unpredictably. If voltage supply unit can
not meet this condition or if it is needed to provide completely safe operating,
the process of initialization by which a new reset enabling display to operate
normally must be applied.
Algorithm according to the initialization is being performed depends on
whether connection to the microcontroller is through 4- or 8-bit interface. All
left over to be done after that is to give basic commands and of course- to
display messages. The algorithm is as shown in the figure 6.5

Fig 6.5 algorithm for initialization of 8-bit LCD
Contrast Control:
To have a clear view of the characters on the LCD, contrast should be
adjusted. To adjust the contrast, the voltage should be varied. For this, a
preset is used which can behave like a variable voltage device. As the voltage of
this preset is varied, the contrast of the LCD can be adjusted.
Potentiometer
Variable resistors used as potentiometers have all three terminals
connected. This arrangement is normally used to vary voltage, for example to
set the switching point of a circuit with a sensor, or control the volume
(loudness) in an amplifier circuit. If the terminals at the ends of the track are

connected across the power supply, then the wiper terminal will provide a
voltage which can be varied from zero up to the maximum of the supply.
LCD interface with the microcontroller (4-bit mode):
Chapter 7
Firmware Implementation of the project design
The firmware programmed in LPC2148 is designed to communicate with

Finger print and operates according the commands received from the Switches.
Therefore, the main firmware programmed can be divided into three parts:
1. Receive the Data from Finger print and processing and validating.
2. And take the data from switches and comparing with the data base
and updating the data base.
3. and display the command and display the result with respect to
the switch operations.

KEIL ARM Is Used For The Development Of Finger Print Based Electronic
Voting Machine
7.1.Vision3 Overview
The Vision3 IDE is a Windows-based software development platform that

combines a robust editor, project manager, and makes facility. Vision3
integrates all tools including the C compiler, macro assembler, linker/locator,
and HEX file generator. Vision3 helps expedite the development process of
your embedded applications by providing the following:
Full-featured source code editor,
Device database for configuring the development tool setting,
Project manager for creating and maintaining your projects,
Integrated make facility for assembling, compiling, and linking your

embedded applications,
Dialogs for all development tool settings,
True integrated source-level Debugger with high-speed CPU and

peripheral simulator,
Advanced GDI interface for software debugging in the target hardware

and for connection to Keil ULINK,
Flash programming utility for downloading the application program into

Flash ROM,
Links to development tools manuals, device datasheets & user's guides.
The Vision3 IDE offers numerous features and advantages that help you
quickly and successfully develop embedded applications. They are easy to use
and are guaranteed to help you achieve your design goals.

The Vision3 IDE and Debugger is the central part of the Keil
development tool chain. Vision3 offers a Build Mode and a Debug Mode.In the
Vision3 Build Mode you maintain the project files and generate the
application.
In the Vision3 Debug Mode you verify your program either with a powerful
CPU and peripheral simulator or with the Keil ULINK USB-JTAG Adapter (or
other AGDI drivers) that connect the debugger to the target system. The ULINK
allows you also to download your application into Flash ROM of your target
system.
Features and Benefits
Feature Benefit
The Vision3 Simulator is the only Write and test application code before
debugger that completely simulates production hardware is available.
all on-chip peripherals. Investigate different hardware
configurations to optimize the hardware
design.
Simulation capabilities may be Sophisticated systems can be accurately

expanded using the Advanced simulated by adding your own peripheral
Simulation Interface (AGSI). drivers.
The Code Coverage feature of the Safety-critical systems can be thoroughly

Vision3 Simulator provides tested and validated. Execution analysis
statistical analysis of your reports can be viewed and printed for
program's execution. certification requirements.

The Vision3 Device Database Mistakes in tool settings are practically

automatically configures the eliminated and tool configuration time is
development tools for the target minimized.
microcontroller.
The Vision3 IDE integrates Quickly access development tools and

additional third-party tools like third-party tools. All configuration details
VCS, CASE, and FLASH/Device are saved in the Vision3 project.
Programming.
The ULINK USB-JTAG Adapter The same tool can be used for debugging
supports both Debugging and Flash and programming. No extra configuration
programming with configurable time required.
algorithm files.
Identical Target Debugger and Shortens your learning curve.

Simulator User Interface.
Vision3 incorporates project Accelerates application development. While

manager, editor, and debugger in a editing, you may configure debugger
single environment. features. While debugging, you may make
source code modifications.
Interface
The Vision3 User Interface consists of menus, toolbar buttons, keyboard

shortcuts, dialog boxes, and windows that you use as you interact with and
manage the various aspects of your embedded project.
The menu bar provides menus for editor operations, project

maintenance, development tool option settings, program debugging,
external tool control, window selection and manipulation, and on-line
help.

The toolbar buttons allow you to rapidly execute Vision3 commands. A

Status Bar provides editor and debugger information. The various
toolbars and the status bar can be enabled or disabled from the View
Menu commands.
Keyboard shortcuts offer quick access to Vision3 commands and may

be configured via the menu command Edit Configuration Shortcut
Key.
The following sections list the Vision3 commands that can be reached by
menu commands, toolbar buttons, and keyboard shortcuts. The Vision3
commands are grouped mainly based on the appearance in the menu bar:
File Menu and File Commands
Edit Menu and Editor Commands
Outlining Menu
Advanced Menu
Selecting Text Commands
View Menu
Project Menu and Project Commands
Debug Menu and Debug Commands
Flash Menu
Peripherals Menu
Tools Menu
SVCS Menu

Window Menu
Help Menu
7.2.Creating Applications
This chapter describes the Build Mode of Vision3 and is grouped into the
following sections:
Create a Project: explains the steps required to setup a simple

application and to generate HEX output.
Project Target and File Groups: shows how to create application variants
and organized the files that belong to a project.
Tips and Tricks: provides information about the advanced features of the
Vision3 Project Manager.
This chapter uses the ARM as target architecture and only explains
generic features of the Vision3 IDE. Architecture specific information
(like bank switching for 8051) can be found in the Getting Started User's
Guide of the related toolchain.
Debugging
This chapter describes the Debug Mode of Vision3 and shows you how
to use the user interface to test a sample program. Also discussed are
simulation mode and the different options available for program debugging.
You can use Vision3 Debugger to test the applications you develop. The
Vision3 Debugger offers two operating modes that are selected in the Options
for Target Debug dialog.

Use Simulator configures the Vision3 Debugger as software-only

product that simulates most features of a microcontroller without
actually having target hardware. You can test and debug your embedded
application before the hardware is ready. Vision3 simulates a wide
variety of peripherals including the serial port, external I/O, and timers.
The peripheral set is selected when you select a CPU from the device
database for your target.
Use Advanced GDI drivers, like the ULINK Debugger to interface to your
target hardware. For Vision3 various drivers are available that interface
to:
JTAG/OCDS Adapter: which connects to on-chip debugging

systems like the ARM Embedded ICE.?
Monitor: that may be integrated with user hardware or is available

on many evaluation boards.
Emulator: which connects to the CPU pins of the target hardware?
In-System Debugger: which is part of the user application program

and provides basic test functions?
Test Hardware: such as the Infineon Smart Card ROM Monitor

RM66P or the Philips SmartMX DBox.
The Status Bar shows the current active debugging tool. In simulation
mode, timing statistics are provided.

Simulation
The Vision3 Debugger incorporates a C script language you can use to

create Signal Functions. Signal functions let you simulate analog and digital
input to the microcontroller. Signal functions run in the background while
Vision3 simulates your target program.
The Vision3 simulator simulates the timing and logical behavior of

serial communication protocols like UART, IC, SPI, and CAN. But Vision3
does not simulate the I/O port toggling of the physical communication pins on
the I/O port.
To provide fast simulation speed and optimum access to communication

peripherals, the logic behavior of communication peripherals is reflected in
virtual registers that are listed with the DIR VTREG command. This has the
benefit that you can easily write debug functions that stimulate complex
peripherals.
The chapter contains several Signal function temples that you may use
to simulate:
Digital Input
Push Button
Interrupt Signal
Impulse Patterns
Analog Input
Square Wave Signal
Saw Tooth Signal

Sine Wave
Noise Signal
Signal Combination
UART Communication
CAN Communication
IC Communication
SPI Communication
7.3. Flash Programming
Vision3 integrates Flash Programming Utilities in the project environment. All

configurations are saved in context with your current project.
You may use external command-line driven utilities (usually provided by the
chip vendor) or the Keil ULINK USB-JTAG Adapter. The Flash Programming
Utilities are configured under
Project Options Utilities.
Flash Programming may be started from the Flash Menu or before starting the
Vision3 Debugger when you enable Project Options Utilities Update
Target before Debugging.
For more information refer to the following topics:
Configure Flash Menu: configures the Flash Menu for using an external
command-line based utility or the Keil ULINK USB-JTAG Adapter.
ULink Configuration: explains the configuration settings for the Keil

ULINK USB-JTAG Adapter.

Pre-Download Scripts: allows to you program multiple applications or

configure the BUS system which is required for ULINK when you
program off-chip Flash devices.
Flash Algorithms: explains you how to create own Flash Program

Algorithms for the Keil ULINK USB-JTAG Adapter.
HEX File Flash Download: explains how to program existing HEX files.
The screenshot of 3vision is as shown in figure 7.1

Fig 7.1 screenshot of keil 3vision

Flash Magic
The screenshot of FLASH MAGIC is as shown in figure 7.2
Fig 7.2 screenshot of flashmagic

7.4.CODE:
/* Voting mechain using Finger print; */

#include <lpc214x.h>
#include "serial.h"
#include"lcd.h"
#define sw1 0x00100000
unsigned char i=0,fp[20],j=0,str[4],s=0,rec,dummy;
unsignedchar
enroll[12]={0xEF,0X01,0XFF,0XFF,0XFF,0XFF,0X01,0X00,0X03,0X01,0X00,0X05};
unsignedchar
generate_ch[13]={0xEF,0X01,0XFF,0XFF,0XFF,0XFF,0X01,0X00,0X04,0x02,0X01,0X00,0X0
8};
unsignedchar store[11]={0xEF,0X01,0XFF,0XFF,0XFF,0XFF,0X01,0X00,0X06,0X06,0X01};
unsignedchar
identify[12]={0xEF,0X01,0XFF,0XFF,0XFF,0XFF,0X01,0X00,0X03,0X11,0X00,0X15};
unsigned char b1=0,b2=0,i1=0,i2=0,id=0,id1=0,id2=0,cnt=0,eeprom_add=0,aa,n=0;
void clearfp(void);
void convert (unsigned char temp_value);
unsignedchar part_A=0,part_B=0,part_C=0,part_D=0,check=0,count=0,enroll_check=0,en_byte;
void long_delay (void );
/*-------------------------------------------------------------------------
main program
--------------------------------------------------------------------------*/
int main (void )
{
lcd_init();
again:
lcd_cmd(0x01,0);
delay(1000);
message(0," welcome ");
//lcd_cmd(0x01,0);
lcd_cmd(0xc0,0);
message(0,"EVM with FP");
delay(1000);
i=0;
while(1)
{
/******* Enrolling your ID *********************/
if((IOPIN0&sw1)==0) //checking for sw1

{
while((IOPIN0&sw1)==0);
lcd_cmd(0x01,0);
message(0,"Enrolling....");
i=0;
while(i<12)
{
send_ch_UART0(enroll[i]);
i++;
}
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();

rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
dummy=UART1_getch();
if(!rec)
{
lcd_cmd(0x01,0);
message(0,"Enrolling ok");
}
else
{
lcd_cmd(0x01,0);
message(0,"Enrolling not ok");
goto again;
}
i=0;
while(i<13)
{
send_ch_UART0(generate_ch[i]);
i++;
}
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();

rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
if(!rec)
{
lcd_cmd(0x01,0);
message(0,"gen char ok");
}
else
{
lcd_cmd(0x01,0);
message(0,"genchar not ok");
goto again;
}
i=0;
while(i<11)
{
send_ch_UART0(store[i]);
i++;
}
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();

rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
rec=UART1_getch();
if(!rec)
{
lcd_cmd(0x01,0);
message(0,"store ok");
}
else
{
lcd_cmd(0x01,0);
message(0,"store not ok");
goto again;
}
//check=1;
//enroll_check =0;
//en_byte=12;
}
/*********** identifying your ID *******************/

{
lcd_cmd(0x01,0);
message(0,"Identfying...");
i=0;
while(i<12)
{
send_ch_UART0(identify[i]);
i++;
}
check=1;
enroll_check =1;
en_byte=16;
}
/*********** final result *******************/

{
lcd_cmd(0x01,0);
message(1,"A B C D");
lcd_cmd(0xc0,0);
convert(part_A);
lcd_cmd(0xc4,0);
convert(part_B);
lcd_cmd(0xc7,0);
convert(part_C);
lcd_cmd(0xcc,0);

convert(part_D);
long_delay();
long_delay();
part_A=part_B=part_C=part_D=0;
goto again;
/********* receiving data from FP *********/
if(check==1)
{
count=0;
check=0;
while(count<en_byte)
{
fp[count]=UART0_getch();
count++;
}
long_delay();
n=0;
while(n<20)
{
if((fp[n]==0xEF)&&(fp[n+1]==0x01)&&(fp[n+9]==0x00))
{
lcd_cmd(0x01,0);
lcd_cmd(0x80,0);
message(1," Successfully ");

lcd_cmd(0xc0,0);
message(0xc0," completed");
b1=0; b2=0; i1=0; i2=0; id=0;
b1=fp[n+11]/10;
b2=fp[n+11]%10;
long_delay();
long_delay();
long_delay();
// lcd_cmd(0xc0,0);
// message(0xc0,"Id:");
// lcd_cmd(0xC3,0);
// lcd_cmd(b1+0x30,1);
// lcd_cmd(b2+0x30,1);
i1=b1-48;
i1=i1*10;
i2=b2-48;
i2=i2*1;
id=i1+i2;
long_delay();
if(enroll_check ==1)
{
lcd_cmd(0x01,0);
message(1," Plz poll ur vote ");
// clearfp();
enroll_check=0;
goto poll;
}
goto again;

else
{
lcd_cmd(0x01,0);
message(1," Failed");
long_delay();
goto again;
}
}
}
}
/*-----------------------------------------------------
polling your vote
----------------------------------------------------*/
poll:
while(1)
{
if((IOPIN0&sw1)==0) //sw1
{
part_A++;
lcd_cmd(0x01,0);
message(1,"Vote for part A");
long_delay();
goto again;
}
{
part_B++;

lcd_cmd(0x01,0);
message(1,"Vote for part B");
long_delay();
goto again;
// goto again;
}
{
part_C++;
lcd_cmd(0x01,0);
message(1,"Vote for part C");
long_delay();
goto again;
// goto again;
}
{
part_D++;
lcd_cmd(0x01,0);
message(1,"Vote for part D");
long_delay();
goto again;
// goto again;
}
}
}
/*------------------------------------------------
Clear the string clearfp
------------------------------------------------*/

void clearfp(void)
{
unsigned char cl=0;
while(cl<20)
{
fp[cl]=' ';
cl++;
}
j=0;
}
/*---------------------------------------------------------------------------------------
;convertion program Binary to ASCii ;
--------------------------------------------------------------------------------------*/
void convert(unsigned char temp_value)
{
unsigned char value,d1,d2,d3,k=0;
temp_value = temp_value;
value=temp_value/10;
d3=temp_value%10;
d1=value/10;
d2=value%10;
d1=d1+30;
// lcddata(d1);
delay(10);
d2=d2+30;
lcd_cmd(d2,1);
delay(4);
k++;

// msgdisplay(".");
d3=d3+0x30;
lcd_cmd(d3,1);
delay(10);
k=0;
}
/*---------------------------------------------------------------------------------
; long delay ;
----------------------------------------------------------------------------------*/
void long_delay (void )
{
unsigned int g;
for(g=0;g<500;g++)
delay(40000);
}
Chapter 8
Results and Discussions
8.1 Results
Assemble the circuit on the PCB as shown in Fig 5.1. After assembling
the circuit on the PCB, check it for proper connections before switching on the
power supply.
The EVM consists of a controller and switching unit , both the units are
working independently and in collaboration with each other as well.
The CU is accepting fingerprints in enrolling mode and is responding
accordingly.
In identifying and vote casting mode, the CU checks for finger print
detection routine

In identifying and vote casting mode, CU communicates with switching unit

in order to exchange various signals.
CU is counting the votes for individual candidate (20 in number) and total
number of votes cast can be checked at anytime.
In result mode, the CU displays the votes of individual candidate, in
consecutive order, whenever the Result Button is pressed.
The total number of votes can be checked in result mode.
In total, the complete system (including all the hardware components and
software routines) is working as per the initial specifications and requirements
of our project. Because of the creative nature of the design, and due to lack of
time, some features could not be fine-tuned and are not working properly. So
certain aspects of the system can be modified as operational experience is
gained with it. As the users work with the system, they develop various new
ideas for the development and enhancement of the project
8.2 Conclusion
The implementation of Finger print based voting machine using
microcontroller is done successfully. The communication is properly done
without any interference between different modules in the design. Design is
done to meet all the specifications and requirements. Software tools like Keil
Uvision Simulator, Flash Magic to dump the source code into the
microcontroller, Orcad Lite for the schematic diagram have been used to
develop the software code before realizing the hardware.
The performance of the system is more efficient. Reading the Data and
verifying the information with the already stored data and perform the specified
task is the main job of the microcontroller. The mechanism is controlled by the
microcontroller.

Circuit is implemented in Orcad and implemented on the microcontroller

board. The performance has been verified both in software simulator and
hardware design. The total circuit is completely verified functionally and is
following the application software. It can be concluded that the design
implemented in the present work provide portability, flexibility and the data
transmission is also done with low power consumption.
8.3.Advantages
Cost effective
Low power consumption
It is economical
Less manpower required
Time conscious, as less time required for voting & counting
Avoids invalid voting
Saves transportation cost due to its compact size
Convenient on the part of voter
8.4.Applications
This project can be used as an voting machine that can prevent rigging
during the elections in the polling booths.
Fast track voting which could be used in small scale elections, like
resident welfare association, panchayat level election and other
society level elections.
It could also be used to conduct opinion polls during annual share
holders meeting.
It could also be used to conduct general assembly elections where
number of candidates are less than or equal to eight in the current
situation

CHAPTER 9
FUTURE SCOPE
Number of candidates could be increased.
It could be interfaced with printer to get the hard copy of the result almost
instantly from the machine itself.
It could also be interfaced with the personal computer and result could be
stored in the central server and its backup could be taken on the other
backend servers.
Again, once the result is on the server it could be relayed on the network to
various offices of the election conducting authority. Thus our project could
make the result available any corner of the world in a matter of seconds

CHAPTER 10
REFERENCES
1. http://www.aimglobal.org/technologies/rfid/what_is_rfid.asp
2. http://www.rfidjournal.com/faq
3. http://www.technovelgy.com/ct/Technology-Article.asp
4. http://www.perada.eu/documents/articles-perspectives/an-
introduction-to-rfid-technology.pdf
5. http://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-
2007.pdf
6. www.ieee.org
7. http://www.zntu.edu.ua/base/lection/rpf/lib/zhzh03/8051_tutorial.pdf
8. http://www.taltech.com/TALtech_web/resources/intro-sc.html
9. http://focus.ti.com/lit/ds/symlink/max232.pdf
10. http://www.kmitl.ac.th/~kswichit/89prog/index.html
11. http://www.microdigitaled.com/8051/Software/keil_tutorial.pdf

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Finger print based electronic voting machine

Engr Rana Muhammad Shakeel

plz like my page:

For MORE PROJECTS:

FINGER PRINT BASED ELECTRONIC VOTING MACHINE

This project examines policy regarding the electronic approaches and

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1.1 Objective of the project

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1.2 Background of the Project

1.3 Organization of the Thesis

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Chapter 5 description of Finger Print module

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The embedded software is also called firm ware. The desktop/laptop

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3.1 Project Design

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Hardware implementation deals in drawing the schematic on the plane

The firmware part deals in programming the microcontroller so that it

MAX 232 ARM 7TDMI

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Fig 3.1 : block diagram

3.2 Power Supply:

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Fig 3.2 components of power supply

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Finger Print Module :

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LCD display and Switches:

The firmware programmed in LPC2148 is designed to communicate with

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3.3.System wiring diagram and working procedure:

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Fig 3.3: wiring diagram

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project Finger print technology and Embedded systems to implement the

The working of our EVM an be explained in three modes

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Identification and vote casting mode

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function as processing/controlling unit. For example, the remote control you

The key features of microcontrollers include:

High Integration of Functionality

Field Programmability, Flexibility

Microcontrollers often use EEPROM or EPROM as their storage device to

Assembly language is often used in microcontrollers and since they

Most microcontrollers will also combine other devices such as:

A Timer module to allow the microcontroller to perform tasks for certain

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An ADC to allow the microcontroller to accept analogue input data for

Figure 4.1 a typical microcontroller device and its different subunits

4.2.Microcontrollers versus Microprocessors

Microcontroller differs from a microprocessor in many ways. First and

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The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-

16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

In-System Programming/In-Application Programming (ISP/IAP) via on-

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Individual enable/disable of peripheral functions as well as peripheral

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The block diagram of LPC2148 is shown in figure 4.2 below

Fig : 4.2Block diagram