A Multilevel PWM Inverter Topology for Photovoltaic Applications

V.G. Agelidis D.M. Baker W.B. Lawrance C.V. Nayar

Centre for Renewable Energy Systems Technology Australia (CRESTA)
School of Electrical & Computer Engineering
Curtin University of Technology
GPO Box U1987, Perth, WA, 6001
AUSTRALIA

Abstract - A multilevel pulse-width modulated (PWM) single-

phase voltage-source inverter topology for photovoltaic
applications is discussed in this paper. The use of the phase
opposition (PO) carrier disposition multicarrier PWM
switching technique for this topology is presented. Inverter
switch control signals are derived. A 5-level and a 3-level
PWM voltage waveform across the load is generated, for high
and low modulation indexes respectively. Performance
characteristics including total harmonic distortion for a
range of operating conditions of the inverter are provided.
Theoretical considerations discussed in this paper are
supported with simulation and experimental results taken Fig. 1: The power circuit of the multilevel inverter for photovoltaic
from a low power laboratory prototype. applications.

I. INTRODUCTION increments of the reference waveform amplitude [ 121. The

inverter topology is suitalble for PV applications because
Solar technology in the form of photovoltaic based the separate voltage sources required suit the use of solar
inverter controlled remote area power supplies is utilised arrays.
extensively when extension of the electricity grid is not The paper is organised in the following way. Section I1
economically feasible [ 11. Appropriate voltage control presents the power iinverter topology capable of
methods adjusted for the various inverter topologies are synthesising multilevel PWM waveforms across the load.
used for systems that are not connected to the grid [2]. Section I11 introduces a switching technique suitable for
Improving the output waveform of the inverter reduces its the multilevel topology. In Section IV, the control signals
respective harmonic content, and hence the size of the for the inverter switches are derived. Simulation results for
filter used and the level of the electromagnetic interference the inverter system under consideration and experimental
(EM) gcnerated by the switching operation of the results taken from a low-power laboratory prototype are
converter. provided and discussed in Sections V and VI respectively.
Typically two or three level waveforms are produced Finally, conclusions are made in Section VII.
[2]. Multilevel technology promises a number of
advantages over the conventional technology especially for 11. SYSTEM DESCRIPTION
high power applications [3-81. Such methods however are
easily applicable in medium and low power applications The power circuit of the multilevel inverter topology
[9] and a number of them suit the PV applications [ 10-111. under consideration is shown in Fig. 1. It is constructed by
Several advantages of multilevel inverters over adding a bi-directional switch to the conventional bridge
conventional ones include an improved output waveform, topology. The bi-direction(a1switch controls current flow to
since the multilevel signal approaches the sinusoidal signal and from the neutral point of the two separate DC voltage
closer than the three-level signal, smaller filter size, lower sources and is composed of the two switches Sopand So,,.
switching losses, lower EM1 and lower acoustic noise. The inverter power circuit, with the appropriate control
Various multilevel switching techniques have been used, can apply across the load five different voltage levels,
investigated and presented within the technical literature namely 2E, E, 0, -E, -2E.
with their respective characteristics and advantages Switches SI, S2, S3, !j.4 have a voltage rating of 2E
theoretically discussed [ 121. However, regardless of the which is the DC bus voltage (Fig. 1). Switches Sop and So,
switching technique chosen, the gating signals to suit a have a voltage rating of E which is half the DC
particular inverter topology must be derived as it is not a bus voltage. As a consequence these two switches would be
straightforward approach. of a lower cost than switches S, through S4. The
The objective of this paper is to report the application antiparallel diodes across, the switches allow continuous
of a multicarrier PWM technique [12] to a single-phase current flow and thus help to maintain a sinusoidal output
multilevel inverter topology [ 111. The PWM technique is current. Furthermore, thr: bidirectional switch could be
the phase opposition (PO) carrier disposition method built with the two switches Sopand So,connected simply in
which uses several triangular carriers disposed in series and not in parallel ?withthe extra blocking diodes as
contiguous bands, with each carrier displaced by shown in Fig. 1.

IEEE Catalog Number: 97TH8280 - 589 - ISIE'97 - Guimarks, Portugal

-

1 ModeII: 0 < 0 i < # ~ and # 2 < ~ t 2 7 r (2)

ModeIII: 7 c < ~ t < # ~and # 4 < ~ t 1 2 ~ (3)
0.5 Mode IV: #3 < a t <-#4 (4)
In order to control the inverter, a multicarrier
disposition PWM technique is used. Multicarrier
disposition PWM techniques recently presented in [ 121
0
entail the natural sampling of a single modulating or
reference waveform typically being sinusoidal, through
several carrier signals typically being triangular. For an n-
-0.5 level system, that is to produce a phase voltage waveform
with n-1 levels plus the zero, n-I carrier signals are
required. They all have the same frequency and peak-peak
-1
2n amplitude, and each structured such that all carriers are
contiguous.
In general, the phase displacement between any two of
Fig. 2 : Multilevel inverter switching modes with respect to the per unit (pu)
amplitude of the output signal. the contiguous triangular carriers is free, therefore a
number of combinations can be studied as follows:
1. The carriers are alternatively in opposition (APO
disposition).
HighLevel 11 2E I E I o* I -E
2. All the carriers above the zero value reference are in
~ o w ~ e v e1 l E 0 I -E I -2E
phase but in opposition with those below (PO
~~

Table 1: Multilevel inverter modes of operation and voltage levels of the disposition).
inverter unfiltered output voltage signal across the load. 3. All the carriers are in phase (PH disposition).
Additional combinations of carrier phase displacement
are possible for the 5-level model, however the minor
differences evident between these and the aforementioned
techniques selected for investigation would result in
similar output waveform characteristics.
The multilevel phase opposition (PO) multicarrier
disposition method (Fig. 3) was used to derive the switch
gating signals for the multilevel inverter under
consideration (Fig. 1).
The exchanging phase angles can be shown to be
Table 2: Multilevel inverter switch states and state of the inverter unfiltered dependant the amp1itude index Or
output voltage signal across the load. modulation index, MO, as in Fig. 4. For the 5-level PO
disposition PWM technique then, the amplitude
modulation index as defined as follows:
111. A MULTILEVEL PWM TECHNIQUE M a =- 4
2AC
During One cycle of the output frequency of 50 Hz the where A, is the per unit (pu) carrier (triangular) peak-peak
inverter operates through four modes. These operational value and A , is the (pu) peak value of the modulating
modes are shown in Fig. 2 with respect to the per unit (PU) (sinusoidal) signal.
output voltage signal. Furthermore, the frequency modulation index is defined
Each of these operational modes has a high level and a as:
low level as shown in Table 1. The five output voltage
fc (6)
levels are obtained by the switch combinations shown in Mf =-so
Table 2. wheref, is the frequency of the carrier (triangular) signal
From Table 1 and Table 2, the voltage levels 0 and a d fo is the frequency of the modulating (sinusoidal)
O* are the same value. However, for commutation
purposes the switch configuration is different for the zero Whilst A, A,, or equivalently when the amplitude
~

voltage level in the first half cycle of the output voltage to modulation index is greater than 0.5, the exchanging phase
that in the second half cycle.
angles are defined by:
As can be seen from Fig. 2, the interval of each mode
varies with the amplitude of the required output sinusoid. = sin-1 ( AA,
m] (7)
The phase angles of mode change h, h, h and &
determine also the time that the inverter operates within a 42 = 7c - 41 (8)
certain mode. For clarity purposes and referring to Fig. 2, 43 = K + + l (9)
the four modes fall within the following boundaries:
#4 =2fl-41 (10)
Mode I: 41 < ~t s 42 (1)

IEEE Catalog Number: 97THS280 -590- ISIE97 - Guimarbs, Portugal

 For A, SA^, or equivalently when the amplitude
modulation index is less than 0.5, the exchanging phase
angles are equal to
n decision signals together through appropriate logic gates.
41 = 4 2 'T
3n
43 = 4 4 =1
The variation in the mode exchange angles with the
modulation index are shown in Fig. 4. Therefore for the
modulation index less than 0.5 the inverter does not
operate in either Mode I or Mode IV and as such produces
only a three level output as shown in Fig. 10.
During the first half cycle of the output voltage and
assuming that the modulation index is greater than 0.5, the
inverter produces three output levels namely 0, E and 2E.
During the second half cycle the inverter produces another
three voltage levels namely 0*, -E and -2E. As can be seen
from Table 2 switch Szis OFF during the first half cycle
and ON for the second half cycle. Conversely switch S4 is
ON for the first half cycle and OFF for the second half
cycle. Therefore the switching frequency of switches S, and
S4 is equal to the output frequency of 50 Hz and thus low
frequency switches such as BJTs can be used. Also the
switching function for Szis opposite to that for S4. Table 2
also shows that the switching function for Sopis opposite to
that for S I and the switching function for So,is opposite to
that for S3. That is, whenever switch Sop is ON, switch SI is
OFF and whenever switch So, is ON, switch S3 is OFF and
vice versa.
In order to operate the inverter then, the switch gating
signals need to be derived. However due to the above
relationships only three gating signals need to be found
with these being the ones for switches Sop,So, and SZ. The
gating signals for switches S I , S3 and S4 are simply the
logical inverse of the gating signals for switches Sop,So,
and S2 respectively.
IV. CONTROL SIGNALS
For illustrative purposes only, the PO carrier
disposition PWM technique (Fig. 3) with a carrier
frequencyf, of 1800 Hz was used. The frequency of the
modulating signal was chosen to be 50 Hz. The frequency
modulation index is then M ~ 3 6 . For this carrier
disposition PWM technique as mentioned earlier, the
carrier signals above zero are all in phase and out of phase
with all carriers below zero. This is shown in Fig. 3. The
unfiltered output voltage waveform across the load using
the multilevel inverter shown in Fig. 1 then results in that
of Fig. 5 when M,=0.8.
From Table 2 the switch gating signals can be derived
to match the output voltage level given in Fig. 5. The
construction of these switch gating signals from the
switching state table is shown in Fig. 6 . At a particular
instant in time, if the load voltage is 0 then switches Son,
SI
and S, are OFF and switches Sop,S3and S4 are ON. If the
load voltage is 2E then switches Sop,S2 and S3are OFF and
switches So,, SI and S, are ON. This process is followed for
the whole cycle of the output waveform.
Now that the switching technique and carrier frequency
IEEE Catalog Number: 97TH8280 - 591 -
have been set, the derivatiion of the gating signals in the
physical inverter control needs be explained. The gating
signals are constructed by adding portions of the PWM
The PWM decision signals, as explained in Section 111, are
derived from the intersectlions between the carrier signals
and the modulating signal. The decision signals for the PO
disposition method are given in Fig 8, and this shows the
decision signals only occurring during those time intervals
where the modulating signal intersects with the respective
carrier signal.
From Fig. 8 and referring to Fig. 3, C1 represents
carrier 1 and modulating signal intersections; C2 represents
carrier2 and modulating signal intersections; C3 represents
carrier3 and modulating signal intersections and C,
represents carrier4 and modulating signal intersections.
The switch gating signals are made up of portions of these
signals. There are six regions that make up one cycle of the
output and these are defiined in Fig. 9. The regions are
given by the mode exchange phase angles qh, &, & and b4
defined in section I11 and Fig. 9. Thus the six regions are
as follows:
(i) 0 < time 5 Qll,
(ii) < time 5 42,
(iii) (z < time s A-,
(iv) n < tJmeI 4 3 ,
(v) 4 3 < time I 4 4 ,
(vi) b4 < time < 2a
and are shown in Fig. 9.
Having the PWM decision signals of Fig. 9 and the
output region pulses of Fig. 8 it is now possible to define
the switching signal for each switch. The Boolean
expressions that follow would be implement by the use of
logical AND and OR gales. The switching functions of
Fig. 6 are then given by
Sop =RI +R2 *Cl +R3 +R4 *C3 + R , +&*C3 (13)
So, = RI C2 + R2 +R3 C2 -I
R4 +Rs C4 +& (14)
s, =Top (15)
S2 = R4 + R , +& (16)
s3 = so, (17)
S4 =Rl+R;!+R3 (18)
where " + is a logical OR., " 0 I' is a logical AND and
I'
I' - 'I is a logical inverse or NOT.
When constructing the physical circuit the signals C1,
C, C3 and C4 come from comparators which compare the
respective carrier signal and the modulating signal; the
signals R I , R2, R3, R4,Rs and R6 come from a memory
device (EPROM) which varies the pulse duration
according to eqns. (7), (8)i (9) and (10). These signals are
then passed through appropriate logic gates as defined by
the above equations.
For an amplitude modlulation index less than 0.5, the
duration of the R2 and h ! ~ signals is zero. However the
above logic still produces the appropriate switch gating
signals to produce the required output. Since the amplitude
modulation index is less than 0.5, the multilevel output
ISIE'97 - GuimarLs, Portugal
 0.

.2

L.3
3
Frequency @Hz)

Fig. 7: Frequency spectra of the inverter unfiltered output voltage across the
Fig. 3: The multicamier phase opposition (PO) disposition PWM technique load vs. modulation index, Mu for the multicanier phase opposition
for M, = 0.8, A4 - 36. disposition PWM technique and forM - 36, fo= 50 Hz..
f- f-
271 -

c2

I .............
P
____
__----_____------
C__-----.

c3
i
niu I 'B ua
I

0 I I I 1 I I I I , t
0 5 10 15 20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (ms)
Modulation Index, Ma
Fig. 4 : Variation in mode exchange angles VS. modulation index, Ma. Fig. 8: Decision signals of the multicarrier phase opposition disposition
PWM technique and forM, = O.S,Mf= 36, fo= 50 Hz..

RI

R4

5 10 15 R6 I
Thc ("6)
0 41 P n 43 c
Fig. 5 : Inverter output voltage waveform (5-level) with multicarrier phase
opposition disposition PWM technique for Mu = 0.8,M - 36, fo= 50 Hz. Fig. 9: Output regions for gating signals whenMU > 0.5.
f-

f------
s3 ni

s4 1 0
0 5 io 15 20

Time (ms)

Fig. 6: Inverter switch gating signals for multicarrier phase opposition Fig. 10: Inverter output voltage waveform (3-level) with multicarrier phase
disposition PWM technique forM, = 0.8, Mf= 36,fo = 50 Hz. opposition disposition PWM technique for M, = 0.4,M - 36, fo = 50 Hz.
f-

IEEE Catalog Number: 97THSZ80 - 592 - ISIE'97 - GuimarHes, Portugal

 reduces to three level as explained in section I11 and shown
in Fig. 10. The corresponding switch gating signals for
2 1 M,=0.4 and M ~ 3 are6 shown in Fig. 11.

V. SIMULATION RESULTS
SZ 2The multilevel inverter was simulated for the
parameters previously discussed. The results are presented
in Figs. 5 and 10 for modulation index of 0.8 and 0.4
s4
respectively. It is revealed that the inverter produces a
0 5 IO I5 20 voltage output signal that has a different number of levels
Time (ms) depending upon the modulation index.
Fig. 11: Inverter switch gating signals for the multicarrier phase opposition The performance of the inverter with the multilevel
disposition PWM technique, andM, =0.4,Mf= 36, A= 50 Hz..
PWM technique used was evaluated for various values of
DF2
the amplitude modulation inidex.
The second-order distorlion factor is chosen because it
reflects the amount of harmonic distortion that remains in
a particular waveform after ithe signal has been subjected to

%DF2 = x($)
a second-order filter, and it is defined as follows:
m

y n=2,3 .......
The calculated values of the distortion factor as a
function of the modulation index are plotted in Fig. 12.

0 0.1 0.2 0.3 04 0.5 0.6 0.7 0.8 0.9 1 VI. EXPERIMENTAL RESULTS
MU
Fig. 12: Distortion factor DF2 for second-order filtering for the multilevel
inverter with the multicarrier phase opposition disposition PWM technique
The multilevel inverter under consideration was built
vs. modulation index and forM - 36,f,= 50 Hz. and tested in the laboratory. The phase opposition
f- disposition PWM technique was used to control the
inverter. The carrier frequeincy was chosen to be 1800 Hz.
The inverter output voltage is shown in Figs. 13 and 14 for
modulation index of 0.8 and 0.4 respectively. Comparison
of Figs. 5 and 13 and Figs. 10 and 14 reveals that the
simulation and experimental results are in close
agreement. Furthermore, the load current waveform for an
inductive load is shown for the two modulation indexes of
0.8 and 0.4 in Figs. 13 and 14 respectively.

VII. CONCLUSION
I .I

Fig. 13: Experimental results - Inverter voltage waveform for Ma=0.8, The principles of operation of a multilevel (5-level)
A4 -36 and current waveform for inductive passive load. PWM single-phase inverter topology suitable for
f photovoltaic applications have been presented in this
paper. A phase-opposition (PO) carrier disposition PWM
technique has been used along with the appropriate logic
circuit to derive the inverter switch gating signals. The
inverter generates a 5-level output waveform for
modulation indexes above 0.5 and a 3-level output
waveform for modulation indexes below 0.5. Theoretical
considerations have been verified by simulation and
experimentally on a low-power laboratory prototype.

VIII. ACKNOWLEDGEMENT

The authors want to express their appreciation to Mr.

Fig. 14: Experimental results - Inverter voltage waveform for Ma=0.4, Daniel Taylor for his assistance with the generation of
M -36 and current waveform for inductive passive load.
f simulated waveforms and graphics.

IEEE Catalog Number: 97TH8280 - 593 - ISIE97 - Guimar&s, Portugal

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ISIE'97 - Guimariies, Portugal