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VER : F3B
VM9M Block Diagram Intel UMA
A A

FAN & THERMAL POWER


Penryn EMC1423-1-AIZL-TR
PG 31 REGULATOR CPU VR
POWER (478 Micro-FCPGA) +1.5V_RUN/+1.05V_VCCP PG 37 PG 39
CLOCK REGULATOR REGULATOR
SLG8SP513V +1.8V_SUS /+0.9V_DDR_VTT +3.3V_ALW/+5V_SUS/+15V_ALW
BATT (QFN-64)
PG 3,4
AC/BATT CHARGER PG 36 PG 17 PG 38 PG 40
CONNECTOR 800/1066 MHz
RUN POWER SW
PG 42 +3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V PG 41 LVDS Panel Connector
Cantiga (WXGA) PG 17

B
VGA B

CRT CONN.
DDR2-SODIMM*2 667/800 MHZ DDR II 1299 uFCBGA PG 19
PG 15,16
PG 5,6,7,8,9,10 RTL8111DL RJ45/Magnetics
GLAN PG 34
PG 34
DMI interface
SATA-ODD SATA PCIE
PG 28 PCIE MINI-CARD
WLAN
PG 26
SATA-HDD SATA PCIE
PG 28 ICH9-M
PCIE
Bluetooth USB 2.0 676 BGA
C USB2.0 EXPRESS-CARD34 C
PG 26 PG 21
USB2.0
IHDA USB conn x 2 PG 27
PG 11,12,13,14
USB conn x 2
Board to board PG 33
LPC
USB2.0
AUDIO/AMP Panel Connector
MODEM (AMOM) (To CCD) PG 18
CX20583-10z
CX20548-11Z
PCIE 3-in-1 Card Reader Card Reader CONN.
PG 32 Board to board KBC
ITE8502 R5U230(1394a+Media)
18X8 1394a CONN
Keyboard
Audio PG 23 Board to board PG 33
Audio SPK RJ-11conn PG 29
D
Jacks x2 D

conn 2Wx1 SPI PS/2


PG 32 PG 33
PG 32 USER QUANTA
FLASH
2M bytes
Touchpad INTERFACE COMPUTER
PG 30 Title
Schematic Block Diagram
PG 24 PG 29 Size Document Number Rev
VM9M 1A

Date: Monday, June 08, 2009 Sheet 1 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

Table of Contents Power States


CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION SIGNAL ACTIVE IN
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,18,24,36,37,3,8,39,40,44 MAIN POWER S0~S5
3-4 Penryn
+RTC_CELL +3.0V~+3.3V 11,14,23,24 RTC S0~S5
5-10 Cantiga
A 11-14 ICH9M +3.3V_ALW +3.3V 3,23,24,30,35,36,38,40,41,42,45 8051 POWER ALWON S0~S5 A

15-16 DDRII SO-DIMM(200P)


+5V_ALW2 +5V 37,38,40,41,42 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18 LCD Conn. +15V_ALW +15V 11,18,40,41 LARGE POWER +5V_ALW S0~S5
19 CRT Conn
+3.3V_LAN +3.3V 34 LAN POWER
21 Express card
23 SIO (ITE8512) +5V_SUS +5V 14,27,30,39,40,41,44 SLP_S5# CTRLD POWER SUS_ON
24 FLASH/RTC
+3.3V_SUS +3.3V 3,11,12,13,14,18,25,30,37,39,41,45 SLP_S5# CTRLD POWER 3.3V_SUS_ON
25 BLANK PAGE
26 Mini Card / BT +1.8V_SUS +1.8V 6,8,9,15,37,38,41 SODIMM POWER DDR_ON
27 USB
+0.9V_DDR_VTT +0.9V 16,38,41 SODIMM POWER 0.9V_DDR_VTT_ON
28 SATA Conn
29 TP / KEYBOARD +5V_RUN +5V 14,18,19,21,25,28,29,30,31,32,41,44 SLP_S3# CTRLD POWER RUN_ON
30 SWITCH /LED 3,6,8,9,11,12,13,14,15,17,30,31,32,34,18,19,
+3.3V_RUN +3.3V 20,21,23,25,26,28,41,44,45 SLP_S3# CTRLD POWER 3.3V_RUN_ON
31 FAN & Thermal
B 32 Audio CODEC/Phone Jack +1.5V_RUN +1.5V 4,9,14,26,37,41,44 CALISTOGA/ICH8 POWER 1.5V_RUN_ON B

33 Board To Board
+1.05V_VCCP +1.05V 3,4,6,8,9,11,14,37,44 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
34 LAN / TRANSFORM
35 BLANK PAGE +VCC_CORE +0.7V~+1.77V 4,39 CPU CORE POWER IMVP_VR_ON
36 Battery Selector & Charger LCDVCC_TST_EN
+LCDVCC +3.3V 18 LCD Power & ENVDD
37 1.05VCCP / 1.5VRUJN
38 DDR2_1.8VSUS, 0.9V +5V_MOD +5V 28 Module Power
39 CPU_MAX17410(2phase)
+5V_HDD +5V 28 HDD Power
40 MAX17020 (+5.5V,+3,3V)
41 RUN Power Switch +PBATT +10V~+17V 42 MAIN BATTERY CHG_PBATT
42 DCIN,Batt
43 PAD& SCREW
44 EMI CAP
45 SMBUS BLOCK
46 Power Block Dianram
C C

GND PLANE PAGE DESCRIPTION

GND ALL

D D

QUANTA
Title
COMPUTER
Index & Power Status

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 2 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

H_A#[3..16] U16A H_D#[0..63] U16B H_D#[0..63]


[5] H_A#[3..16] [5] H_D#[0..63] H_D#[0..63] [5]
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# [5] D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# [5] D[1]# D[33]#
H_A#5 H_D#2 H_D#34

ADDR GROUP 0
L4 G5 H_BPRI# [5] E26 V24
H_A#6 A[5]# BPRI# H_D#3 D[2]# D[34]# H_D#35
K5 G22 V26
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 H5 H_DEFER# [5] F23 V23
H_A#8 N2 A[7]# DEFER# F21 H_D#5 G25 D[4]# D[36]# T22 H_D#37
A[8]# DRDY# H_DRDY# [5] D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# [5] D[6]# D[38]#
H_A#10 H_D#7 H_D#39

DATA GRP 0

DATA GRP 2
N3 H_BR0# [5] E23 U23
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 F1 K24 Y25
H_A#12 P2 A[11]# BR0# R26 56 H_D#9 G24 D[8]# D[40]# W22 H_D#41
H_A#13 A[12]# H_IERR# H_D#10 D[9]# D[41]# H_D#42

CONTROL
L2 D20 1 2 +1.05V_VCCP J24 Y23
A
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43 A
P4 B3 H_INIT# [11] J23 W24
H_A#15 A[14]# INIT# H_D#12 D[11]# D[43]# H_D#44
P1 H22 W25
H_A#16 R1 A[15]# H4 H_D#13 F26 D[12]# D[44]# AA23 H_D#45
A[16]# LOCK# H_LOCK# [5] D[13]# D[45]#
M1 H_D#14 K22 AA24 H_D#46
[5] H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 Reserve from EMI R90 1 2 0 603 H_D#15 H23 AB25 H_D#47
[5] H_REQ#[0..4] RESET# H_RESET# [5] D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# [5]
H_REQ#4 L1 H_D#[0..63] H_D#[0..63]
H_A#[17..35] REQ[4]# [5] H_D#[0..63] H_D#[0..63] [5]
G6 H_D#16 N22 AE24 H_D#48
[5] H_A#[17..35] HIT# H_HIT# [5] D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# [5] D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# ITP_BPM#0 H_D#19 D[18]# D[50]# H_D#51

ADDR GROUP 1
R3 AD4 PAD T30 R23 AB22
H_A#20 A[19]# BPM[0]# ITP_BPM#1 H_D#20 D[19]# D[51]# H_D#52
W6
A[20]# BPM[1]#
AD3 PAD T34 Layout Note: L23
D[20]# D[52]#
AB21
H_A#21 ITP_BPM#2 H_D#21 H_D#53

XDP/ITP SIGNALS
U4 AD1 PAD T112 Place voltage M24 AC26
H_A#22 A[21]# BPM[2]# ITP_BPM#3 H_D#22 D[21]# D[53]# H_D#54

DATA GRP 1
Y5 AC4 L22 AD20

DATA GRP 3
A[22]# BPM[3]# PAD T29 divider within D[22]# D[54]#
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
A[23]# PRDY# PAD T111 D[23]# D[55]#
H_A#24 R4 AC1 ITP_BPM#5 0.5" of GTLREF H_D#24 P25 AF23 H_D#56
H_A#25 A[24]# PREQ# ITP_TCK H_D#25 D[24]# D[56]# H_D#57
T5 AC5 pin P23 AC25
H_A#26 T3 A[25]# TCK AA6 ITP_TDI H_D#26 P22 D[25]# D[57]# AE21 H_D#58
H_A#27 A[26]# TDI ITP_TDO H_D#27 D[26]# D[58]# H_D#59
W2 AB3 T24 AD21
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 AB5 R24 AC22
H_A#29 A[28]# TMS ITP_TRST# H_D#29 D[28]# D[60]# H_D#61
Y4 AB6 L25 AD23
H_A#30 U2 A[29]# TRST# C20 ITP_DBRESET# H_D#30 T25 D[29]# D[61]# AF22 H_D#62
A[30]# DBR# PAD T114 D[30]# D[62]#

2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 W3 A[31]# R290 L26 D[31]# D[63]# AE25
A[32]# [5] H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 [5]
H_A#33 AA4 THERMAL R16 56 +1.05V_VCCP 1K/F M26 AF24
A[33]# [5] H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 [5]
H_A#34 AB2 N24 AC20
A[34]# [5] H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 [5]
B H_A#35 AA3 D21 H_PROCHOT# B
A[35]# PROCHOT# PAD T1

1
V1 A24 H_THERMDA V_CPU_GTLREF AD26 R26 COMP0 Note:
[5] H_ADSTB#1 ADSTB[1]# THERMDA GTLREF
THERMDC
B25 H_THERMDC R14 2 1 *1K/F_NC CPU_TEST1 C23
TEST1
MISC COMP[0]
COMP[1]
U26 COMP1
H_DPRTSTP need to daisy chain

1
A6 R17 2 1 *1K/F_NC CPU_TEST2 D25 AA1 COMP2
[11] H_A20M# A20M# TEST2 COMP[2] from ICH9 to IMVP6 to CPU.
H_THERMTRIP# R289 PAD T96 CPU_TEST3 COMP3
ICH

[11] H_FERR# A5 C7 H_THERMTRIP# [6,11] C24 Y1


C4 FERR# THERMTRIP# 2K/F PAD T97 CPU_TEST4 AF26 TEST3 COMP[3]
[11] H_IGNNE# IGNNE# TEST4
PAD T110 CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# [6,11,39]
D5 H CLK PAD T95 CPU_TEST6 A26 B5
[11] H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# [11]

2
C6 PAD T33 CPU_TEST7 C3 D24
[11] H_INTR LINT0 TEST7 DPWR# H_DPWR# [5]
[11] H_NMI B4 A22 CLK_CPU_BCLK [17] [6,17] CPU_MCH_BSEL0 B22 D6 H_PWRGOOD [11]
LINT1 BCLK[0] BSEL[0] PWRGOOD
[11] H_SMI# A3 A21 CLK_CPU_BCLK# [17] [6,17] CPU_MCH_BSEL1 B23 D7 H_CPUSLP# [5]
SMI# BCLK[1] BSEL[1] SLP#
[6,17] CPU_MCH_BSEL2 C21 AE6 H_PSI# [39]
BSEL[2] PSI#
Quard Core Only
F6 D2 Penryn Ball-out Rev 1a
TDI_1/RSV RSVD[06] PAD T32
D3
TDO_2/RSV COMP0
N5 COMP1
BMP_1#[0]/RSV COMP2
M4
BMP_1#[1]/RSV
FSB BCLK BSEL2 BSEL1 BSEL0
B2 COMP3
BMP_1#[2]/RSV
AE8
BMP_1#[3]/VSS 533 133 0 0 1
D8
DCLKPH_1/VSS

2
F8
ACLKPH_1/VSS
667 166 0 1 1
D22 R99 R98 R18 R19
GTLREF_2/RSV 54.9/F 27.4/F 54.9/F 27.4/F
T2
THRMDA_1/RSV 800 200 0 1 0
V3
THRMDC_1/RSV
AA8
HFPLL_1/VSS
1066 266 0 0 0

1
AC8
AA7 SPARE_1[4]/VSS
BR1#/VCC
Comp0,2 connect with Zo=27.4ohm,Comp1,3
C
Penryn Ball-out Rev 1a
connect with Zo=55ohm, make those traces C
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
Place under CPU
10/20mils
Populate ITP700Flex for bringup REM_DIODE1_P
+3.3V_RUN
3

U17
1

Q4 2 C413 1 10 SMBCLK1
VDD SCL SMBCLK1 [17,18,23]
MMST3904-7-F 2200P
2
DP1 SDA
9 SMBDAT1
SMBDAT1 [17,18,23]
to EC
1

ITP_BPM#5 R94 1 2 56 +1.05V_VCCP REM_DIODE1_N 50 3 8 THERM_ALERT# THERM_ALERT# [13]


DN1 ALERT#
ITP_TDO R96 1 2 *56_NC H_THERMDA 4 7 SYS_SHDN#
DP2 SYS_SHDN#
1

ITP_TMS R95 1 2 56 C408 5 6


2200P DN2 GND +3.3V_RUN
ITP_TDI R97 1 2 56 EMC1423-1-AIZL-TR
2

H_THERMDC 50
C416
THERM_STP# [40]

2
0.1U
2

R331
Cap should close to thermal IC 16
R92 1 2 56 ITP_TCK
Layout Note: 402 OTP 100 degree C 6.8K/F
Place R92~R97
close to CPU Stephen 5/7

1
R93
Q29
D 1 2 56 ITP_TRST# D
2N7002W-7-F

1 3
QUANTA
2 Title
COMPUTER
+3.3V_RUN
Penryn Processor (HOST BUS)

Size Document Number Rev


VM9M 1A

Date: Saturday, June 06, 2009 Sheet 3 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+VCC_CORE +VCC_CORE U16D


U16C A4 P6
VSS[001] VSS[082]
A7 AB20 A8 P21
VCC[001] VCC[068] VSS[002] VSS[083]
A9 AB7 A11 P24
+VCC_CORE VCC[002] VCC[069] VSS[003] VSS[084]
All use 10U 4V(+-20%,X6S,0805)Pb-Free. A10
VCC[003] VCC[070]
AC7 A14
VSS[004] VSS[085]
R2
A12 AC9 A16 R5
VCC[004] VCC[071] VSS[005] VSS[086]
A13 AC12 A19 R22
A15 VCC[005] VCC[072] AC13 A23 VSS[006] VSS[087] R25
VCC[006] VCC[073] VSS[007] VSS[088]
1

1
A17 AC15 AF2 T1
C147 C136 C124 C110 C98 A18 VCC[007] VCC[074] AC17 B6 VSS[008] VSS[089] T4
10U *10U_NC 10U 10U 10U VCC[008] VCC[075] VSS[009] VSS[090]
A20 AC18 B8 T23
A VCC[009] VCC[076] VSS[010] VSS[091] A
2

2
805 805 805 805 805 B7 AD7 B11 T26
4 4 4 4 4 VCC[010] VCC[077] VSS[011] VSS[092]
B9 AD9 B13 U3
B10 VCC[011] VCC[078] AD10 B16 VSS[012] VSS[093] U6
VCC[012] VCC[079] VSS[013] VSS[094]
B12 AD12 B19 U21
+VCC_CORE B14 VCC[013] VCC[080] AD14 B21 VSS[014] VSS[095] U24
VCC[014] VCC[081] VSS[015] VSS[096]
B15 AD15 B24 V2
B17 VCC[015] VCC[082] AD17 C5 VSS[016] VSS[097] V5
VCC[016] VCC[083] VSS[017] VSS[098]
B18 AD18 C8 V22
VCC[017] VCC[084] VSS[018] VSS[099]
1

1
B20 AE9 C11 V25
C87 C71 C57 C142 C82 VCC[018] VCC[085] VSS[019] VSS[100]
C9 AE10 C14 W1
10U *10U_NC 10U 10U 10U C10 VCC[019] VCC[086] AE12 C16 VSS[020] VSS[101] W4
VCC[020] VCC[087] VSS[021] VSS[102]
2

2
805 805 805 805 805 C12 AE13 C19 W23
4 4 4 4 4 C13 VCC[021] VCC[088] AE15 C2 VSS[022] VSS[103] W26
VCC[022] VCC[089] VSS[023] VSS[104]
C15 AE17 C22 Y3
VCC[023] VCC[090] VSS[024] VSS[105]
8 inside cavity, north side, secondary layer. C17
VCC[024] VCC[091]
AE18 C25
VSS[025] VSS[106]
Y6
C18 AE20 D1 Y21
VCC[025] VCC[092] VSS[026] VSS[107]
D9 AF9 D4 Y24
+VCC_CORE VCC[026] VCC[093] VSS[027] VSS[108]
D10 AF10 AA2
D12 VCC[027] VCC[094] AF12 D11 VSS[109] AA5
VCC[028] VCC[095] VSS[029] VSS[110]
D14 AF14 D13
D15 VCC[029] VCC[096] AF15 D16 VSS[030] AA11
VCC[030] VCC[097] VSS[031] VSS[112]
1

1
D17 AF17 D19 AA14
C111 C73 C138 C371 C83 VCC[031] VCC[098] VSS[032] VSS[113]
D18 AF18 D23 AA16
10U *10U_NC *10U_NC 10U 10U VCC[032] VCC[099] +1.05V_VCCP VSS[033] VSS[114]
E7 AF20 D26 AA19
VCC[033] VCC[100] VSS[034] VSS[115]
2

2
805 805 805 805 805 E9 E3 AA22
4 4 4 4 4 VCC[034] VSS[035] VSS[116]
E10 G21 E6 AA25
E12 VCC[035] VCCP[01] V6 E8 VSS[036] VSS[117] AB1
VCC[036] VCCP[02] VSS[037] VSS[118]

1
E13 J6 E11 AB4
+VCC_CORE E15 VCC[037] VCCP[03] K6 + C361 E14 VSS[038] VSS[119] AB8
VCC[038] VCCP[04] 220U VSS[039] VSS[120]
B E17 M6 E16 AB11 B
E18 VCC[039] VCCP[05] J21 3528 E19 VSS[040] VSS[121] AB13
VCC[040] VCCP[06] VSS[041] VSS[122]

2
E20 K21 4 E21 AB16
VCC[041] VCCP[07] VSS[042] VSS[123]
1

1
F7 M21 E24 AB19
C387 C392 C88 C379 C375 VCC[042] VCCP[08] VSS[043] VSS[124]
F9 N21 F5 AB23
10U *10U_NC 10U 10U 10U F10 VCC[043] VCCP[09] N6 VSS[044] VSS[125] AB26
VCC[044] VCCP[10] VSS[126]
2

2
805 805 805 805 805 F12 R21 F11 AC3
4 4 4 4 4 F14 VCC[045] VCCP[11] R6 +1.5V_RUN F13 VSS[046] VSS[127] AC6
VCC[046] VCCP[12] VSS[047] VSS[128]
F15 T21 F16
VCC[047] VCCP[13] VSS[048]
8 inside cavity, south side, secondary layer. F17
VCC[048] VCCP[14]
T6 F19
VSS[049] VSS[130]
AC11
F18 V21 F2 AC14
VCC[049] VCCP[15] VSS[050] VSS[131]
F20 W21 F22 AC16
VCC[050] VCCP[16] VSS[051] VSS[132]
F25 AC19
+VCC_CORE AA9 B26 G4 VSS[052] VSS[133] AC21
VCC[052] VCCA[01] VSS[053] VSS[134]
AA10 C26 G1 AC24
VCC[053] VCCA[02] VSS[054] VSS[135]
AA12 G23 AD2
VCC[054] VSS[055] VSS[136]

1
AA13 AD6 C365 C360 G26 AD5
VCC[055] VID[0] VID0 [39] VSS[056] VSS[137]
1

AA15 AF5 0.01U 10U H3 AD8


VCC[056] VID[1] VID1 [39] VSS[057] VSS[138]
C148 C383 C143 C127 C101 C372 AA17 AE5 805 H6 AD11
VCC[057] VID[2] VID2 [39] VSS[058] VSS[139]

2
10U 10U 10U 10U 10U *10U_NC AA18 AF4 25 4 H21 AD13
VCC[058] VID[3] VID3 [39] VSS[059] VSS[140]
2

805 805 805 805 805 805 AA20 AE3 H24 AD16
VCC[059] VID[4] VID4 [39] VSS[060] VSS[141]
4 4 4 4 4 4 AB9 AF3 J2 AD19
VCC[060] VID[5] VID5 [39] VSS[061] VSS[142]
AC10 AE2 VID6 [39] J5 AD22
VCC[061] VID[6] VSS[062] VSS[143]
6 inside cavity, north side, primary layer. AB10
VCC[062]
J22
VSS[063] VSS[144]
AD25
AB12
VCC[063]
Layout Note: J25
VSS[064] VSS[145]
AE1
AB14 AF7 VCCSENSE K1 AE4
+VCC_CORE VCC[064] VCCSENSE VCCSENSE [39] Place C363 near PIN VSS[065] VSS[146]
AB15 K4
AB17 VCC[065] B26. K23 VSS[066] AE11
VCC[066] VSSSENSE VSS[067] VSS[148]
AB18 AE7 VSSSENSE [39] K26 AE14
VCC[067] VSSSENSE VSS[068] VSS[149]
L3 AE16
C VSS[069] VSS[150] C
1

Penryn Ball-out Rev 1a L6 AE19


.
C393 C388 C384 C376 C380 C60 VSS[070] VSS[151]
. L21 AE23
10U *10U_NC 10U *10U_NC 10U 10U VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
2

805 805 805 805 805 805 +VCC_CORE M2 A2


4 4 4 4 4 4 VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]

1
M22 AF8
R78 VSS[075] VSS[156]
6 inside cavity, south side, primary layer. M25
VSS[076] VSS[157]
AF11
100/F N1 AF13
VSS[077] VSS[158]
N4 AF16
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160]

2
N26 AF21
VCCSENSE VSS[080] VSS[161]
P3 A25
VSSSENSE VSS[081] VSS[162]
AF25
VSS[163]

1
+1.05V_VCCP Penryn Ball-out Rev 1a
R79
100/F
1

C59

2
C125 C56 C99 C126 C100
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U Layout Note:
2

402 402 402 402 402 402


16 16 16 16 16 16
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
Layout out: length matched to within 25
Place these inside socket cavity on North side secondary. mil. Place PU and PD within
2 inch of CPU.

D D

QUANTA
Title
COMPUTER
Penryn Processor (POWER)

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 4 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

U15A H_A#[3..35]
H_A#[3..35] [3]
H_D#[0..63] A14 H_A#3
[3] H_D#[0..63] H_A#_3
H_D#0 F2 C15 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 F16
A
H_D#2 H_D#_1 H_A#_5 H_A#6 A
F8 H13
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 C18
H_D#4 G2 H_D#_3 H_A#_7 M16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 J13
H_D#6 H2 H_D#_5 H_A#_9 P16 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 R16
H_D#8 D4 H_D#_7 H_A#_11 N17 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 M13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 E17
H_D#11 H_D#_10 H_A#_14 H_A#15
M11 P17
H_D#12 J1 H_D#_11 H_A#_15 F17 H_A#16
+1.05V_VCCP H_D#13 H_D#_12 H_A#_16 H_A#17
J2 G20
H_D#14 N12 H_D#_13 H_A#_17 B19 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
J6 J16
H_D#16 P2 H_D#_15 H_A#_19 E20 H_A#20
H_D#_16 H_A#_20
1

H_D#17 L2 H16 H_A#21


R21 H_D#18 H_D#_17 H_A#_21 H_A#22
R2 J20
H_D#19 H_D#_18 H_A#_22 H_A#23
221/F N9 L17
H_D#20 L6 H_D#_19 H_A#_23 A17 H_A#24
H_D#21 H_D#_20 H_A#_24 H_A#25
M5 B17
H_D#_21 H_A#_25
2

H_SWING H_D#22 J3 L16 H_A#26


H_D#23 H_D#_22 H_A#_26 H_A#27
N2 C21
H_D#_23 H_A#_27
1

H_D#24 R1 J17 H_A#28


H_D#_24 H_A#_28
2

R22 H_D#25 N5 H20 H_A#29


100/F C31 H_D#26 N6 H_D#_25 H_A#_29 B18 H_A#30
H_D#27 H_D#_26 H_A#_30 H_A#31
0.1U P13 K17
H_D#_27 H_A#_31
1

16 H_D#28 N8 B20 H_A#32


H_D#_28 H_A#_32
2

H_D#29 L7 F21 H_A#33


402 H_D#30 H_D#_29 H_A#_33 H_A#34
N10 K21
H_D#31 H_D#_30 H_A#_34 H_A#35
B M3 L20 B
H_D#32 Y3 H_D#_31 H_A#_35
H_D#33 H_D#_32
AD14 H12 H_ADS# [3]
H_D#34 Y6 H_D#_33 H_ADS# B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 [3]
H_RCOMP H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 [3]
H_D#36 Y12 A9
H_D#_36 H_BNR# H_BNR# [3]
2

HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# [3]
R23 H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# [3]
24.9/F H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# [3]
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# [3]
Layout Note: H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK [17]
1

H_D#42 AA13 AH6


H_RCOMP trace should be H_D#43 H_D#_42 HPLL_CLK# CLK_MCH_BCLK# [17]
AA9 J11 H_DPWR# [3]
10-mil wide with 20-mil H_D#44 AA11 H_D#_43 H_DPWR# F9
H_D#_44 H_DRDY# H_DRDY# [3]
spacing. H_D#45 AD11 H9 H_HIT# [3]
H_D#46 H_D#_45 H_HIT#
AD10 E12 H_HITM# [3]
H_D#47 H_D#_46 H_HITM#
AD13 H11 H_LOCK# [3]
H_D#48 AE12 H_D#_47 H_LOCK# C9
H_D#_48 H_TRDY# H_TRDY# [3]
H_D#49 AE9
H_D#50 H_D#_49
AA2
H_D#51 H_D#_50
AD8
H_D#52 H_D#_51
AA3
H_D#53 H_D#_52
AD3 J8 H_DINV#0 [3]
H_D#54 AD7 H_D#_53 H_DINV#_0 L3
H_D#_54 H_DINV#_1 H_DINV#1 [3]
H_D#55 AE14 Y13
H_D#_55 H_DINV#_2 H_DINV#2 [3]
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 [3]
H_D#57 AC1
H_D#58 AE3 H_D#_57 L10
H_D#_58 H_DSTBN#_0 H_DSTBN#0 [3]
H_D#59 AC3 M7
H_D#_59 H_DSTBN#_1 H_DSTBN#1 [3]
H_D#60 AE11 AA5
C H_D#_60 H_DSTBN#_2 H_DSTBN#2 [3] C
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 [3]
H_D#62 AG2
H_D#63 H_D#_62
AD6 L9 H_DSTBP#0 [3]
H_D#_63 H_DSTBP#_0
M8 H_DSTBP#1 [3]
H_DSTBP#_1
AA6 H_DSTBP#2 [3]
H_SWING C5 H_DSTBP#_2 AE5
+1.05V_VCCP H_SWING H_DSTBP#_3 H_DSTBP#3 [3]
H_RCOMP E3
H_RCOMP B15
H_REQ#_0 H_REQ#0 [3]
K13 H_REQ#1 [3]
H_REQ#_1
2

F13 H_REQ#2 [3]


R294 H_REQ#_2
B13 H_REQ#3 [3]
1K/F H_REQ#_3
[3] H_RESET# C12 B14 H_REQ#4 [3]
H_CPURST# H_REQ#_4
[3] H_CPUSLP# E11
H_CPUSLP# B6
H_RS#_0 H_RS#0 [3]
1

F12 H_RS#1 [3]


H_RS#_1 C8
H_RS#_2 H_RS#2 [3]
H_REF A11
H_AVREF
B11
H_DVREF
1

CANTIGA_1p0
1

R295
2K/F C368
0.1U
2

402 For EA test use


2

16

Layout Note: 1 H_DSTBP#0


ET10
1 H_D#7
Place the 0.1 uF ET2
H_D#12
ET14 1
D decoupling capacitor 1 H_DSTBN#1 D
ET9
within 100 mils from ET8 1 H_DSTBP#1
GMCH pins. 1 H_D#29
ET13

QUANTA
1 H_D#21
ET3
1 H_D#32
ET18

Title
COMPUTER
Cantiga (HOST)

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 5 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

U15B U15C

+1.8V_SUS M36 +VCC_PEG


N36 RSVD1 AP24
RSVD2 SA_CK_0 M_CLK_DDR0 [15]

2
R33 AT21 +3.3V_RUN L32 R81 49.9/F
RSVD3 SA_CK_1 M_CLK_DDR1 [15] [18] BIA_PWM L_BKLT_CTRL
R56 T37 VCC3G_PCIE_R

CONTROL/COMPENSATION
T33 AV24 M_CLK_DDR3 [15] [23] PANEL_BKEN G32 2 1
1K/F AH9 RSVD4 SB_CK_0 AU20 R65 10K/F L_CTRL_CLK M32 L_BKLT_EN PEG_COMPI T36
RSVD5 SB_CK_1 M_CLK_DDR4 [15] L_CTRL_CLK PEG_COMPO
AH10
RSVD6 R70 10K/F L_CTRL_DATA
AH12 AR24 M_CLK_DDR#0 [15] M33
RSVD7 SA_CK#_0 L_CTRL_DATA

1
SM_RCOMP_VOH AH13 AR21 LCD_DDCCLK K33 H44
RSVD8 SA_CK#_1 M_CLK_DDR#1 [15] [18] LCD_DDCCLK L_DDC_CLK PEG_RX#_0
K12 AU24 LCD_DDCDAT J33 J46
RSVD9 SB_CK#_0 M_CLK_DDR#3 [15] [18] LCD_DDCDAT L_DDC_DATA PEG_RX#_1
1

1
C120 C132 AL34 AV20 L44
RSVD10 SB_CK#_1 M_CLK_DDR#4 [15] PEG_RX#_2
0.01U 2.2U AK34 +3.3V_RUN L40
805 R73 RSVD11 PEG_RX#_3
AN35 BC28 DDR_CKE0_DIMMA [15,16] [18] ENVDD M29 N41
RSVD12 SA_CKE_0 L_VDD_EN PEG_RX#_4
2

25 10 3.01K/F AM35 AY28 R80 2 1 2.2K LCD_DDCCLK L_IBG C44 P48


RSVD13 SA_CKE_1 DDR_CKE1_DIMMA [15,16] LVDS_IBG PEG_RX#_5
T24 AY36 R75 2 1 2.2K LCD_DDCDAT B43 N44
D RSVD14 SB_CKE_0 DDR_CKE3_DIMMB [15,16] PAD T31 LVDS_VBG PEG_RX#_6 D

2
BB36 DDR_CKE4_DIMMB [15,16] E37 T43
SM_RCOMP_VOL SB_CKE_1 LVDS_VREFH PEG_RX#_7

RSVD
B31 E38 U43
RSVD15 LVDS_VREFL PEG_RX#_8

LVDS
AJ6 BA17 DDR_CS0_DIMMA# [15,16] [18] LCD_ACLK- C41 Y43
RSVD16 SA_CS#_0 LVDSA_CLK# PEG_RX#_9
1

C112 C131 M1 AY16 L_IBG C40 Y48


RSVD17 SA_CS#_1 DDR_CS1_DIMMA# [15,16] [18] LCD_ACLK+ LVDSA_CLK PEG_RX#_10

2
0.01U 2.2U R48 AV16 PAD T106 B37 Y36
SB_CS#_0 DDR_CS2_DIMMB# [15,16] LVDSB_CLK# PEG_RX#_11
805 1K/F AR13 R83 PAD T107 A37 AA43
SB_CS#_1 DDR_CS3_DIMMB# [15,16] LVDSB_CLK PEG_RX#_12
2

25 10 AY21 2.4K/F AD37


RSVD20 PEG_RX#_13
BD17 M_ODT0 [15,16] [18] LCD_A0- H47 AC47
SA_ODT_0 LVDSA_DATA#_0 PEG_RX#_14
1

AY17 E46 AD39


SA_ODT_1 M_ODT1 [15,16] [18] LCD_A1- LVDSA_DATA#_1 PEG_RX#_15

1
A47 BF15 +1.8V_SUS G40
RSVD21 SB_ODT_0 M_ODT2 [15,16] [18] LCD_A2- LVDSA_DATA#_2
BG23 AY13 M_ODT3 [15,16] A40 H43
RSVD22 SB_ODT_1 LVDSA_DATA#_3 PEG_RX_0
BF23 J44

GRAPHICS
RSVD23 PEG_RX_1

2
BH18 BG22 SMRCOMPP H48 L43
RSVD24 SM_RCOMP [18] LCD_A0+ LVDSA_DATA_0 PEG_RX_2
BF18 BH21 SMRCOMPN R87 D45 L41
RSVD25 SM_RCOMP# [18] LCD_A1+ LVDSA_DATA_1 PEG_RX_3
*1K/F_NC F40 N40
[18] LCD_A2+ LVDSA_DATA_2 PEG_RX_4
BF28 SM_RCOMP_VOH B40 P47
SM_RCOMP_VOH BH28 SM_RCOMP_VOL LVDSA_DATA_3 PEG_RX_5 N43

DDR
SM_RCOMP_VOL PEG_RX_6

1
PAD T108 A41 T42
V_DDR_MCH_REF_L LVDSB_DATA#_0 PEG_RX_7
AV42 V_DDR_MCH_REF PAD T26 H38 U42
SM_VREF LVDSB_DATA#_1 PEG_RX_8
AR36 PAD T25 G37 Y42
SM_PWROK LVDSB_DATA#_2 PEG_RX_9

2
BF17 R32 1 2 499/F J37 W47
+3.3V_RUN SM_REXT R86 LVDSB_DATA#_3 PEG_RX_10
BC36 T24 PAD Y37
SM_DRAMRST# *1K/F_NC PEG_RX_11
PAD T109 B42 AA42
R69 PM_EXTTS#0 LVDSB_DATA_0 PEG_RX_12
1 2 10K B38 +1.8V_SUS PAD T27 G38 AD36
R63 PM_EXTTS#1 DPLL_REF_CLK MCH_DREFCLK [17] LVDSB_DATA_1 PEG_RX_13
1 2 10K A38 PAD T28 F37 AC48
DPLL_REF_CLK# MCH_DREFCLK# [17] LVDSB_DATA_2 PEG_RX_14

1
E41 K37 AD40

PCI-EXPRESS
DPLL_REF_SSCLK DREF_SSCLK [17] LVDSB_DATA_3 PEG_RX_15

CLK

1
F41
DPLL_REF_SSCLK# DREF_SSCLK# [17]
J41
R47 PEG_TX#_0
F43 CLK_MCH_3GPLL [17]
M46
PEG_CLK 80.6/F R52 75/F_4 PEG_TX#_1
E43 CLK_MCH_3GPLL# [17] F25 M47
PEG_CLK# R45 75/F_4 TVA_DAC PEG_TX#_2
H25 M40
TVB_DAC PEG_TX#_3

2
SMRCOMPP R46 75/F_4 K25 M42
TVC_DAC PEG_TX#_4

TV
SMRCOMPN R48
PEG_TX#_5
Layout Note: DMI_RXN_0
AE41 DMI_MRX_ITX_N0 [12] H24
TV_RTN PEG_TX#_6
N38

1
Location of all MCH_CFG strap AE37 T40
DMI_RXN_1 DMI_MRX_ITX_N1 [12] PEG_TX#_7
AE47 DMI_MRX_ITX_N2 [12] U37
resistors needs to be close to DMI_RXN_2 AH39 R43 PEG_TX#_8 U40
DMI_RXN_3 DMI_MRX_ITX_N3 [12] PEG_TX#_9
C minmize stub. 80.6/F C31
TV_DCONSEL_0 PEG_TX#_10
Y40 C
AE40 E32 AA46
DMI_RXP_0 DMI_MRX_ITX_P0 [12] TV_DCONSEL_1 PEG_TX#_11

2
[3,17] CPU_MCH_BSEL0 T25 AE38 DMI_MRX_ITX_P1 [12] AA37
CFG_0 DMI_RXP_1 PEG_TX#_12
[3,17] CPU_MCH_BSEL1 R25 AE48 DMI_MRX_ITX_P2 [12] AA40
CFG_1 DMI_RXP_2 PEG_TX#_13
P25 AH40 AD43
[3,17] CPU_MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_MRX_ITX_P3 [12] PEG_TX#_14
PAD T4 CFG3 P20 AC46
CFG4 CFG_3 PEG_TX#_15
PAD T11 P24 AE35 DMI_MTX_IRX_N0 [12]
CFG5 CFG_4 DMI_TXN_0 VGA_BLU
PAD T35 C25 AE43 DMI_MTX_IRX_N1 [12] [19] VGA_BLU
E28 J42
CFG6 CFG_5 DMI_TXN_1 VGA_BLU CRT_BLUE PEG_TX_0
PAD T14 N24 AE46 DMI_MTX_IRX_N2 [12] L46
CFG7 CFG_6 DMI_TXN_2 VGA_GRN VGA_GRN PEG_TX_1
PAD T13 M24 AH42 G28 M48
DMI

CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 [12] [19] VGA_GRN CRT_GREEN PEG_TX_2


PAD T8 CFG8 E21 VGA_RED M39
CFG9 CFG_8 VGA_RED PEG_TX_3
CFG

PAD T42 C23 AD35 J28 M43


CFG_9 DMI_TXP_0 DMI_MTX_IRX_P0 [12] [19] VGA_RED CRT_RED PEG_TX_4

VGA
CFG10 C24 AE44 R47
PAD T12 CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 [12] PEG_TX_5
PAD T6 CFG11 N21 AF46 R55 R49 R53 Layout Note: G29 N37
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 [12] CRT_IRTN PEG_TX_6
PAD T7 CFG12 P21 AH43 150/F 150/F 150/F T39
CFG13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 [12] Place 150 ohm PEG_TX_7
PAD T10 T21 [19] G_CLK_DDC2 H32 U36
CFG14 CFG_13 termination resistors CRT_DDC_CLK PEG_TX_8
PAD T3 R20 [19] G_DAT_DDC2 J32 U39
CFG_14 CRT_DDC_DATA PEG_TX_9

1
PAD T91
CFG15 M20
CFG_15
close to GMCH. [19] VGAHSYNC
R58 1 2 30/F J29
CRT_HSYNC PEG_TX_10
Y39
PAD T118 CFG16 L21 R64 1 2 1.3K/F E29 Y46
CFG17 H21 CFG_16 R66 1 2 30/F L29 CRT_TVO_IREF PEG_TX_11 AA36
GRAPHICS VID

PAD T9 CFG_17 [19] VGAVSYNC CRT_VSYNC PEG_TX_12


CFG18 P29 AA39
PAD CFG_18 PEG_TX_13
CFG19 R28 AD42
PAD T94 CFG_19 PEG_TX_14
CFG20 T28 B33 AD46
PAD T115 CFG_20 GFX_VID_0 T105 PAD PEG_TX_15
B32 T100 PAD
GFX_VID_1 G33
GFX_VID_2 T21 PAD
F33 T18 PAD CANTIGA_1p0
GFX_VID_3
[13] PM_BMBUSY# R29 E33 T20 PAD
PM_SYNC# GFX_VID_4
B7
[3,11,39] H_DPRSTP# PM_EXTTS#0 PM_DPRSTP#
[15] PM_EXTTS#0
N33
PM_EXTTS#1 PM_EXT_TS#_0
P32
[15] PM_EXTTS#1 PM_EXT_TS#_1
PM

AT40 C34 T104 PAD


[13,23] PWROK PLTRST#_R PWROK GFX_VR_EN
AT11
H_THERMTRIP# RSTIN#
T20
[3,11] H_THERMTRIP# THERMTRIP#
R32
[13,39] DPRSLPVR DPRSLPVR
Low=DMIx2
AH37 +1.05V_VCCP CFG5 DMI X2 Select High=DMIx4(Default)
CL_CLK CL_CLK0 [13]
AH36 CL_DATA0 [13]
CL_DATA
B BG48
NC_1 CL_PWROK
AN36
ICH_CL_PWROK [13,23] Non-iAMT PCI Express Low= Reveise Lane B
ME

2
BF48
NC_2 CL_RST#
AJ35 ICH_CL_RST0# [13] CFG9 Graphic Lane High=Normal operation
BD48 AH34 R68
NC_3 CL_VREF MCH_CLVREF
BC48
NC_4
1K/F FSB Dynamic Low=Dynamic ODT Disable
BH47
NC_5
CFG16 ODT High=Dynamic ODT Enable(default).
BG47
NC_6

1
BE47 N28 T16 PAD MCH_CLVREF DMI Lane Low=Normal(default).
NC_7 DDPC_CTRLCLK
BH46
NC_8 DDPC_CTRLDATA
M28 T19 PAD CFG19 Reversal High=Lane Reversed

1
BF46 G36 T23 PAD
NC_9 SDVO_CTRLCLK
2
NC

R292
100 BG45
NC_10 SDVO_CTRLDATA
E36 T22 PAD Low=Only SDVO or PCIEx1 is
2 1 PLTRST#_R BH44 K36 C144 R77 SDVO/PCIE
[12,21,23,26,33,34] PLTRST# NC_11 CLKREQ# CLK_3GPLLREQ# [17] operational (defaults)
BH43 H36 0.1U 499/F CFG20
MISC

NC_12 ICH_SYNC# MCH_ICH_SYNC# [13] Concurrent High=SDVO and PCIEx1 are operating
1

BH6 16
NC_13 Operation
2
BH5
NC_14 402
simultaneously via PEG port
BG4 B12 R296 2 1 56 +1.05V_VCCP
NC_15 TSATN
BH3
NC_16
Low=No SDVO Device Present
BF3 (default)
NC_17
BH2
NC_18
SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present
BG2 B28 T98 PAD
BE2 NC_19 HDA_BCLK B30
NC_20 HDA_RST# T103 PAD
BG1 B29 T101 PAD
NC_21 HDA_SDI
HDA

BF1 C29 T102 PAD


NC_22 HDA_SDO
BD1 A28 T99 PAD
NC_23 HDA_SYNC
BC1
NC_24
F1
NC_25

CANTIGA_1p0

A A

QUANTA
Title
COMPUTER
Cantiga (VGA,DMI)

Size Document Number Rev


VM9M 1A

Date: Saturday, June 06, 2009 Sheet 6 of 46


5 4 3 2 1
1 2 3 4 5 6 7 8

[15] DDR_A_D[0..63] [15] DDR_B_D[0..63]


U15D U15E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 [15,16] SB_DQ_0 SB_BS_0 DDR_B_BS0 [15,16]
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
A SA_DQ_1 SA_BS_1 DDR_A_BS1 [15,16] SB_DQ_1 SB_BS_1 DDR_B_BS1 [15,16] A
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 [15,16] SB_DQ_2 SB_BS_2 DDR_B_BS2 [15,16]
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 AJ36 SA_DQ_3 BB20 DDR_A_RAS# DDR_B_D4 AJ46 SB_DQ_3
SA_DQ_4 SA_RAS# DDR_A_RAS# [15,16] SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# [15,16] SB_DQ_5 SB_RAS# DDR_B_RAS# [15,16]
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# DDR_A_WE# [15,16] SB_DQ_6 SB_CAS# DDR_B_CAS# [15,16]
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE#
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# [15,16]
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 AU46
DDR_A_D10 SA_DQ_9 DDR_B_D10 SB_DQ_9
AU40 DDR_A_DM[0..7] [15] BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 AM37 AY48 DDR_B_DM[0..7] [15]
DDR_A_D12 AN41 SA_DQ_11 SA_DM_0 AT41 DDR_A_DM1 DDR_B_D12 AT47 SB_DQ_11 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 AY41 AR47 AY47
DDR_A_D14 AU44 SA_DQ_13 SA_DM_2 AU39 DDR_A_DM3 DDR_B_D14 BA47 SB_DQ_13 SB_DM_1 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 BB12 BC47 BF35
DDR_A_D16 AV39 SA_DQ_15 SA_DM_4 AY6 DDR_A_DM5 DDR_B_D16 BC46 SB_DQ_15 SB_DM_3 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 AT7 BC44 BA3

A
DDR_A_D18 SA_DQ_17 SA_DM_6 DDR_A_DM7 DDR_B_D18 SB_DQ_17 SB_DM_5 DDR_B_DM6
BA40 AJ5 BG43 AP1

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 DDR_A_DQS[0..7] [15] BF43 AK2
DDR_A_D20 AV41 SA_DQ_19 AJ44 DDR_A_DQS0 DDR_B_D20 BE45 SB_DQ_19 SB_DM_7
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] [15]
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1

MEMORY
BB41 BA43 BF40 AV48
DDR_A_D23 SA_DQ_22 SA_DQS_2 DDR_A_DQS3 DDR_B_D23 SB_DQ_22 SB_DQS_1

MEMORY
BC40 BC37 BF41 BG41 DDR_B_DQS2
DDR_A_D24 SA_DQ_23 SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3
AY37 AW12 BG38 BG37
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 BC8 BF38 BH9
DDR_A_D26 AV37 SA_DQ_25 SA_DQS_5 AU8 DDR_A_DQS6 DDR_B_D26 BH35 SB_DQ_25 SB_DQS_4 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 AM7 DDR_A_DQS#[0..7] [15] BG35 AU1
DDR_A_D28 AY38 SA_DQ_27 SA_DQS_7 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 SB_DQ_27 SB_DQS_6 AN6 DDR_B_DQS7
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] [15]
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 AV36 SA_DQ_29 SA_DQS#_1 BA44 DDR_A_DQS#2 DDR_B_D30 BG34 SB_DQ_29 SB_DQS#_0 AV47 DDR_B_DQS#1
DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
B AW36 BD37 BH34 BH41 B
DDR_A_D32 BD13 SA_DQ_31 SA_DQS#_3 AY12 DDR_A_DQS#4 DDR_B_D32 BH14 SB_DQ_31 SB_DQS#_2 BH37 DDR_B_DQS#3
DDR_A_D33 SA_DQ_32 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D33 SB_DQ_32 SB_DQS#_3 DDR_B_DQS#4
AU11 BD8 BG12 BG9
DDR_A_D34 BC11 SA_DQ_33 SA_DQS#_5 AU9 DDR_A_DQS#6 DDR_B_D34 BH11 SB_DQ_33 SB_DQS#_4 BC2 DDR_B_DQS#5
SA_DQ_34 SA_DQS#_6 SB_DQ_34 SB_DQS#_5
SYSTEM

DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6


SA_DQ_35 SA_DQS#_7 SB_DQ_35 SB_DQS#_6

SYSTEM
DDR_A_D36 AU13 DDR_B_D36 BH12 AN5 DDR_B_DQS#7
SA_DQ_36 DDR_A_MA[0..14] [15,16] SB_DQ_36 SB_DQS#_7
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11
SA_DQ_37 SA_MA_0 SB_DQ_37 DDR_B_MA[0..14] [15,16]
DDR_A_D38 BD12 BC24 DDR_A_MA1 DDR_B_D38 BF8 AV17 DDR_B_MA0
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BC12 BG24 BG7 BA25
DDR_A_D40 BB9 SA_DQ_39 SA_MA_2 BH24 DDR_A_MA3 DDR_B_D40 BC5 SB_DQ_39 SB_MA_1 BC25 DDR_B_MA2
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 BG25 BC6 AU25
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 BA24 AY3 AW25
DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
AV9 BD24 AY1 BB28
DDR_A_D44 BA11 SA_DQ_43 SA_MA_6 BG27 DDR_A_MA7 DDR_B_D44 BF6 SB_DQ_43 SB_MA_5 AU28 DDR_B_MA6
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 BF25 BF5 AW28
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 AW24 BA1 AT33
DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
BA6 BC21 BD3 BD33
DDR

DDR_A_D48 AV5 SA_DQ_47 SA_MA_10 BG26 DDR_A_MA11 DDR_B_D48 AV2 SB_DQ_47 SB_MA_9 BB16 DDR_B_MA10

DDR
DDR_A_D49 SA_DQ_48 SA_MA_11 DDR_A_MA12 DDR_B_D49 SB_DQ_48 SB_MA_10 DDR_B_MA11
AV7 BH26 AU3 AW33
DDR_A_D50 SA_DQ_49 SA_MA_12 DDR_A_MA13 DDR_B_D50 SB_DQ_49 SB_MA_11 DDR_B_MA12
AT9 BH17 AR3 AY33
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 AY25 AN2 BH15
DDR_A_D52 SA_DQ_51 SA_MA_14 DDR_B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
AU5 AY2 AU33
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 AV1
DDR_A_D54 AT5 SA_DQ_53 DDR_B_D54 AP3 SB_DQ_53
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 AR1
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AM11 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 AL2
DDR_A_D58 AJ9 SA_DQ_57 DDR_B_D58 AJ1 SB_DQ_57
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 AH1
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AN12 AM2
C
DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 C
AM13 AM3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AJ11 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

D D

QUANTA
Title
COMPUTER
Cantiga (DDR2)

Size Document Number Rev


VM9M 1A

Date: Saturday, June 06, 2009 Sheet 7 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

U15G U15F
+1.8V_SUS +3.3V_RUN

AP33 W28 R60 10 D3


VCC_SM_1 VCC_AXG_NCTF_1 +VCC_GMCH_L
AN33 V28 1 2 1 2 AG34
VCC_SM_2 VCC_AXG_NCTF_2 VCC_1
BH32 W26 AC34
BG32 VCC_SM_3 VCC_AXG_NCTF_3 V26 RB751V-40 AB34 VCC_2
VCC_SM_4 VCC_AXG_NCTF_4 VCC_3
BF32 W25 AA34
BD32 VCC_SM_5 VCC_AXG_NCTF_5 V25 Y34 VCC_4
VCC_SM_6 VCC_AXG_NCTF_6 +1.05V_VCCP VCC_5
BC32 W24 V34
BB32 VCC_SM_7 VCC_AXG_NCTF_7 V24 U34 VCC_6
VCC_SM_8 VCC_AXG_NCTF_8 VCC_7
BA32 W23 AM33
D VCC_SM_9 VCC_AXG_NCTF_9 VCC_8 D
AY32 V23 AK33
VCC_SM_10 VCC_AXG_NCTF_10 VCC_9

1
AW32 AM21 AJ33
AV32 VCC_SM_11 VCC_AXG_NCTF_11 AL21 + C359 AG33 VCC_10
VCC_SM_12 VCC_AXG_NCTF_12 VCC_11

1
AU32 AK21 220U AF33
AT32 VCC_SM_13 VCC_AXG_NCTF_13 W21 3528 C356 C150 C139 C35 VCC_12
VCC_SM_14 VCC_AXG_NCTF_14

2
AR32 V21 Layout Note: 4 22U 0.22U 0.22U 0.1U AE33

POWER
VCC_SM_15 VCC_AXG_NCTF_15 VCC_13

VCC CORE
AP32 U21 805 603 603 402 AC33
VCC_SM_16 VCC_AXG_NCTF_16 370 mils from edge. 4 10 10 16 VCC_14
AN32 AM20 AA33
VCC_SM_17 VCC_AXG_NCTF_17 VCC_15
BH31
VCC_SM_18 VCC_AXG_NCTF_18
AK20 Layout Note: Y33
VCC_16
BG31 W20 Inside GMCH cavity. W33
BF31 VCC_SM_19 VCC_AXG_NCTF_19 U20 V33 VCC_17
VCC_SM_20 VCC_AXG_NCTF_20 VCC_18
BG30 AM19 U33
BH29 VCC_SM_21 VCC_AXG_NCTF_21 AL19 AH28 VCC_19
VCC_SM_22 VCC_AXG_NCTF_22 VCC_20
BG29
VCC_SM_23 VCC_AXG_NCTF_23
AK19 Layout Note: AF28
VCC_21
BF29 AJ19 Inside GMCH cavity for VCC_AXG. AC28
VCC_SM_24 VCC_AXG_NCTF_24 VCC_22
BD29 AH19 AA28
VCC_SM_25 VCC_AXG_NCTF_25 VCC_23
VCC SM

BC29 AG19 +1.05V_VCCP AJ26


VCC_SM_26 VCC_AXG_NCTF_26 VCC_24
BB29 AF19 AG26
BA29 VCC_SM_27 VCC_AXG_NCTF_27 AE19 AE26 VCC_25
VCC_SM_28 VCC_AXG_NCTF_28 VCC_26

1
AY29 AB19 + + AC26
AW29 VCC_SM_29 VCC_AXG_NCTF_29 AA19 C77 C75 C70 C79 C149 C94 C14 C13 AH25 VCC_27
VCC_SM_30 VCC_AXG_NCTF_30 0.1U 0.1U 22U 10U 1U 0.47U *220U_NC *220U_NC VCC_28
AV29 Y19 AG25
VCC_SM_31 VCC_AXG_NCTF_31 VCC_29

2
AU29 W19 402 402 805 603 603 603 AF25
VCC_SM_32 VCC_AXG_NCTF_32 16 16 4 6.3 10 10 VCC_30
AT29
VCC_SM_33 VCC_AXG_NCTF_33
V19 Layout Note: AG24
VCC_31
AR29 U19 370 mils from edge. AJ23
VCC_SM_34 VCC_AXG_NCTF_34 VCC_32 +1.05V_VCCP
AP29 AM17 AH23

POWER
VCC_SM_35 VCC_AXG_NCTF_35 AK17 AF23 VCC_33
VCC_AXG_NCTF_36 VCC_34
BA36 AH17 AM32
BB24 VCC_SM_36/NC VCC_AXG_NCTF_37 AG17 T32 VCC_NCTF_1 AL32
VCC_SM_37/NC VCC_AXG_NCTF_38 VCC_35 VCC_NCTF_2
C BD16 AF17 AK32 C
BB21 VCC_SM_38/NC VCC_AXG_NCTF_39 AE17 VCC_NCTF_3 AJ32
VCC_SM_39/NC VCC_AXG_NCTF_40 VCC_NCTF_4
AW16 AC17 AH32
AW13 VCC_SM_40/NC VCC_AXG_NCTF_41 AB17 VCC_NCTF_5 AG32
VCC_SM_41/NC VCC_AXG_NCTF_42 VCC_NCTF_6
AT13 Y17 AE32
VCC_SM_42/NC VCC_AXG_NCTF_43 +1.8V_SUS VCC_NCTF_7
+1.05V_VCCP VCC_AXG_NCTF_44
W17
V17
VCC_SM VCC_NCTF_8
AC32
AA32
VCC GFX NCTF

VCC_AXG_NCTF_45 AM16 VCC_NCTF_9 Y32


VCC_AXG_NCTF_46 VCC_NCTF_10
Y26 AL16 W32
AE25 VCC_AXG_1 VCC_AXG_NCTF_47 AK16 VCC_NCTF_11 U32
VCC_AXG_2 VCC_AXG_NCTF_48 VCC_NCTF_12

1
AB25 AJ16 + C64 AM30
VCC_AXG_3 VCC_AXG_NCTF_49 C121 220U/2.5V_7343 C134 C135 VCC_NCTF_13
AA25 AH16 AL30
VCC_AXG_4 VCC_AXG_NCTF_50 0.1U 22U 22U VCC_NCTF_14
AE24 AG16 AK30
VCC_AXG_5 VCC_AXG_NCTF_51 VCC_NCTF_15

2
AC24 AF16 402 805 805 AH30
VCC_AXG_6 VCC_AXG_NCTF_52 16 4 4 VCC_NCTF_16
AA24 AE16 AG30
VCC_AXG_7 VCC_AXG_NCTF_53 VCC_NCTF_17
Y24
VCC_AXG_8 VCC_AXG_NCTF_54
AC16 Layout Note: Leon 3/25 VCC_NCTF_18
AF30
AE23 AB16 Place C195 where LVDS AE30
VCC_AXG_9 VCC_AXG_NCTF_55 VCC_NCTF_19
AC23
VCC_AXG_10 VCC_AXG_NCTF_56
AA16
and DDR2 taps. Layout Note: VCC_NCTF_20
AC30
AB23 Y16 Place on the edge. AB30
VCC_AXG_11 VCC_AXG_NCTF_57 VCC_NCTF_21
AA23 W16 AA30
VCC_AXG_12 VCC_AXG_NCTF_58 VCC_NCTF_22
AJ21 V16 Y30
VCC_AXG_13 VCC_AXG_NCTF_59 VCC_NCTF_23
AG21 U16 W30
VCC_AXG_14 VCC_AXG_NCTF_60 VCC_NCTF_24

VCC NCTF
AE21 V30
AC21 VCC_AXG_15 VCC_NCTF_25 U30
VCC_AXG_16 +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP VCC_NCTF_26
AA21 AL29
VCC_AXG_17 VCC_NCTF_27
Y21 AK29
VCC_AXG_18 VCC_NCTF_28
AH20 AJ29
AF20 VCC_AXG_19 VCC_NCTF_29 AH29
VCC_AXG_20 VCC_NCTF_30
2

2
AE20 AG29
VCC_AXG_21 C85 C117 C128 C109 VCC_NCTF_31
AC20 AE29
B VCC_AXG_22 VCC_NCTF_32 B
AB20 *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC AC29
VCC_AXG_23 VCC_NCTF_33
1

1
AA20 16 16 16 16 AA29
VCC_AXG_24 VCC_NCTF_34
T17 402 402 402 402 Y29
VCC_AXG_25 VCC_NCTF_35
T16 W29
VCC_AXG_26 VCC_NCTF_36
AM15 V29
AL15 VCC_AXG_27 +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP VCC_NCTF_37 AL28
VCC_AXG_28 VCC_NCTF_38
AE15 AK28
AJ15 VCC_AXG_29 VCC_NCTF_39 AL26
VCC_AXG_30 VCC_NCTF_40
AH15 AK26
VCC_AXG_31 VCC_NCTF_41
2

2
AG15 AK25
VCC_AXG_32 C118 C102 C39 VCC_NCTF_42
AF15 AK24
VCC_AXG_33 VCC_NCTF_43
AB15 *0.1U_NC *0.1U_NC *0.1U_NC AK23
VCC_AXG_34 VCC_NCTF_44
1

1
AA15 16 16 16
VCC_AXG_35
VCC GFX

Y15 402 402 402


VCC_AXG_36
V15
U15 VCC_AXG_37
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40 VCCSM_LF1 CANTIGA_1p0
U14 AV44
VCC_AXG_41 VCC_SM_LF1
VCC SM LF

+1.05V_VCCP T14 BA37 VCCSM_LF2


VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
AM40
VCC_SM_LF3 VCCSM_LF4
AV21
VCC_SM_LF4
2

AY5 VCCSM_LF5
VCC_SM_LF5 AM10 VCCSM_LF6
R30 VCC_SM_LF6 VCCSM_LF7
BB13
*10_NC VCC_SM_LF7
1

1
1

AJ14 C52 C38 C33 C93 C152 C151 C156


VCC_AXG_SENSE 0.1U 0.1U 0.22U 0.22U 0.47U 1U 1U
AH14
VSS_AXG_SENSE
2

A 402 402 603 603 603 603 603 A


2

16 16 10 10 10 10 10

QUANTA
R25
*10_NC

COMPUTER
1

CANTIGA_1p0 Title
Cantiga (VCC,NCTF)

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 8 of 46


5 4 3 2 1
5 4 3 2 1

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
L29 BLM18PG181SN1D U15H +1.05V_VCCP
+3.3V_RUN +VCCA_CRTDAC
603 U13
VTT_1

1
T13
VTT_2

1
C385 C386 +VCCA_CRTDAC B27 U12
VCCA_CRT_DAC_1 VTT_3

1
0.01U 0.1U A26 T12 C72 C54 C84 C49 + C363
VCCA_CRT_DAC_2 VTT_4

2
25 402 U11 2.2U 4.7U 0.47U 4.7U 220U
16 VTT_5 603 603 6.3 603 3528
T11
VTT_6

2
+VCCA_DAC_BG A25 U10 10 6.3 6.3 4

CRT
+VCCA_DAC_BG VCCA_DAC_BG VTT_7
B25 T10
VSSA_DAC_BG VTT_8 U9
VTT_9

1
D
Remove R300 0ohm resistor VTT_10
T9 Place on the edge. D
C382 C381 U8 Close to VTT
Ray 5/27 0.1U 0.01U +VCCA_DPLLA VTT_11
F47 T8
VCCA_DPLLA VTT_12

2
402 25 U7

VTT
16 +VCCA_DPLLB VTT_13
L48 T7
VCCA_DPLLB VTT_14 U6
+VCCA_HPLL VTT_15
AD1 T6

PLL
VCCA_HPLL VTT_16 U5
VTT_17
Non-iAMT 45mA MAx. 40mA MAx. C402
+VCCA_MPLL AE1
VCCA_MPLL VTT_18
T5
V3
+1.05V_VCCP 1000P 50 VTT_19
+1.05V_VCCP
FB_120ohm+-25%_100mHz 10uH+-20%_100mA VTT_20
U3
L9 10uH 2 1 +VCC_TX_LVDS J48 V2
_200mA_0.2ohm DC 2 1+VCCA_DPLLA
VCCA_LVDS VTT_21
U2

A LVDS
L2 BLM11A05S 805 J47 VTT_22 T2
VSSA_LVDS VTT_23

1
+VCCA_HPLL V1
+1.5V_RUN VTT_24

1
603 + C160 U1
*220U_NC C159 C158 VTT_25
2

C17 3528 10U 0.1U AD48


VCCA_PEG_BG

2
4.7U C15 4 603 402

1
603 0.1U 6.3 16
1

6.3 402 C397 Remove L6 0ohm resistor

A PEG
16 L37 10uH 0.1U
Ray 5/27

2
2 1 +VCCA_DPLLB 402 +VCCA_PEG_PLL AA48
L3 BLM11A05S 805 16 VCCA_PEG_PLL

1
+VCCA_MPLL

1
603 0.1Caps should be + C405 AR20 +1.05V_VCCP
R20 0.5/F *220U_NC C398 C404 VCCA_SM_1
placed 200 mils AP20
1 2 3528 10U 0.1U AN20 VCCA_SM_2
with in its pins. VCCA_SM_3
POWER
2

2
1

1
603 4 603 402 AR17
+VCCA_MPLL_L C21 6.3 16 AP17 VCCA_SM_4 C86 C95
VCCA_SM_5
1

C 0.1U AN17 1U 10U C


VCCA_SM_6
2

2
C364 402 AT16 603 603
22U 16 +1.05V_VCCP VCCA_SM_7 10 6.3
AR16

A SM
VCCA_SM_8
2

1206 AP16
10 VCCA_SM_9 L7 805
2

1
C68 C20 C19 C92 1uH/300MA
Remove R12 0ohm 4.7U 22U 22U 1U +1.8V_SUS

1
Ray 6/1 603 805 805 603
1

2
6.3 4 4 10

1
R39
AP28 C80 1/F
VCCA_SM_CK_1 0.1U 603
AN28 B22
VCCA_SM_CK_2 VCC_AXF_1

2
1
L8 AP25 B21 402

AXF
2 1 +VCCA_SM_CK AN25 VCCA_SM_CK_3 VCC_AXF_2 A21 16 C62
+1.05V_VCCP VCCA_SM_CK_4 VCC_AXF_3
1uH/300mA AN24 10U
VCCA_SM_CK_5

2
1

1
C115 C103 C116 AM28 603
22U 1U 1U C106 VCCA_SM_CK_NCTF_1 6.3
AM26

A CK
805 603 603 0.1U AM25 VCCA_SM_CK_NCTF_2 L33
VCCA_SM_CK_NCTF_3
2

2
4 10 10 402 AL25 BF21 +VCC_SM_CK +1.8V_SUS
16 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 C407 1uH/300MA
AM24 BH20

SM CK
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2

1
AL24 BG20 1000P 805
+1.05V_VCCP VCCA_SM_CK_NCTF_6 VCC_SM_CK_3
AM23 BF20
BLM21P221SGPT VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 50
AL23 +3.3V_RUN
VCCA_SM_CK_NCTF_8

2
L32 +VCCA_PEG_PLL
805
1

1
K47 +VCC_TX_LVDS
+VCC_TVDACA VCC_TX_LVDS C396
B24
R308 VCCA_TV_DAC_1 0.1U
FB_220ohm+-25%_100MHz A24 C35

TV
VCCA_TV_DAC_2 VCC_HV_1

2
1/F B35 402 Remove R316 0ohm
_2A_0.1ohm DC 603 VCC_HV_2
A35 16

HV
B VCC_HV_3 +VCC_PEG
Ray 6/1 B
1 2

+VCC_HDA A32
VCC_HDA

HDA
C401 V48 +1.05V_VCCP
10U VCC_PEG_1
U48
VCC_PEG_2
2

603 V47

PEG
VCC_PEG_3

1
6.3 U47
VCC_PEG_4

D TV/CRT

1
+VCCD_TVDAC M25 U46 + C403 C410
VCCD_TVDAC VCC_PEG_5 220U C414 4.7U
+VCCD_QDAC L28 3528 22U 603
VCCD_QDAC

2
C27 0.1U AH48 +VCC_RXR_DMI 4 1206 6.3
+VCCA_MPLL VCC_DMI_1 10
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC 2 1 AF1
VCCD_HPLL VCC_DMI_2
AF48
C406 0.1U AH47

DMI
L27 +VCC_TVDACA +VCCD_PEG_PLL VCC_DMI_3
+3.3V_RUN 2 1 AA47 AG47
BLM18PG181SN1D 402 16 VCCD_PEG_PLL VCC_DMI_4
1

603
C373 C374 M38
VCCD_LVDS_1
LVDS
0.01U 0.1U +1.8V_SUS L37 A8 +VTTLF1
VCCD_LVDS_2 VTTLF1
2

25 402 L1 +VTTLF2 L34 +1.05V_VCCP


VTTLF2

VTTLF
1

16 AB2 +VTTLF3 2 1
Remove R85 0ohm resistor C157 C153 VTTLF3

1
Ray 5/27 1U *10U_NC 91nH/1.5A
2

603 603 C400


10 6.3 CANTIGA_1p0 0.1U

2
Remove R304 0ohm resistor 402
+1.5V_RUN 16
Ray 5/27
+VCCD_TVDAC +1.05V_VCCP
BLM21P221SGPT
1

L35 +VCCD_PEG_PLL
A C390 C108 805 A
1

0.1U 0.01U
2

402 25 +VTTLF1

QUANTA
16 FB_220ohm+-25%_100MHz R310 +VTTLF2
L31 1/F +VTTLF3
+VCCD_QDAC _2A_0.1ohm DC 603

COMPUTER
1 2

BLM18PG181SN1D
603 C32 C29 C36
1

C409 0.47U 0.47U 0.47U Title


2

C395 C122 10U 603 603 603 Cantiga (POWER)


2

0.1U 0.01U 603 10 10 10


2

402 25 6.3 Size Document Number Rev


16 VM9M 1A

Date: Saturday, June 06, 2009 Sheet 9 of 46


5 4 3 2 1
5 4 3 2 1

U15J
U15I BG21 AH8
VSS_199 VSS_297
L12 Y8
VSS_200 VSS_298
AU48 AM36 AW21 L8
VSS_1 VSS_100 VSS_201 VSS_299
AR48 AE36 AU21 E8
AL48 VSS_2 VSS_101 P36 AP21 VSS_202 VSS_300 B8
VSS_3 VSS_102 VSS_203 VSS_301
BB47 L36 AN21 AY7
AW47 VSS_4 VSS_103 J36 AH21 VSS_204 VSS_302 AU7
VSS_5 VSS_104 VSS_205 VSS_303
AN47 F36 AF21 AN7
AJ47 VSS_6 VSS_105 B36 AB21 VSS_206 VSS_304 AJ7
VSS_7 VSS_106 VSS_207 VSS_305
AF47 AH35 R21 AE7
D VSS_8 VSS_107 VSS_208 VSS_306 D
AD47 AA35 M21 AA7
VSS_9 VSS_108 VSS_209 VSS_307
AB47 Y35 J21 N7
Y47 VSS_10 VSS_109 U35 G21 VSS_210 VSS_308 J7
VSS_11 VSS_110 VSS_211 VSS_309
T47 T35 BC20 BG6
N47 VSS_12 VSS_111 BF34 BA20 VSS_212 VSS_310 BD6
VSS_13 VSS_112 VSS_213 VSS_311
L47 AM34 AW20 AV6
G47 VSS_14 VSS_113 AJ34 AT20 VSS_214 VSS_312 AT6
VSS_15 VSS_114 VSS_215 VSS_313
BD46 AF34 AJ20 AM6
VSS_16 VSS_115 VSS_216 VSS_314
BA46 AE34 AG20 M6
VSS_17 VSS_116 VSS_217 VSS_315
AY46 W34 Y20 C6
AV46 VSS_18 VSS_117 B34 N20 VSS_218 VSS_316 BA5
VSS_19 VSS_118 VSS_219 VSS_317
AR46 A34 K20 AH5
AM46 VSS_20 VSS_119 BG33 F20 VSS_220 VSS_318 AD5
VSS_21 VSS_120 VSS_221 VSS_319
V46 BC33 C20 Y5
R46 VSS_22 VSS_121 BA33 A20 VSS_222 VSS_320 L5
VSS_23 VSS_122 VSS_223 VSS_321
P46 AV33 BG19 J5
VSS_24 VSS_123 VSS_224 VSS_322
H46 AR33 A18 H5
VSS_25 VSS_124 VSS_225 VSS_323
F46 AL33 BG17 F5
BF44 VSS_26 VSS_125 AH33 BC17 VSS_226 VSS_324 BE4
VSS_27 VSS_126 VSS_227 VSS_325
AH44 AB33 AW17
AD44 VSS_28 VSS_127 P33 AT17 VSS_228
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
BC3
AV3
AL3
U44 N32 H17 R3
T44 VSS_32 VSS_131 VSS_232 VSS_330
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
K32
F32
C32
C17

BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
P3
F3
BA2
BC43 A31 AW2
AV43 VSS_36 VSS_135 AN29 AU16 VSS_334 AU2
VSS_37 VSS_136 VSS_237 VSS_335
C AU43 T29 AN16 AR2 C
AM43 VSS_38 VSS_137 N29 N16 VSS_238 VSS_336 AP2
VSS_39 VSS_138 VSS_239 VSS_337
J43 K29 K16 AJ2
C43 VSS_40 VSS_139 H29 G16 VSS_240 VSS_338 AH2
VSS_41 VSS_140 VSS_241 VSS_339
BG42 F29 E16 AF2
AY42 VSS_42 VSS_141 A29 BG15 VSS_242 VSS_340 AE2
VSS_43 VSS_142 VSS_243 VSS_341
AT42 BG28 AC15 AD2
AN42 VSS_44 VSS_143 BD28 W15 VSS_244 VSS_342 AC2
VSS_45 VSS_144 VSS_245 VSS_343
AJ42 BA28 A15 Y2
AE42 VSS_46 VSS_145 AV28 BG14 VSS_246 VSS_344 M2
VSS_47 VSS_146 VSS_247 VSS_345
N42 AT28 AA14 K2
VSS_48 VSS_147 VSS_248 VSS_346
L42 AR28 C14 AM1
VSS_49 VSS_148 VSS_249 VSS_347
BD41 AJ28 BG13 AA1
AU41 VSS_50 VSS_149 AG28 BC13 VSS_250 VSS_348 P1
VSS_51 VSS_150 VSS_251 VSS_349
AM41 AE28 BA13 H1
VSS_52 VSS_151 VSS_252 VSS_350
AH41 AB28
VSS_53 VSS_152
AD41 Y28 U24
AA41 VSS_54 VSS_153 P28 AN13 VSS_351 U28
VSS_55 VSS_154 VSS_255 VSS_352
Y41 K28 AJ13 U25
VSS_56 VSS_155 VSS_256 VSS_353
U41 H28 AE13 U29
VSS_57 VSS_156 VSS_257 VSS_354
T41 F28 N13
VSS_58 VSS_157 VSS_258
M41 C28 L13
VSS_59 VSS_158 VSS_259
G41 BF26 G13 AF32
B41 VSS_60 VSS_159 AH26 E13 VSS_260 VSS_NCTF_1 AB32
VSS_61 VSS_160 VSS_261 VSS_NCTF_2
BG40 AF26 BF12 V32
VSS_62 VSS_161 VSS_262 VSS_NCTF_3
BB40 AB26 AV12 AJ30
VSS_63 VSS_162 VSS_263 VSS_NCTF_4
AV40 AA26 AT12 AM29
AN40 VSS_64 VSS_163 C26 AM12 VSS_264 VSS_NCTF_5 AF29
VSS_65 VSS_164 VSS_265 VSS_NCTF_6

VSS NCTF
H40 B26 AA12 AB29
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 BH25 J12 U26
B VSS_67 VSS_166 VSS_267 VSS_NCTF_8 B
AT39 BD25 A12 U23
VSS_68 VSS_167 VSS_268 VSS_NCTF_9
AM39 BB25 BD11 AL20
VSS_69 VSS_168 VSS_269 VSS_NCTF_10
AJ39 AV25 BB11 V20
VSS_70 VSS_169 VSS_270 VSS_NCTF_11
AE39 AR25 AY11 AC19
VSS_71 VSS_170 VSS_271 VSS_NCTF_12
N39 AJ25 AN11 AL17
L39 VSS_72 VSS_171 AC25 AH11 VSS_272 VSS_NCTF_13 AJ17
VSS_73 VSS_172 VSS_273 VSS_NCTF_14
B39 Y25 AA17
BH38 VSS_74 VSS_173 N25 Y11 VSS_NCTF_15 U17
VSS_75 VSS_174 VSS_275 VSS_NCTF_16
BC38 L25 N11
VSS_76 VSS_175 VSS_276
BA38 J25 G11 BH48
VSS_77 VSS_176 VSS_277 VSS_SCB_1

VSS SCB
AU38 G25 C11 BH1
VSS_78 VSS_177 VSS_278 VSS_SCB_2
AH38 E25 BG10 A48
VSS_79 VSS_178 VSS_279 VSS_SCB_3
AD38 BF24 AV10 C1
AA38 VSS_80 VSS_179 AD12 AT10 VSS_280 VSS_SCB_4 B2
VSS_81 VSS_180 VSS_281 VSS_SCB_5
Y38 AY24 AJ10 A3
U38 VSS_82 VSS_181 AT24 AE10 VSS_282 VSS_SCB_6
VSS_83 VSS_182 VSS_283
T38 AJ24 AA10 E1
VSS_84 VSS_183 VSS_284 NC_26
J38 AH24 M10 D2
VSS_85 VSS_184 VSS_285 NC_27
F38 AF24 BF9 C3
C38 VSS_86 VSS_185 AB24 BC9 VSS_286 NC_28 B4
VSS_87 VSS_186 VSS_287 NC_29
BF37 R24 AN9 A5
VSS_88 VSS_187 VSS_288 NC_30
BB37 L24 AM9 A6
VSS_89 VSS_188 VSS_289 NC_31
AW37 K24 AD9 A43
AT37 VSS_90 VSS_189 J24 G9 VSS_290 NC_32 A44

NC
VSS_91 VSS_190 VSS_291 NC_33
AN37 G24 B9 B45
VSS_92 VSS_191 VSS_292 NC_34
AJ37 F24 BH8 C46
VSS_93 VSS_192 VSS_293 NC_35
H37 E24 BB8 D47
C37 VSS_94 VSS_193 BH23 AV8 VSS_294 NC_36 B47
VSS_95 VSS_194 VSS_295 NC_37
BG36 AG23 AT8 A46
A BD36 VSS_96 VSS_195 Y23 VSS_296 NC_38 F48 A
VSS_97 VSS_196 NC_39
AK15 B23 E48
AU36 VSS_98 VSS_197 A23 NC_40 C48
VSS_99 VSS_198 NC_41

CANTIGA_1p0
NC_42
B48
QUANTA
CANTIGA_1p0

Title
COMPUTER
Cantiga (VSS)

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 10 of 46


5 4 3 2 1
1 2 3 4 5 6 7 8

32.768KHZ R160 10M


2 1
+RTC_CELL
W2

1
ICH_RTCX1 1 4 ICH_RTCX2

2 3 R334
1

1
332K/F
C234 32.768KHZ C238

2
15P/50V 15P/50V ICH_INTVRMEN
2

2
A A

+RTC_CELL

ICH9M Internal VR Enable Strap ICH9M LAN100 SLP Strap


1

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05)
R169 R174 R329 Low = Internal VR Disabled Low = Internal VR Disabled
1M 20K 20K ICH_INTVRMEN ICH_LAN100_SLP
High = Internal VR Enabled(Default) High = Internal VR Enabled(Default)
2

ICH_RTCRST# +1.05V_VCCP
ICH_SRTCRST#
ICH_INTRUDER# U19A
ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_LAD0 [23,26]

2
ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_LAD1 [23,26]
1

L6 R325 R172 R324


FWH2/LAD2 LPC_LAD2 [23,26]
C247 C440 ICH_RTCRST# A25 K2 *56_NC *56_NC 56
RTCRST# FWH3/LAD3 LPC_LAD3 [23,26]
1U/10V 1U/10V ICH_SRTCRST# F20
SRTCRST#
2

ICH_INTRUDER# C22 K3
INTRUDER# FWH4/LFRAME# LPC_LFRAME# [23,26]

1
H_DPRSTP#

RTC
LPC
ICH_INTVRMEN B22 J3 H_DPSLP#
INTVRMEN LDRQ0# PAD T89
A22 J1 H_FERR#
LAN100_SLP LDRQ1#/GPIO23 PAD T150

T37 PAD GLAN_CLK E25 N7 SIO_A20GATE


GLAN_CLK A20GATE SIO_A20GATE [23]
R216 1 2 33 ACZ_BIT_CLK AJ27
[32] ICH_AZ_CODEC_BITCLK A20M# H_A20M# [3]
C13
LAN_RSTSYNC H_DPRSTP# +3.3V_RUN
Reserved for DPRSTP#
AJ25 H_DPRSTP# [3,6,39]
2

B LAN_RXD0 F14 AE23 H_DPSLP# B


L23
Intel Nineveh T67 PAD
LAN_RXD1 LAN_RXD0 DPSLP# H_DPSLP# [3]
T70 PAD G13
design. LAN_RXD2 LAN_RXD1 H_FERR#_L 2 H_FERR#
*22uH_NC T68 PAD D14 AJ26 1 H_FERR# [3]
LAN_RXD2 FERR#

2
LAN / GLAN
402 T69 PAD LAN_TXD0 R323 56
T66 PAD LAN_TXD1 D13 AD22 R234
LAN_TXD2 LAN_TXD0 CPUPWRGD H_PWRGOOD [3] R208 10K
T65 PAD D12
LAN_TXD1
1

E13 AF25 8.2K


R204 *10K_NC LAN_TXD2 IGNNE# H_IGNNE# [3]

1
2

+3.3V_SUS 2 1 B10 AE22 SIO_A20GATE


GLAN_DOCK#/GPIO56 INIT# H_INIT# [3]
C293 AG25 SIO_RCIN#
INTR H_INTR [3]

CPU
*27P/50V_NC R151 24.9/F B28 L3 SIO_RCIN#
GLAN_COMPI RCIN# SIO_RCIN# [23]
1

+1.5V_PCIE_ICH 1 2 GLAN_COMP B27


GLAN_COMPO
AF23 H_NMI [3]
ACZ_BIT_CLK AF6 NMI AF24
HDA_BIT_CLK SMI# H_SMI# [3] +1.05V_VCCP
ACZ_SYNC AH4
R223 1 HDA_SYNC
[32] ICH_AZ_CODEC_SYNC 2 33 ACZ_SYNC AH27 H_STPCLK# [3]
ACZ_RST# STPCLK#
AE7
HDA_RST#

2
R213 1 2 33 ACZ_RST# AG26 1 2 H_THERMTRIP#
[23,32] ICH_AZ_CODEC_RST# THRMTRIP# H_THERMTRIP# [3,6]
AF4 R35 56 R161
[32] ICH_AZ_CODEC_SDIN0 HDA_SDIN0
R217 1 2 33 ACZ_SDOUT PAD AG4 AG27 56
[32] ICH_AZ_CODEC_SDOUT T141 HDA_SDIN1 TP9 PAD T117
T142 PAD AH3
HDA_SDIN2

IHDA
T85 PAD AE5
HDA_SDIN3

1
Place all series terms close to ICH9 except for SDIN input H_THERMTRIP#
ACZ_SDOUT AG5 AH11
lines,which should be close to source. HDA_SDOUT SATA4RXN
AJ11
SATA4RXP
AG7 AG12 PAD T71
HDA_DOCK_EN#/GPIO33 SATA4TXN
AE8 AF12 PAD T74
HDA_DOCK_RST#/GPIO34 SATA4TXP
[30] SATA_ACT# AG8 AH9
SATALED# SATA5RXN
AJ9
C SATA5RXP C
[28] SATA_RX0- AJ16 AE10 PAD T76
SATA0RXN SATA5TXN
Master HDD [28] SATA_RX0+ AH16 AF10 PAD T75
SATA0RXP SATA5TXP

SATA
SATA_TX0-_C AF17
SATA_TX0+_C SATA0TXN
AG17 AH18 CLK_PCIE_SATA# [17]
C267 0.01U/16V SATA_TX0-_C SATA0TXP SATA_CLKN
[28] SATA_TX0- AJ18 CLK_PCIE_SATA [17]
C263 0.01U/16V SATA_TX0+_C AH13 SATA_CLKP
[28] SATA_TX0+ [28] SATA_RX1- SATA1RXN
SATA ODD AJ13 AJ7 24.9/F R347
[28] SATA_RX1+ SATA1RXP SATARBIAS#
SATA_TX1-_C AG14 AH7 SATABIAS 1 2 Place within 500mils
C274 0.01U/16V SATA_TX1-_C SATA_TX1+_C SATA1TXN SATARBIAS
[28] SATA_TX1- AF14 of ICH9 ball
C269 0.01U/16V SATA_TX1+_C SATA1TXP
[28] SATA_TX1+
ICH9M REV 1.0

+3.3V_RUN
2

XOR Chain Entrance Strap R218


*1K_NC
ICH RSVD HDA SDOUT Description
1

0 0 RSVD ACZ_SDOUT
ICH_RSVD [13]
0 1 Enter XOR Chain
2

D 1 0 Normal Operation (Default) R336 D


*1K_NC
1 1 Set PCIE port config bit 1
QUANTA
1

Title
COMPUTER
ICH9-M (CPU,SATA,LPC,LAN,CODEC)

Size Document Number Rev


VM9M 1A

Date: Saturday, June 06, 2009 Sheet 11 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

U19D
Place TX DC blocking caps close ICH9. N29 V27 DMI_MTX_IRX_N0 [6]
PERN1 DMI0RXN
MiniWWAN N28
PERP1 DMI0RXP
V26 DMI_MTX_IRX_P0 [6]
P27 U29 DMI_MRX_ITX_N0 [6]
PETN1 DMI0TXN
P26 U28 DMI_MRX_ITX_P0 [6]

Direct Media Interface


PETP1 DMI0TXP
[26] PCIE_RX2- L29 Y27 DMI_MTX_IRX_N1 [6]
C227 1 2 0.1U 16 PCIE_TXN2_C L28 PERN2 DMI1RXN Y26
[26] PCIE_TX2- [26] PCIE_RX2+ PERP2 DMI1RXP DMI_MTX_IRX_P1 [6]
C228 1 2 0.1U 16 PCIE_TXP2_C PCIE_TXN2_C M27 W29
[26] PCIE_TX2+ PETN2 DMI1TXN DMI_MRX_ITX_N1 [6]
MiniWLAN PCIE_TXP2_C M26 W28
PETP2 DMI1TXP DMI_MRX_ITX_P1 [6]
C276 1 2 0.1U 16 PCIE_TXN4_C J29 AB27
[21] PCIE_TX4- PERN3 DMI2RXN DMI_MTX_IRX_N2 [6]
C275 1 2 0.1U 16 PCIE_TXP4_C MiniWPAN J28 AB26

PCI-Express
A [21] PCIE_TX4+ PERP3 DMI2RXP DMI_MTX_IRX_P2 [6] A
K27 AA29 DMI_MRX_ITX_N2 [6]
PETN3 DMI2TXN
K26 AA28 DMI_MRX_ITX_P2 [6]
PETP3 DMI2TXP
C2234 1 2 0.1U 16 PCIE_TXN5_C G29 AD27
[33] PCIE_TX5- [21] PCIE_RX4- PERN4 DMI3RXN DMI_MTX_IRX_N3 [6]
C2237 1 2 0.1U 16 PCIE_TXP5_C G28 AD26
[33] PCIE_TX5+ [21] PCIE_RX4+ PERP4 DMI3RXP DMI_MTX_IRX_P3 [6]
PCIE_TXN4_C H27 AC29
PETN4 DMI3TXN DMI_MRX_ITX_N3 [6]
Express Card PCIE_TXP4_C H26 AC28
PETP4 DMI3TXP DMI_MRX_ITX_P3 [6]
C229 1 2 0.1U 16 GLAN_TXN_C E29 T26
[34] PCIE_TX6-/GLAN_TX- [33] PCIE_RX5- PERN5 DMI_CLKN CLK_PCIE_ICH# [17]
C230 1 2 0.1U 16 GLAN_TXP_C E28 T25
[34] PCIE_TX6+/GLAN_TX+ [33] PCIE_RX5+ PERP5 DMI_CLKP CLK_PCIE_ICH [17]
PCIE_TXN5_C F27
PCIE_TXP5_C PETN5
1394+Cardreader F26
PETP5 DMI_ZCOMP
AF29
AF28 DMI_COMP 1 2 Place within 500mils of ICH9
DMI_IRCOMP +1.5V_PCIE_ICH
C29 R322 24.9/F
[34] PCIE_RX6-/GLAN_RX- PERN6/GLAN_RXN
[34] PCIE_RX6+/GLAN_RX+ C28 AC5 ICH_USBP0- [27]
GLAN_TXN_C D27
PERP6/GLAN_RXP USBP0N
AC4 ICH_USBP0+ [27]
Side Pair Left
GLAN_TXP_C PETN6/GLAN_TXN USBP0P
Giga Bit LOM D26
PETP6/GLAN_TXP USBP1N
AD3 ICH_USBP1- [27]
Side Pair Left
AD2 ICH_USBP1+ [27]
SPI_CLK_R D23 USBP1P AC1
T39 PAD ICH_USBP2- [33]
SPI_CS#0_R D24
SPI_CLK USBP2N
AC2 ICH_USBP2+ [33]
Side Pair Right
T44 PAD SPI_CS0# USBP2P
ICH_SPI_CS1#_R F23 AA5 ICH_USBP3- [33]
T82 PAD SPI_CS1#/GPIO58/CLGPIO6 USBP3N Side Pair Right
AA4 ICH_USBP3+ [33]
SPI_MOSI USBP3P
Boot BIOS Strap D25 AB2

SPI
T40 PAD ICH_USBP4- [18]
SPI_MISO E23
SPI_MOSI USBP4N
AB3 ICH_USBP4+ [18]
Camera
T45 PAD SPI_MISO USBP4P
GNT0# SPI_CS1# USBP5N
AA1 PAD T113 Mini Card (WWAN)
PCI Pullups
USB_OC0_1# N4 AA2
[27] USB_OC0_1# OC0#/GPIO59 USBP5P PAD T148
LPC 11 No stuff No stuff N5
OC1#/GPIO40 USBP6N
W5 ICH_USBP6- [26]
Bluetooth
[33] USB_OC_3#
USB_OC_3#
N6
OC2#/GPIO41 USB USBP6P
W4 ICH_USBP6+ [26] RP37
+3.3V_RUN
PCI 10 No stuff Stuff P6
OC3#/GPIO42 USBP7N
Y3 ICH_USBP7- [21]
Express Card
B OC4# M1 Y2 ICH_USBP7+ [21] PCI_FRAME# 6 5 B
OC5# OC4#/GPIO43 USBP7P PCI_TRDY# PCI_PLOCK#
SPI 01 Stuff No stuff N2
OC5#/GPIO29 USBP8N
W1 ICH_USBP8- [26]
Mini Card (WLAN)
7 4
OC6# M4 W2 ICH_USBP8+ [26] PCI_DEVSEL# 8 3 PCI_STOP#
OC7# M3 OC6#/GPIO30 USBP8P V2 PCI_REQ1# 9 2 PCI_PIRQD#
OC7#/GPIO31 USBP9N PAD T90
OC8# N3 V3 10 1 PCI_PERR#
OC8#/GPIO44 USBP9P PAD T147 +3.3V_RUN
OC9# N1 U5
OC9#/GPIIO45 USBP10N PAD T83
OC10# P5 U4
OC10#/GPIO46 USBP10P PAD T84
OC11# P3 U1 +3.3V_RUN
OC11#/GPIO47 USBP11N PAD T145 RP38
U2 PAD T144
R354 22.6/F USBP11P PCI_IRDY# 6 5
+3.3V_SUS 1 2 USBRBIAS AG2 PCI_PIRQC# 7 4 PCI_PIRQA#
RP39 USBRBIAS PCI_PIRQE# PCI_REQ0#
AG1 8 3
OC7# USBRBIAS# PCI_PIRQB# ICH_IRQH_GPIO5
6 5 Places within 500 mils 9 2
OC6# 7 4 OC9# ICH9M REV 1.0 10 1 PCI_SERR#
OC5# USB_OC_3#
of the ICH9 +3.3V_RUN
8 3
OC4# 9 2 USB_OC0_1#
10 1 OC8# PCI_REQ2# R202 2 1 8.2K +3.3V_RUN
+3.3V_SUS
10KX8
OC10# R207 2 1 10K +3.3V_SUS
OC11# R225 2 1 10K

+3.3V_RUN

GPIO3 R211 2 1 8.2K


C C
GPIO4 R238 2 1 8.2K
U19B GPIO54 R386 2 1 8.2K
D11 F1 PCI_REQ0#
AD0 REQ0#
C8
D9 AD1 PCI GNT0#
G4
B6
PCI_GNT0#
PCI_REQ1#
PAD T2080
CLK_PCI_ICH BIOS should not enable the
AD2 REQ1#/GPIO50 internal GPIO pull up resistor.

2
E12 A7 PCI_GNT1#
AD3 GNT1#/GPIO51 PAD T86
E9 F13 PCI_REQ2#
AD4 REQ2#/GPIO52 PCI_GNT2# R224
C9 F12 PAD T73
AD5 GNT2#/GPIO53 GPIO54 *10_NC
E10 E6
AD6 REQ3#/GPIO54 PCI_GNT3#
B7 F6 PAD T77
AD7 GNT3#/GPIO55

2 1
C7
AD8
C5 D8
G11 AD9 C/BE0# B4 C306
AD10 C/BE1# *8.2P_NC
F8 D6
AD11 C/BE2#

1
F11 A5
AD12 C/BE3#
E7
AD13 PCI_IRDY#
A3
AD14 IRDY#
D3 Reserved for 16
D2 E3 EMI.Place
F10 AD15 PAR R1
AD16 PCIRST# PCI_DEVSEL# resister and cap
D5 C6
AD17 DEVSEL# PCI_PERR# close to ICH.
D10 E4
AD18 PERR# PCI_PLOCK#
B3 C2 PAD T88
F7 AD19 PLOCK# J4 PCI_SERR#
AD20 SERR# PCI_STOP#
C3 A4
AD21 STOP# PCI_TRDY#
F3 F5
AD22 TRDY# PCI_FRAME#
F4 D7
C1 AD23 FRAME#
AD24 PLTRST#
G7 C14 PLTRST# [6,21,23,26,33,34]
D H7 AD25 PLTRST# D4 CLK_PCI_ICH D
AD26 PCICLK CLK_PCI_ICH [17]
D1 R2
G5 AD27 PME#
AD28
H6
G1
H3
AD29
AD30 QUANTA
AD31

PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# Title
COMPUTER
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 GPIO3 ICH9-M (USB,DMI,PCIE,PCI)
E1 K6
PCI_PIRQC# PIRQB# PIRQF#/GPIO3 GPIO4
J6 F2
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 ICH_IRQH_GPIO5 Size Document Number Rev
C4 G2 PAD T93
PIRQD# PIRQH#/GPIO5 VM9M 1A
ICH9M REV 1.0
Date: Saturday, June 06, 2009 Sheet 12 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+3.3V_SUS
Non-iAMT
RP41
1 2 ICH_SMBDATA
3 4 ICH_SMBCLK

2.2KX2

Place these close to ICH9.

Non-iAMT ASF 2.0 CLK_ICH_48M


+3.3V_SUS +3.3V_SUS Non-iAMT
A A

2
RP36 R194 2 1 10K RSV_ICH_CL_RST1# +3.3V_RUN
1 2 ICH_SMLINK0 R197 2 1 10K ICH_RI# R226
3 4 ICH_SMLINK1 R203 2 1 10K SIO_EXT_SCI# *10_NC
R179 2 1 1K PCIE_WAKE#

1 1
2
*10KX2_NC

ICH_SMBCLK R191 1 2 0 ICH_SMLINK0 R175 C309


ICH_SMBDATA R193 1 2 0 ICH_SMLINK1 8.2K *4.7P_NC

2
1
U19C
ICH_SMBCLK G16 AH23 50
[21] ICH_SMBCLK ICH_SMBDATA SMBCLK SATA0GP/GPIO21
[21] ICH_SMBDATA A13 AF19
RSV_ICH_CL_RST1# SMBDATA SATA1GP/GPIO19 CLK_ICH_14M
T60 PAD E17 AE21

SMB
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SATA
ICH_SMLINK0

GPIO
T58 PAD C17 AD20
SMLINK0 SATA5GP/GPIO37

2
T57 PAD ICH_SMLINK1 B18
+3.3V_RUN SMLINK1 CLK_ICH_14M
H1 CLK_ICH_14M [17]
ICH_RI# CLK14 CLK_ICH_48M R721
F19 AF3 CLK_ICH_48M [17]
RI# CLK48

Clocks
*10_NC
2

T81 PAD RSV_LPCPD# R4 P1 ICH_SUSCLK


SUS_STAT#/LPCPD# SUSCLK PAD T146

1 1
+3.3V_SUS 1 2 G19
R237 R24 1K SYS_RESET#
C16 SIO_SLP_S3# [23]
8.2K SLP_S3# C457
[6] PM_BMBUSY# M6 E16 PAD T64
PMSYNC#/GPIO0 SLP_S4# *4.7P_NC
G17 SIO_SLP_S5# [23]
SLP_S5#
1

2
CLKRUN# USB_MCARD1_DET# A17
[26] USB_MCARD1_DET# SMBALERT#/GPIO11
C10
S4_STATE#/GPIO26
2

A14 50
[17] H_STP_PCI# STP_PCI#/GPIO15
E19 G20 PWROK
[17] H_STP_CPU# STP_CPU#/GPIO25 PWROK PWROK [6,23]
R236 DPRSLPVR
DPRSLPVR [6,39]

SYS GPIO
B *10_NC CLKRUN# L4 M2 B

Power MGT
[23] CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 R346 8.2K
1

PCIE_WAKE# E20 B13 ICH_BATLOW# 2 1 +3.3V_SUS


[21,26,34] PCIE_WAKE# WAKE# BATLOW#
IRQ_SERIRQ M5
[23] IRQ_SERIRQ SERIRQ
Option to " Disable " THERM_ALERT# AJ23 R3
[3] THERM_ALERT# THRM# PWRBTN# SIO_PWRBTN# [23]
PWROK R192 2 1 10K
clkrun. Pulling it down IMVP_PWRGD RSV_ICH_LAN_RST#
[23,39] IMVP_PWRGD D21 D20 PAD T47
will keep the clks VRMPWRGD LAN_RST# DPRSLPVR R352 1 2 100K
running. T133 PAD A20 D22 ICH_RSMRST#
ICH_RSMRST# [23]
TP8 RSMRST# ICH_RSMRST# R157 2 1 10K
T51 PAD AG19 R5 CLK_PWRGD [17]
TACH1/GPIO1 CK_PWRGD RSV_ICH_LAN_RST# R176 2
T129 PAD AH21 1 10K
TACH2/GPIO6 ICH_CL_PWROK
[23] SIO_EXT_WAKE# AG21 R6 ICH_CL_PWROK [6,23]
SIO_EXT_SMI# TACH3/GPIO7 CLPWROK ICH_CL_PWROK R206 2 1 1M
[23] SIO_EXT_SMI#
SIO_EXT_SCI#
A21
C12
GPIO8
B16
Non-iAMT
[23] SIO_EXT_SCI# LANPHYPC/GPIO12 SLP_M# PAD T137
T135 PAD C21
ENGDET/GPIO13
T61 PAD AE18 F24 CL_CLK0 [6]
PCIE_MCARD1_DET# R235 2 1 4.7K K1 TACH0/GPIO17 CL_CLK0 B19 RSV_ICH_CL_CLK1
[26] PCIE_MCARD1_DET# GPIO18 CL_CLK1 PAD T52
AF8

GPIO
T78 PAD

Controller Link
GPIO20
T126 PAD AJ22 F22 CL_DATA0 [6]
SCLOCK/GPIO22 CL_DATA0 RSV_ICH_CL_DATA1 +3.3V_SUS
T128 PAD A9 C19 PAD T134
QRT_STATE0/GPIO27 CL_DATA1
T50 PAD D19
QRT_STATE1/GPIO28 R180 2
[17] SATA_CLKREQ# L1 C25 CL_VREF0 RSV_GPIO10 1 10K
AE19 SATACLKREQ#/GPIO35 CL_VREF0 A19
T54 PAD SLOAD/GPIO38 CL_VREF1
T127 PAD AG22
SDATAOUT0/GPIO39
T56 PAD AF21 F21 ICH_CL_RST0# [6]
SDATAOUT1/GPIO48 CL_RST0# CL_RST1#
T46 PAD AH24 D18 PAD T53
A8 GPIO49 CL_RST1#
T140 PAD GPIO57/CLGPIO5
A16 RSV_GPIO24
MEM_LED/GPIO24 PAD T136
SPKR M7 C18 RSV_GPIO10
C [32] SPKR SPKR ALERT#/GPIO10 PAD T49 C
MCH_ICH_SYNC#_R AJ24 C11 RSV_GPIO14
[6] MCH_ICH_SYNC# MCH_SYNC# NETDETECT/GPIO14 PAD T72
B21 C20 RSV_WOL_EN
[11] ICH_RSVD TP3 WOL_EN/GPIO9 PAD T48
T132 PAD
T131 PAD
TP9
TP10
AH20
AJ20
TP9 MISC R201 8.2K
TP11 TP10
T130 PAD AJ21 2 1 +3.3V_SUS
TP11 +3.3V_RUN
ICH9M REV 1.0 Non-iAMT

2
+3.3V_RUN R168
3.24K/F
1

+3.3V_RUN
Non-iAMT

1
R210
*1K_NC SMbus address D2 CL_VREF0
+3.3V_RUN

2
4
2

1
SPKR These are for

1
RP27 R164
R249 1
backdrive issue.
2 100K PCIE_MCARD1_DET# 2.2KX2 C240 453/F
No Reboot strap. 0.1U

2
2

16
1
3

2
Low = Default. Q19
402
SPKR High = No Reboot. [21] ICH_SMBDATA 3 1 SDATA [15,26]

2N7002W-7-F
+3.3V_RUN
CL_VREF0/1 ~=0.405V
+3.3V_RUN
D R327 2 1 *10K_NC MCH_ICH_SYNC#_R D
R209 2 1 10K IRQ_SERIRQ
2

R328 2 1 10K THERM_ALERT#

QUANTA
Q18
[21] ICH_SMBCLK 3 1 SCLK [15,26]

+3.3V_SUS 2N7002W-7-F
Title
COMPUTER
ICH9-M (PM,GPIO,SMB,CL)
R178 2 1 10K RSV_WOL_EN
R337 2 1 10K SIO_EXT_SMI# Size Document Number Rev
R344 1 2 100K USB_MCARD1_DET# VM9M 1A

Date: Saturday, June 06, 2009 Sheet 13 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

U19F
U19E +RTC_CELL A23 A15 +1.05V_VCCP
AA26 H5 VCCRTC VCC1_05[01] B15 +1.05V_VCCP +1.5V_RUN
VSS[001] VSS[107] VCC1_05[02]

2
AA27 J23 A6 C15 D11
VSS[002] VSS[108] V5REF VCC1_05[03]

2
AA3 J26 C443 C441 D15 1
VSS[003] VSS[109] VCC1_05[04] R198
AA6 J27 0.1U *0.1U_NC AE1 E15 C268 C282
VSS[004] VSS[110] V5REF_SUS VCC1_05[05]

1
AB1 AC22 R212 10 16 16 F15 0.1U 0.1U 3 1 2
VSS[005] VSS[111] VCC1_05[06]

1
AA23 K28 +5V_RUN 1 2 402 AA24 L11 16 16
AB28 VSS[006] VSS[112] K29 AA25 VCC1_5_B[01] VCC1_05[07] L12 2 10 805
VSS[007] VSS[113] D12 VCC1_5_B[02] VCC1_05[08] 402 402
AB29 L13 AB24 L14
AB4 VSS[008] VSS[114] L15 2 1 +ICH_V5REF_RUN AB25 VCC1_5_B[03] VCC1_05[09] L16 BAT54C T/R
VSS[009] VSS[115] +3.3V_RUN VCC1_5_B[04] VCC1_05[10]
AB5 L2 AC24 L17
VSS[010] VSS[116] RB751V-40 VCC1_5_B[05] VCC1_05[11]
AC17
VSS[011] VSS[117]
L26 2mA AC25
VCC1_5_B[06] VCC1_05[12]
L18

2
AC26 L27 AD24 M11
A VSS[012] VSS[118] C288 VCC1_5_B[07] VCC1_05[13] A
AC27
VSS[013] VSS[119]
L5 AD25
VCC1_5_B[08] VCC1_05[14]
M18 1uH+-20%_800mA
AC3
VSS[014] VSS[120]
L7 Non-iAMT 0.1U AE25
VCC1_5_B[09] VCC1_05[15]
P11

1
R351 10 L38 +1.5V_RUN

CORE
AD1 M12 16 AE26 P18
VSS[015] VSS[121] VCC1_5_B[10] VCC1_05[16] 1uH R320 1
AD10 M13 +5V_SUS 1 2 402 AE27 T11
AD12 VSS[016] VSS[122] M14 AE28 VCC1_5_B[11] VCC1_05[17] T18 +1.5V_DMIPLL 2 1+1.5V_DMIPLL_R 2 1
VSS[017] VSS[123] D13 VCC1_5_B[12] VCC1_05[18]
AD13 M15 AE29 U11
VSS[018] VSS[124] VCC1_5_B[13] VCC1_05[19]

2
AD14 M16 +3.3V_SUS 2 1 +ICH_V5REF_SUS F25 U18
VSS[019] VSS[125] VCC1_5_B[14] VCC1_05[20] C435 C436
AD17 M17 G25 V11
VSS[020] VSS[126] VCC1_5_B[15] VCC1_05[21]

2
AD18 M23 RB751V-40 2mA H24 V12 0.01U 10U
VSS[021] VSS[127] VCC1_5_B[16] VCC1_05[22]

1
AD21 M28 C458 H25 V14 25 6.3
AD28 VSS[022] VSS[128] M29 J24 VCC1_5_B[17] VCC1_05[23] V16 603
0.1U
VSS[023] VSS[129] VCC1_5_B[18] VCC1_05[24]

1
AD29 N11 16 J25 V17
AD4 VSS[024] VSS[130] N12 K24 VCC1_5_B[19] VCC1_05[25] V18 L22
VSS[025] VSS[131] 402 VCC1_5_B[20] VCC1_05[26]
AD5 N13 K25 +VCC_DMI_ICH +1.05V_VCCP
VSS[026] VSS[132] VCC1_5_B[21] BLM21PG331SN1D
AD6
VSS[027] VSS[133]
N14 L23
VCC1_5_B[22] 23mA

1
AD7 N15 L24 R29 805
VSS[028] VSS[134] VCC1_5_B[23] VCCDMIPLL C254
48mA

VCCA3GP
AD9 N16 L25
VSS[029] VSS[135] VCC1_5_B[24] 4.7U
AE12 N17 M24 W23
VSS[030] VSS[136] VCC1_5_B[25] VCC_DMI[1]

2
AE13 N18 M25 Y23 603
VSS[031] VSS[137] VCC1_5_B[26] VCC_DMI[2] 6.3
AE14
VSS[032] VSS[138]
N26
+1.5V_RUN
N23
VCC1_5_B[27] 2mA
AE16 N27 N24 AB23 +1.05V_VCCP
VSS[033] VSS[139] VCC1_5_B[28] V_CPU_IO[1]
AE17 P12 N25 AC23
VSS[034] VSS[140] VCC1_5_B[29] V_CPU_IO[2]

1
AE2
VSS[035] VSS[141]
P13 P24
VCC1_5_B[30] VCC3_3 308mA
AE20 P14 P25 AG29 +3.3V_RUN C246 C262 C255
VSS[036] VSS[142] L21 VCC1_5_B[31] VCC3_3[01] *0.1U_NC *4.7U_NC
AE24
VSS[037] VSS[143]
P15 FB_330ohm+-25%_100mHz_ R24
VCC1_5_B[32]
0.1U

2
AE3 P16 BLM21PG331SN1D R25 AJ6 16 16 603
AE4 VSS[038] VSS[144] P17 805 1.5A_0.09 ohm DC R26 VCC1_5_B[33] VCC3_3[02] 6.3
VSS[039] VSS[145] VCC1_5_B[34] 402
AE6 P2 R27 AC10
AE9 VSS[040] VSS[146] P23 +1.5V_PCIE_ICH T24 VCC1_5_B[35] VCC3_3[07]
VSS[041] VSS[147] VCC1_5_B[36]

2
B AF13
VSS[042] VSS[148]
P28 646mA T27
VCC1_5_B[37] VCC3_3[03]
AD19 B
AF16 P29 T28 AF20 C313 C241 C300

VCCP_CORE
VSS[043] VSS[149] VCC1_5_B[38] VCC3_3[04]
AF18 P4 T29 AG24 0.1U 0.1U 0.1U
VSS[044] VSS[150] VCC1_5_B[39] VCC3_3[05]

1
1

AF22 P7 U24 AC20 16 16 16


VSS[045] VSS[151] VCC1_5_B[40] VCC3_3[06]
2

2
AH26 R11 + C429 U25
VSS[046] VSS[152] 220U C232 C244 C245 VCC1_5_B[41] 402 402 402
AF26 R12 V24 B9
VSS[047] VSS[153] 3528 10U 10U 2.2U VCC1_5_B[42] VCC3_3[08]
AF27 R13 V25 F9
VSS[048] VSS[154] VCC1_5_B[43] VCC3_3[09]
2

2
AF5 R14 4 603 603 10 U23 G3 Remove R348 0ohm resistor
VSS[049] VSS[155] 6.3 6.3 805 VCC1_5_B[44] VCC3_3[10] C298 C249 C291
AF7 R15 W24 G6 Ray 5/27
AF9 VSS[050] VSS[156] R16 W25 VCC1_5_B[45] VCC3_3[11] J2 *0.1U_NC *0.1U_NC 0.1U
VSS[051] VSS[157] VCC1_5_B[46] VCC3_3[12]

PCI

1
AG13 R17 K23 J7 16 16 16
VSS[052] VSS[158] VCC1_5_B[47] VCC3_3[13] +3.3V_RUN
AG16 R18 Y24 K7 402
VSS[053] VSS[159] VCC1_5_B[48] VCC3_3[14]
AG18
VSS[054] VSS[160]
R28 Y25
VCC1_5_B[49] 11mA Remove R229 0ohm resistor
AG20 T12 AJ4 +VCC_HDA_ICH
VSS[055] VSS[161] +VCCSATPLL VCCHDA Ray 5/27
AG23 T13 AJ19
VSS[056] VSS[162] +1.5V_RUN VCCSATAPLL +3.3V_SUS

1
AG3 T14 AJ3 +VCCSUSHDA
VSS[057] VSS[163] VCCSUSHDA C451
AG6 T15 +1.5V_RUN AC16
AG9 VSS[058] VSS[164] T16 AD15 VCC1_5_A[01] AC8 TP_VCCSUS1.05_1 0.1U +VCCSUSHDA
VSS[059] VSS[165] VCC1_5_A[02] VCCSUS1_05[1] PAD T80

2
1
AH12 T17 Remove R342 0ohm resistor AD16 F17 TP_VCCSUS1.05_2 16
VSS[060] VSS[166] VCC1_5_A[03] VCCSUS1_05[2] PAD T62

1
AH14 T23 C273 AE15 11mA
VSS[061] VSS[167] Ray 5/27 1U VCC1_5_A[04] 402 C307

ARX
AH17 B26 AF15
VSS[062] VSS[168] VCC1_5_A[05]
2

AH19 U12 10 AG15 AD8 TP_VCCSUS1.5_1 0.1U


VSS[063] VSS[169] VCC1_5_A[06] VCCSUS1_5[1] PAD T79

2
AH2 U13 603 AH15 16
AH22 VSS[064] VSS[170] U14 AJ15 VCC1_5_A[07] F18 TP_VCCSUS1.5_2 1 2
VSS[065] VSS[171] VCC1_5_A[08] VCCSUS1_5[2] C264 0.1U 402
AH25 U15
VSS[066] VSS[172] L40
AH28 U16 +1.5V_RUN AC11
VSS[067] VSS[173] 10uH VCC1_5_A[09]
AH5 U17 AD11 A18
VSS[068] VSS[174] VCC1_5_A[10] VCCSUS3_3[01] +3.3V_SUS
1

AH8 AD23 805 AE11 D16


VSS[069] VSS[175] VCC1_5_A[11] VCCSUS3_3[02]

VCCPSUS
AJ12 U26 10uH+-20%_100mA C270 AF11 D17
VSS[070] VSS[176] 1U VCC1_5_A[12] VCCSUS3_3[03]

ATX
AJ14 U27 AG10 E22
C VSS[071] VSS[177] VCC1_5_A[13] VCCSUS3_3[04] C
2

AJ17 U3 +VCCSATPLL 47mA 10 AG11


VSS[072] VSS[178] VCC1_5_A[14]

1
AJ8 V1 603 AH10
VSS[073] VSS[179] VCC1_5_A[15]
1

B11 V13 AJ10 AF1 C289 C290 C272


VSS[074] VSS[180] C447 C448 VCC1_5_A[16] VCCSUS3_3[05] 0.22U/10V 0.22U/10V
B14
VSS[075] VSS[181]
V15 VCC1_5_A TOTAL 1.342A VCCSUS 3_3 212mA 0.1U

2
B17 V23 1U 10U AC9 16
VSS[076] VSS[182] VCC1_5_A[17]
2

B2 V28 10 6.3 T1
VSS[077] VSS[183] 603 603 VCCSUS3_3[06] 402
B20 V29 AC18 T2
B23 VSS[078] VSS[184] V4 AC19 VCC1_5_A[18] VCCSUS3_3[07] T3
VSS[079] VSS[185] VCC1_5_A[19] VCCSUS3_3[08]
B5
VSS[080] VSS[186]
V5
VCCSUS3_3[09]
T4 WWAN Noise - ICH improvements
B8 W26 AC21 T5
VSS[081] VSS[187] VCC1_5_A[20] VCCSUS3_3[10]
C26 W27 T6
VSS[082] VSS[188] VCCSUS3_3[11]
C27 W3 G10 U6
VSS[083] VSS[189] +1.5V_RUN VCC1_5_A[21] VCCSUS3_3[12]

1
VCCPUSB

E11 Y1 G9 U7
VSS[084] VSS[190] VCC1_5_A[22] VCCSUS3_3[13] C265 C312 C318 C248 C311
E14
VSS[085] VSS[191]
Y28 11mA VCCSUS3_3[14]
V6
E18 Y29 AC12 V7 *0.1U_NC *0.1U_NC *0.1U_NC *0.1U_NC 0.1U
VSS[086] VSS[192] VCC1_5_A[23] VCCSUS3_3[15]

2
E2 Y4 AC13 W6 16 16 16 16 16
VSS[087] VSS[193] +1.5V_RUN VCC1_5_A[24] VCCSUS3_3[16]
E21 Y5 AC14 W7 402 402 402 402 402
VSS[088] VSS[194] VCC1_5_A[25] VCCSUS3_3[17]
E24 AG28 Y6
VSS[089] VSS[195] VCCSUS3_3[18]
E5 AH6 AJ5 Y7
VSS[090] VSS[196] VCCUSBPLL VCCSUS3_3[19]
2

E8 AF2 T7
VSS[091] VSS[197] VCCSUS3_3[20]
2

F16 B25 C450 AA7


VSS[092] VSS[198] C286 VCC1_5_A[26] +VCCCL1_05
USB CORE

F28 0.1U AB6 G22


VSS[093] VCC1_5_A[27] VCCCL1_05
1

F29 A1 16 0.1U AB7


VSS[094] VSS_NCTF[01] VCC1_5_A[28]
1

G12 A2 16 AC6 G23 +VCCCL1_5


VSS[095] VSS_NCTF[02] 402 VCC1_5_A[29] VCCCL1_5
G14 A28 402 AC7
VSS[096] VSS_NCTF[03] VCC1_5_A[30]

1
G18 A29
VSS[097] VSS_NCTF[04]

2
G21 AH1 TP_VCCSUSLAN1 A10 A24 +3.3V_RUN C250 C252
VSS[098] VSS_NCTF[05] T139 PAD VCCLAN1_05[1] VCCCL3_3[1]
TP_VCCSUSLAN2 C251 *1U_NC
G24
VSS[099] VSS_NCTF[06]
AH29
Non-iAMT T138 PAD A11
VCCLAN1_05[2] VCCCL3_3[2]
B24 0.1U

2
10
G26
VSS[100] VSS_NCTF[07]
AJ1 Non-iAMT *0.1U_NC 16

1
D G27 AJ2 +3.3V_RUN A12 19mA 16 603 D
VSS[101] VSS_NCTF[08] VCCLAN3_3[1] 402
G8
VSS[102] VSS_NCTF[09]
AJ28 19mA B12
VCCLAN3_3[2] 402
2

H2 AJ29
VSS[103] VSS_NCTF[10]
QUANTA
H23 B1 C235 ICH_GLANPLL A27
VSS[104] VSS_NCTF[11] VCCGLANPLL +1.5V_RUN
H28 B29 0.1U
VSS[105] VSS_NCTF[12]
1

23mA
GLAN POWER

H29 16 D28
VSS[106] VCCGLAN1_5[1]
ICH9M REV 1.0 +1.5V_PCIE_ICH
402 D29
E26
E27
VCCGLAN1_5[2]
VCCGLAN1_5[3]
L39 1uH/300mA_8 ICH_GLANPLL
Title
COMPUTER
VCCGLAN1_5[4]
1

1
C237 80mA C433 C434 ICH9-M (POWER,GND)
4.7U A26 10U 2.2U
+3.3V_RUN VCCGLAN3_3
6.3 805 603 Size Document Number Rev
2

603 1mA ICH9M REV 1.0 10 10 VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 14 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

A is required to route to Top +1.8V_SUS +1.8V_SUS +1.8V_SUS +1.8V_SUS


DDR_A_DM[0..7] [7]
SoDIMM for AMTto function. DDR_A_D[0..63] [7] DDR_B_DM[0..7] [7]
V_DDR_MCH_REF V_DDR_MCH_REF
DDR_A_DQS[0..7] [7] DDR_B_D[0..63] [7]
Ch.A SODIMM needs to be DDR_A_DQS#[0..7] [7] DDR_B_DQS[0..7] [7]
populated for Intel AMT support. CN3
DDR_A_MA[0..13] [7,16]
CN2
DDR_B_DQS#[0..7]
DDR_B_MA[0..13]
[7]
[7,16]
1 2 1 2
3 VREF VSS46 4 DDR_A_D4 V_DDR_MCH_REF 3 VREF VSS46 4 DDR_B_D4
DDR_A_D0 VSS47 DQ4 DDR_A_D5 DDR_B_D0 VSS47 DQ4 DDR_B_D1 V_DDR_MCH_REF
5 6 5 6
DDR_A_D1 7 DQ0 DQ5 8 DDR_B_D5 7 DQ0 DQ5 8
DQ1 VSS15 DDR_A_DM0 DQ1 VSS15 DDR_B_DM0
9 10 9 10
DDR_A_DQS#0 11 VSS37 DM0 12 DDR_B_DQS#0 11 VSS37 DM0 12
DQS#0 VSS5 DQS#0 VSS5

1
DDR_A_DQS0 13 14 DDR_A_D7 DDR_B_DQS0 13 14 DDR_B_D6
A DQS0 DQ6 DQS0 DQ6 A

1
15 16 DDR_A_D6 C177 C181 15 16 DDR_B_D3
DDR_A_D3 VSS48 DQ7 0.1U 2.2U DDR_B_D2 VSS48 DQ7 C176 C179
17 18 17 18
DQ2 VSS16 DQ2 VSS16

2
DDR_A_D2 19 20 DDR_A_D13 402 603 DDR_B_D7 19 20 DDR_B_D12 0.1U 2.2U
DQ3 DQ12 DQ3 DQ12

2
21 22 DDR_A_D9 16 10 21 22 DDR_B_D13 402 603
DDR_A_D12 23 VSS38 DQ13 24 DDR_B_D8 23 VSS38 DQ13 24 16 10
DDR_A_D8 DQ8 VSS17 DDR_A_DM1 DDR_B_D9 DQ8 VSS17 DDR_B_DM1
25 26 25 26
27 DQ9 DM1 28 27 DQ9 DM1 28
DDR_A_DQS#1 VSS49 VSS53 DDR_B_DQS#1 VSS49 VSS53
29 30 M_CLK_DDR0 [6] 29 30 M_CLK_DDR3 [6]
DDR_A_DQS1 DQS#1 CK0 DDR_B_DQS1 DQS#1 CK0
31 32 M_CLK_DDR#0 [6] 31 32 M_CLK_DDR#3 [6]
DQS1 CK0# DQS1 CK0#
33 34 33 34
DDR_A_D10 35 VSS39 VSS41 36 DDR_A_D14 DDR_B_D10 35 VSS39 VSS41 36 DDR_B_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15 DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 38 37 38
39 DQ11 DQ15 40 39 DQ11 DQ15 40
VSS50 VSS54 VSS50 VSS54
41 42 41 42
DDR_A_D21 VSS18 VSS20 DDR_A_D20 DDR_B_D17 VSS18 VSS20 DDR_B_D16
43 44 43 44

PC4800 DDR2 SDRAM


DDR_A_D17 DQ16 DQ20 DDR_A_D16 DDR_B_D20 DQ16 DQ20 DDR_B_D21
45 46 45 46
DQ17 DQ21 DQ17 DQ21
47 48 47 48
DDR_A_DQS#2 49 VSS1 VSS6 50 PM_EXTTS#0 DDR_B_DQS#2 49 VSS1 VSS6 50 PM_EXTTS#1
DQS#2 NC3 PM_EXTTS#0 [6] DQS#2 NC3 PM_EXTTS#1 [6]

PC4800 DDR2 SDRAM


DDR_A_DQS2 51 52 DDR_A_DM2 DDR_B_DQS2 51 52 DDR_B_DM2
DQS2 DM2 DQS2 DM2
DDR_A_D22
53
55
VSS19 SO-DIMM (200P)
VSS21
54
56 DDR_A_D18 DDR_B_D22
53
55
VSS19 VSS21
54
56 DDR_B_D18 +1.8V_SUS Place these Caps near So-Dimm1.
DDR_A_D23 DQ18 DQ22 DDR_A_D19 DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 58 57 58
DQ19 DQ23 DQ19 DQ23
59 60 59 60

SO-DIMM (200P)
DDR_A_D24 61 VSS22 VSS24 62 DDR_A_D29 DDR_B_D29 61 VSS22 VSS24 62 DDR_B_D24
DDR_A_D25 DQ24 DQ28 DDR_A_D28 DDR_B_D28 DQ24 DQ28 DDR_B_D25
63 64 63 64
DQ25 DQ29 DQ25 DQ29

1
65 66 65 66 C114 C74 C140 C104 C25
DDR_A_DM3 VSS23 VSS25 DDR_A_DQS#3 DDR_B_DM3 VSS23 VSS25 DDR_B_DQS#3 2.2U 2.2U 2.2U 2.2U 2.2U
67 68 67 68
69 DM3 DQS#3 70 DDR_A_DQS3 69 DM3 DQS#3 70 DDR_B_DQS3 603 603 603 603 603
NC4 DQS3 NC4 DQS3

2
B 71 72 71 72 10 10 10 10 10 B
DDR_A_D30 73 VSS9 VSS10 74 DDR_A_D31 DDR_B_D26 73 VSS9 VSS10 74 DDR_B_D31
DDR_A_D26 DQ26 DQ30 DDR_A_D27 DDR_B_D27 DQ26 DQ30 DDR_B_D30
75 76 75 76
77 DQ27 DQ31 78 77 DQ27 DQ31 78
VSS4 VSS8 VSS4 VSS8 +1.8V_SUS
[6,16] DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA [6,16] [6,16] DDR_CKE3_DIMMB 79 80 DDR_CKE4_DIMMB [6,16]
81 CKE0 CKE1 82 81 CKE0 CKE1 82
VDD7 VDD8 VDD7 VDD8
83
NC1 A15
84 83
NC1 A15
84 Place these Caps near So-Dimm2.
DDR_A_BS2 85 86 DDR_B_BS2 85 86
[7,16] DDR_A_BS2 A16_BA2 A14 DDR_A_MA14 [7,16] [7,16] DDR_B_BS2 A16_BA2 A14 DDR_B_MA14 [7,16]
87 88 87 88
DDR_A_MA12 89 VDD9 VDD11 90 DDR_A_MA11 DDR_B_MA12 89 VDD9 VDD11 90 DDR_B_MA11
A12 A11 A12 A11

1
DDR_A_MA9 91 92 DDR_A_MA7 DDR_B_MA9 91 92 DDR_B_MA7 C16 C22 C28 C30 C18
DDR_A_MA8 A9 A7 DDR_A_MA6 DDR_B_MA8 A9 A7 DDR_B_MA6 2.2U 2.2U 2.2U 2.2U 2.2U
93 94 93 94
A8 A6 A8 A6 603 603 603 603 603
95 96 95 96
VDD5 VDD4 VDD5 VDD4

2
DDR_A_MA5 97 98 DDR_A_MA4 DDR_B_MA5 97 98 DDR_B_MA4 10 10 10 10 10
DDR_A_MA3 A5 A4 DDR_A_MA2 DDR_B_MA3 A5 A4 DDR_B_MA2
99 100 99 100
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_B_MA1 A3 A2 DDR_B_MA0
101 102 101 102
A1 A0 A1 A0
103 104 103 104
DDR_A_MA10 105 VDD10 VDD12 106 DDR_A_BS1 DDR_B_MA10 105 VDD10 VDD12 106 DDR_B_BS1
A10/AP BA1 DDR_A_BS1 [7,16] A10/AP BA1 DDR_B_BS1 [7,16]
DDR_A_BS0 107 108 DDR_A_RAS# DDR_B_BS0 107 108 DDR_B_RAS# +1.8V_SUS
[7,16] DDR_A_BS0 BA0 RAS# DDR_A_RAS# [7,16] [7,16] DDR_B_BS0 BA0 RAS# DDR_B_RAS# [7,16]
DDR_A_WE# 109 110 DDR_B_WE# 109 110 Place these Caps near So-Dimm1.
[7,16] DDR_A_WE# WE# S0# DDR_CS0_DIMMA# [6,16] [7,16] DDR_B_WE# WE# S0# DDR_CS2_DIMMB# [6,16]
111 112 111 112
DDR_A_CAS# VDD2 VDD1 M_ODT0 DDR_B_CAS# VDD2 VDD1 M_ODT2
[7,16] DDR_A_CAS# 113 114 M_ODT0 [6,16] [7,16] DDR_B_CAS# 113 114 M_ODT2 [6,16]
CAS# ODT0 CAS# ODT0

1
115 116 DDR_A_MA13 115 116 DDR_B_MA13
[6,16] DDR_CS1_DIMMA# S1# A13 [6,16] DDR_CS3_DIMMB# S1# A13

1
117 118 117 118 + C65
M_ODT1 VDD3 VDD6 M_ODT3 VDD3 VDD6 C44 C90 C129 C40 *220U_NC
[6,16] M_ODT1 119 120 [6,16] M_ODT3 119 120
ODT1 NC2 ODT1 NC2 0.1U 0.1U 3528
121 122 121 122 *0.1U_NC *0.1U_NC
VSS11 VSS12 VSS11 VSS12

2
DDR_A_D36 123 124 DDR_A_D33 DDR_B_D32 123 124 DDR_B_D36 16 402 402 16 4
DDR_A_D32 125 DQ32 DQ36 126 DDR_A_D37 DDR_B_D33 125 DQ32 DQ36 126 DDR_B_D37 16 16
DQ33 DQ37 DQ33 DQ37
127 128 127 128
DDR_A_DQS#4 VSS26 VSS28 DDR_A_DM4 DDR_B_DQS#4 VSS26 VSS28 DDR_B_DM4 +1.8V_SUS
129 130 129 130
C
DDR_A_DQS4 DQS#4 DM4 DDR_B_DQS4 DQS#4 DM4 C
131
DQS4 VSS42
132 131
DQS4 VSS42
132 Place these Caps near So-Dimm2.
133 134 DDR_A_D34 133 134 DDR_B_D38
DDR_A_D35 VSS2 DQ38 DDR_A_D39 DDR_B_D34 VSS2 DQ38 DDR_B_D39
135 136 135 136
DDR_A_D38 DQ34 DQ39 +3.3V_RUN DDR_B_D35 DQ34 DQ39
137
DQ35 VSS55
138 Non-iAMT 137
DQ35 VSS55
138

1
139 140 DDR_A_D44 139 140 DDR_B_D44
DDR_A_D41 141 VSS27 DQ44 142 DDR_A_D45 DDR_B_D41 141 VSS27 DQ44 142 DDR_B_D45 C24 C34 C37 C145
DDR_A_D40 DQ40 DQ45 DDR_B_D40 DQ40 DQ45 0.1U
143 144 143 144 *0.1U_NC *0.1U_NC *0.1U_NC
DQ41 VSS43 DQ41 VSS43

2
1

145 146 DDR_A_DQS#5 145 146 DDR_B_DQS#5 16 16 16 402


DDR_A_DM5 VSS29 DQS#5 DDR_A_DQS5 C8 C11 DDR_B_DM5 VSS29 DQS#5 DDR_B_DQS5 16
147 148 147 148
DM5 DQS5 2.2U 0.1U DM5 DQS5
149 150 149 150
VSS51 VSS56 VSS51 VSS56
2

DDR_A_D47 151 152 DDR_A_D43 603 402 DDR_B_D47 151 152 DDR_B_D43
DDR_A_D46 DQ42 DQ46 DDR_A_D42 10 16 DDR_B_D42 DQ42 DQ46 DDR_B_D46
153 154 153 154
DQ43 DQ47 DQ43 DQ47
155 156 155 156
DDR_A_D48 157 VSS40 VSS44 158 DDR_A_D52 DDR_B_D52 157 VSS40 VSS44 158 DDR_B_D50
DDR_A_D53 DQ48 DQ52 DDR_A_D49 DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 160 159 160
161 DQ49 DQ53 162 161 DQ49 DQ53 162
VSS52 VSS57 VSS52 VSS57
163 164 M_CLK_DDR1 [6] 163 164 M_CLK_DDR4 [6]
NCTEST CK1 NCTEST CK1
165 166 M_CLK_DDR#1 [6] 165 166 M_CLK_DDR#4 [6]
VSS30 CK1# VSS30 CK1# +3.3V_RUN
DDR_A_DQS#6
DDR_A_DQS6
167
169 DQS#6 VSS45
168
170 DDR_A_DM6
DDR_B_DQS#6
DDR_B_DQS6
167
169 DQS#6 VSS45
168
170 DDR_B_DM6 Non-iAMT
DQS6 DM6 DQS6 DM6
171 172 171 172
DDR_A_D50 VSS31 VSS32 DDR_A_D51 DDR_B_D54 VSS31 VSS32 DDR_B_D48
173 174 173 174
DQ50 DQ54 DQ50 DQ54

1
DDR_A_D55 175 176 DDR_A_D54 DDR_B_D51 175 176 DDR_B_D55
177 DQ51 DQ55 178 177 DQ51 DQ55 178 C9 C10
DDR_A_D56 VSS33 VSS35 DDR_A_D60 DDR_B_D56 VSS33 VSS35 DDR_B_D61 2.2U 0.1U
179 180 179 180
DQ56 DQ60 DQ56 DQ60

2
DDR_A_D61 181 182 DDR_A_D57 DDR_B_D57 181 182 DDR_B_D60 603 402
DQ57 DQ61 DQ57 DQ61 10 16
183 184 183 184
DDR_A_DM7 185 VSS3 VSS7 186 DDR_A_DQS#7 DDR_B_DM7 185 VSS3 VSS7 186 DDR_B_DQS#7
DM7 DQS#7 DM7 DQS#7
D DDR_A_D59
187
189 VSS34 DQS7
188
190
DDR_A_DQS7
DDR_B_D62
187
189 VSS34 DQS7
188
190
DDR_B_DQS7
Non-iAMT D
DQ58 VSS36 DQ58 VSS36
DDR_A_D58 191
193 DQ59 DQ62
192
194
DDR_A_D62
DDR_A_D63 Non-iAMT DDR_B_D59 191
193 DQ59 DQ62
192
194
DDR_B_D58
DDR_B_D63
VSS14 DQ63 VSS14 DQ63 +3.3V_RUN
QUANTA
SDATA 195 196 SDATA 195 196
[13,26] SDATA SDA VSS13 SDA VSS13
SCLK 197 198 SCLK 197 198 R10 10K
[13,26] SCLK SCL SA0 SCL SA0
+3.3V_RUN 199 200 +3.3V_RUN 199 200 2 1
VDD(SPD) SA1 VDD(SPD) SA1
COMPUTER
2

DDR2_SODIMM 2-1734073-2
SMbus address A0 R7 R8 SMbus address A4 R9 Title
10K 10K 10K DDR2 SO-DIMM (200P) X 2
Non-iAMT CLOCK 0,1 CLOCK 2,3
Size Document Number Rev
CKE 0,1 CKE 2,3
1

VM9M 1A

Date: Saturday, June 06, 2009 Sheet 15 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+0.9V_DDR_VTT Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

A A

1
C47 C81 C91 C96 C105 C113 C123 C154 C58 C50 C61 C146 C130 C141
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U

2
402 402 402 402 402 402 402 402 402 402 402 402 402 402
16 16 16 16 16 16 16 16 16 16 16 16 16 16

+0.9V_DDR_VTT

1
C46 C89 C55 C45 C97 C43 C66 C133 C53 C107 C76 C155 C69 C137
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2

2
402 402 402 402 402 402 402 402 402 402 402 402 402 402
16 16 16 16 16 16 16 16 16 16 16 16 16 16

[7,15] DDR_A_MA[0..13]
B B
+0.9V_DDR_VTT
DDR_B_MA[0..13] [7,15]
RP19 RP21
DDR_A_MA7 2 1 1 2 DDR_B_MA11
DDR_A_MA11 4 3 3 4 DDR_B_MA7

56x2 56x2
RP14 RP17
DDR_A_MA4 2 1 1 2 DDR_B_MA6
DDR_A_MA6 4 3 3 4 DDR_B_MA4

56x2 56x2
RP7 RP5
DDR_A_RAS# 2 1 1 2 DDR_B_RAS#
[7,15] DDR_A_RAS# DDR_B_RAS# [7,15]
DDR_A_BS1 4 3 3 4 DDR_B_BS1
[7,15] DDR_A_BS1 DDR_B_BS1 [7,15]
56x2 56x2
RP1 RP2
DDR_A_MA13 2 1 1 2 M_ODT2
M_ODT2 [6,15]
M_ODT0 4 3 3 4 DDR_B_MA13
[6,15] M_ODT0
56x2 56x2
RP22 RP11
DDR_A_BS2 2 1 1 2 DDR_B_MA3
[7,15] DDR_A_BS2
DDR_A_MA12 4 3 3 4 DDR_B_MA1

56x2 56x2
RP18 RP20
C C
DDR_A_MA9 2 1 1 2 DDR_B_MA8
Please these resistor DDR_A_MA8 4 3 3 4 DDR_B_MA12 Please these resistor
closely DIMMB,all 56x2 56x2
closely DIMMA,all
trace length<750 mil. RP13 RP15 trace length<750 mil.
DDR_A_MA3 2 1 1 2 DDR_B_MA5
DDR_A_MA5 4 3 3 4 DDR_B_MA9

56x2 56x2
RP6 RP8
DDR_A_BS0 2 1 1 2 DDR_B_WE#
[7,15] DDR_A_BS0 DDR_B_WE# [7,15]
DDR_A_MA10 4 3 3 4 DDR_B_BS0
DDR_B_BS0 [7,15]
56x2 56x2
RP3 RP4
DDR_A_CAS# 2 1 1 2 DDR_B_CAS#
[7,15] DDR_A_CAS# DDR_B_CAS# [7,15]
DDR_A_WE# 4 3 3 4 DDR_B_MA10
[7,15] DDR_A_WE#
56x2 56x2
RP10 RP9
DDR_A_MA0 2 1 1 2 DDR_B_MA0
DDR_A_MA2 4 3 3 4 DDR_B_MA2

56x2 56x2
R33 1 2 56 R34 2 1 56
[6,15] M_ODT1 M_ODT3 [6,15]
DDR_A_MA1 R44 1 2 56 R59 2 1 56
DDR_B_BS2 [7,15]
R42 1 2 56 R40 2 1 56
[6,15] DDR_CS0_DIMMA# DDR_CS2_DIMMB# [6,15]
R36 1 2 56 R38 2 1 56
[6,15] DDR_CS1_DIMMA# DDR_CS3_DIMMB# [6,15]
R72 1 2 56 R67 2 1 56
[6,15] DDR_CKE0_DIMMA DDR_CKE3_DIMMB [6,15]
D R71 1 2 56 R74 2 1 56 D
[6,15] DDR_CKE1_DIMMA DDR_CKE4_DIMMB [6,15]
R57 1 2 56 R62 2 1 56
[7,15] DDR_A_MA14 DDR_B_MA14 [7,15]

QUANTA
Title
COMPUTER
DDR2 RES ARRAY

Size Document Number Rev


VM9M 1A

Date: Wednesday, June 03, 2009 Sheet 16 of 46


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

Add capacitor pads for improving WWAN.


C224 20P 50 FSA
U4
C194 1 2 *27P_NC 50 FSC
C206 1 2 *27P_NC 50 PCI_SIO
+CK_VDD_PCI 9 61 4 3 RP23
VDD_PCI CPU-0 CLK_CPU_BCLK [3]
C216 1 2 *27P_NC 50 PCI_ICH 4 60 2 1 0x2
VDD_REF CPU-0# CLK_CPU_BCLK# [3]
+CK_VDD_PLL3 23
VDD_PLL3
+CK_VDD_48 16 58 4 3 RP24 CLK_MCH_BCLK [5]
+CK_VDD_SRC 46 VDD_48 CPU-1 57 2 1 0x2
VDD_SRC CPU-1# CLK_MCH_BCLK# [5]

CK505
62
A VDD_CPU A
54 4 3 RP25 CLK_PCIE_MINI1 [26]
SRC-8/CPU_ITP
+CK_VDD_MAIN 19 53 2 1 0x2 CLK_PCIE_MINI1# [26]
Y1 VDD_IO SRC-8#/CPU_ITP#
CLK_XTAL_IN 1 2 CLK_XTAL_OUT
27
33
VDD_IO
VDD_IO
QFN64
43 20 3 4 RP31 MCH_DREFCLK [6]
VDD_IO SRC-0/DOT96
14.318MHZ 52 21 1 2 0x2 MCH_DREFCLK# [6]
VDD_IO SRC-0#/DOT96#
2

2
C187 C188 56
33P 33P VDD_IO
24 3 4 RP32 DREF_SSCLK [6]
SRC-1/SE1
15 25 1 2 0x2 DREF_SSCLK# [6]
GND SRC-1#/SE2
1

1
50 50
14.318MHz 18
22 GND 28 2 1 RP33 CLK_PCIE_SATA [11]
GND SRC-2/SATA
26 29 4 3 0x2 CLK_PCIE_SATA# [11]
30 GND SRC-2#/SATA#
GND
36 31 2 1 RP40 CLK_PCIE_CARD [33]
SATA_CLKREQ# R118 1 2 475/F 49 GND CR#_C/SRC-3 32 4 3 0x2
[13] SATA_CLKREQ# GND CR#_D/SRC-3# CLK_PCIE_CARD# [33]
CLK_3GPLLREQ# R121 1 2 475/F 59
[6] CLK_3GPLLREQ# GND
1 34 2 1 RP30 CLK_MCH_3GPLL [6]
GND SRC-4
35 4 3 0x2 CLK_MCH_3GPLL# [6]
CLK_LPC_DEBUG R131 2 1 33 8 SRC-4#
[26] CLK_LPC_DEBUG CR#_A/PCI-0
10 45 H_STP_PCI# [13]
11 CR_B/PCI-1 PCI_STOP#/SRC-5 44
TME/PCI-2 CPU_STOP#/SRC5-5# H_STP_CPU# [13]
CLK_PCI_8512 R127 2 1 33 PCI_SIO 12
[23] CLK_PCI_8512 SRC5_EN/PCI-3
27M_SEL 13 48 4 3 RP43
27M_SEL/PCI-4 SRC-6 CLK_PCIE_EXPCARD [21]
[12] CLK_PCI_ICH
CLK_PCI_ICH R138 2 1 33 PCI_ICH 14 47 2 1 0x2 CLK_PCIE_EXPCARD# [21]
ITP_EN/PCIF-5# SRC-6#
Remove R107 0ohm
CLK_ICH_48M R143 2 1 33 51 R108 1 2 475/F MINI1CLK_REQ#
[13] CLK_ICH_48M Ray 5/27 CR#_F/SRC-7 R199 1
MINI1CLK_REQ# [26]
50 2 475/F CARD_CLK_REQ# [21]
R145 2.2K FSA CR#_E/SRC-7#
[3,6] CPU_MCH_BSEL0 17
FSB 64 FSA/USB48 37
[3,6] CPU_MCH_BSEL1 FSB/TEST_MODE SRC-9
B R116 2 1 10K FSC 5 38 B
[3,6] CPU_MCH_BSEL2 FSC/TEST_SEL/REF SRC-9#
CLK_ICH_14M R114 2 1 33 55 41 2 1 RP28
[13] CLK_ICH_14M RESET# SRC-10 CLK_PCIE_ICH [12]
[13] CLK_PWRGD 63 42 4 3 0x2 CLK_PCIE_ICH# [12]
CK_PWRGD/PD# SRC-10#
CLK_XTAL_OUT 2 40 4 3 RP29
XOUT CR#_H/SRC-11 CLK_PCIE_LOM [34]
CLK_XTAL_IN 3 39 2 1 0x2 CLK_PCIE_LOM# [34]
CLK_LPC_DEBUG XIN CR#_G/SRC-11#
[3,18,23] SMBDAT1 6
7 SDATA 65
[3,18,23] SMBCLK1 SCLK GND
2

C205
33P EMI 4/3 +3.3V_RUN
SLG8SP513V
1

50 CLK_3GPLLREQ# R122 2 1 10K


SATA_CLKREQ# R119 2 1 10K
MINI1CLK_REQ# R109 2 1 10K
+3.3V_RUN

+3.3V_RUN

H_STP_PCI# R111 1 10K PCI_SIO R130 1 2 *10K_NC


+3.3V_RUN UMA without iAMT H_STP_CPU# R112
2
2 1 10K

2
L16 BLM21PG600SN1D R142
+CK_VDD_MAIN *10K_NC
805
120 ohms@100Mhz FSC FSB FSA CPU SRC PCI

1
1

C215 C213 C207 C195 C178 C182 C211 PCI_ICH


C
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U *10U_NC
1 0 1 100 100 33 C
2

402 402 402 402 402 402 603


16 16 16 16 16 16 6.3
0 0 1 133 100 33

2
R135
0 1 1 166 100 33
L17 BLM21PG600SN1D R113 2.2
+CK_VDD_PCI
10K 0 1 0 200 100 33
1 2
805
0 0 0 266 100 33

1
1

120 ohms@100Mhz
C199
0.1U
1 0 0 333 100 33
2

402
16
1 1 0 400 100 33
R136 2.2
+CK_VDD_PLL3
1 1 1 RSVD 100 33
1 2
1

C214 27M_SEL
0.1U
2

402 27M_SEL PIN20 PIN21 PIN24 PIN25


16
(PIN13)
R140 2.2 96/ 96/
1 2 +CK_VDD_48 0=UMA DOT96T DOT96C 100M_T 100M_C
1

C210 C212
1 = Disc.
0.1U 4.7U 27M_SEL GRFX down SRCT0 SRCC0 27Mout 27MSSout
2

D 402 603 D
16 6.3

R317 2.2 2 R132 QUANTA


1 2 +CK_VDD_SRC 10K

COMPUTER
1

C180 Title
0.1U CLOCK GENERATOR
2

402
16 Size Document Number Rev
VM9M 1A

Date: Saturday, June 06, 2009 Sheet 17 of 46


1 2 3 4 5 6 7 8
5 4 3 2 1

+LCDVCC +3.3V_RUN

41
J1
+15V_ALW +3.3V_RUN +LCDVCC 40

41
Q12 40 LCD_ACLK-
39 LCD_ACLK- [6]
FDC655BN 39 LCD_ACLK+
38 LCD_ACLK+ [6]
38

1
6 37
37

2
5 4 36 LCD_A2- C6 C5 C351
36 LCD_A2- [6]
R277 2 35 LCD_A2+ 0.1U 0.047U 0.1U
35 LCD_A2+ [6]

2
330K 1 34 402 402
34

2
33 LCD_A1- 16 10 16
33 LCD_A1- [6]

2
R278 32 LCD_A1+
D 32 LCD_A1+ [6] D

3
47 C352 C7 31
LCDVCC_ON 805 22U 0.01U 31 LCD_A0-
30 LCD_A0- [6]
30

1
1206 29 LCD_A0+
29 LCD_A0+ [6]

1
2
10 25 28
28

2
27 LCD_DDCCLK [6]
R276 C350 27
26 LCD_DDCDAT [6]
*100K_NC 0.01U 26 25
25 +PWR_SRC +5V_RUN

1
25 24 USBP4_D+
24

1
USBP4_D-
23
23
22
For Camera
+3.3V_SUS 22 21
21 +5V_RUN

3
20 DMIC_CLK [32]
20

1
2 2 19 DMIC_DATA [32]
Q13 19 C12 C4 C353
18
18

1
Q16 2N7002W-7-F 17 0.1U 0.1U 0.1U
17 +3.3V_RUN

2
R274 2N7002W-7-F 16 603 603 402
47K 16 25 25 16
15 +LCDVCC
15
14
14
Support the new imbeded 13
13 LCD_TST [23]

2
12 BACKLITEON
diagnostics. 12 11
11 SMBCLK1 [3,17,23]
10 SMBDAT1 [3,17,23]
10
[6] ENVDD 1
9
9 Adress : A9H --Contrast

3
8 LCD_BAK# [23]
3 EN_LCDVCC 2 8 7 AAH --Backlight
7 PWM_VADJ [23]
Q17 6
6 LCD_CBL_DET# [23]
2

2 D19 2N7002W-7-F 5
[23] LCDVCC_TST_EN 5

1
BAT54C T/R R319 4
10K
4 3
3
C 2 +PWR_SRC
C
2 1

42
1
1

50671-04041-001

42

2
C3 C2
33P 33P
Stephen 5/7

1
50 50
Camera

R3 0
[12] ICH_USBP4+ 1 2 USBP4_D+
[12] ICH_USBP4- 1 2 USBP4_D-
R4 0 +PWR_SRC
+PWR_SRC
stephen 6/03 40mil 40mil

Remove R11 0ohm


Ray 6/1
+3.3V_RUN
2

R285
*10K_NC C23 *33P_NC
B B
2 1 LCD_ACLK-
C26 *33P_NC
1

BACKLITEON 1 2 LCD_ACLK+
[6] BIA_PWM
C208 *33P_NC
1 2 LCD_A2-
For DPST support C218 *33P_NC
1 2 LCD_A2+
C219 *33P_NC
1 2 LCD_A1-
C220 *33P_NC
1 2 LCD_A1+
C221 *33P_NC
1 2 LCD_A0-
C222 *33P_NC
1 2 LCD_A0+

close to J1 for EMI solution

A A

QUANTA
Title
COMPUTER
LCD CONN & CK-SSCD

Size Document Number Rev


VM9M 1A

Date: Saturday, June 06, 2009 Sheet 18 of 46


5 4 3 2 1
A B C D E

4 4

+3.3V_RUN +5V_RUN

2
D1

2
SDM10K45-7-F

1
Layout Note:
Setting R,G,B treac D23 D24 D31
impedance to 50 ohm.

3
*DA204U_NC *DA204U_NC *DA204U_NC
+5V_CRT_REF
L30 BLM18BB750SN1D RED
[6] VGA_RED
603

16
L28 BLM18BB750SN1D GREEN JVGA1
[6] VGA_GRN
603 070546FR015S21JZR
6