EXPERIMENT - 8

AIM: To Design and simulate D, T, SR, JK and master-slave flip flops.

EDA TOOL USED:Xilinx ISE 14.7

METHODOLOGY:
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can
store one bit of information. The main difference between latches and flip-flops is that for
latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes.
GATED SR LATCH AND ITS TRUTH TABLE:

When using static gates as building blocks, the most fundamental latch is the simple SRlatch,
where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR
logic gates. The stored bit is present on the output marked Q. Gated SR Latch is accomplished by
adding an enable input to the original implementationof the latch that allow the latch to be
enabled or disabled in accordance with the enable input.

TRUTH TABLE:

E S R Q Q_BAR
0 X X LATCH LATCH
1 0 0 LATCH LATCH
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0
Q(next) = E ? (S +QR):Q

GATED D LATCH AND ITS TRUTH TABLE:

The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that
removesthe possibility of invalid input states.

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 TRUTH TABLE:

E D Q Q_BAR
0 0 Latch Latch
0 1 Latch Latch
1 0 0 1
1 1 1 0
Q(next) = E?D:Q;

GATED JK LATCH AND ITS TRUTH TABLE:

JK latch is also extension of Gated SR latch by removing possibility of metastable state with
introduction of toggle state.

TRUTH TABLE:

E S R Q Q_BAR
0 X X LATCH LATCH
1 0 0 LATCH LATCH
1 0 1 0 1
1 1 0 1 0
1 1 1 Q_BAR Q

Q(next) = E ? (JQ+RQ) : Q

GATED T LATCH AND ITS TRUTH TABLE:

T latch can be considered extension of JK

latch.
TRUTH TABLE:

E T Q Q_BAR
0 0 Latch Latch
0 1 Latch Latch
1 0 Latch Latch
1 1 Q_BAR Q

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 Q(next) = E ? (Q^T) : Q

Flip-flops are clocked circuits whose output may change on an active edge of the clock signal
based onits input. Unlike latches, which are transparent and in which output can change when the
gated signal isasserted upon the input change, flip-flops normally would not change the output
upon input change evenwhen the clock signal is asserted. Flip-flops are widely used in
synchronous circuits.

Charatcterstics shown by all the above latches are similar to flipflops except in place of enable
signal an edge trigger signal (clock ) mechanism is to be included.

Master Slave FlipFlop:

Master Slave flip flopare the cascaded combination of two flip-flops among which the first is
designated as master flip-flop while the next is called slave flip-flop.

TRUTH TABLE:

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GATED SR LATCH:
VERILOG CODE:
Gate Level:
modulesr_latch_with_enable(q,q_bar,preset, andinitial_r(w_r,r,en);
clear,en,s,r); nor one(w1,w_r,q_bar);
input s; nor two(w2,w_s,q);
input r; and three(w3,preset,~clear);
input preset; and four(w4,~preset,clear);
input clear; or five(q,w1,w3);
inputen; or six(q_bar,w2,w4);
output q;
outputq_bar; endmodule

wire w1,w2,w3,w4,w_s,w_r; DataFlow:

andintial_s(w_s,s,en);

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modulesr_latch_with_enable(q,q_bar,preset, input preset;
clear,en,s,r); input clear;
input s; inputen;
input r; output q;
input preset; outputq_bar;
input clear;
inputen; reg q;
output q; regq_bar;
outputq_bar;
always@(*)
assign q = begin
(preset&(~clear))|(~((en&r)|q_bar)); case({preset,clear,en,s,r})
assignq_bar = 5'b10000,5'b10001,5'b10010,5'b10011,5'b10
((~preset)&(clear))|(~((en&s)|q)); 100,5'b10101,5'b10110,5'b10111:begin q <=
1;q_bar <= 0;end
endmodule 5'b01000,5'b01001,5'b01010,5'b01011,5'b01
100,5'b01101,5'b01110,5'b01111:begin q <=
0;q_bar <= 1;end
Behavioral: 5'b00100:begin q <= q;q_bar<= q_bar;end
5'b00101:begin q <= 0;q_bar <= 1;end
5'b00110:begin q <= 1;q_bar <= 0;end
modulesr_latch_with_enable
default:begin q <= q;q_bar<= q_bar;end
(q,q_bar,preset,clear,en,s,r);
endcase
input s;
end
input r;

RTL SCHEMATIC:

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TEST FIXTURE:
preset = 1;clear = 0;s = 1;r = 0;en =0 ;
#50;s = 0;r = 0;
#50;s = 0;r = 1;
#50;s = 0;r = 0;
#50;preset = 0;clear = 1;s = 1;r = 0;
#50;s = 0;r = 0;
#50;s = 0;r = 1;
#50;s = 0;r = 0;
#50;preset = 0;clear = 0;s = 1;r = 0;
#50;s = 0;r = 0;
#50;s = 0;r = 1;
#50;s = 0;r = 0;
always
#18 en = ~en;

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OUTPUT:

GATED D LATCH:
VERILOG CODE:
Gate Level:
moduleD_Latch_with_enable(q,q_bar,preset,clear,d,en);
input d;
input en;
input preset;
input clear;
output q;
outputq_bar;

wired_bar;
not first(d_bar,d);
sr_latch_with_enable second(q,q_bar,preset,clear,en,d,d_bar);
endmodule

Behavioral:

moduleD_Latch_with_enable(q,q_bar,preset,clear,d,en);
input d;
inputen;
input preset;
input clear;
output q;
outputq_bar;

reg q;
regq_bar;
always@(*)
begin
case({preset,clear,en,d})

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4'b1000,4'b1001,4'b1010,4'b1011:begin q <= 1;q_bar <= 0;end
4'b0100,4'b0101,4'b0110,4'b0111:begin q <= 0;q_bar <= 1;end
4'b0010:begin q <= 0;q_bar <= 1;end
4'b0011:begin q <= 1;q_bar <= 0;end
default:begin q <= q;q_bar<= q_bar;end
endcase
end

endmodule
RTL SCHEMATIC:

TEST FIXTURE:
preset = 1;clear = 0;d = 0;en =0 ;
#50;d = 1;
#50;preset = 0;clear = 1;d = 0;
#50;d = 1;
#50;preset = 0;clear = 0;d = 0;
#50;d = 1;
#50; d = 0;
always
#18 en = ~en;

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OUTPUT:

JK LATCH:
VERILOG CODE:
moduleJK_latch(q,q_bar,preset,clear,j,k,en); input clear;
input j; input en;
input k; output q;
input en; output q_bar;
input preset;
input clear; reg q;
output q; regq_bar;
output q_bar;
always@(*)
wires,r; begin
case({preset,clear,en,s,r})
and a1(s,j,q_bar); 5'b10000,5'b10001,5'b10010,5'b10011,5'b10
and a2(r,k,q); 100,5'b10101,5'b10110,5'b10111:begin q <=
1;q_bar <= 0;end
sr_latch_with_enablesr1(q,q_bar,preset,clear 5'b01000,5'b01001,5'b01010,5'b01011,5'b01
,en,s,r); 100,5'b01101,5'b01110,5'b01111:begin q <=
0;q_bar <= 1;end
endmodule 5'b00100:begin q <= q;q_bar<= q_bar;end
5'b00101:begin q <= 0;q_bar <= 1;end
5'b00110:begin q <= 1;q_bar <= 0;end
modulesr_latch_with_enable(q,q_bar,preset, default:begin q <= q;q_bar<= q_bar;end
clear,en,s,r); endcase
input s; end
input r;
input preset; endmodule

TEST FIXTURE:
en = 0;preset = 1;clear = 0;j = 1;k = 0; #50;j = 0;k = 1;
#50;j = 0;k = 0; #50;j = 0;k = 0;

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#50;j = 1;k = 1; #50;j = 0;k = 1;
#50;preset = 0;clear = 1;j = 1;k = 0; #50;j = 0;k = 0;
#50;j = 0;k = 0; #50;j = 1;k = 1;
#50;j = 0;k = 1; always
#50;j = 0;k = 0; #18 en = ~en;
#50;j = 1;k = 1;
#50;preset = 0;clear = 0;j = 1;k = 0;
#50;j = 0;k = 0;
RTL SCHEMATIC:

OUTPUT:

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T LATCH:
VERILOG CODE:
moduleT_latch_with_enable(q,q_bar,preset,clear,t,en);
input t;
input en;
input preset;
input clear;
output q;
output q_bar;

JK_latchfirst(q,q_bar,preset,clear,t,t,en);

endmodule

RTL SCHEMATIC:

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TEST FIXTURE:
en = 0;preset = 1;clear = 0;t = 0;
#50;t = 1;
#50;preset = 0;clear = 1;t = 0;
#50;t = 1;
#50;preset = 0;clear = 0;t = 0;
#74;t = 1;
#100;t = 0;
always
#25 en = ~en;
OUTPUT:

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SR FLIPFLOP:
VERILOG CODE:
Data Flow Level

module Sr_flip(input [1:0] s,input clk,output begin

q,qnop q=0;
); qnop=0;
Sr_latch gu({s[0]&clk,s[1]&clk},q,qnop); end
endmodule always @(*)
begin
module Sr_latch(input [1:0] s,output reg q=~(qnop|s[0]);
q,qnop qnop=~(q|s[1]);
); end
initial endmodule

Gate Level nor (Qbar, S, Q);

module SR_latch_gate (input R, input S,

output Q, output Qbar); endmodule
nor (Q, R, Qbar);

Behavioural Level
module SP_flip(input [1:0]s,input endcase
clk,reset,output reg sr end
); endmodule
always@(posedge clk or negedge reset)
begin TEST FIXTURE:
if(set)
sr<=1; s = 01;
if(reset==0) clk = 0;
sr<=0; set=0;
case(s) reset =1;
2'b01:sr<=0; #5 reset=0;
2'b10:sr<=1; #35
2'b11:sr<=1'bx; s=00;

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 #35 #35
s=10; s=11;

RTL SCHEMATIC:

OUTPUT:

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D FLIPFLOP:
VERILOG CODE:
module D_FF(input set,reset,clk,d,output begin
reg q,q_bar); q <= 1'b0;
q_bar<= 1'b1;
always@(posedge clk or posedge set or end
posedge reset) else
begin begin
if (set) q <= d;
begin q_bar<= ~d;
q <= 1'b1; end
q_bar<= 1'b0; end
end endmodule
else if (reset)

TEST FIXTURE:
#25;d = 1;
set = 0; reset = 0;clk = 0;d = 0; #25;d = 0;
#100;set = 1; reset = 0; end
#100;set = 0; reset = 1; always
#100;set = 0; reset = 0;d = 1; #20 clk = ~clk;

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RTL SCHEMATIC:

OUTPUT:

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JK FLIPFLOP:

VERILOG CODE:
module jk_ff(input j,k,set,reset,clk,output q <= q_bar;
reg q,q_bar); q_bar<= q;
end
always@(posedge clk or posedge set else
or posedge reset) begin
begin q <= 1'bx;
if (set) q_bar<= 1'bx;
begin end
q <= 1'b1; end
q_bar<= 1'b0;
end endmodule
else if (reset)
begin TEST FIXTURE:
q <= 1'b0;
q_bar<= 1'b1; clk = 0;set = 1; reset = 0;j = 1;k = 0;
end #50;j = 0;k = 0;
else if( j == 0 & k == 1) #50;j = 0;k = 1;
begin #50;j = 0;k = 0;
q <= 1'b0; #50;j = 1;k = 1;
q_bar<= 1'b1; #50;set = 0; reset = 1;j = 1;k = 0;
end #50;j = 0;k = 0;
else if ( j == 1 & k == 0) #50;j = 0;k = 1;
begin #50;j = 0;k = 0;
q <= 1'b1; #50;j = 1;k = 1;
q_bar<= 1'b0; #50;set = 0; reset = 0;j = 1;k = 0;
end #50;j = 0;k = 0;
else if(j == 0 & k == 0) #50;j = 0;k = 1;
begin #50;j = 0;k = 0;
q <= q; #50;j = 1;k = 1;
q_bar<= q_bar;
end always
else if(j == 1 & k == 1) #10 clk = ~clk;
begin

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RTL SCHEMATIC:

OUTPUT:

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T-FLIPFLOP:
VERILOG CODE:
module T_FF(input set,reset,clk,t, output reg q_bar<= q_bar;
q,q_bar); end
else
always@(posedge clk or posedge set or begin
posedge reset) q <= q_bar;
begin q_bar<= q;
if (set) end
begin end
q <= 1'b1; endmodule
q_bar<= 1'b0; TEST FIXTURE:
end clk = 0;set = 1; reset = 0;t = 0;
else if (reset) #50;t = 1;
begin #50; set = 0; reset = 1;t = 0;
q <= 1'b0; #50;t = 1;
q_bar<= 1'b1; #50; set = 0; reset = 0;t = 0;
end #100;t = 1;
else if(t == 0) always #10 clk = ~clk;
begin
q <= q;

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RTL SCHEMATIC:

OUTPUT:

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MASTER SLAVE FLIPFLOP:
VERILOG CODE:
FILE 1: begin
module MASTER_SLAVE(input clk,j,k case({en,s,r})
,output reg q,qbar); 3'b100:
begin
q <= q;
wire m,mbar,s,r,clkbar; qbar<= qbar;
and a1(s,j,qbar); end
and a2(r,k,q); 3'b101:
not a3(clkbar,clk); begin
q <= 0;
latch a4(m,mbar,s,r,clk); qbar<= 1;
latch a5(q,qbar, m, mbar, clkbar); end
3'b110:
endmodule begin
q <= 1;
FILE 2: qbar<= 0;
module latch(input s,r,en , output reg end
q,qbar,); default:
begin
initial q <= q;
begin qbar<= qbar;
q <= 0; end
qbar<= 1; endcase
end end

always@(*) #1 endmodule

TEST FIXTURE:

initial begin #205;j = 0;k = 0;

clk = 0;j = 0;k = 0; #205;j = 1;k = 1;
#200;j = 1;k = 0; end
#205;j = 0;k = 0; always
#205;j = 0;k = 1; #25 clk = ~clk

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RTL SCHEMATIC:

OUTPUT:

RESULT:

Design and simulation of D, T, SR, JK & master slave flipflops has been completed.

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