VHDL Lab

2. Write a VHDL code for parameterized up/down counter .Test using test bench .
FIG 2: UP/DOWN COUNTER
Description
The figure above shows an up/down counter. If the counter is enabled, up or down counting
operation can be performed. If up/down is ‘HIGH’ ,then the counter counts up, else the counter
counts down.
iNPUT output
clear enable count clk qa, qb, qc
1 x x x 0,0,0
0 x x d2,d1,d0
0 0 x q=q
0 1 1 q = q+1
0 1 0 q = q-1
Table 2:Truth Table for Up/Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------
entity updown is
generic (n:natural:=4);
port(count,clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));
end updown;
-------------------------------------------------
architecture behav of updown is
begin
gate: process(clock,reset,count)
variable temp:unsigned((n-1) downto 0);
begin
if(reset='1') then
temp := "0000";
q <= std_logic_vector(temp);
elsif(clock'event and clock='1' and count='1') then
temp := temp +1;
elsif(clock'event and clock='1' and count='0') then
temp := temp-1;
end if;
end process gate;
end behav;
Test Bench
library ieee;
-------------------------------------------------------------------------------------------------------
entity updown_tb is
end updown_tb;
-------------------------------------------------------------------------------------------------------
architecture behav of updown_tb is
signal count_tb,clock_tb,reset_tb: std_logic;
signal q_tb: std_logic_vector(3 downto 0);
begin
dut: entity work.updown
port map(count => count_tb,clock => clock_tb,reset => reset_tb,q => q_tb);
--------------------------------------------------------------------------------------------------------
-- Concurrent process to offer Clock inputs
start:process
begin
for i in 0 to 30 loop
clock_tb <= '1';
wait for 2 ns;

clock_tb <= '0';
wait for 2 ns;
end loop;
wait;
end process start;
start1:process
begin
reset_tb <= '1';
wait for 4 ns;
reset_tb <= '0';
wait for 43 ns;
end loop;
wait;
end process start1;
start2:process
begin
count_tb <= '1';
wait for 34 ns;

count_tb <= '0';
wait for 45 ns;
end loop;
wait;
end process start2;
end behav;
Ring Counter
library ieee;
-------------------------------------------------
entity ring is
port(clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));
end ring;
-------------------------------------------------
architecture behav of ring is
begin
gate: process(clock,reset)
begin
if(reset='1') then
temp := "0001";
elsif(clock'event and clock='1' ) then
temp := (temp(0) & temp(n-1 downto 1));
end if;
end process gate;
end behav;
Test bench
library ieee;
-------------------------------------------------------------------------------------------------------
entity ring_tb is
end ring_tb;
-------------------------------------------------------------------------------------------------------
architecture behav of ring_tb is
signal clock_tb,reset_tb: std_logic;
signal q_tb: std_logic_vector(3 downto 0);
begin
dut: entity work.ring
port map(clock => clock_tb,reset => reset_tb,q => q_tb);
--------------------------------------------------------------------------------------------------------
-- Concurrent process to offer Clock inputs
start:process
begin
clock_tb <= '1';
wait for 2 ns;

clock_tb <= '0';
wait for 2 ns;
end loop;
wait;
end process start;
start1:process
begin
reset_tb <= '1';
wait for 4 ns;
reset_tb <= '0';
wait for 43 ns;
end loop;
wait;
end process start1;
end behav;
Johnson Counter
library ieee;
-----------------------------------------------
entity johnsoncounter is
port(clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));
end johnsoncounter;
------------------------------------------------
architecture behav of johnsoncounter is
begin
gate: process(clock)
begin
if((clock'event) and (clock='1')) then
if(reset='1') then
temp := "0000";
else
temp := (not temp(0) & temp((n-1) downto 1));

end if;
end if;
end process gate;
end behav;
Test Bench
library ieee;
-------------------------------------------------
entity johnsoncounter_tb is
end johnsoncounter_tb;
-------------------------------------------------
architecture behav of johnsoncounter_tb is
signal clock_tb,reset_tb:std_logic;
signal q_tb:std_logic_vector(3 downto 0);
begin
dut: entity work.johnsoncounter
port map(clock=>clock_tb,reset=>reset_tb,q=>q_tb);
start: process
begin
clock_tb <= '1';
wait for 5 ns;
clock_tb <='0';
wait for 5 ns;
end process start;
start1: process
begin
reset_tb <= '1';
wait for 2 ns;
reset_tb <= '0';
wait for 40 ns;
end process start1;
end behav;
Barrel Shifter
library ieee;
------------------------------------------
entity barrelshifter is
generic (n:natural:=8;s:natural:=3);
port(datain: in std_logic_vector((n-1) downto 0);
dataout:out std_logic_vector((n-1) downto 0);
shift: in std_logic);
end barrelshifter;
architecture behav of barrelshifter is
begin
start: process(datain,shift)
begin
if(shift='1') then
dataout <= (datain((s-1) downto 0) & datain((n-1) downto s));
else
dataout <= (datain((n-s-1) downto 0) & datain((n-1) downto (n-s)));
end if;
end process start;

end behav;
Test Bench
library ieee;
-------------------------------------------------
entity barrelshifter_tb is
end barrelshifter_tb;
architecture behav of barrelshifter_tb is
signal datain_tb:std_logic_vector(7 downto 0):="00000000";
signal dataout_tb:std_logic_vector(7 downto 0);
signal shift_tb:std_logic;
begin
dut: entity work.barrelshifter
port map(datain => datain_tb,dataout => dataout_tb,shift => shift_tb);
start: process
variable temp:unsigned (7 downto 0):="00000000";
begin
temp := temp + 1;
datain_tb <= std_logic_vector(temp);
wait for 5 ns;
end loop;
end process start;
start1: process
begin
shift_tb <= '1';
wait for 50 ns;
shift_tb <= '0';
wait for 50 ns;
end process start1;
end behav;
Binary 2 BCD
library ieee;
----------------------------------------------
entity bin2bcd is
port(datain: in std_logic_vector(3 downto 0);
dataout: out std_logic_vector(4 downto 0));

end bin2bcd;
architecture behav of bin2bcd is
begin
start: process(datain)
variable temp:unsigned(4 downto 0):="00000";
variable temp1:unsigned(3 downto 0):="0000";
begin
temp1 := unsigned(datain);
temp := "00000";
if (temp > 4) then
temp := temp + 3;
temp := (temp+temp)+("000"&temp1(3));
--dataout <= std_logic_vector(temp);
else
temp := (temp+temp)+("000"&temp1(3));
--dataout <= std_logic_vector(temp);
end if;
temp1:=temp1(2 downto 0) & "0";
end loop;
dataout <= std_logic_vector(temp);
end process start;
end behav;
Test Bench
library ieee;
-----------------------------------------
entity bin2bcd_tb is
end bin2bcd_tb;
-----------------------------------------
architecture behav of bin2bcd_tb is
signal dataout_tb:std_logic_vector(4 downto 0):="00000";
begin
name:entity work.bin2bcd
port map(datain => datain_tb,dataout => dataout_tb);
start: process
begin
wait for 5 ns;
temp := temp+1;
wait for 5 ns;
end loop;
wait;
end process start;
end behav;
Gray2excess3
library ieee;
----------------------------------------------
entity gray2excess3 is
dataout1,dataout: out std_logic_vector(3 downto 0)
);
end gray2excess3;
architecture behav of gray2excess3 is
begin
variable temp:unsigned(3 downto 0);
begin
temp(3) := (datain(3));
temp(2) := temp(3) xor datain(2);

if(temp < "1101") then
dataout <= std_logic_vector(temp + "0011");
else
dataout <= "ZZZZ";
end if;
end process start;
end behav;
Test Bench
library ieee;
-----------------------------------------
entity gray2excess3_tb is
end gray2excess3_tb;
-----------------------------------------
architecture behav of gray2excess3_tb is
signal dataout_tb1:std_logic_vector(3 downto 0):="0000";
begin
name:entity work.gray2excess3
port map(datain => datain_tb,dataout=> dataout_tb,dataout1=> dataout_tb1);
start: process
begin
wait for 5 ns;
temp:= temp+1;
wait for 5 ns;
end loop;
wait;
end process start;
end behav;
Excess2gray
library ieee;
----------------------------------------------
entity xs32gray is
dataout1,dataout: out std_logic_vector(3 downto 0)
);
end xs32gray;
architecture behav of xs32gray is
begin
variable temp:unsigned(3 downto 0);
begin
temp := unsigned(datain);
temp := temp-3;
dataout1 <= std_logic_vector(temp);
temp := ('0' & temp(3 downto 1)) xor temp;
dataout <= std_logic_vector(temp);
end process start;
end behav;
Test bench
library ieee;
-----------------------------------------
entity xs32gray_tb is
end xs32gray_tb;
-----------------------------------------
architecture behav of xs32gray_tb is
signal dataout_tb1:std_logic_vector(3 downto 0):="0000";
begin
name:entity work.xs32gray
port map(datain => datain_tb,dataout=> dataout_tb,dataout1=> dataout_tb1);
start: process
begin
wait for 5 ns;
temp:= temp+1;
wait for 5 ns;

end loop;
wait;
end process start;
end behav;

VHDL Lab

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VHDL Lab

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2. Write a VHDL code for parameterized up/down counter .Test using test bench .

FIG 2: UP/DOWN COUNTER

Table 2:Truth Table for Up/Down Counter

port(count,clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));

architecture behav of updown is

variable temp:unsigned((n-1) downto 0);

elsif(clock'event and clock='1' and count='1') then

temp := temp +1;

elsif(clock'event and clock='1' and count='0') then

end process gate;

architecture behav of updown_tb is

signal count_tb,clock_tb,reset_tb: std_logic;

signal q_tb: std_logic_vector(3 downto 0);

dut: entity work.updown

-- Concurrent process to offer Clock inputs

clock_tb <= '1';

wait for 2 ns;

wait for 2 ns;

end process start;

reset_tb <= '1';

wait for 4 ns;

reset_tb <= '0';

wait for 43 ns;

end process start1;

count_tb <= '1';

wait for 34 ns;

wait for 45 ns;

end process start2;

port(clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));

architecture behav of ring is

variable temp:unsigned((n-1) downto 0);

elsif(clock'event and clock='1' ) then

temp := (temp(0) & temp(n-1 downto 1));

end process gate;

architecture behav of ring_tb is

signal clock_tb,reset_tb: std_logic;

signal q_tb: std_logic_vector(3 downto 0);

dut: entity work.ring

port map(clock => clock_tb,reset => reset_tb,q => q_tb);

-- Concurrent process to offer Clock inputs

clock_tb <= '1';

wait for 2 ns;

wait for 2 ns;

end process start;

reset_tb <= '1';

wait for 4 ns;

reset_tb <= '0';

wait for 43 ns;

end process start1;

port(clock,reset:in std_logic;q:out std_logic_vector((n-1) downto 0));

architecture behav of johnsoncounter is

variable temp:unsigned((n-1) downto 0);

if((clock'event) and (clock='1')) then

temp := (not temp(0) & temp((n-1) downto 1));

end process gate;

architecture behav of johnsoncounter_tb is

signal q_tb:std_logic_vector(3 downto 0);

clock_tb <= '1';

wait for 5 ns;

wait for 5 ns;

end process start;

reset_tb <= '1';