Ee315b Reader 2013 Stanford Dataconverters PDF

EE315B
VLSI Data Conversion Circuits
- Autumn 2013 -
Boris Murmann
Stanford University
murmann@stanford.edu
Table of Contents
Chapter 1 Introduction
Chapter 2 Sampling, Reconstruction, Quantization
Chapter 3 Spectral Performance Metrics
Chapter 4 Nyquist Rate DACs
Chapter 5 Sampling Circuits
Chapter 6 Voltage Comparators
Chapter 7 Flash ADCs
Chapter 8 SAR ADCs
Chapter 9 Pipeline ADCs
Chapter 10 Time Interleaving
Chapter 11 Oversampling ADCs and DACs
Chapter 12 Energy Limits in A/D Converters
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Introduction
Boris Murmann
Stanford University
Copyright 2013 by Boris Murmann
B. Murmann EE315B - Chapter 1 1
Motivation (1)
This course
Signal
A/D
Conditioning
Analog
Digital
Media and
Processing
Transducers
Signal
D/A
Conditioning
Sensors, Actuators,
Antennas, Storage Media, ...

Motivation (2)
Benefits of digital signal processing

Reduced sensitivity to "analog" noise
Enhanced functionality and flexibility
Amenable to automated design & test
Direct benefit from the scaling of VLSI technology
"Arbitrary" precision
Issues
Data converters are difficult to design
Especially due to ever-increasing performance requirements
Data converters often present a performance bottleneck
Speed, resolution or power dissipation of the A/D or D/A
converter can limit overall system performance
A/D Converter ca. 1954
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html

Data Converter Applications (1)
Consumer electronics
Audio, TV, Video
Digital Cameras
Automotive control
Appliances
Toys
Communications
Mobile Phones
Personal Data Assistants
Wireless Transceivers
Routers, Modems
Data Converter Applications (2)
Computing and Control

Storage media
Sound Cards
Data acquisition cards
Instrumentation
Lab bench equipment
Semiconductor test equipment
Scientific equipment
Medical equipment

Example 1
[Poulton, ISSCC 2003]

High performance digital
oscilloscopes rely on extremely
high performance ADCs
Example
20 GSample/s, 8-bit ADC
10 W Power dissipation
Example 2
Schvan, ISSCC 2008

Time interleaved architecture using 160 (!) SAR ADCs for
optical networks

Example 3
A typical cell phone contains:

4 Rx ADCs
Dual Standard, I/Q
4 Tx DACs
3 Auxiliary ADCs Audio, Tx/Rx power
control, Battery
8 Auxiliary DACs charge
control, display, ...
A total of 19 data converters!
Example 4
[Mehta, ISSCC2005]
Low-cost, single chip solutions require embedded data

conversion
Example: 802.11g Wireless LAN chip
2x 11-bit DAC, 176 MSamples/s
2x 9-bit ADC, 80 MSamples/s

Trend Toward Lower ADC Energy
-6
10
-8
10
P/f s [J]
-10
10
-12
10 ISSCC & VLSI 2006-2013
ISSCC & VLSI 1998-2005
20 30 40 50 60 70 80 90 100 110
SNDR [dB]
B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
Course Objective
Acquire a thorough understanding of the basic principles and

challenges in data converter design
Focus on concepts that are unlikely to expire within the next
decade
Preparation for further study of state-of-the-art "fine-tuned"
realizations
Strategy
Acquire breadth via a complete system walkthrough and a
survey of existing architectures
Acquire depth through a midterm project that entails design
and thorough characterization of a specific circuit example in
modern technology

Staff and Website
Teaching assistant
Vaibhav Tripathi
Administrative support
Ann Guerra, Allen 207
Lecture videos are provided on the web, but please come to
class to keep the discussion intercative
Coursework web page
http://coursework.stanford.edu/homepage/F13/F13-EE-315B-01.html
Please visit the discussion forum regularly
Only enrolled students have full access
Preparation
Course prerequisites
EE214B or equivalent
Device physics and models
Transistor level analog circuits, elementary gain stages
Frequency response, feedback, noise
Prior exposure to Spice, Matlab
Basic signals and systems
Basic probability
Please talk to me if you are not sure whether you have the
required background

Analog Circuit Sequence
Assignments
Homework: (20%)
Handed out on Tue, due following Tue after lecture (1 pm)
Lowest HW score is dropped in final grade calculation
Midterm Project: (40%)
Transistor level design and simulation of a data converter
sub-block (no layout)
Prepare a project report in the format and style of an IEEE
journal paper
Final Exam (40%)

Honor Code
Please remember you are bound by the honor code

I will trust you not to cheat
I will try not to tempt you
But if you are found cheating it is very serious
There is a formal hearing
You can be thrown out of Stanford
Save yourself and me a huge hassle and be honest
For more info
http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/
honorcode.pdf
Tools and Technology
Primary tools
Cadence Virtuoso Schematic Editor
Cadence Virtuoso Analog Design Environment
Cadence SpectreRF simulator
You can use your own tools/setups at own risk
Getting started
Read tutorials and setup info provided in the CAD section of the
course website
EE315A/B Technology
0.18-m CMOS
BSIM3v3 models provided under /usr/class/ee315b/models

Reference Books
M. Pelgrom, Analog-to-Digital Conversion, Springer, 2010

Gustavsson, Wikner, Tan, CMOS Data Converters for
Communications, Kluwer, 2000
A. Rodrguez-Vzquez, F. Medeiro, and E. Janssens, CMOS Telecom
Data Converters, Kluwer Academic Publishers, 2003
W. Kester, The Data Conversion Handbook, Newnes, 2005
http://www.analog.com/library/analogdialogue/archives/39-06/data_conversion_handbook.html
B. Razavi, Data Conversion System Design, IEEE Press, 1995

R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters,
Wiley-IEEE Press, 2004
R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-
Analog Converters, 2nd ed., Kluwer, 2003
J. G. Proakis, and D. G. Manolakis, Digital Signal Processing,
Prentice Hall, 1995
Course Topics
Ideal sampling, reconstruction and quantization

Sampling circuits
Voltage comparators
Nyquist-rate ADCs and DACs
Oversampled ADCs and DACs
Data converter performance trends and limits
Data converter testing, simulation techniques

Sampling, Reconstruction, Quantization
Boris Murmann
Stanford University
The Data Conversion Problem
Real world signals

Continuous time, continuous amplitude
Digital abstraction
Discrete time, discrete amplitude
Two problems
How to discretize in time and amplitude
A/D conversion
How to "undescretize" in time and amplitude
D/A conversion

Overview
We'll fist look at these building blocks from a functional, "black

box" perspective
Refine later and look at implementations
Uniform Sampling and Quantization
Most common way of performing A/D

conversion
Sample signal uniformly in time
Quantize signal uniformly in
amplitude
Key questions
How much "noise" is added due
to amplitude quantization?
How can we reconstruct the
signal back into analog form?
How fast do we need to sample?
Must avoid "aliasing"

Aliasing Example (1)
1
fs = = 1000kHz
Amplitude
Ts
fsig = 101kHz
Time
f
v sig ( t ) = cos ( 2 fin t ) v sig ( n ) = cos 2 in n
fs
n 101
t n Ts = = cos 2 n
fs 1000
1
fs = = 1000kHz
Amplitude
Ts
fsig = 899kHz
Time
899 899 101

v sig ( n ) = cos 2 n = cos 2 1 n = cos 2 n
1000 1000 1000

1
fs = = 1000kHz
Amplitude
Ts
fsig = 1101kHz
Time
1101 1101 101

v sig ( n ) = cos 2 n = cos 2 1 n = cos 2 n
1000 1000 1000
Consequence
The frequencies fsig and Nfs fsig (N integer), are

indistinguishable in the discrete time domain

Sampling Theorem
In order to prevent aliasing, we need

fs
fsig ,max <
2
The sampling rate fs=2fsig,max is called the Nyquist rate

Two possibilities
Sample fast enough to cover all spectral components,
including "parasitic" ones outside band of interest
Limit fsig,max through filtering
Brick Wall Anti-Alias Filter

Practical Anti-Alias Filter
Desired Parasitic
Signal Tone
Continuous Attenuation
Time
0 B fs/2 fs-B fs ... f
Discrete
Time
0 B/fs 0.5 f/fs
Need to sample faster than Nyquist rate to get good attenuation

"Oversampling"
How much Oversampling?
[v.d. Plassche, p.41]

Alias
Rejection
Filter Order
fs/fsig,max
Can tradeoff sampling speed against filter order

In high speed converters, making fs/fsig,max>10 is usually
impossible or too costly
Means that we need fairly high order filters

Classes of Sampling
Nyquist-rate sampling (fs > 2fsig,max)
Nyquist data converters
In practice always slightly oversampled
Oversampling (fs >> 2fsig,max)
Oversampled data converters
Anti-alias filtering is often trivial
Oversampling also helps reduce "quantization noise"
More later
Undersampling, subsampling (fs < 2fsig,max)
Exploit aliasing to mix RF/IF signals down to baseband
See e.g. Pekau & Haslett, JSSC 11/2005
Subsampling
Aliasing is "non-destructive" if signal is band limited around some

carrier frequency
Downfolding of noise is a severe issue in practical subsampling mixers
Typically achieve noise figure no better than 20 dB (!)

The Reconstruction Problem
As long as we sample fast

enough, x(n) contains all
information about x(t)
fs > 2fsig,max
How to reconstruct x(t) from x(n)?
Ideal interpolation formula

x( t ) = x( n ) g( t nTs )
n =
sin( fs t )
g(t ) =
fs t
Very hard to build an analog

circuit that does this
Zero-Order Hold Reconstruction
The most practical way of

reconstructing the continuous
time signal is to simply "hold" the
discrete time values
Either for full period Ts or a
fraction thereof
Other schemes exist, e.g.
partial-order hold
See [Jha, TCAS II, 11/2008]
What does this do to the signal

spectrum?
We'll analyze this in two steps
First look at infinitely narrow
reconstruction pulses
Dirac Pulses
xd(t) is zero between pulses

Note that x(n) is undefined at
these times

xd ( t ) = x( t ) ( t nTs )
n =
Multiplication in time means

convolution in frequency
Resulting spectrum
1 n
Xd ( f ) = X f
Ts n = Ts
Spectrum
Spectrum of Dirac signal contains replicas of Vin(f) at integer

multiples of the sampling frequency

Finite Hold Pulse
Consider the general case with a

rectangular pulse 0 < Tp Ts
The time domain signal on the left
follows from convolving the Dirac
sequence with a rectangular unit pulse
Spectrum follows from multiplication with
Fourier transform of the pulse
sin( fTp ) jfTp
Hp (f ) = Tp e
fTp
Tp sin( fTp ) jfTp

n
Xp (f ) = e Xf
Ts fTp n = Ts
Amplitude Envelope
Envelope with Hold Pulse Tp=Ts
0.9
0.8
0.7
0.6
Tp sin( fTp )
abs(H(f))
0.5
Ts fTp
0.4
0.3
0.2
0.1
0
0 0.5 1 1.5 2 2.5 3
f/fs
f/fs

Envelope with Hold Pulse Tp=0.5Ts
0.9
0.8
Tp=Ts
0.7
0.6
Tp sin( fTp ) abs(H(f))
0.5
Ts fTp
0.4
Tp=0.5Ts
0.3
0.2
0.1
0
0 0.5 1 1.5 2 2.5 3
f/fs
f/f s
Example
1
Spectrum of
Continuous Time 0.5
Pulse Train (Arbitrary
Example) 0
0 0.5 1 1.5 2 2.5 3
1
ZOH Transfer
Function 0.5
("Sinc Distortion")
0
0 0.5 1 1.5 2 2.5 3
1
ZOH output, original spectrum

Spectrum of 0.5
Staircase
Approximation 0
0 0.5 1 1.5 2 2.5 3
f/fs

Reconstruction Filter
1
Also called
0.9
smoothing filter
Filter
0.8
Same situation
0.7
as with anti-alias
Spectrum
0.6 filter
0.5 A brick wall
0.4 filter would be
nice
0.3
Oversampling
0.2
helps reduce
0.1
filter order
0
0 0.5 1 1.5 2 2.5 3
f/fs
Summary
Must obey sampling theorem fs > 2fsig,max,

Usually dictates anti-aliasing filter
If sampling theorem is met, continuous time signal can be
recovered from discrete time sequence without loss of
information
A zero order hold in conjunction with a smoothing filter is the
most common way to reconstruct
May need to add pre- or post-emphasis to cancel droop due
to sinc envelope
Oversampling helps reduce order of anti-aliasing and
reconstruction filters

Recap
Next, look at
Transfer functions of quantizer and DAC
Impact of quantization error
Quantization of an Analog Signal

Transfer Function
Quantization step
Vq (quantized output)
Slope=1
Quantization error has
sawtooth shape
Bounded by /2, +/2
Ideally
x (input) Infinite input range and
Error eq=q-x infinite number of
quantization levels
eq (quantization error)
+/2 In practice
Finite input range and
finite number of
-/2 quantization levels
Output is a digital word
x (input) (not an analog voltage)

Conceptual Model of a Quantizer
Encoding block determines how quantized levels are mapped

into digital codes
Note that this model is not meant to represent an actual
hardware implementation
Its purpose is to show that quantization and encoding are
conceptually separate operations
Changing the encoding of a quantizer has no interesting
implications on its function or performance
Encoding Example for a B-Bit Quantizer
111
Example: B=3
110 23=8 distinct output codes
Digital Output
101
100 Diagram on the left shows
011 "straight-binary encoding"
010
001
See e.g. Analog Devices "MT-
000 009: Data Converter Codes" for
other encoding schemes
Analog Input
http://www.analog.com/en/content/0
,2886,760%255F788%255F91285,
eq (quantization error)
00.html
+/2
Quantization error grows out of
bounds beyond code boundaries
-/2 We define the full scale range
FSR (FSR) as the maximum input range
x (input)
that satisfies |eq| /2
Implies that FSR=2B

Nomenclature
Overloading - Occurs when an input outside
the FSR is applied
Transition level Input value at the
transition between two codes. By standard
convention, the transition level T(k) lies
between codes k-1 and k
Code width The difference between
adjacent transition levels. By standard
convention, the code width W(k)=T(k+1)-T(k)
Note that the code width of the first and
last code (000 and 111 on previous slide)
is undefined
LSB size (or width) synonymous with
code width [IEEE Standard 1241-2000]
Implementation Specific Technicalities
So far, we avoided specifying the absolute location of the code

range with respect to "zero" input
The zero input location depends on the particular
implementation of the quantizer
Bipolar input, mid-rise or mid-tread quantizer
Unipolar input
The next slide shows the case with
Bipolar input
The quantizer accepts positive and negative inputs
Represents the common case of a differential circuit
Mid-rise characteristic
The center of the transfer function (zero), coincides with a
transition level

Bipolar Mid-Rise Quantizer
111
110
Digital Output 101
100
011
010
001
000
Analog Input
-FSR/2 0 +FSR/2
Nothing new here
Bipolar Mid-Tread Quantizer

In theory, less sensitive to infinitesimal disturbance around zero
In practice, offsets larger than /2 (due to device mismatch)
often make this argument irrelevant
Asymmetric full-scale range, unless we use odd number of codes
111
110
Digital Output
101
100
011
010
001
000
Analog Input
FSR/2 + /2 0 FSR/2 - /2
Unipolar Quantizer
Usually define origin where first code and straight line fit intersect
Otherwise, there would be a systematic offset
Usable range is reduced by /2 below zero
111
110
Digital Output
101
100
011
010
001
000
Analog Input
0 FSR - /2
Effect of Quantization Error on Signal

Two aspects
How much noise power does quantization add to samples?
How is this noise power distributed in frequency?
Quantization error is a deterministic function of the signal
Should be able answer above questions using a
deterministic analysis
But, unfortunately, such an analysis strongly depends on the
chosen signal and can be very complex
Strategy
Build basic intuition using simple deterministic signals
Next, abandon idea of deterministic representation and
revert to a "general" statistical model (to be used with
caution!)

Ramp Input
Applying a ramp signal (periodic sawtooth) at the input of the
quantizer gives the following time domain waveform for eq
0.6
0.4
0.2
e (t) []
0
q
-0.2
-0.4
0 50 100 150
Time [arbitrary units]
What is the average power of this waveform?

Integrate over one period
T/2
1 2
T T/ 2
eq2 = eq2 ( t )dt eq ( t ) = t eq2 =
T 12
Sine Wave Input

1 1
Vin
0.8 0.8
V
q
0.6 0.6
0.4 0.4
0.2 0.2
eq(t) []
[Volts]
0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Time [arbitrary units] Time [arbitrary units]
Integration is not straightforward

Quantization Error Histogram
Sinusoidal input signal with fsig=101Hz, sampled at fs=1000Hz

8-bit quantizer
Mean=0.000LSB, Var=1.034LSB2/12
120
100
80
Count
60
40
20
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
e /
q
Distribution is "almost" uniform

Can approximate average power by integrating uniform
distribution
Statistical Model of Quantization Error

Assumption: eq(x) has a uniform probability density
This approximation holds reasonably well in practice when
Signal spans large number of quantization steps
Signal is "sufficiently active"
Quantizer does not overload
+ / 2
eq
Mean eq =
deq = 0
/ 2
+ / 2
eq 2 2
Variance eq2 =
deq =
12
/ 2

Reality Check (1)
Input sequence consists of 1000 samples drawn from Gaussian

distribution, 4=FSR
Mean=-0.004LSB, Var=1.038LSB2/12
150
100
Count
50
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
eq/
Error power close to that of uniform approximation
Reality Check (2)
Another sine wave example, but now fsig/fs=100/1000

What's going on here?
Mean=-0.000LSB, Var=0.629LSB2/12
500
400
300
Count
200
100
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
eq/

Analysis (1)
Amplitude fsig/fs=100/1000
Time
Sampled signal is repetitive and has only a few distinct values

This also means that the quantizer generates only a few
distinct values of eq; not a uniform distribution
Analysis (2)
f
v sig ( n ) = cos 2 in n
fs
Signal repeats every m samples, where m is the smallest

integer that satisfies
fin
m = integer
fs
101
m = integer m = 1000
1000
100
m = integer m = 10
1000
This means that eq(n) has at best 10 distinct values, even if we

take many more samples

Signal-to-Quantization-Noise Ratio
Assuming uniform distribution of eq and a full-scale sinusoidal

input, we have
2
1 2B

Psig 2 2
SQNR = = 2
= 1.5 22B = 6.02B + 1.76 dB
Pqnoise
12
B (Number of Bits) SQNR

8 50 dB
12 74 dB
16 98 dB
20 122 dB
Quantization Noise Spectrum (1)

How is the quantization noise power distributed in frequency?
First think about applying a sine wave to a quantizer, without
sampling (output is continuous time)
+ many more harmonics
[Y. Tsividis, ICASSP 2004]
Quantization results in an "infinite" number of harmonics

Now sample the signal at the output
All harmonics (an "infinite" number of them) will alias into
band from 0 to fs/2
Quantization noise spectrum becomes "white"
[Y. Tsividis, ICASSP 2004]
Interchanging sampling and quantization wont change this

situation

Can show that the quantization noise power is indeed
distributed (approximately) uniformly in frequency
Again, this is provided that the quantization error is
"sufficiently random"
2 2

12 fs
References
W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., pp. 446-72,
July 1948.
B. Widrow, "A study of rough amplitude quantization by means of Nyquist
sampling theory," IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 1956.
A. Sripad and D. A. Snyder, "A necessary and sufficient condition for
quantization errors to be uniform and white," IEEE Trans. Acoustics, Speech,
and Signal Processing, pp. 442-448, Oct 1977.

Ideal DAC
Essentially a digitally controlled voltage, current or charge source

Example below is for unipolar DAC
Ideal DAC does not introduce quantization error!
Static Nonidealities
Static deviations of transfer characteristics from ideality

Offset
Gain error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Useful references
Analog Devices MT-010: The Importance of Data Converter
Static Specifications
http://www.analog.com/en/content/0,2886,761%255F795%255F91286,00.html
"Understanding Data Converters," Texas Instruments
Application Report LAA013, 1995.
http://focus.ti.com/lit/an/slaa013/slaa013.pdf

Offset and Gain Error
Conceptually simple, but lots of (uninteresting) subtleties in how

exactly these errors should be defined
Unipolar versus bipolar, endpoint versus midpoint
specification
Definition in presence of nonlinearities
General idea (neglecting staircase nature of transfer functions):
ADC Offset and Gain Error
Definitions based on bottom and top endpoints of transfer characteristic

LSB before first transition and LSB after last transition
Offset is the deviation of bottom endpoint from its ideal location
Gain error is the deviation of top endpoint from its ideal location with
offset removed
Both quantities are measured in LSB or as percentage of full-scale range
Gain Error
Dout Dout
Ideal Ideal
Vin Vin
Offset
DAC Offset and Gain Error
Same idea, except that endpoints are directly defined by analog

output values at minimum and maximum digital input
Also note that errors are specified along the vertical axis
Comments on Offset and Gain Errors

Definitions on the previous slides are the ones typically used in industry
IEEE Standard suggest somewhat more sophisticated definitions
based on least square curve fitting
Technically more suitable metric when the transfer characteristics are
significantly non-uniform or nonlinear
Generally, it is non-trivial to build a converter with very good gain/offset
specifications
Nevertheless, since gain and offset affect all codes uniformly, these
errors tend to be easy to correct
E.g. using a digital pre- or post-processing operation
Also, many applications are insensitive to a certain level of gain and
offset errors
E.g. audio signals, communication-type signals, ...
More interesting aspect: linearity

DNL and INL

Differential Nonlinearity (DNL)
In an ideal world, all ADC codes would have equal width; all
DAC output increments would have same size
DNL(k) is a vector that quantifies for each code k the deviation
of this width from the "average" width (step size)
DNL(k) is a measure of uniformity, it does not depend on gain
and offset errors
Scaling and shifting a transfer characteristic does not alter its
uniformity and hence DNL(k)
Let's look at an example
ADC DNL Example (1)
Code (k) W [V]

0 undefined
1 1
2 0.5
3 1
4 1.5
5 0
6 1.5
7 undefined

ADC DNL Example (2)
What is the average code width?
ADC with perfect uniformity would divide the range between
first and last transition into 6 equal pieces
Hence calculate average code width (i.e. LSB size) as
7.5V 2V
Wavg = = 0.9167V
6
Now calculate DNL(k) for each code k using
W(k) Wavg
DNL(k) =
Wavg
Result
Code (k) DNL [LSB]

1 0.09
2 -0.45
3 0.09
4 0.64
5 -1.00
6 0.64
Positive/negative DNL implies wide/narrow code, respectively

DNL = -1 LSB implies missing code
Impossible to have DNL < -1 LSB for an ADC
But possible to have DNL > +1 LSB
Can show that sum over all DNL(k) is equal to zero

A Typical ADC DNL Plot
[Ahmed, JSSC 12/2005]
People speak about DNL often only in terms of min/max number

across all codes
E.g. DNL = +0.63/-0.91 LSB
Might argue in some cases that any code with DNL < -0.9 LSB
is essentially a missing code
Why ?
Impact of Noise
[W. Kester, "ADC Input Noise: The

Good, The Bad, and The Ugly. Is
No Noise Good Noise?" Analogue
Dialogue, Feb. 2006]
In essentially all moderate to high-resolution ADCs, the transition

levels carry noise that is somewhat comparable to the size of an LSB
Noise "smears out" DNL, can hide missing codes
Especially for converters whose input referred (thermal) noise is
larger than an LSB, DNL is a "fairly useless" metric

DAC DNL
Same idea applies
Find output increments for each digital code
Find increment that divides range into equal steps
Calculate DNL for each code k using
Step(k) Stepavg
DNL(k) =
Stepavg
One difference between ADC and DAC is that DAC DNL can be
less than -1 LSB
How ?
Non-Monotonic DAC
Step(3) Stepavg
DNL(3) =
Stepavg
0.5V 1V
= = 1.5LSB
1V
In a DAC, DNL < -1LSB implies non-monotinicity

How about a non-monotonic ADC?

Non-Monotonic ADC
Code 2 has two transition levels W(2) is ill defined

DNL is ill-defined!
Not a very big issue, because a non-monotonic ADC is usually
not what we'll design for in practice
Integral Nonlinearity (INL)

General idea
For each "relevant point" of the transfer characteristic,
quantify distance from a straight line drawn through the
endpoints
An alternative, less common definition uses a least square fit
line as a reference
Just as with DNL, the INL of a converter is by definition
independent of gain and offset errors

ADC INL Example (1)
"Straight line" reference

is uniform staircase
between first and last
transition
INL for each code is
T(k) Tuniform (k)
INL(k) =
Wavg
Obviously INL(1) = 0
and INL(7) = 0
INL(0) is undefined
ADC INL Example (2)

Can show that k 1
INL(k) = DNL(i)
i =1
Means that once we computed DNL, we can easily find INL

using a cumulative sum operation on the DNL vector
Using DNL values from last lecture, we find
Code (k) DNL [LSB] INL [LSB]

1 0.09 0
2 -0.45 0.09
3 0.09 -0.36
4 0.64 -0.27
5 -1.00 0.36
6 0.64 -0.64
7 undefined 0

Result
A Typical ADC DNL/INL Plot
[Ishii, Custom
Integrated Circuits
Conference, 2005]
DNL/INL signature often reveals architectural details

E.g. major transitions
We'll see more examples in the context of DACs
Since INL is a cumulative measure, it turns out to be less
sensitive than DNL to thermal noise "smearing"
DAC INL
Same idea applies
Find ideal output values that lie on a straight line between
endpoints
Calculate INL for each code k using
Vout (k) Voutuniform (k)

INL(k) =
Stepavg
Interesting property related to DAC INL

If for all codes |INL| < 0.5 LSB, it
follows that all |DNL| < 1 LSB
A sufficient (but not necessary)
condition for monotonicity
How to Measure DNL/INL in the Lab?
DAC
Apply all input codes, measure output with a precision
voltmeter
ADC
A little more tricky
One option is to build a servo loop that finds the code
transitions
See e.g. Kester, page 5.36
A more popular approach is histogram testing

Basic Histogram Test Setup
Kester, p. 5.39
Histogram Example
Kester, p. 5.40

Sinusoidal Input
Kester, p. 5.42
Preferred over ramp or
triangular test signals
It is easier much easier
to generate a high
fidelity sinusoid
The histogram now
takes on a bathtub
shape, which can be
mathematically inverted
to find the DNL
Correction for Sinusoidal pdf
References
M. V. Bossche, J. Schoukens, and J. Renneboog, Dynamic
Testing and Diagnostics of A/D Converters, IEEE TCAS,
Aug. 1986
IEEE Standard 1057
Kester, Section 5.4
It turns out that is not necessary to know the exact amplitude
and offset of the sine wave input
There exists some confusion about this
The code on the next slide does all the required math to undo
the bathtub shape

DNL/INL Code
function [dnl,inl] = dnl_inl_sin(y); % transition levels

%DNL_INL_SIN T = -cos(pi*ch/sum(h));
% dnl and inl ADC output
% input y contains the ADC output % linearized histogram
% vector obtained from quantizing a hlin = T(2:end) - T(1:end-1);
% sinusoid
% truncate at least first and last

% Boris Murmann, Aug 2002
% bin, more if input did not clip ADC
% Bernhard Boser, Sept 2002
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% histogram boundaries
minbin=min(y);
maxbin=max(y); % calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
% histogram dnl= [0 hlin_trunc/lsb-1];

h = hist(y, minbin:maxbin); misscodes = length(find(dnl<-0.9));
% cumulative histogram % calculate inl

ch = cumsum(h); inl= cumsum(dnl);
DNL/INL Code Test
% converter model
DNL = +0.7 / -0.71 LSB, 0 missing codes (DNL<-0.9)
B = 6; % bits 1
range = 2^(B-1) - 1; 0.5

DNL [LSB]
% thresholds (ideal converter) 0
th = -range:range; % ideal thresholds

-0.5
th(20) = th(20)+0.7; % error

-1
-30 -20 -10 0 10 20 30
code
INL = +0.76 / -0.063 LSB

fs = 1e6; 0.8
fx = 494e3 + pi; % try fs/10! 0.6

INL [LSB]
C = round(100 * 2^B / (fs / fx)); 0.4
0.2
0
t = 0:1/fs:C/fx;
-0.2
x = (range+1) * sin(2*pi*fx.*t); -30 -20 -10 0
code
10 20 30
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);

Limitations of ADC Histogram Testing
Cannot detect non-monotonicity

The histogram does not capture in which order the codes
occurred
Cannot detect erratic dynamics
E.g. 123, 123, , 123, 0, 124, 124,
Must look directly at ADC output to detect these
Similarly, random noise is not detected and improves DNL
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10,
Reference
B. Ginetti and P. Jespers, Reliability of Code Density Test
for High Resolution ADCs, Electronics Letters, pp. 2231-
2233, Nov. 1991
Hiding DNL Problems in the Noise
INL suggests that there

may be missing codes
But, DNL is "smeared
out" by noise and does
not show this
Always look at both
DNL/INL
INL usually does not lie
[Source: David Robertson, Analog Devices]

Spectral Performance Metrics
Boris Murmann
Stanford University
Dynamic Performance Metrics
Time domain
Glitch impulse, aperture uncertainty, settling time,
We'll look at these later, in the context of specific circuits
Frequency domain
Performance metrics follow from looking at converter or
building block output spectrum
"Spectral performance metrics"
Basic idea: Apply one or more tones at converter input
Expect same tone(s) at output, all other frequency components
represent nonidealities
Important to realize that both static (DNL, INL) and dynamic
errors contribute to frequency domain non-ideality

Alphabet Soup of Spectral Metrics
SNR - Signal-to-noise ratio

SNDR (SINAD) - Signal-to-(noise+distortion) ratio
ENOB - Effective number of bits
DR - Dynamic range
SFDR - Spurious free dynamic range
HD Harmonic distortion
THD - Total harmonic distortion
ERBW - Effective Resolution Bandwidth
IMD - Intermodulation distortion
MTPR - Multi-tone power ratio
DAC Tone Test/Simulation Setup

Typical DAC Output Spectrum
[Hendriks, "Specifying Communications DACs, IEEE Spectrum, July 1997]
ADC Tone Test/Simulation Setup
Basic idea
Apply a clean sinusoid
Compute ADC performance metrics based on output spectrum

Aside: How to Make a Clean
Sinusoid in the Lab?
BP Filter
Amplitude
Signal generator harmonics
...
0 fin 2fin 3fin 4fin ... f
www.tte.com, or
www.allenavionics.com
Discrete Fourier Transform Basics
DFT takes a block of N time domain samples (spaced Ts=1/fs)

and yields a set of N frequency bins
N1
X(k) = x(n)e j2kn/N
n=0
Bin k represents frequency content at kfs/N [Hz]

DFT frequency resolution
Proportional to 1/(NTs) in [Hz/bin]
NTs is total time spent gathering samples
A DFT with N=2integer can be found using a computationally
efficient algorithm
FFT = Fast Fourier Transform

Matlab Example
clear; 50
N = 100;
fs = 1000;
40
fx = 100;
DFT Magnitude
30
x = cos(2*pi*fx/fs*[0:N-1]);
s = abs(fft(x));
plot(s, 'linewidth', 2); 20
10
0
0 20 40 60 80 100
Bin #
Normalized Plot with Frequency Axis

N = 100;
fs = 1000;
0
fx = 100;
FS = 1; % full-scale amplitude
-50
DFT Magnitude [dBFS]
x = FS*cos(2*pi*fx/fs*[0:N-1]); -100
s = abs(fft(x));
% remove redundant half of spectrum -150
s = s(1:end/2);
% normalize magnitudes to dBFS -200
% dbFS = dB relative to full-scale
s = 20*log10(2*s/N/FS); -250
% frequency vector
-300
f = [0:N/2-1]/N;
-350
plot(f, s, 'linewidth', 2); 0 0.1 0.2 0.3 0.4 0.5
xlabel('Frequency [f/fs]') Frequency [f/fs]
ylabel('DFT Magnitude [dBFS]')

Another Example
0
Same as before, but
-10
now fx=101
-20

This doesn't look the
-30
spectrum of a
sinusoid -40
What's going on? -50
-60
-70
-80
-90
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
Spectral Leakage
The DFT computes the
spectrum of the periodic
repetition of its input
A sequence that contains a non-
integer number of sine wave
cycles has discontinuities in its
periodic repetition
Discontinuity looks like a
high frequency signal
component
Power spreads across
spectrum
Two ways to deal with this
Ensure integer number of
periods
Windowing

Integer Number of Cycles
0
N = 100;
cycles = 9; -50

fs = 1000;
-100
fx = fs*cycles/N;
-150
Usable test -200

frequencies are
limited to a multiple -250
of fs/N
-300
-350
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
Windowing
Spectral leakage can be attenuated by windowing the time
samples prior to the DFT
Windows taper smoothly down to zero at the beginning and the
end of the observation window
Time domain samples are multiplied by window coefficients on a
sample-by-sample basis
Means convolution in frequency
Sine wave tone and other spectral components smear out
over several bins
Lots of window functions to chose from
Tradeoff: attenuation versus smearing
Example: Hann Window

Hann Window
N=64;
wvtool(hann(N))
Time domain Frequency domain

50
1
0.8 0
Magnitude (dB)
Amplitude
0.6
-50
0.4
-100
0.2
0 -150
10 20 30 40 50 60 0 0.2 0.4 0.6 0.8
Samples Normalized Frequency ( rad/sample)
Spectrum with Window
N = 100; 0
No window
fs = 1000;
Hann window
-20
fx = 101;
A = 1;
-40
x = A*cos(2*pi*fx/fs*[0:N-1]); -60
s = abs(fft(x));
x1 = x.*hann(N); -80
s1 = abs(fft(x1));
-100
-120
-140
0 0.1 0.2 0.3 0.4 0.5
f/fs

Integer Cycles versus Windowing
Integer number of cycles
Test signal falls into single DFT bin
Requires careful choice of signal frequency
Ideal for simulations
In lab measurements, can lock sampling and signal
frequency generators (PLL)
"Coherent sampling"
Windowing
No restrictions on signal frequency
Signal and harmonics distributed over several DFT bins
Beware of smeared out nonidealities
Requires more samples for given accuracy
More info
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1040
Example
N = 2048;
Now that we've cycles = 67;
"calibrated" our test fs = 1000;
system, let's look at fx = fs*cycles/N;
some spectra that LSB = 2/2^10;
involve nonidealities
%generate signal, quantize (mid-tread) and take FFT
First look at x = cos(2*pi*fx/fs*[0:N-1]);
quantization noise x = round(x/LSB)*LSB;
introduced by an s = abs(fft(x));
ideal quantizer s = s(1:end/2)/N*2;
% calculate SNR
sigbin = 1 + cycles;
noise = [s(1:sigbin-1), s(sigbin+1:end)];
snr = 10*log10( s(sigbin)^2/sum(noise.^2) );

Spectrum with Quantization Noise
2048 point FFT, SNR=61.90dB
0
-20
Spectrum looks fairly uniform

-40
Signal-to-quantization noise
ratio is given by power in
-60
signal bin, divided by sum of
all noise bins
-80
-100
-120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
SQNR
0
Signal Power
SQNR =
Quantization Noise Power
-20
2
1 VFS
2 2 3 2N -40
= 2
= 2
1 VFS 2
-60
12 2N
= 6.02 N + 1.76 [dB] -80
= 6.02 10 + 1.76 [dB] -100
= 61.9 dB
-120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]

FFT Noise Floor

0
2048
Nfloor = 61.9 dBc 10log
-20
2

= 61.9 dBc 30.1 dB -40
= 92 dBc
-60
-80
Depends on FFT size
Plot is useless if FFT -100
size is not specified

-120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
DFT Plot Annotation
DFT plots are fairly meaningless unless you clearly specifiy the
underlying conditions
Most common annotation
Specify how many DFT points were used (N)
Less common options
Shift DFT noise floor by 10log10(N/2)dB
Normalize with respect to bin width in Hz and express noise
as power spectral density
"Noise power in 1 Hz bandwidth"

Periodic Quantization Noise
Same as before, but cycles =

64 (instead of 67) 0
fx = fs64/2048 = fs/32
-20

Quantization noise is highly
deterministic and periodic -40
For more random and "white" -60

quantizion noise, it is best to
make N and cycles mutually -80
prime
-100
GCD(N,cycles)=1
-120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
Typical ADC Output Spectrum
Fairly uniform noise floor due 2048 point FFT, SNR=55.99dB

0
to additional electronic noise
Harmonics due to -20
nonlinearities
-40
Definition of SNR
Signal Power -60
SNR =
Total Noise Power
-80
Total noise power includes all
bins except DC, signal, and -100
2nd through 7th harmonic

-120
Both quantization noise 0 0.1 0.2 0.3 0.4
Frequency [f/fs]
and electronic noise affect
SNR

SNDR and ENOB
Definition
2048 point FFT, SNR=55.9dB, SNDR=47.5dB
0
Signal Power
SNDR =
Noise and Distortion Power -20

Noise and distortion power -40
includes all bins except DC
and signal -60
Effective number of bits -80
-100
SNDR(dB)-1.76dB
ENOB =
6.02dB
-120
0 0.1 0.2 0.3 0.4
Frequency [f/fs]
Effective Number of Bits

Is a 10-Bit converter with 47.5dB SNDR really a 10-bit
converter?
47.5dB 1.76dB
ENOB = = 7.6
6.02dB
We get ideal ENOB only for zero electronic noise, perfect

transfer function with zero INL, ...
Low electronic noise is costly
Cutting thermal noise down by 2x, can cost 4x in power
dissipation
Rule of thumb for good power efficiency: ENOB < B-1
B is the "number of wires" coming out of the ADC or the so
called "stated resolution"

Survey Data
SNR(dB)-1.76dB
SNRBits =
6.02dB
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on

Selected Areas in Communications, pp. 539-50, April 1999
Dynamic Range
Maximum Signal Power

DR = SNRpeak
Minimum Detectable Signal
SNR
(dB)
PEAK SNR OVERLOAD
FULL SCALE
0dB
DYNAMIC INPUT
RANGE Input Power
AMPLITUDE
[dB]
(dB)
MDS

SFDR
Definition of "Spurious Free 2048 point FFT, SFDR=48.3dB

0
Dynamic Range"
-20
Signal Power

SFDR =
Largest Spurious Power
-40
Largest spur is often (but not -60
necessarily) a harmonic of the

-80
input tone
-100
-120
0 0.1 0.2 0.3 0.4
Frequency [f/fs]
SDR and THD
Signal-to-distortion ratio
2048 point FFT, THD=-48.2dB
Signal Power 0
SDR =
Total Distortion Power
-20
Total harmonic distortion -40
Total Distortion Power 1

THD = = -60
Signal Power SDR
-80
By convention, total distortion
power consists of 2nd through 7th -100
harmonic
-120
Is there a 6th and 7th harmonic in 0 0.1 0.2 0.3 0.4
Frequency [f/fs]
the plot to the right?

Lowering the Noise Floor

0
Increasing the FFT size let's
us lower the noise floor and -20

reveal low level harmonics
-40
-60
-80
-100
-120
0 0.1 0.2 0.3 0.4
Frequency [f/fs]
Aliasing

Harmonics can appear at 0
"arbitrary" frequencies
due to aliasing -20
-40
f1 = fx = 0.3125 fs
f2 = 2 f1 = 0.6250 fs 0.3750 fs -60
f3 = 3 f1 = 0.9375 fs 0.0625 fs
-80
f4 = 4 f1 = 1.2500 fs 0.2500 fs
f5 = 5 f1 = 1.5625 fs 0.4375 fs -100
-120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]

Intermodulation Distortion
f1 f2
Amplitude SECOND
ORDER
THIRD
PRODUCTS
ORDER
PRODUCTS
f2 - f1 f1 + f2
2f1 - f2 2f2 - f1
Frequency f
IMD is important in multi-channel communication systems

Third order products are generally difficult to filter out
MTPR
-20 MTPR
Amplitude [dB]
-40
-60
-80
-100
-120
0.00E+00 4.00E+06 8.00E+06 1.20E+07 1.60E+07 2.00E+07 2.40E+07 2.80E+07 3.20E+07
Frequency(Hz)
Frequency [Hz]
Useful metric in multi-tone transmission systems

E.g. OFDM

Frequency Dependence (1)
All of the above discussed metrics generally depend on frequency

Sampling frequency and input frequency
[Analog Devices, AD9203 Datasheet ]
Frequency Dependence (2)
[Texas Instruments, ADS5541 Datasheet ]

ERBW
Defined as the input frequency at which the SNDR of a

converter has dropped by 3dB
Equivalent to a 0.5-bit loss in ENOB
ERBW > fs/2 is not uncommon, especially in converters
designed for sub-sampling applications
ERBW is only a useful metric when the SNDR is relatively flat
initially and gracefully degrades at high frequencies
Relationship Between INL and

Harmonic Distortion (1)
The INL of an ADC often takes on a quadratic or cubic bow
Meaning that the transfer function can be approximated by
x+a2x2 or x+a3x3
The resulting harmonic distortion usually sets the low frequency
SFDR
Ideal
Quadratic bow
Cubic bow
Output
Input

Relationship Between INL and
Harmonic Distortion (2)
The expression below provides an analytical relationship

between the peak INL due a cubic bow and the resulting HD3
The result provides a reasonable bound even if the INL is not
perfectly cubic
Rule of thumb: HD -20log(2B/INL)
E.g. 1 LSB INL at 10 bits HD -60 dB
4 2
20

3 3
Example of a cubic INL

[Lee, JSSC 12/2007]
B. Murmann 39
SNR Degradation due to DNL (1)
[Source: Ion Opris]
For an ideal quantizer we assumed uniform quatization error

over /2
Let's add uniform DNL over 0.5 LSB and repeat math...

SNR Degradation due to DNL (2)
Integrate triangular pdf
+
e e2 2
e =2
2
1 de = 6 SNR = 6.02 B 1.25 [dB]
0
3dB
Compare to ideal quantizer
+ /2
e2 2
e =
2
de = SNR = 6.02 B + 1.76 [dB]
/2
12
Bottom line: non-zero DNL across many codes can easily cost a
few dB in SNR
"DNL noise"
Noise Figure of an ADC
2
2 1 2 1 VFS 1
Vin,rms = V = = 1V 2
2 2 2 2
2
Vin,rms 1 1V 2
Pin = = = 10mW = 10dBm
R 2 50

Quantization Noise in 1Hz

fs 0

NPSD = Pin SQNR 10log 2
1 Hz -20


100MHz -40
= 10dBm 61.9dB 10log
1Hz
-60
dBm
= 131.9
Hz
-80
For comparison:
-100
dBm
NPSD,Rsource = 174
Hz -120
0 0.1 0.2 0.3 0.4 0.5
Frequency [f/fs]
Spot Noise Figure (1)
Total Noise at ADC Input Noise due to ADC

F=
Noise due to Source Resistor Noise due to Source Resistor
dBm dBm
NF = 10log(F) = 174 131.9 = 43.1dB
Hz Hz
Ouch!

Spot Noise Figure (2)
fs
dBm
NF = 174 + Pin SQNR 10log 2
Hz 1 Hz

1 V 2
FS fs
2N 2
+ 10log
dBm 2 2 3
= 174 10log 2 10log
Hz R 2 1 Hz

Improve NF by increasing R (need a transformer),

resolution (N) and fs
Real World Example
Analog Devices, Tutorial MT-006

Nyquist Rate DACs
Boris Murmann
Stanford University
Overview
D/A conversion is typically accomplished through the division or

multiplication of a reference voltage, current or charge
Basic configurations
Thermometer
Binary weighted
Segmented
Implementation choices
Resistive, capacitive, current steering
Nyquist rate, oversampling, PWM

Our discussion will focus mainly on high-speed current steering

Resistor String DAC
LSB MSB

VRE F xxxxx xxxxx
d0 d0 d1 d1 d2 d2
Simple, inherently
monotonic
Small area up to ~8 bits
See e.g. Pelgrom,
JSSC 12/1990
OUT
Unsuitable for high-
resolution, high-speed
designs
Thermometer DAC Using Switched Currents
Inherently monotonic
Need large encoder
with 2B-1 outputs
Impractical for large
B (high resolution)

Thermometer DAC Principle
15
14 14
Output
13 13 13
12 12 12 12
11 11 11 11 11
10 10 10 10 10 10
9 9 9 9 9 9 9
8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7
6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input Code
Binary Weighted DAC
No encoder needed
Monotonicity is not
guaranteed
Consider transition
100000. to
011111.
2B-1 source must
match sum of others
to within 1 LSB to
make transition
monotonic

Binary Weighted DAC Principle
MSB Transition
Problem
Implementation of Weighted Elements

Segmented DAC
Binary weighted
section with Bb bits
Thermometer section
with Bt = B-Bb bits
Typically Bt ~ 48
Reasonably small
encoder
Easier to achieve
monotonicity
Segmented DAC (2-2)
Transition
Problem Limited
to LSB Section

Static Errors (1)
DNL and INL due to unit element mismatch
Systematic Errors
Contact and wiring resistance (IR drop)
Edge effects in unit element arrays
Process gradients
Finite current source output resistance
Systematic errors can be mitigated by proper layout and
switching sequence design
See e.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]
Static Errors (2)
In the best possible scenario, we are then limited by random errors,

which are due to material roughness, randomness in etching, etc.
The distribution of random errors is usually well approximated by a
Gaussian PDF (central limit theorem)
References
C. Conroy et al., Statistical Design Techniques for D/A
Converters, IEEE J. Solid-State Ckts., pp. 1118-28, Aug. 1989.
P. Crippa, et al., "A statistical methodology for the design of high-
performance CMOS current-steering digital-to-analog converters,"
IEEE Trans. CAD of ICs and Syst. pp. 377-394, Apr. 2002.

Gaussian Distribution
( x )2
1
2 2
x
f(x) = e X=
2
0.4
0.3
f(x)
0.2
0.1
0
-3 -2 -1 0 1 2 3
x/X
Yield (1)
2
+C X
1 C
P ( C X +C ) =
2
e 2 dX = erf
2

C
1
0.8
C)
P(-X xX +X)
0.6
P(-C
0.4
0.2
0
0 0.5 1 1.5 2 2.5 3
X/
C

Yield (2)
C P(-C X C) [%] C P(-C X C) [%]
0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937
Example
Measurements show that the current in a production lot of
current sources follows a Gaussian distribution with = 0.1 mA
and = 10 mA
What fraction of current sources is within 3% (or 1%) of
the mean?
Relative matching ("coefficient of variation")
I 0.1mA
u = = stdev = = 1%
I 10mA
Fraction of current sources within 3%

C = 3 99.73%
Fraction of current sources within 1%
C = 1 68.27%

Mismatch in MOS Current Sources

I = I1 I2 gmVt + I1

I g
m Vt +
I1 I1
1 W
= Cox A Vt A
2 L Vt = =
WL
WL
Example
W=500m, L=0.2m, gm/ID=10S/A, AVt=5mV-m, A=1%-m
2 2
S 5mV 1%
I = 10 + = ( 0.5%)2 + ( 0.1%)2 = 0.51%
A 10 10
1I
DNL of Thermometer DAC
1 N
Ik I
Step(k) Stepavg N j =1 j Ik I I
DNL(k) = = N
=
Stepavg 1 I I
I
N j =1 j
I
stdev (DNL(k) ) = stdev = u
I
Standard deviation of DNL for each code is simply equal to

relative matching (u) of unit elements
Example
Say we have unit elements with u = 1% and want 99.73% of
all converters to meet the spec
Which DNL specification value should go into the datasheet?

DNL Yield Example (1)
First cut solution
For 99.73% yield, need C = 3
DNL = u = 1%
3 DNL = 3%
DNL specification for a yield of 99.73% is 0.03 LSB
Independent of target resolution (?)
Not quite right
Must keep in mind that a converter will meet specs only if all
codes meet DNL spec, i.e. DNL(k) < DNLspec for all k
A converter with more codes is less likely to have all codes
meet the specification
Let's see if this is significant

Let's say there are N codes, and assume that all DNL(k) values
are independent, then
P(all codes meet spec) = P(single code meets spec)N
P(all codes meet spec)1/N = P(single code meets spec)
Lets look at two examples N=63 (6 bits) and N=4095 (12 bits)
0.99731/63 = 0.99995708
0.99731/4095 = 0. 99999929929
Can calculate modified confidence intervals using Matlab
For N=63, C = sqrt(2)*erfinv(0.99731/63) = 4.09
For N=4095, C = sqrt(2)*erfinv(0.99731/4095) = 4.97
Refined result for 99.97% yield
N=63: DNL spec should be 0.0409 LSB
N=4095: DNL spec should be 0.0497 LSB

Getting a more accurate yield estimate for the preceding
example wasn't all that hard
Unfortunately things won't always be that simple
E.g. in a segmented DAC, DNL(k) are no longer independent
The "typical" DAC designer tends to rely on simulations rather
than trying to formulate "exact" yield equations
Get rough estimate using simple (often optimistic)
expressions
Run "Monte Carlo" simulations in Matlab to find actual yield
or to center specs
Still important to have a qualitative feel for what may cause
discrepancies
INL (1)
Iout (k) Iout,uniform (k)

INL(k) =
Stepavg
k
k N k
Ij I
N j=1 j
N Ij
j =1 j =1
= = k
1 N k N
I
N j =1 j
Ij + Ij
j =1 j = k +1
A N
= k
A +B
A N A X
var (INL(k) ) = var k = N2 var = N2 var
A +B A +B Y

INL (1)
For a quotient of random variables
2
X 2X 2Y cov ( X, Y )
var X 2 + 2 2
Y Y
X Y
X Y
[Dennis E. Blumenfeld, Operations Research Calculations Handbook, Online:

http://www.engnetbase.com/ejournals/books/book_summary/toc.asp?id=701]
After identifying the means (), variances (2) and covariance

(cov) needed in the above approximation, it follows that
k
var (INL(k)) k 1 u2
N
k
INL (k) u k 1
N
INL (2)
6
N=64
N=128
INL (k)/u
0
0 20 40 60 80 100 120 140
k
Standard deviation of INL is maximum at mid-scale (k=N/2)
N N/ 2 1 1
INL u 1 = u N u 2B
2 N 2 2
For a more elaborate derivation of this result see

[Kuboki et al., IEEE Trans. Circuits & Systems, 6/1982]

Achievable Resolution
2
B log2 4 INL = 2 + 2log2 INL

u
u
Example: INL= 0.1 LSB (at mid-scale code)
u B
1% 8.6
0.5% 10.6
0.2% 13.3
0.1% 15.3
INL Yield
Again, we should ask how many DACs will meet the spec for a
given INL (worst code)
It turns out that this is a very difficult math problem
Two solutions
Do the math
G. I. Radulov et al., "Brownian-Bridge-Based Statistical
Analysis of the DAC INL Caused by Current Mismatch," IEEE
TCAS II, pp. 146-150, Feb. 2007.
Yield simulations
Good rule of thumb
For high target yield (>95%), the probability of "all codes
meet INL spec" is very close to "worst code meets INL spec"

DNL/INL of Binary Weighted DAC
INL same as for thermometer DAC

Why?
DNL is not same for all codes, but depends on transition
Consider worst case: 0111 1000
Turning on MSB and turning off all LSBs
2
DNL ( ) (
= 2B 1 1 u2 + 2B 1 u2 = 2B 1 u2
14 4244 3 1424 3
) ( )
0111... 1000... 8I 4I 2I I
Example
B = 12, u = 1% DNL = 0.64 LSB
Much worse than thermometer DAC
DNL (4-bit Example)
15
10
2 )22
u
D NL //
( DNL
0
0 2 4 6 8 10 12 14
DAC input code
code

Simulation Example
DNL and INL of 12 Bit converter (from converter decision thresholds)
2
-1 / +0.1 LSB, avg=-9.3e-005, std.dev=0.035, range=1.4
-1.3
DNL [in LSB]

1
-1
-2
500 1000 1500 2000 2500 3000 3500 4000
bin
code
2
INL [in LSB]
-0.8 / +0.8 LSB, avg=-1.1e-013, std.dev=0.37, range=1.6

1
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
code
Another Random Run

DNL and INL of 12 Bit converter (from converter decision thresholds)
2
DNL [in LSB]
-0.9 / +0.4 LSB, avg=-7.5e-005, std.dev=0.039, range=1.3

1
-1
500 1000 1500 2000 2500 3000 3500 4000
code
bin
2
INL [in LSB]
-0.7 / +0.7 LSB, avg=3.3e-014, std.dev=0.33, range=1.3

1
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
code
Peak DNL not at mid-scale!
Important to realize that this is just one single statistical
outcome
Multiple Simulation Runs (100)
Overlay Plot RMS DNL and INL
[Lin & Bult, JSSC 12/1998]
DNL/INL of Segmented DAC
INL
Example: B=Bb+Bt=4+4=8
Same as in thermometer
DAC
DNL
Worst case occurs when
16I 16I 16I
LSB DAC turns off and
one more MSB DAC
element turns on
Essentially same DNL as
a binary weighted DAC 8I 4I 2I I
with Bb+1 bits

Comparison
Binary
Thermometer Segmented
Weighted
INL 1
u 2B
(worst case) 2
DNL
u u 2Bb +1 1 u 2B 1
(worst case)
Number of
Switched 2B 1 Bb + 2Bt 1 B
Elements
Example (B=12, u=1%)
INL DNL Number of

DAC Architecture Switched
(worst) (worst) Elements
Thermometer 0.32 0.01 4095

Binary Weighted 0.32 0.64 12
Segmented (Bb=7, Bt=5) 0.32 0.16 38

Dynamic DAC Errors (1)
Finite settling time and slewing

Finite RC time constant
Signal dependent slewing
Feedthrough
Coupling from switch signals to DAC output
Clock feedthrough
Glitches due to timing errors
Current sources wont switch simultaneously
Dynamic DAC errors are generally hard to model!
Dynamic DAC Errors (2)
References
Gustavsson, Chapter 12
M. Albiol, J.L. Gonzalez, E. Alarcon, "Mismatch and dynamic
modeling of current sources in current-steering CMOS D/A
converters," IEEE TCAS I, pp. 159-169, Jan. 2004
Doris, van Roermund, Leenaerts, Wide-Bandwidth High
Dynamic Range D/A Converters, Springer 2006.
T. Chen and G.G.E. Gielen, "The analysis and improvement
of a current-steering DAC's dynamic SFDR," IEEE Trans.
Ckts. Syst. I, pp. 3-15, Jan. 2006.

Glitch Impulse (1)
DAC output waveform depends on timing
Consider binary weighted DAC transition 0111 1000
10
ideal
5 Ideal
0
1 1.5 2 2.5 3
10
early
5 LSBs early, MSB late

0
1 1.5 2 2.5 3
10
late
5 LSBs late, MSB early

0
1 1.5 2 2.5 3
Time
Glitch Impulse (2)
Worst case glitch impulse (area): t 2B-1

LSB area: T
Need t 2B-1 << T which implies t << T/2B-1
fs [MHz] B t [ps]
1 12 << 488
20 16 << 1.5
1000 10 << 2

Commercial Example
Implementation Example
[T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80-MHz 8-

bit CMOS D/A Converter, IEEE J. of Solid-State Circuits, pp. 983-988, Dec. 1986.]

Mitigating IR Drop
Basic Differential Pair Switch

Commonly Used Techniques
Retiming
Latches in (or close to) each current cell
Latch controlled by global clock to ensure that current cells
switch simultaneously (independent of decoder delays)
Make before break
Ensure uninterrupted current flow, so that tail current source
remains active
Low swing driver
Drive differential pair with low swing to minimize coupling
from control signals to output
Cascoded tail current source for high output impedance
Ensures that overall impedance at output nodes is code
independent (necessary for good INL)
Example Current Cell Implementation
[Barkin & Wooley, JSSC 4/2004]

Constant Clock Load Latch
D Q
MN1
INV1
INV2
DB QB
MN2
INV6 INV3
Capacitive load seen MN3

INV7
at CLK the same for CLKB
all possible cases,
H-L, L-H, H-H or L-L INV5
MN4 INV4
CLK
Mercer, US patent ,7,023,255 4/4/2006
High Performance DAC Examples (1)
100MHz
1GHz
[Van den Bosch, JSSC 3/2001]

[Schafferer, ISSCC 2004]
[Schafferer, ISSCC 2004]

[Lin, ISSCC 2009]
Binary Weighted Charge Redistribution DAC
CP (top plate parasitic)
+
2N1 C 8C 4C 2C C C VOUT

VRE F
b1 bN3 bN2 bN1 bN

(msb) (lsb)
2B C B
bi
Vout = B
Vref i
2 C + Cp i =1 2
Can redistribute charge onto OTA + feedback capacitor to

mitigate gain error due to Cp

Charge-based Pipeline DAC (1)
[Manganaro et al., "A dual 10-b 200-MSPS pipelined D/A converter with DLL-based
clock synthesizer," IEEE JSSC 11/2004]
Charge-based Pipeline DAC (2)
(fclk=200MHz)

Sampling Circuits
Boris Murmann
Stanford University
Recap
How to build circuits that "sample"?

Ideal Dirac sampling is impractical
Need a switch that opens, closes and acquires signal within
an infinitely small time
Practical solution
"Track and hold"

Outline
Elementary track-and-hold circuit and its nonidealities

First order improvements to elementary track-and-hold
Advanced techniques
Clock bootstrapping
Bottom plate sampling
Settling and noise analysis in charge-redistribution
track-and-hold circuit
Noise simulation example
Ideal Track-and-Hold Circuit

Signal Nomenclature
time
Continuous Time Signal
T/H Signal
("Sampled Data Signal")
Clock
Discrete Time Signal
Circuit with MOS Switch
Pedestal Error

Nonidealities
Finite acquisition time

Tracking nonlinearity
Signal dependent hold instant
Thermal noise
Clock jitter
Hold mode feedthrough and leakage
Charge injection and clock feedthrough
Finite Acquisition Time
Consider various input signal scenarios
1. Input is a sampled data signal, i.e. the

output of another switched capacitor stage
2. Input is a slowly varying continuous time
signal, e.g. the input of an oversampling
ADC
3. Input is a rapidly varying continuous time
signal, e.g. the input of a Nyquist or sub-
sampling ADC

Finite Acquisition Time Case 1
For simplicity, neglect finite rise time of the input signal
Consider worst case the output is required to settle from 0 to
the full-scale voltage of the system (VFS)
First order MOS switch model
= RC
(
Vout (t) = VFS 1 e t / )
Finite Acquisition Time Case 1

Ts
T /
Vout,err s = VFSe 2 = VFSeN
2
Typically think about settling error in terms of the number of settling

time constants (N) required for LSB settling in a B-bit system
B N
N 1 VFS
VFS e
2 2B 6 >4.9
10 >7.6
Ts / 2
N=

(
ln 2 2B ) 14 >10.4
18 >13.2

Finite Acquisition Time Case 2 & 3
Consider a sinusoidal input around 0, and 0 also as the initial
condition for Vout (for notational simplicity)
Vin (t) = A cos( t + )

t
A cos( ) A cos( t + )
Vout (t) = e +
2 2
1 +4
144
2444 3 14
144 2 2 3
+2444
initial transient steady-state response
= atan()
At t=Ts/2, the error in the held signal consists of two parts

Residual error due to initial exponentially decaying initial
transient term
In order to minimize this error, we need to chose N
appropriately, as calculated for the step input scenario
Error due to magnitude attenuation and phase shift in the steady
state term
This error depends only on the RC time constant and the
input frequency; it cannot be reduced by extending the
length of the track phase
How significant is the error due to the steady-state term?

As an example, lets compute the percent amplitude error for the
N values derived previously ( LSB, B-bit settling to a step)
A
A
2
1 + ( ) 1 1 1
A err = = 1 = 1 = 1
A 1 + ( )
2 2 2
T /2 f
1 + 2fin s 1 + in
N N fs
B N Aerr (fin = fs/20) Aerr (fin = fs/2)

6 4.9 0.052% 4.9%
10 7.6 0.021% 2.1%
14 10.4 0.011% 1.1%
18 13.2 0.007% 0.7%
Summary Finite Acquisition Time
Precise settling to an input step is accomplished within 513

RC time constants (depending on precision)
Precise tracking of a high-frequency continuous time input
signal tends to impose more stringent requirements
Number to remember: ~1% attenuation error at Nyquist
(fin=fs/2) for N ~10
In applications where attenuation is tolerable, the RC time
constant requirements then tend to follow from the distortion
specs
The larger the attenuation, the larger the instantaneous
voltage drop across the (weakly nonlinear) MOSFET
undesired harmonics
Lets look at that next

Voltage Dependence of Switch
W V
ID(triode) = Cox VGS Vt DS VDS
L 2
1
dI
1

D(triode)
RON =
dVDS Cox
W
VDS 0 ( V Vt )
L GS
1
RON =
W
Cox ( Vin Vt )
L
Two problems
RON is modulated by Vin (assuming e.g. =VDD=const.)
Transistor turn off is signal dependent, occurs when =Vin+Vt
Track Mode Nonlinearity
[Razavi, Data Conversion System Design, p.16]
Output tracks well when input voltage is low

Gets distorted when voltage is high due to increase in RON

Analysis
K 2
ID K ( VGS Vt ) VDS VDS
2
dVout K 2
C = K ( Vout Vt )( Vin Vout ) ( Vin Vout )
dt 2
"All" we need to do is solve the above differential equation

Can use Volterra Series analysis
General method that allows us to calculate the frequency
domain response of nonlinear circuits with memory
See e.g. Stanford EE214
Luckily someone has already done this for us
See [Yu, TCAS II, 2/1999]
Result
Amplitude of third harmonic

HD3 =
Amplitude of fundamental
2 2
1 A 1 A fin
=
4 VGS Vt 4 VGS Vt fs N
VGS is the "quiescent point" value of the gate-source voltage; i.e.

in the zero crossing of the sine input
For low distortion
Make amplitude smaller than VGS-Vt
Low swing bad for SNR
Make 1/ much larger than (input frequency)
Big switch may cost lots of power to drive, comes with large
parasitic capacitances

Numerical Example
Parameters
VDD = VCK = 1.8V
Signal is centered about VDD/2 = 0.9V
VGS-Vt = 1.8V-0.9V-0.45V = 0.45V
A = 0.2V
N = 0.5Ts/ = 10
fin = fs/2
2
1 0.2 1
HD3 = 42dB
4 0.45 2 10
Not all that great
Signal Dependent Sampling Instant (1)
()
Tf
Must make fall time of sampling clock (Tf) much faster than
maximum dVin/dt

Signal Dependent Sampling Instant (2)
Distortion analysis result (see Yu, TCAS II, 2/1999]
Amplitude of third harmonic

HD3 =
Amplitude of fundamental
2
3 A
Tf
8 VCK
Example: VCK = 1.8V, A = 0.5V, Tf = 100ps, = 2100MHz
2
3 0.5
HD3 2100 106 100 1012 = 79dB
8 1.8
Hold Mode Feedthrough
CDS
Want to make Rout as small as possible

Consider using a T-switch when hold-mode
feedthrough is a problem (for low-speed
applications)
Consider using half circuit cross coupling for
high-speed applications

Hold Mode Leakage
Example:
Gate Leakage Data
A. Annema, et al., Analog circuits in ultra-deep-submicron CMOS, IEEE J. Solid-State Circuits, pp. 132-143, Jan. 2005.
In 65nm CMOS, gate capacitance droop rate is ~1V/s (!)

Issue is solved with high-k dielectrics in post-65nm technologies

Thermal Noise (1)
Questions
What is the noise variance of the Vout samples in hold mode?
What is the spectrum of the discrete time sequence
representing these samples?
Nearly white, provided that the number of settling time
constants (N) is large (see EE315A for a derivation)
Thermal Noise (2)
Sample values Vout(n) correspond to instantaneous values of the

track mode noise process
From Parseval's theorem, we know that the time domain power
(or variance) of this process is equal to its power spectral
density integrated over all frequencies
Further, given that the process is ergodic, this number must also be equal to the "ensemble" variance,
i.e. the variance of a sample taken at a particular time
2 2
v out 1
= 4kTR
f 1 + sRC
2
1 kT
var [ Vout (n)] = 2
v out,tot = 4kTR df =
0
1 + j2f RC C

Alternative Derivation
The equipartition theorem says that each degree of freedom"

(typically a quadratic energy variable) of a system in thermal
equilibrium holds an average energy of kT/2
In our system, the degree of freedom is the energy stored on the
capacitor
1 1
Cv out 2 = kT
2 2
kT
v out 2 =
C
Implications of kT/C Noise
Example: suppose we make the kT/C noise equal to the

quantization noise of a B-bit ADC
2
kT 2 VFS 2B
= = C = 12kT
V
,
C 12 2B FS
For a given B, both C and R (via N on slide 19) are fully determined
Example numbers for VFS=1V and fs=100MHz:
B C [pF] R []
8 0.003 246,057
10 0.052 12,582
12 0.834 665
14 13.3 36
16 213 1.99
18 3,416 0.11

Commercial Example
How to Estimate Thermal Noise

in the Lab?
One option is to look at the measured SNR and back-calculate
the thermal component by subtraction of quantization noise and
DNL noise
Another (potentially better) option is to take a code histogram
with grounded input
S. Ruscak and L. Singer, Using Histogram

Techniques to Measure A/D Converter Noise
http://www.analog.com/library/analogDialogue/
archives/29-2/cnvtrnoise.html

Sampling Jitter
In any sampling circuit, electronic noise causes random timing
variations in the actual sampling clock edge
Adds "noise" to samples, especially if dVin/dt is large
Vin = Change in V in during t dVin

Vin t
dt
t = Sampling jitter
Analysis
Consider sine wave input signal
Assume t is random with zero mean and standard deviation t
Analysis
dV 2 dV 2
2
E { }
Vin2 E

in
dt t = E dt E t

in

2
{ }
d
2
1 2
E A cos [ 2 fin t ] 2t ( 2 A fin ) 2t
dt 2
1
1
= 2 =
1

2

Result
1.E+11
1.E+10
1.E+09
fin [Hz]
t = 0.1ps
1.E+08
t = 1ps
1.E+07 t = 10ps
1.E+06
1.E+05
10 20 30 40 50 60 70 80 90 100 110 120
SNR
SNR [dB]
jitter [dB]
aperture
ADC Performance Survey (ISSCC & VLSI 97-12)
Data: http://www.stanford.edu/~murmann/adcsurvey.html

Why is it Hard to Achieve Low Jitter?
Inverters have little to no

supply rejection Noisy VDD
Example:
1V supply, 20ps rise time
100mV noise on the supply Jittered
corresponds to about 2ps Jitter Output
of jitter Free Clock
Clock
In addition, there is thermal
amplitude noise (kT/C) that
also translates into jitter
How Well Can We Do?
In todays optimized designs, jitter numbers as low as 50 fsrms have

been achieved, see e.g. Ali, JSSC 8/2006
However, several hundred psrms are more common, especially
in noisy SoC environments
Differential signaling can help (particularly at the chip boundary),

but comes with diminishing returns due to reduced amplitude
and signal slope (relative to inverters)

Significance of Jitter
In light of the above reasoning, sampling jitter has become one

of the main showstoppers for further improvements in the ADC
speed-resolution product
Example
fin = 10GHz, t = 300ps SNRjitter = 34.5dB (ouch!)
What saves us in many application is that the signal is not a
sinusoid, but instead spread in some way across frequency
Proper analysis for applications that push the boundaries must
therefore take the signal properties into account
Reference: Da Dalt, TCAS1, 9/2002
Generalized Calculation
Da Dalt showed that in general, the jitter SNR can be computed

using the curvature of the signals autocorrelation function
1 0
= =
0
Side note
In this result, the signal is assumed to be stationary
An extension for cyclostationary signals was provided by El-
Chammas, TCAS1, May 2009
Useful for systems with simple signal constellations, such as NRZ

Intuition
Gradual decay in
autocorrelation
Slow
signal
Sharp decay in
Fast autocorrelation
signal
Example: High-Speed Link

White Info Channel

TX RX
Source h(t)
Rx is the autocorrelation function of the input signal (assumed to

be white and stationary in this example)
Ry is the autocorrelation function of the signal at the sampler
= = [ ]

Example
Chanel Frequency Response Chanel Impulse Response
0
5
-10
-20 4
-30
h(t) [V/ns]
S21 [dB]
3
-40
fs/2
-50 2
-60
1
-70
-80 0
0 5 10 15 20 4.4 4.6 4.8 5 5.2
f [GHz] Time [ns]
Example
Convolved Impulse Response Second Derivative

-5
x 10
0.12 1
0.5
0.1
0
0.08
w''() [1/ps2]
-0.5
w()
0.06 -1
-1.5
0.04
-2
0.02
-2.5
0 -3
-1 -0.5 0 0.5 1 -0.5 0 0.5
[ns] [ns]

Example
0 2.8 10 1 1
= =
= 2.3 10
0 0.12

1
= 20 log = 46.8 (Better!)
300
Another way to think about this is to compute the sinusoid

frequency that causes the same jitter noise
1
, = = 2.4
2
Bottom line: the fact that the signal is wideband and filtered by
the channel helps, but the jitter spec will still be non-trivial
How to Measure/Quantify the Sampling

Jitter of an ADC in the Lab?
Use sinusoids as a test signal

Method 1: Leverage the known proportionalities and extract jitter
estimate using an amplitude and frequency sweep
RMS jitter is noise proportional to input frequency
RMS is noise proportional to input amplitude
This works well when jitter is the dominant issue, and not masked
by other nonidealities (like thermal noise)
Method 2: Leverage the fact that jitter causes cyclostationary noise
Jitter causes almost no noise near peaks of sinusoid, but lots of
noise near zero crossing
Noise beat at twice the signal frequency

Jitter Noise Beat
[Aaron Buchwald]
Can back calculate jitter noise by comparing
variance at zero crossing with variance near peak
(which is set by thermal and quantization noise)
Jitter Estimation Based on Spectrum
Reference
D.M. Hummels, W. Ahmed, W., F.H. Irons, "Measurement of random
sample time jitter for ADCs," Proc. ISCAS, pp.708-711, May 1995.
Spectrum of squared sequence

contains a tone proportional to jitter
After removal of harmonics:

Matlab Code
% Jitter estimation technique proposed by Hummels, ISCAS 1995
% x is a vector that contains an integer number of cycles of a sampled sine wave
function [sigma_jitter_est, sigma_noise_est, fsin] = estimate_jitter(x, show_plot)
% take fft, remove DC, signal and harmonics

N = length(x);
s = fft(x);
[sigamp, sigbin]=max(abs(s));
A_est = sigamp/N*2;
cycles = sigbin-1;
fsin = cycles/N;
harmbins = 1 + abs([2:8]*cycles - N*round([2:8]*cycles/N));
sn=s;
sn(1)=eps;
sn(sigbin)=eps;
sn(N+2-sigbin)=eps;
sn(harmbins) =eps;
sn(N+2-harmbins)=eps;
% inverse fft, compute jitter and noise estimates

xinv = ifft(sn, 'symmetric');
s_inv = abs(fft(xinv.^2));
jitterbin = 1 + abs(2*cycles - N*round(2*cycles/N));
sigma_jitter_est = sqrt(2*2*s_inv(jitterbin)/N/(2*pi*fsin)^2/A_est^2);
sigma_noise_est = sqrt(s_inv(1)/N-2*s_inv(jitterbin)/N);
Charge Injection and Clock Feedthrough
Pedestal Error
Analyze two extreme cases

Very large Tf (slow gating)
Very small Tf (fast gating)

Slow Gating

H
VIN + V T
V IN
t
L HOLD
VO
VIN
V
V
t
toff
All channel charge has disappeared by toff without introducing

error; it is absorbed by the input source
Slow Gating Model for t > toff
Vout = Vin Vout
Col
Vout = Vin ( Vin + Vt L ) = Vin (1 + ) + Vos
Col + C
Col Col
= Vos = ( Vt L )
Col + C Col + C
Gain Error Offset Error
Example: C=1pF, L=0V, Vt=0.45V, W=20m, Col=0.1fF/m, Col=2fF
= 0.2% Vos = 0.9mV

Fast Gating
Channel charge
H cannot change
VIN + VT
instantaneously
Surface t
Potential Qch Resulting surface
S potential decays via
L charge flow to source
t < to
VO and drain
V IN Charge divides
S V
V
t > to t between source and
drain depending on

1 1 impedances loading
(1-)Q
2Qchch Q
2 Qch
ch
these nodes
Charge Split Ratio Data
Tf
RonC2
G. Wegmann et al., "Charge injection in analog MOS switches," IEEE J. Solid-

State Circuits, pp. 1091-1097, June 1987.
Y. Ding and R. Harjani, "A universal analytic charge injection model," Proc.
ISCAS, pp. 144-147, May 2000.

Interpretation
RonC2 and Tf are usually comparable, or at least not more than

an order of magnitude apart
This brings us into the range of 0.11 on the chart by
Wegmann
This means that the charge split will in practice have some
dependence on the impedances seen on the two sides of the
transistor
Remember: Slightly more charge will go to the side with lower
impedance
Fast Gating Model for t > toff
Vout = Vin Vout = Vin (1 + ) + Vos
Col 1Q Assuming 50/50

Vout = Vin ( H L ) + ch charge split
Col + C 2 C
Qch = WLCox [ H Vin Vt ]
1 WLCox Col 1 WLCox

= Vos = ( H L ) ( H Vt )
2 C Col + C 2 C
Example: C=1pF, H-L=1.8V, Vt=0.45V, W=20m, LCox=2fF/m

Col=0.1fF/m, Col=2fF
= +2% Vos = 30.6mV

Transition Fast/Slow Gating
Fast gating Slow gating Fast gating Slow gating
| | |Vos|
TtFf TtfF
|| and |Vos| decrease as the fall time of (Tf) increases and

approach the limit case of slow gating
Unfortunately, high-speed switched capacitor circuits tend to

operate in fast gating regime
Impact of Technology Scaling
1 Qch 1 T
V = s = N RC
2 C 2fs 2
V L2
N
1 L2 fs
R =
W Qch
Cox ( V Vt )
L GS
Charge injection error to speed ratio benefits from shorter

channels and increases in mobility (e.g. due to strain)

Outline

Advanced techniques
Clock bootstrapping
Improvements
Charge cancelation
Try to cancel channel charge by injecting a charge packet
with opposite sign
Differential sampling
Use a differential circuit to suppress offset
CMOS switch
Try to balance the nonidealities of NMOS device with a
parallel PMOS

Charge Cancellation
Q1 = 0.5Qch1 + Qol1
S
L =L
W =0.5W Q2 Qch2 + 2Qol2 0.5Qch1 + Qol1
1 2
1
Q1 Q2 0
[Eichenberger and Guggenbhl, JSSC 8/89]
Cancellation is never perfect, since channel charge of M1 will not

exactly split 50/50
E.g. if Rs is very small, most of M1s channel charge will flow
toward the input voltage source
Not a precision technique, just an attempt to do a partial clean-up
Differential Sampling (1)

VID = VI1 VI2 VOD = VO1 VO2

VO1
+
VI1 C
CH VI1 + VI2 VO1 + VO2
VIC = VOC =
2 2
+
VO2 VO1 = (1 + 1 ) VI1 + VOS1
VI2 C
CH VO2 = (1 + 2 ) VI2 + VOS2

+ +
VOD = 1 + 1 2 VID + ( 1 2 ) VIC + ( VOS1 VOS2 ) 1 + 1 2 VID
2 2
+ V + VOS2 1 + 2 V + VOS2
VOC = 1 2 VID + 1 + 1 2 VIC + OS1 1+ VIC + OS1
4 2 2 2 2

Differential Sampling (2)
Assuming good matching between the two half circuits, we have

Small residual offset in VOD
Good rejection of coupling noise, supply noise,
Small common-mode to differential-mode gain
Unfortunately, VOD has essentially same gain error as the basic
single ended half circuit
This also means that there will be nonlinear terms
Out simplistic analysis assumed that the channel charge is
linearly related to Vin
This is true only to first order (consider e.g. backgate effect)
Expect to see nonlinear distortion along with gain error
CMOS Switch

Qchn WnLnCox ( H VIN Vtn )

VO
+
VIN CH (
Qchp WpLpCox VIN L Vtp )

Assuming fast gating, 50/50 charge split and WnLn = WpLp
1 1
Qchn + Qchp C V Vtp
Vo 2 2 = ox VIN H L + tn
C C 2 2

Charges fully cancel e.g. for VIN = (H-L)/2 = VDD/2, and Vtn=|Vtp|,
but there is still signal dependent residual injection

On Resistance of CMOS Switch
At least in principle, adding a PMOS can also help with the

problem of signal dependent Ron in track mode
For increasing VIN, NMOS resistance goes up, PMOS
resistance goes down

VO
+
VIN CCH

1 1
R
W W
nCox ( VGSn Vtn ) pCox VGSp Vtp
L n L p
( )
Analysis
1 1
R
W W
(
nCox ( VGSn Vtn ) pCox VGSp Vtp
L n L p
)
1
R
W W W W
nCox ( VDD Vtn ) nCox pCox v in pCox Vtp
L n L L L p
n p
1 W W
R if n = p
W L n L p
(
nCox VDD Vtn Vtp
L n
)
Independent of Vin too good to be true!

Missing factors
Backgate effect
Short channel effects

Real CMOS Switch
100
NMOS
80 PMOS
NMOS || PMOS
60
R []
40
20
0
0 0.5 1 1.5
Vin [V]
Design
Size P/N ratio to minimize change in R over input range
Size P and N simultaneously to meet distortion specs
PMOS brings limited benefit unless the input signal range is
large or centered near VDD
Outline

Advanced techniques
Clock bootstrapping

Clock Bootstrapping
+ +
VDD VDD VGS=VDD=const.
Cboot - Cboot
-
Vin
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
Phase 1
Cboot is precharged to VDD
Sampling switch is off
Phase 2
Sampling switch is on with VGS=VDD=const.
To first order, both Ron and channel charge are signal
independent
Waveforms
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.

Circuit Implementation
Switch
A. Abo et al., A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-

Digital Converter, IEEE J. Solid-State Circuits, pp. 599, May 1999
Limitations
Efficacy of bootstrap circuit is

reduced by
Backgate effect
Cpar
Parasitic capacitance
between at top plate of C3
1
R

W Cpar
Vin Vtn [ Vin ]
Cboot
nCox VDD

L n Cboot + Cpar Cboot + Cpar 1424 3
Backgate effect

Alternative Implementation
Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of
switched opamp circuits," Electronics Letters, Jan. 1999.
Less complex, but Cpar tends to be larger due to two parasitic

well capacitances
Performance of Bootstrapped Samplers
Bootstrapped top plate sampling (as opposed to bottom plate

more later) tends to work very well up to ~10bit resolution
Example
[Louwsma, JSSC 4/2008]

High-Speed Example without Bootstrap
[Choi and Abidi, JSSC 12/2001]
For lower resolution applications, it can be OK to drop the

bootstrap circuit
Bottom Plate Sampling
What if we want to do much better, e.g. 16 bits?

Basic idea
Sample signal at the "grounded" side of the capacitor to
achieve signal independent sampling
References
D. G. Haigh and B. Singh, A switching scheme for SC filters
which reduces the effect of parasitic capacitances
associated with switch control terminals, in Proc. IEEE Int.
Symp. Circuits and Systems, 1983, pp. 586589.
K.-L. Lee and R. G. Meyer, Low-Distortion Switched-
Capacitor Filter Design Techniques, IEEE J. Solid-State
Circuits, pp. 1103-1113, Dec. 1985.
First look at single ended half circuit for simplicity

Bottom Plate Sampling Analysis (1)
Turn M2 off "slightly" before M1

Typically a few hundred ps
delay between falling edges
of e and
During turn off, M2 injects charge
1
Q2 Q2 WLCox ( H Vtn )
2
To first order, the charge injected
by M2 is signal independent
Voltage across C
Q 2
VC = Vin +
C
Next, turn off M1

M1 will inject signal dependent
charge onto the series
combination of C and the
parasitic capacitance at its
bottom plate (Cpar)
Looks like, this is not much
different from the conventional
top-plate sampling?
But wait
1
Q1 WLCox ( H Vin Vtn )
2

Interesting observation
Even though M1 injects
some charge, the total
charge at node X cannot
change!
Idea
Process total charge at
node X instead of looking at
voltage across C
The charge can be processed
Q X = CVin Q2 in two ways
Open-loop
Charge injected by M2
(Signal independent) Closed-loop (charge
redistribution)
Open-Loop Charge Processing
Q X = CVin Q2
1 2
QX C Q2
VX = = Vin
Vin C + Cp C + Cp C + Cp
M1
C
Vx (no term due to signal
1e dependent charge!)
1 Cpar
M2 1e
2
Remaining drawback
Cpar (and buffer input capacitance) is usually weakly nonlinear
and will introduce some harmonic distortion

Closed-Loop Charge Processing
Amplifier forces voltage at node X to zero

Means that charge at node X must redistribute onto
feedback capacitor Cf
Charge Conservation Analysis
Charge at node X during 1: Q X1 = CVin Q2 + 0 Cf
Charge at node X during 2: Q X2 = Cf Vout
Q X1 = Q x2
Charge Conservation:
CVin Q2 = Cf Vout
C Q2
Vout = Vin +
Cf Cf
Offset term due to signal independent injection from M2 can be

easily removed using a differential architecture

Clock Generation
[A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD

Thesis, UC Berkeley, 1999]
Fully Differential Circuit

Analysis (1)
Q1m = CVinp + Q Q2m = CVxm Cf Vop Vxm ( )

Q1p = CVinm + Q (
Q2p = CVxp Cf Vom Vxp )
1) Q1m = Q2m Vop + Vom
Vxm = Vxp = Voc
2) Q1p = Q2p 2
Analysis (2)
Subtracting 1) and 2) yields

C
Vop Vom =
Cf
( Vinp Vinm )
Adding 1) and 2) yields
( ) ( )
C Vinp + Vinm + 2Q = ( C + Cf ) Vxp + Vxm Cf Vop + Vop ( )
Q Cf C
Vxc = + V oc V ic
C + Cf C + C f C + Cf
Variations in Vic show up as common mode variations at the

amplifier input
Need amplifier with good CMRR

T/H with Common Mode Cancellation
S.H. Lewis & P.R. Gray, "A Pipelined 5 MSample/s 9-bit Analog-to-Digital Converter", IEEE
J. Solid-State Circuits, pp. 954-961, Dec. 1987
Shorting switch allows to re-distribute only differential charge on

sampling capacitors
Common mode at OPAMP input becomes independent of common
mode at circuit input terminals (IN+/IN-)
Original idea: Yen & Gray, JSSC 12/1982
Analysis (1)
During 1 During 2
C C
V
C C
V
V V
V V
V V
C C
V
C C
Charge conservation at Vip,Vim and Vfloat
( Vip + Vim ) C = ( Vfloat Vxp ) C + ( Vfloat Vxm ) C

Vic = Vfloat Vxc
Vfloat = Vic + Vxc

Analysis (2)
Common mode charge conservation at amplifier inputs
Vic C Voc Cf = ( Vfloat Vxc ) C ( Voc Vxc ) Cf
Vic C = ([ Vic + Vxc ] Vxc ) C + Vxc Cf
0 = Vxc
Amplifier input common mode (Vxc) is independent of

Input common mode (Vic)
Output common mode (Voc)
Flip-Around T/H
[W. Yang et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at
Nyquist Input", IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001]
Sampling caps are "flipped around" OTA and used as feedback

capacitors during 2
Main advantage: improved feedback factor (lower noise, higher speed)
Main disadvantage: OTA is subjected to input common mode variations

Sampling Network Design Considerations
M1- switches only needed to

1- M1-
set common mode; M1 is
actual sampling switch
Make M1 larger than M1-
1+
1 M1 Ideally turn off M1- before M1
1+
In practice, usually OK to
turn off simultaneously
In track mode, the total path
1- M1- resistance is R(M3) plus
[Lin, Kim and Gray, JSSC 4/1991] bottom plate switch resistance
1- Since R(M3) is signal
dependent, make its
1
resistance small compared
1+ to that of bottom plate
2 network
Schematic Entry and Layout of M1
Use antiparallel devices to implement M1

Needed in simulation to guarantee circuit symmetry
E.g. BSIM model is not necessarily perfectly symmetric with
respect to drain/source!
Needed in layout to ensure symmetry in presence of
drain/source asymmetry due to processing artifacts

What Ultimately Limits Linearity?
Track mode nonlinearity due to R=f(Vin)
Mitigate using clock bootstrapping and proper partitioning of
total path resistance
Eventually, bootstrapping falls apart high frequencies, due to
parasitics capacitances inside the bootstrap circuit
Mismatch in half-circuit charge injection due to R=f(Vin)
Bottom plate switches in the two half circuits see input
dependent impedance; this creates input dependent charge
injection mismatch
Bootstrapping helps; ultimately limited by backgate effect
This effect is often fairly independent of frequency
(somewhat dependent on realization of top plate switch)
In high performance designs, can achieve ~80-100dB linearity
up to a few hundreds of MHz
Capacitors
Metal-Insulator-Metal (MIM) Vertical Parallel Plate (VPP)
[Ng, Trans. Electron Dev., 7/2005] [Aparicio, JSSC 3/2002]
Typically 1-2 fF/m2 (10-20 fF/m2 for advanced structures)

For 1 fF/m2, a 10 pF capacitor occupies ~100m x 100m
Both MIM and VPP capacitors have good electrical properties
Mostly worry about parasitic caps
Series and parallel resistances are often not a concern

Plate Parasitics
Ideal Capacitor
Symbol
Typical Integrated
Circuit Capacitor
Node n1 is usually the "physical" top plate of the capacitor

Makes nomenclature very confusing, since this plate is
typically used as the "electrical" bottom plate in a sampling
circuit (in the context of "bottom plate sampling")
Typical values for a MIM capacitor
=1%, =10%
Proper Connection of Capacitors
Fat plate is oriented away from virtual ground nodes to avoid

reduction of feedback factor and reduce potential noise coupling

Outline

Advanced techniques
Clock bootstrapping
Settling and Noise Analysis
Cf
1 2
Cs Gm
CL

First Order Amplifier Model
Piecewise linear half-circuit
x xd o od
2
x n o o
gm v x for gm v x < ID
io =
ID sign ( v x ) else
Linear Settling (Small Input Step)
Vofinal
t=0
0
-Vistep
(
v o (t) = Vofinal 1 e t / )
(ignoring feedforward zero)
Important parameter: Return factor or "feedback factor"

Cf
=
Cf + Cs + Cx

Waveform Detail
Dynamic Static
Error d(t) Error 0
0.8
out o,ideal
out,ideal
0.6
V o/V
V /V
0.4
0.2
0
0 2 4 6 8 10
t/
Static Settling Error

Ideal output voltage for t
Cs
Vofinal,ideal = Vistep
Cf
Actual output voltage (from detailed analysis)

Cs T0
Vofinal = Vistep T0 = gmro = avo
Cf 1 + T0
Define static settling error

T
Vofinal Vofinal,ideal 1
1 + T 1 1
0 = = =
Vofinal,ideal 1 1+ T T
Example: T0=1000 0.1% static settling error

Dynamic Settling Error
dynamic (t) =
v o (t) Vofinal Vofinal 1 e
=
(t /
)
Vofinal
= e t /
Vofinal Vofinal
ts
N= = ln ( d )

dynamic N
1% 4.6
0.1% 6.9
0.01% 9.2
Time Constant
Cf
=
C f + Cs + C x
1
R= CLtot = CL + (1 ) Cf
gm
1 CLtot
=
gm

Transconductor Current
t=0 Vofinal
0
-Vistep
(
v o (t) = Vofinal 1 e t / )
During linear settling, the current delivered by the transconductor is

dv o (t) V
io CLtot = CLtot ofinal e t /
dt
Peak current occurs at t=0
Vofinal
io max = CLtot

Slewing
The amplifier can deliver a maximum current of ID
If |io|max > ID, slewing occurs
Vofinal
io max = CLtot > ID

Vofinal gm 1
CLeff >I >
1 CLtot D ID Vofinal

gm
Example: =0.5, Vofinal=0.5V gm/ID > 4 S/A will result in slewing

Very hard to avoid slewing, unless
We are willing to bias at very low gm/ID (power inefficient)
Feedback factor is small (large closed-loop gain, CS/Cf)
Output voltage swing is small

Output Waveform with Initial Slewing
(
v o (t) = Voslew + Volin 1 e (t tslew )/ )
ID
v o (t) = t = SR t
CLtot
Continuous derivative in the transition slewinglinear requires
ID Volin ID
= Volin =
CLtot CLtot
Dynamic Error with Slewing

CLtot
Voslew = Vofinal Volin t slew = ( Vofinal Volin )
ID
Using the above result, we can now calculate the dynamic error
during the final linear settling portion
For t > t slew : (

v o (t) = Voslew + Volin 1 e (
t t slew ) /
)
d (t) =
v o (t) Vfinal Voslew + Volin 1 e
=
(
( t t slew ) /
)
Vofinal
Vfinal Vofinal
Volin ( t t slew ) /
d (t) = e
Vofinal

Noise Analysis
Cf
1 2
Cs Gm
CL
Noise due to switches Noise due to amplifier and switches
Tracking Phase (1)
Variable of interest is total integrated

"noise charge" at node X, qx2
C Cumbersome to compute using
standard analysis
C
V X
Find transfer function from each
noise source (3 resistors) to qx
Integrate magnitude squared
expressions from zero to infinity
and add
Much easier
Use equipartition theorem

Tracking Phase Noise Charge
Energy stored at node X is

1 q2x 1 q2x
=
2 Ceff 2 Cs + Cf
C
Apply equipartition theorem
C
V X 1 q2x 1
= kT
2 Cs + C f 2
q2x = kT ( Cs + Cf )
Note that any additional parasitic

capacitance at node X will
increase the sampled noise
charge!
Redistribution Phase Noise
4kTRon f
>1 excess noise factor

1
R
Gm
4kTRon1f 4kT
f
Gm
In a proper design, Ron1 and Ron2 will be much smaller than

1/Gm, else the switches would significantly affect the dynamics,
which would be very wasteful
It is much easier to design switches with low on-resistance
than an amplifier with very large Gm

Output Referred Noise Comparison
2
C 2
Ron1 noise referred to vo N1 = 4kTRon1f s H( j)
Cf
2
Ron2 noise referred to vo N2 = 4kTRon2 f H( j)
2
4kT C 2
Amplifier noise referred to vo Na = f 1 + s H( j)
Gm Cf
2
Cs
1 + 2
Na Cf Na Cs
= >> 1 = 1+ >> 1
N1 GmRon1 C 2 N2 GmRon2 Cf
s

Cf
Amplifier noise dominates over noise due to Ron1, Ron2
Total Integrated Amplifier Noise
1
R
Gm
4kTGm f
2
v o2 1 1
= 4kT R
f R j CLtot
2
1 R 1 kT
v o2 = 4kT f df =
0
R 1 + j RCLtot CLtot

Adding up the Noise Contributions
1 2
q2x = kT ( Cs + Cf )
2 q2x Cs + C f kT Cs 2 1 kT
v o,1 = = kT = 1 + v o,2
C2f C2 C Cf
CLtot
f f
2 kT Cs 1 kT
v o,tot = 1 + +
Cf Cf CLtot
Noise in Differential Circuits
In differential circuits, the noise power is doubled (because there

are two half circuits contributing to the noise)
But, the signal power increases by 4x
Looks like a 3dB win?
2
DRsingle
V 2
o DRdiff
( 2V )
o
=2
V o2
kT kT kT
2
C C C
Yes, theres a 3dB win in DR, but it comes at twice the power
dissipation (due to two half circuits)
Can get the same DR/power in a single ended circuit by
doubling all cap sizes and gm

Outline

Advanced techniques
Clock bootstrapping
SC Noise Simulation
There are at least three ways to simulate noise in switched
capacitor circuits
Basic .ac/.noise Spice simulations
Simulate noise in each clock phase separately
Activate 1 switches, run .noise and integrate noise
charge at relevant node over all frequencies and refer to
output
Activate 2 switches, run .noise and integrate noise over
all frequencies at the output
Sum integrated noise from the two phases
This is analogous to the way we carried out the hand
analysis

SC Noise Simulation
Periodic Steady State Simulation
First run PSS analysis to find the periodic operating point
Analogous to .op for .ac/noise
Next run PNOISE analysis
Computes total noise, taking all clock phases, noise
aliasing, noise correlations, etc. into account
Transient Noise
Direct simulation of all noise sources using a transient
simulation
Most physical way of simulating noise
Example T/H Circuit

OTA Gm chosen such than (Ts/2) / OTA = 10
Switches sized 5 times faster, i.e. N = 510 = 50
vic
vic
Cfp
Clp
cf
cl
voc
vocs
vdd
p1
Csm
cs
Csp
cs
p1
Cfm
Clm
cf
cl
vic
vic
fs = 100 MHz, = 2, = 1
Cs = Cf = 100 fF, CL = 500 fF, Cpar 0

.Noise Simulation (f1)
*** Compute noise charge at node X and refer to output via Cf
en vno 0 vcvs vol =( cs*v(x,s) + cf*v(x,f) )/cf
.ac dec 100 100 1000Gig
.noise v(vno) vdummy
(showing half circuit for simplicity)
.Noise Simulation (1)
-15
10
PSD [V2/Hz]
-20
10
-25
10 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]
-4
x 10
6
Integral [uVrms]
4 406Vrms
2
0 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]

.Noise Simulation (2)
-15
10
PSD [V2/Hz]
-20
10
-25
10 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]
-4
x 10
4
Integral [uVrms]
266Vrms
2
0 2 4 6 8 10 12
10 10 10 10 10 10
Frequency [Hz]
2
v out,tot = ( 406Vrms )2 + ( 266Vrms )2 = 485Vrms
PSS Simulation Setup
Set tstab if your circuit needs time

to reach steady state
(e.g. clock bootstrap circuits)
Under options set maxacfreq to

the highest frequency from which
you expect noise to fold down

PSS Waveforms (Clocks)
4.75ns
PNOISE Simulation Setup
Numsidebands fmax/fs, where fmax is the

maximum frequency from which you expect
significant noise folding
timedomain means simulator computes

spectrum of discrete time noise samples at
the specified sampling instant
Sampling instant (4.75ns in this example)

How to Chose Parameters
Maxacfreq must be set commensurate with the speed

of the switches
Common pitfall: Use nice 1m switches must
consider noise from DC to daylight
In our example
1 10
Maxacfreq 10 = N fs
2RonC
Maxacfreq 3 50 100MHz = 15GHz
How to Chose Parameters

In traditional PSS/PNOISE simulators (such as
SpectreRF), simulation time increases rapidly for large
values of Numsidebands
Berkeley Design Automation (BDA) Analog FastSPICE
(AFS) automatically includes an infinite number of
sidebands at significantly reduced simulation times
Maxacfreq 15GHz
Numsidebands = = 150
fs 100MHz

PNOISE Result (SpectreRF)
Sampled Noise PSD Integrated Noise
Transient Noise Using BDA AFS

Simulated 1000 samples
Only one critical setting: noisefmax = 15 GHz

Comparison
Very good agreement between hand calculation and all three
simulation approaches
1 Noise 2 Noise Total

Method Comment
[Vrms] [Vrms] [Vrms]
Calculation 406 245 474 Neglected switch noise during 2
smaller value than .NOISE
.NOISE 406 266 485
PNOISE - - 475 Somewhat smaller than .NOISE
due to finite Maxacfreq and
Numsidebands
TRAN - - 477 Somewhat smaller than .NOISE
NOISE due to statistical fluctuations (can
use more samples)
Advantages of TRAN NOISE
Takes advantage of rapid advancements in very fast,

spice-accurate transient simulators (such as BDA AFS)
Can handle much larger circuits compared to
PSS/PNOISE (PSS tends to have convergence issues
for large circuits)
Intuitive inspection of waveforms
No need to combine noises manually
Compared to .ac/.noise simulation flow
Applicable also to non-periodic circuits

Further Reading on Noise
Basics
B. Murmann, "Thermal Noise in Track-and-Hold Circuits: Analysis and
Simulation Techniques," IEEE Solid-State Circuits Magazine, vol. 4, no.
2, pp. 46-54, June 2012.
SC integrator noise analysis
R. Schreier, J. Silva, J. Steensgaard, and G.C. Temes, "Design-
oriented estimation of thermal noise in switched-capacitor circuits,"
IEEE TCAS1, vol.52, no.11, pp. 2358-2368, Nov. 2005.
Total integrated noise expressions for more complex OTAs
(two-stage, etc.)
A. Dastgheib and B. Murmann, Calculation of Total Integrated Noise in
Analog Circuits, IEEE TCAS1, vol. 55, no. 10, pp. 2988-2993, Oct.
2008.
Transient noise simulation example for a complete ADC
Lennart Mathe and David C. Lee, "Analog-to-Digital Converter
Performance Signoff with Analog FastSPICE Transient Noise at
Qualcomm," Berkeley Design Automation, www.berkeley-da.com.
Summary Sampling Circuits
Three predominant implementation styles

Purely passive
Source follower T/H, up to ~9-10bit accuracy
Charge redistribution or flip-around architecture
In a typical, properly designed circuit only the most fundamental
issues are significant
Jitter, kT/C noise
Charge injection is not a problem if properly handled
E.g., use bottom plate sampling

Voltage Comparators
Boris Murmann
Stanford University
Recap
Ultimately, building a quantizer requires circuit elements that

"make decisions"
The most widely used "decision circuit" is a voltage comparator

Preview - Flash ADC
2B-1
Dout
Vin
2B-1 Decision Levels
Ideal Voltage Comparator
Function
Compare the instantaneous values of two analog voltages
(e.g. an input signal and a reference voltage) and generate a
digital 1 or 0 indicating the polarity of that difference
We essentially want to implement infinite gain

How to Implement High Gain?
Considerations
Amplification need not be linear
Amplification need not be continuous time if comparator is
used in a sampled data system
Clock signal will tell comparator when to make a decision
We will focus on this case, since it is the predominant scenario
Implementation options to be looked at
Multi-stage amplification
E.g. cascade of resistively loaded differential pairs
Regenerative latch using positive feedback
E.g. cross coupled inverters
Input Signal Scenarios
Sampled Data Input

Our focus
Continuous Time Input

Cascade of Open-Loop Amplifiers
gm u 1
In each stage: u = const. A 0 = gmR = 0 = = u
Cgs 0 RC A 0
What is the best choice for a given gain requirement?

Single stage with lots of voltage gain (OTA)?
Only a few stages with moderate gain?
Lots of stages with low gain?
Step Response (1)
When the input is a sampled data signal, we want to achieve the

fastest possible amplification in response to an input step
Vistep Av 1
Vout (s) = Vin (s)A(s) = N u = A v = AN
s 0
(1+ s A )
u v
1/N u

i
t
t 1/N
1/N N 1 A

Vout (t) = Vistep A v 1 e u A v u v
i=0 i!

A(t)

Step Response (2)
10
8
d(N=3)
Step response A(t) 6 10(1-e-1)
4 N=1
N=3
N=5
2
Av*(1-e-1)
0
0 5 10 15
Time t/u
Three stage amplifier wins! (for Av=10)
Delay versus Number of Stages
(
A( d ) = A v 1 e1 ) d (numerically)
50
Av=10
Av=100
40 Av=1000
Delay time d/u
30
20
10
0
2 4 6 8 10 12 14
N (Number of stages)
Using a single stage is a non-starter
The optimum number of stages show a shallow minimum

Optimum Number of Stages
12
Numerical result
Optimum number of stages

10
ln(Av)
0 0 1 2 3 4 5
10 10 10 10 10 10
Av (Total gain)
Nopt ln(A v )
Optimum Gain per Stage
5
Numerical result
A0,opt (Optimum gain per stage)
4.5 e
4
3.5
2.5
1.5
1 0 1 2 3 4 5
10 10 10 10 10 10
Av (Total gain)
Nopt Nopt
Nopt ln(A v ) e A v = A 0,opt A 0,opt e

Cascade of "Integrators" (1)
Intuition
Load resistors (in a cascade of open-loop amplifiers) shunt
current away from load capacitance; this slows down
amplification
Analysis using integrator stages
g N
v o1 = m vin = u vin v oN = u
vin
sC s sN
Cascade of Integrators (2)
Vistep N tN
Vout (s) = u
N
Vout (t) = Vistep N
u
s s N!
10 10
8 8
Step response A(t)
Step response A(t)
6 6
4 4
N=1 (with R) N=3 (with R)

2 2
N=1 (integ) N=3 (integ)
Av*(1-e-1) Av*(1-e-1)
0 0
0 5 10 15 0 5 10 15
Time t/u Time t/u

Cascade of Integrators (3)
Cascade of integrators achieves faster amplification than

cascade of resistively loaded stages
Delay time
1/N Vout ( d )
d = u [(N! A( d ))] A( d ) =
Vinstep
Optimum number of stages approximately given by
Nopt = 1.1ln [ A( d )] + 0.79 [Wu, JSSC 12/1988]
Effective gain per stage is still relatively close to e=2.7183
Regenerative Sense Amplifier (Latch)
Conceptual Circuit
Inverter

Transconductance

t=0

[Figueiredo]

/

/

1: Set up initial condition (vOD0)
2: Enable positive feedback

Simulation Example
I4 I7
vid vip vop vod
vdm vp vp vdm
vic ideal_balun vim vom ideal_balun voc
vcm vm vm vcm
p2!
M0 M4
10u/0.18u 10u/0.18u
p1!
vom vim
p1!
vip vop
C0
M1 M3 cl
C3 5u/0.18u 5u/0.18u
cl
vid
vic
p1!
p1
vdd
V0 V2 V5 p1b
p2!
p1e
vdc:vdd vdc:vic vdc:vid CL=100 fF p1eb p2!
p2
p2b
p2e
clock_gen
Transient Response
Nodes vOP and vON for differential inputs of 1mV, 1V, 1nV and 1pV
2 goes high

Transient Response
Differential Mode Common Mode
Transient Response (Log Scale)
=
/ 600ps 600ps
= = = = 43
ln 10 6 2.3
=
/ ln


Comparison
10
Amplification A(t)
6
4
N=3 (with R)
N=3 (integ)
2
Latch
Av*(1-e-1)
0
0 5 10 15
t/ t/
Time
Latch is much faster than cascade of amplifiers/integrators
Latch Gain
A(d) d/
10 2.3
100 4.6
1,000 6.9
10,000 9.2

"The" Architecture
Why bother using pre-amplification (Av)?

Pre-amplification may be used for several reasons
Lower offset (latch offset tends to be large)
Lower thermal noise
Attenuation of "kickback noise
Separate input from output
Common mode rejection
Basic Topology Examples (1)
Class-A (constant current)
Figure from [Figueiredo, TCAS2, July 2006]

Class-AB
Input pair has constant bias, but latch draws current only
while making a decision
Fully dynamic
Draws (significant) current only while making a decision
Original paper:
[Kobayashi, JSSC, April 1993]

Offset in Latches
vOP vON Inverter switching voltage: VS

VOS,static
Initial common mode: VOC0
CLP CLN Load capacitor mismatch: CL
Static offset (VOS) due to transistor mismatch (primarily Vt)

Dynamic offset due to load capacitor mismatch
For an analysis see Nikoozadeh, TCAS II, Dec. 2006
1 1 10
, Example: 0.3 0.9 = 30
2 2 100
Minimize, if possible
Input Referred Offset with Preamplification
1
2VOS = 2VOS1 + 2VOS2
A 2v
Example: VOS1=3mV, VOS2=30mV, Av=10
1
VOS = ( 3mV )2 + 2
( 30mV )2 = 4.2mV
10

Dealing With Offset
Options depend strongly on the application context

May use an ADC architecture that inherently tolerates offset
More later
May use a relatively coarse tuning mechanism
E.g. tune offset to lie within LSB at the 6-bit level
May have to apply precision techniques
Autozeroing, etc. (see EE315A), for high-end instrumentation
Simply use large transistors
Usually not power efficient
Example: Coarse Offset Tuning

The circuit below uses capacitve imbalance to tune the offset
An example of using a "bug" as a feature
See e.g. Van der Plas, ISSCC 2006
Watch out for PSRR degradation due to circuit imbalance

Example: Precision Comparator
[http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3956]
Used in the AD7671, 16-bit, 1-MS/s successive approximation ADC

Uses cascaded output series offset cancellation (see EE315A)
Electronic Noise in Latch Comparators
Class-A topology
Integrate noise at regenerative node over all frequencies and
refer to the input kT/CL
See Opris, Electronics Letters, July 1997
Dynamic topology
Very hard to analyze due to the time variant behavior
See Nuzzo, IEEE TCAS1, July 2008
Fortunately, the end result is not too far from class-A-like
noise estimation in the decision point kT/CL

Kickback
E.g. Flash ADC

resistor ladder
Kickback Mitigation Techniques
Neutralization Neutralization and Switch Isolation
Figures from [Figueiredo, TCAS2, July 2006]

Kickback Mitigation Techniques
Extra switches act

similar to cascodes
[Sundstrom, MIXDES 2007]
Other Design Considerations
Input capacitance and linearity of input capacitance

Consider e.g. loading of the input network in a flash ADC
Overdrive recovery
Consider a very large input, followed by a very small input of
opposite polarity
Metastability
What if the input is so small that the comparator cannot
decide in the given amount of time?

Overdrive Recovery Test
Latch
activation
1 2
Comparator
input
Preamp
[Razavi, p. 183]
output
The test is passed when the latch output changes polarity in

case 1, but not in case 2
Metastability (1)
The plot below shows the time needed to regenerate a given

differential latch input to full logic swing
35
30
25
20
treg/
= ln
15
10
0 -15 -10 -5 0
10 10 10 10
v
vOD0/V/VDD

Metastability (2)
What if the input is so small that we run out of time?

This is called a metastable state, i.e. at the end of the clock
cycle there is no clear logic decision
The following logic gates will go into an erratic state that is hard
to predict, and so we classify this outcome as an error
In the following analysis we will try to estimate the probability at
which metastable states will occur
Application requirements vary widely
Error correction coding in certain communication sytems can
absorb probabilities of up to 10-3
High-speed wireline links (without coding) or instrumentation
equipment may require probabilities better than 10-18
Metastability (3)
Assume that the maximum available time is tmax
The minum latch input we can regenerate is then

, =
/

In case, we have a preamp, we can do slightly better

1
, =

/
Now assume that the input is uniformly distributed over some
range, and compute the probabily of seeing a metastable state
PDF
,

/

= =
, ,
-vID0,max +vID0,max
-vID0,min +vID0,min

Mean Time to Failure
In some applications it makes sense to think about metastability

in terms of the mean time between metastable events
Mean time to failure (MTF)
2
10
1
=

MTF [days]
0
10
fs=10GHz fs=100MHz
-2
10
-18 -16 -14 -12 -10

10 10 10 10 10
Pmeta
Example: Flash ADC
In a flash ADC, there is always (exactly) one comparator that

sees an input within /2
The probability of seeing a metastable state within the array is
therefore found using vID0,max = /2

/
/

= =
1 V
2 2 2
The graph on the next slide plots an example

Sampling rate fs = 1GHz, tmax 1/2fs = 500ps
B = 6, Av =1, VFS = VDD

Example: Flash ADC
0
10
-5
10
-10
Pmeta 10
-15
10
-20
10
10 20 30 40 50 60 70 80
[ps]
The curve is incredibly steep in the region of Pmeta < 10-5

Very strong incentive to minimize as much as possible
Ultimitaley bounded by Cgg/gm = 1/T
Metastability Detectors?
Why not build a clever logic circuit that detects the metastable
state and overrides it with a valid logic state?
This sounds good, but is difficult to do in reality
Logic gates look like "low pass filters" compared to a latch
A latch provides the maximum possible gain per unit of time;
any gate delay added after the latch (that eats into the
regeneration time) is counterproductive
Most (if not all) metastability detector ideas
proposed in literature tend to create new
metastable states
Related article: R. Ginosar, "Fourteen ways to
fool your synchronizer," 2003

Comparator Examples (1)
Mehr & Dalton, JSSC 7/1999

Mehr & Dalton, JSSC 7/1999

Schinkel, ISSCC 2007: "Double tail sense amplifier"
Miyahara, ASSCC 2009

Lee, JSSC, April 2011
Tripathi, ESSCIRC 2013
6ps

Selected References (1)
1. Y. S. Yee, L. M. Terman and L. G. Heller, A 1mV MOS Comparator, IEEE J. of
Solid-State Circuits, vol. SC-13, pp. 294-297, June 1978.
2. A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, IEEE J. of Solid-State
Circuits, vol. SC-20, pp. 775-779, June 1985.
3. B. J. McCarroll, C. G. Sodini, and H.-S. Lee, A High-Speed CMOS Comparator for
Use in an ADC, IEEE J. of Solid-State Circuits, vol. 23, pp. 159-165, Feb. 1988.
4. J.-T. Wu and B. A. Wooley, A 100-MHz Pipelined CMOS Comparator, IEEE J. Solid-
State Circuits, vol. 23, pp. 1379-1385, Dec. 1988.
5. B. Razavi and B. A. Wooley, A 12-b 5-MSample/s Two-Step CMOS A/D Converter,
IEEE J. Solid-State Circuits, vol. 27, pp. 1667-1678, Dec. 1992.
6. B. Razavi and B. A. Wooley, Design Techniques for High-Speed, High-Resolution
Comparators, IEEE J. Solid-State Circuits, vol. 27, pp. 1916-1926, Dec. 1992.
9. M. Choi and A. A. Abidi, "A 6-b 1.3-GSample/s A/D converter in 0.35-m CMOS,"
IEEE J. Solid-State Circuits, pp. 1847-1858, Dec. 2001.
10. I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-
channel applications," IEEE J. Solid-State Circuits, pp. 912-920, July 1999.
11. I. Mehr and L. Singer, A 55-mW, 10-bit, 40-MSample/s Nyquist-Rate CMOS ADC,
IEEE J. Solid-State Circuits, pp. 318-25, March 2000.
12. G.R. Couranz, and D.F. Wann, "Theoretical and Experimental Behavior of
Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, vol. C-
24, no.6, pp. 604-616, June 1975.

9. H. J. M. Veendrick, The Behavior of Flip-Flops Used as Synchronizers and
Prediction of Their Failure Rate, IEEE J. Solid-State Circuits, April 1980.
10. B. Zojer, et al., A 6-bit/200-MHz full Nyquist A/D converter, IEEE J. Solid-State
Circuits, vol. SC-20, pp. 780-786, June 1985.
11. K.-L.J. Wong and C.-K.K. Yang, "Offset compensation in comparators with minimum
input-referred supply noise," IEEE J. Solid-State Circuits, pp. 837-840, May 2004.
12. A. Graupner, "A Methodology for the Offset-Simulation of Comparators,"
http://www.designers-guide.org/Analysis/comparator.pdf.
13. D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps
Setup+Hold Time," ISSCC Dig. Techn. Papers, pp. 314-315, 2007.
14. P.P. Nuzzo, et al., "Noise Analysis of Regenerative Comparators for Reconfigurable
ADC Architectures, IEEE Trans. Circuits Syst. I, pp.1441-1454, July 2008.
15. B.S. Leibowitz, et al., "Characterization of Random Decision Errors in Clocked
Comparators," Proc. IEEE CICC, pp.691-694, Sep. 2008.
16. Analog Devices, "Find Those Elusive ADC Sparkle Codes and Metastable States"
http://www.analog.com/en/content/0,2886,760%255F788%255F91218,00.html
19. M. Miyahara and A. Matsuzawa, "A low-offset latched comparator using zero-static
power dynamic offset cancellation technique," ASSC, pp. 233-236, Nov. 2008.
20. P.M. Figueiredo, "Comparator Metastability in the Presence of Noise," IEEE TCAS1,
vol. 60, no. 5, pp.1286-1299, May 2013.

Flash ADCs
Boris Murmann
Stanford University
Nyquist ADC Architectures

Nyquist rate
Word-at-a-time
Flash ADC
Instantaneous comparison with 2B-1 reference levels
Multi-step
E.g. pipeline ADCs
Coarse conversion, followed by fine conversion of residuum
Bit-at-a-time
E.g. successive approximation ADCs
Conversion via a binary search algorithm SPEED
Level-at-a-time
E.g. single or dual slope ADCs
Input is converted by measuring the time it takes to
charge/discharge a capacitor from/to input voltage

ADC Survey (ISSCC & VLSI 1997-2013)
10
Flash
10 Folding
Two-Step
Pipeline

8 SAR
10 Other
[Hz]
1000fs Jitter
rms
in,hf
100fs Jitter
f
rms
6
10
4
10
20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
hf
Flash ADC Speed

7
Flash ADCs
6
Microprocessors
Clock Speed [GHz]
0
1996 1998 2000 2002 2004 2006 2008
Year
Modern Flash ADC Architecture
Vadc
CLK
Vin Vadc
Wallace Encoder
T/H Dout
Fast
Speed limited only by comparator
decision
High complexity, large input capacitance
Resolution tends to limited to 6 bits Usually implemented as a fully
differential circuit
Why Use a T/H?
One reason: Timing offsets between comparators may cause

bubbles in the thermometer code
Single bubble
Double
bubble
Fast
moving
input
K. Uyttenhove, M.S.J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-m CMOS," JSSC, pp. 1115-1122, July 2003.

Bubble Problem in a Poor Mans Encoder
e.g. due to
timing offset
between two
comparators
Correct output: 1000, actual output: 1110 (!)
Bubble Tolerant Encoder
Protects against single bubbles

Reference: C. W. Mangelsdorf, A 400-MHz Flash Converter with Error
Correction, IEEE J. Solid-State Circuits, pp. 184-191, Feb. 1990.

Modern Solution: Wallace Encoder
Simply a ones adder

F. Kaess, et al., New encoding
scheme for high-speed flash
ADCs, ISCAS 1997, pp. 58
Complexity used to be an issue in
older technology; not a problem in
sub-100nm CMOS
Number of adders needed for
N bits:
Alternative (or Additional) Solution

Still want to use a T/H, even if bubbles are not a problem
Simplified comparator design
Well-behaved input impedance
T/H need not be all that complex
Source follower T/H
Y. Tamba, and K. Yamakido, "A CMOS 6 b 500 MS/s ADC for a hard disk drive read channel, ISSCC 1999, pp. 324-325

How about Metastability?
Different gates interpret metastable output X differently

Correct output: 0111 or 1000, actual output: 1111 (!)
Again, a simple encoder does not handle this very well
Solution 1: Wallace Encoder
Similar reasoning as with

bubbles
Error due to metastable
input is bounded by 1LSB

Solution 2: Latch Pipelining
Use additional latches to create extra gain before generating

decoder signals
Usually too power hungry and area inefficient
Solution 2: Gray Encoding

Thermometer Code Gray Binary
T1 T2 T3 T4 T5 T6 T7 G3 G2 G1 B3 B2 B1
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 1
1 1 0 0 0 0 0 0 1 1 0 1 0
1 1 1 0 0 0 0 0 1 0 0 1 1
1 1 1 1 0 0 0 1 1 0 1 0 0
1 1 1 1 1 0 0 1 1 1 1 0 1
1 1 1 1 1 1 0 1 0 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1 1 1
Each Ti affects only one Gi

G3 G2 G1 Avoids disagreement
of interpretation by
multiple gates

Efficient Implementation
Reference
C. Portmann and T. Meng, Power-Efficient Metastability Error
Reduction in CMOS Flash A/D Converters, IEEE J. Solid-State
Circuits, pp. 1132-40 , Aug. 1996.
Offset
Typically want offset of each comparator <1/4LSB with high

probability (3 sigma)
If we budget half of the input referred offset for the latch, the
other half for the pre-amp, this means pre-amp offset must
be <1/4LSB / sqrt(2)
AVT 1 FSR
3VOS = 3 <
WL 4 2 2B
E.g. 6-bit flash ADC, FSR=1V
AVT 1 1V
3 < = 2.8mV
WL 4 2 26
Huge!
2 2 2
3 AVT 3 4mV m 2 18.4m
WL > = = 18.4m W > = 102m
2.8mV 2.8mV 0.18m

Re-cap of Options
Simply use large devices

For each extra bit, need to increase width by 4x, also need
to double number of comparators
Assuming constant current density, this means each
additional bit costs 8x in power!
Dynamic offset cancellation (autozeroing, etc.)
Tends to cost speed
More commonly used
Offset averaging
Offset calibration
Incorporation of redundant comparators
Offset Averaging (1)
R2/R1=1.3
[Kattmann & Barrow, ISSCC 1991]

Offset Averaging (2)
DNL/
[Bult & Buchwald, JSSC 12/1997]
[Scholtens & Vertregt, JSSC 12/2002]
6-bit Flash ADC with Averaging
[Choi & Abidi, JSSC 12/2001]
Averaging networks designed to

reduce input referred offset by 3x

Offset Calibration Using Global DAC
S. Sutardja, "360 Mb/s (400 MHz) 1.1 W 0.35m CMOS PRML read channels with 6
burst 8-20 over-sampling digital servo," ISSCC Dig. Techn. Papers, Feb. 1999.
Calibration Using one DAC per Comparator
(Reset switches not shown)

8 8 8 4 2 1
Voutn Voutp MUX/Encoder
Dcalp CAL Vrefn Vinp Vinn Vrefp CAL Dcaln

Vlo Vhi Vlo Vhi
[M. El-Chammas, VLSI 2010]

Offset Calibration at Start-Up
In+
Ref+
Output oscillates between one Out
and zero as the input-referred AVG
Ref-
offset converges to zero In-
INC/
Start-up calibration is DEC
reasonably stable at flash Control Bits
ADC resolutions
The correction circuit shown
Out
on the previous slide has a t
relatively low temperature
dependence
Input-referred
Offset Offset = 0
t
Tuning Range Issue (1)
Ideally, the trim-DAC must bring the offset well within one LSB
of the flash ADC
The required trim-DAC resolution can become unacceptably
large if near minimum-size transistors (with large Vt mismatch)
in the latest technology are used
A clever workaround is to utilize the error correction capability of
the Wallace tree encoder (ones counter)

Tuning Range Issue (2)
[Verma, ISSCC 2013]

+
0
Vref0 - Vref0 (eff)
+
1
Vref1 - Vref1 (eff)
+
2
Vref2 - Vref2 (eff)
+
Vref3 3
- Vref3 (eff)
Ones Counting is Equivalent to Reordering
[Verma, ISSCC 2013]

+
2
Vref0 - Vref0 (eff)
+
0
Vref1 - Vref1 (eff)
+
1
Vref2 - Vref2 (eff)
+
Vref3 3
- Vref3 (eff)
Reduced tuning range

Comparator Redundancy (1)
Interesting idea: Do not worry about offsets at all, just provide

enough levels that properly add up on average
90mW 900mW
Wallace Encoder
Paulus et al., "A 4GS/s 6b flash ADC in 0.13um CMOS," VLSI Circuits Symposium, 2004
Comparator Redundancy (2)
Another idea: Build a "sea of imprecise comparators", then

determine which ones to use
C. Donovan, M. P Flynn, "A 'digital' 6-bit ADC in 0.25-m CMOS," IEEE J.

Solid-State Circuits, pp. 432-437, March 2002.

Differential Pair Redundancy
Idea: Have multiple input pairs and use the one you like
[Chen, VLSI 2013]
Details

Performance Comparison
[Chen, VLSI 2013]
Calibration Using Reference String
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006]

Details
Measured Results

Reducing Complexity
Even with calibration, flash ADCs tend to hit a wall beyond 6 bits
of resolution
Large calibration range
Large input capacitance
Complex encoder
Several techniques have been developed to ease the pain and
potentially allow going beyond 6 bits (at the cost of some speed)
Interpolation
Folding, folding & interpolation
Subranging
Interpolation
Idea
Interpolation between preamp outputs
Reduces number of preamps
Reduced input capacitance
Reduced area, power dissipation
Same number of latches
Important side-benefit
Decreased sensitivity to preamp offset
Improved DNL

Concept
[van de Plassche, p.118]
Differential Implementation
VA + VB
=0 VA = VB
2

Higher Order Interpolation
Resistors produce
additional levels
Define interpolation factor
as ratio ratio of latches
and preamps
The example shown on
this slide has M=8
[H. Kimura et al, A 10-b 300-MHz

Interpolated-Parallel A/D Converter,
IEEE J. of Solid-State Circuits, pp.
438-446, April 1993.
Potential Issues with Interpolation
Must ensure that "linear range" of adjacent preamplifiers

overlaps
Sets upper bound on preamp gain
Resistor string reduces signal path bandwidth
Sets upper bound on interpolation factor, typically around 4
For interpolation factors >2, amplifier nonlinearity can limit the
precision of zero crossings
See e.g. Van de Plassche, p.121

Folding
MSB
VIN
ADC
Digital
Output
LSB
ADC
Folding Circuit
Main idea: Re-use comparator several times across

the full scale range
Simplest Variant
[Verbruggen, JSSC, March 2009]
Folding circuit

Creating Multiple Folds
Parameter K sets output common mode
Folder Output
0.5
Folder Output
Ideal Folder Accurate only at

0
CMOS Folder
zero-crossings
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4
Lowdown
0.1
0.05 Most folding ADCs

do not actually use
Error
0
the folds, but only the
-0.05
zero-crossings!
-0.1
0 0.5 1 1.5 2 2.5 3 3.5 4
Vin /

Multiple Folds Using Only Zero Crossings
Way too complex, need

one folder per decision
in the fine ADC
Idea
Use interpolation to
eliminate some of
the folders
Interpolation
Same idea as discussed previously

Complete Folding & Interpolating ADC
3-bit coarse ADC

3-bit fine ADC
2 folders with 4x
interpolation
8 levels
We have therefore
built a 6-bit ADC
with only 16
comparators
(instead of 63)
8-bit, 70 MS/s Folding and Interpolating ADC
[B. Nauta and G. Venes, JSSC. Dec. 1985]

8-bit, 1.6 GS/s Folding and Interpolating ADC
[Taft et al., JSSC 12/2004]
8b, 10GS/s Folding and Interpolating ADC
[Landolt, PRIME 2012]
For Rohde & Schwarz Scope

0.25um SiGe BiCMOS
9 Watts

Performance
Subranging
4-bit Flash ADC 2+2-bit Subranging ADC

8-bit, 1 GS/s Subranging ADC
Coarse ADC selects tap range for fine ADC
[Chung, VLSI 2011]
Summary Flash ADCs & Extensions
Today, flash ADC design boils down to an effective offset

management approach
Calibration and/or redundancy
Extensions such as averaging, folding, interpolation and
subranging can be used to alleviate the tradeoffs
But these techniques havent been popular in recent years
The reason may be the strong competition from pipelined
and time interleaved architectures
More later

Flash ADCs, Offset Averaging
1. K. Kattmann and J. Barrow, "A Technique for Reducing Differential Non-Linearity
Errors in Flash A/D Converters," ISSCC Digest of Technical Papers, pp. 170-171,
Feb. 1991.
2. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-
mm2," IEEE J. of Solid-State Ckts., pp. 1887-1895, Dec. 1997.
3. M. Choi and A. A. Abidi, A 6 b 1.3 Gsample/s A/D converter in 0.35m CMOS, IEEE
J. Solid-State Circuits, pp. 18471858, Dec. 2001.
4. C. S. Scholtens and M. Vertregt, A 6-b 1.6-Gsample/s Flash ADC in 0.18-m CMOS
Using Averaging Termination, IEEE J. of Solid-State Ckts., vol. 37, pp. 1599-1609,
Dec. 2002.
5. X. Jiang, M-C. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with power-
efficient averaging," IEEE J. of Solid-State Circuits, pp. 532- 535, Feb. 2005.
Folding and Interpolating A/D Converters
6. R.C. Taft et al., "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26
ENOB at Nyquist frequency," IEEE J. Solid-State Ckts., pp. 2107-2115 Dec. 2004.
7. B. Nauta and A. G. W. Venes, A 70-MS/s 110-mW 8-b CMOS Folding and
Interpolating A/D Converter, IEEE J. of Solid-State Circuits, pp. 1302-1308, Dec.
1995.

8. M. P. Flynn and B. Sheahan, A 400-MSample/s, 6-b CMOS Folding and
Interpolating ADC, IEEE J. of Solid-State Circuits, pp. 1932-1938, Dec. 1998.
9. H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori and A. Abidi, A 3.3V, 12b,
50MSample/s A/D converter in 0.6mm CMOS with over 80dB SFDR, ISSCC Digest
of Technical Papers, pp. 40-41, Feb. 2000.
10. M.-J. Choe, B.-S. Song and K. Bacrania, A 13b 40MSample/s CMOS pipelined
folding ADC with background offset trimming, ISSCC Digest of Technical Papers,
pp. 36-37, Feb. 2000.
11. G. Hoogzaad and R. Roovers, A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist
ADC in 0.8 mm2, IEEE J. Solid-State Circuits, pp. 1796-1802, Dec. 1999.
12. K. Nagaraj, F. Chen, T. Le and T. R. Viswanathan, Efficient 6-bit A/D converter using
a 1-bit folding front end, IEEE J. Solid-State Circuits, pp. 1056-1062, Aug. 1999.
13. M.-J. Choe and B.-S. Song, An 8b 100MSample/s CMOS pipelined folding ADC,
VLSI Symposium Digest of Technical Papers, pp. 81-82, Jun. 1999.
14. K. Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1
mm2, IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997.
15. P. Vorenkamp and R. Roovers, A 12-b, 60-MSample/s cascaded folding and
interpolating ADC, IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997.
16. A. G. W. Venes and R. J. van de Plassche, An 80-MHz, 8-b CMOS folding A/D
converter with distributed track-and-hold preprocessing, IEEE J. Solid-State Circuits,
vol. 31, pp. 1846-1853, Dec. 1996.

17. M. P. Flynn and D. J. Allstot, CMOS folding A/D converters with current-mode
interpolation, IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Dec. 1996.
18. R. Roovers and M. S. J. Steyaert, A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D
converter, IEEE J. Solid-State Circuits, vol. 31, pp. 938-944, Jul. 1996.
19. W. T. Colleran and A. A. Abidi, A 10-b, 75-MHz two-stage pipelined bipolar A/D
converter, IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, Dec. 1993.
20. J. van Valburg and R. J. van de Plassche, An 8-b 650-MHz folding ADC, IEEE J.
Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992.
21. R. J. van de Plassche and P. Baltus, An 8-bit 100-MHz full-Nyquist analog-to-digital
converter, IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, Dec. 1988.
22. R. E. J. Van de Grift, I. W. J. M. Rutten and M. van der Veen, An 8-bit video ADC
incorporating folding and interpolation techniques, IEEE J. Solid-State Circuits, vol.
SC-22, pp. 944-953, Dec. 1987.
23. R. E. J. van de Grift and R. J. van de Plassche, A monolithic 8-bit video A/D
converter, IEEE J. Solid-State Circuits, vol. SC-19, pp. 374-378, Jun. 1984.
24. R.C. Taft, et al., "A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating
ADC with 9.1 ENOB at Nyquist frequency," ISSCC Digest of Technical Papers,
pp.78-79, 79a, Feb. 2009.

SAR ADCs
Boris Murmann
Stanford University
Similarity Between Non-Flash ADC

Architectures
Vin
Minimize
Dout
D/A
Most ADC architectures (other than flash) are based on minimizing

the error between input and a D/A signal approximation
SAR ADC uses comparator to sense
Sigma-delta ADC minimizes via integration and feedback
Pipeline uses distributed DAC
B. Murmann 2
Successive Approximation Register ADC
Binary search over DAC output

High accuracy achievable (16+ Bits)
Relies on highly accurate comparator
Moderate speed (1+ MHz)
High Performance Example

Low Power Example
M.D. Scott, B.E. Boser, K.S.J. Pister, "An ultralow-energy ADC for Smart
Dust," IEEE J. Solid-State Circuits, pp. 1123 -1129, July 2003.
Classical Implementation
See e.g. [McCreary, JSSC 12/1975]
C1A = C1B = C C2 = 2C C3 = 4C CB = 2B 1C

Sampling Phase (5-bit Example)
Total charge at node Vx after opening Sx
Q = Vin 32C = Vin Ctotal
Bit5 Test (MSB)
(
Q = Vin Ctotal = (Vx Vref ) 16C + Vx 16C + Cp )
1 Ctotal
Vx = Vref Vin
2 Ctotal + Cp
Vx<0 Vin>0.5Vref Bit5=1

Vx>0 Vin<0.5Vref Bit5=0

Bit4 Test (Assuming Bit5=0)
(
Q = Vin Ctotal = (Vx Vref ) 8C + Vx 24C + Cp )
1 Ctotal
Vx = Vref Vin
4 Ctotal + Cp
Vx<0 Vin>0.25Vref Bit4=1

Vx>0 Vin<0.25Vref Bit4=0
Challenges at High Resolution
Capacitor mismatch
Use self calibration to obtain precision beyond raw
technology matching [Lee, JSSC 12/84]
Minimum capacitor size, e.g. Cmin=10fF 216Cmin = 655pF
Solution: Implement "two-stage" or "multi-stage" capacitor
network to reduce array size [Yee, JSSC 8/79]
Typically mandates some form of calibration
Ultimately, even with calibration, there is still a lower bound
based on kT/C in the sampling phase
E.g. 16-bit resolution, Ctotal ~ 100pF required
How to drive such an ADC at high speeds?

Recent Publication Trend
12
SAR ADC Papers at ISSCC and VLSI Symposium
10
8
Count
0
1996 1998 2000 2002 2004 2006 2008 2010 2012 2014
Year
Recent Innovations in SAR ADCs
Mostly focused on low-to-moderate resolution!

Use of extremely small unit capacitors (<1fF)
E.g. [Shikata, VLSI 2011]
Energy efficient switching techniques
E.g. [Liu, VLSI 2010]
Asynchronous operation
E.g. [Chen, CICC 2006]
Incomplete DAC settling enabled by redundancy
E.g. [Liu, VLSI 2010] 100 MS/s, ~ 9.5 ENOB
SAR ADC pipelining
E.g. [Lee, VLSI 2010] 50MS/s, ~10.5 ENOB
Massive time interleaving
E.g. [Doris, ISSCC 2011] 2.6 GS/s, ~ 8 ENOB

Small Metal Fringe Capacitors
Want to minimize unit caps as much as possible for low-to-

moderate resolution SAR ADCs
0.5fF unit capacitors
[Shikata, VLSI 2011]
B. Murmann
13
13
Asynchronous Timing
[Chen & Brodersen, JSSC 12/2006]
Key insight: At most one of the SAR decisions can be close to

metastability; all others will be very fast
Asynchronous timing exploits this by allocating the most time to
the hardest decision
Energy Efficient Switching (1)
Conventional switching scheme is

wasteful in terms of energy
[Liu, JSSC 4/2010]
[Liu, JSSC 4/2010]
Top plate sampling

First decision free
[Liu, JSSC 4/2010]
Total of 81% switching energy reduction

Caveat: Need comparator with good common-rejection

Constant Common Mode CDAC
[Kull, ISSCC 2013]
MSB cap split into two
[Ginsburg, ISCAS 2005]
Key insight: Do not have to switch entire MSB cap for first DAC transition
Total energy savings of 37%

Resistive DAC
[Wei, ISSCC 2011]
Multi-bit/cycle architecture yielding 8 bits at 400 MS/s
DAC Settling Errors
0(t) t
tdecision
Input bk

-1 x +1 - -
1 2-1 (conceptual model)
b0 b1 b2
Register
1 2-1 2-2
Output x

Error in First Decision
k=0 1 2 3
1
x
0
x
-1
Redundancy (Radix < 2)
x bk

- - -
1 -1 -2
b0 b1 b2 b3
Register
1 -1 -2 -3
Output x

< >


Error in First Decision ( = 22/3)
k=0 1 2 3 4
1
x x Error /2
0
Note that

-1
Tolerable Error ( = 22/3)
k=0 1 2 3 4
1
Tolerable
Error
x
/2
-1

First Hardware Implementation
Z. Boyacigiller, B. Weir, and P. Bradshaw, An error-correcting 14b/20s CMOS A/D

converter, in ISSCC Dig. Techn. Papers, Feb. 1981, pp. 6263.
Other Ways to Introduce Redundancy
Radix = 2, but extra comparators

T. C. Verster, A Method to Increase the Accuracy of Fast-
Serial-Parallel Analog-to-Digital Converters, IEEE Trans. on
Electronic Computers, vol. EC-13, no. 4, pp. 471473, Aug.
1964.
Radix = 2, but extra cycles
V. Giannini et al., An 820W 9b 40MS/s Noise-Tolerant
Dynamic-SAR ADC in 90nm Digital CMOS, in ISSCC Dig.
Techn. Papers, Feb. 2008, pp. 238239.
C.-C. Liu et al., A 10b 100MS/s 1.13mW SAR ADC with
binary-scaled error compensation, in ISSCC Dig. Techn.
Papers, 2010, pp. 386387.

SAR ADC with Redundant Comparator
+ok

+. > +
x
= .

- -

1 2-1 -ok

= <
b0 b1 b2
Register
1 2-1 2-2
R. Vitek et al., A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step
redundancy and digital metastability correction, in Proc. IEEE Custom Integrated Circuits
Conference, Sep. 2012, pp. 14.
Normal Operation
k=0 1 2 3
1
+o1
x
+o0 -o1 x
-o0
-1

k=0 1 2 3
1
x
+o0 x
+o1
0
-o1
-o0
-1
SAR ADC with Redundant Step

bk
x
- - -
1 2-1 2-2
b0 b1 b2 b3
Register
1 2-1 2-2 c

= + = = +.
= = .

x
V. Giannini et al., An 820W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital

CMOS, in ISSCC Dig. Techn. Papers, Feb. 2008, pp. 238239.

Normal Operation
k=0 1 2 3 4
1
x x
0 Characteristic
crossing
-1
k=0 1 2 3 4
1
x x
0
-1

Redundant Step Alternate Method
bk
x
- - -
1 2-1 2-1
b0 b1 b1R b2
Register
1 2-1 2-1 2-2
C.-C. Liu et al., A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation, in
ISSCC Dig. Techn. Papers, Feb. 2010, pp. 386387.
Extra Levels
The addition of the redundant step provides extra levels that help
counter errors in previous decisions
b1R + b2
b2 +0.25+0.125 = 0.375
+0.125 +0.25-0.125 = +0.125
-0.125 -0.25+0.125 = -0.125
-0.25-0.125 = -0.375

Normal Operation
k=0 1 2 2R 3
1
x x
0
-1
k=0 1 2 2R 3
1
x x
0
-1

Potential Speed Benefit of Using
Redundancy
T. Ogawa et al., IEICE Trans. on Fundamentals of

Electronics, Communications and Computer Sciences,
Feb. 2010.
Benefit is clearly significant at high resolution

However, one must carefully evaluate if redundancy helps
significantly at low resolutions (e.g. 6-8 bits)
Metastability in an Asynchronous SAR
Worst case input is near 1/6 VFS
[Chen, JSSC 12/2006]

Example: 8-bit SAR (1)
There are seven easy decisions, and one hard decision

It can be shown that the sum of the easy decisions will take
anywhere between 25-33, depending on the input
For the hard decision, the input is within 1LSB, and we can
assume that it is uniformly distributed
PDF
,
=

-LSB +LSB
vod0,min
2
= ln = ln ln
,

Number of time constants to be allocated for the hard
decision, given a desired metastability rate (B=8)
60
50
40
thard/
30
20
10 -20 -15 -10 -5

10 10 10 10
P meta

Continue using the following assumptions (design and technology

dependent)
Total cycle time Ts = 1ns (1GS/s)
Sampling window = Ts/8
Sum of DAC settling times = Ts/3
Sum of logic delays = Ts/6
The time available for regeneration is treg,tot = (3/8)Ts = 375ps
The metastability rate estimate as a function of is
, , ()
P 2 e =2 e
2 e

0
10
teasy=33
teasy=25
-5
10
-10
10
Pmeta
-15
10
-20
10
4 5 6 7 8 9
[ps]
Incredibly steep tradeoff fast comparator is key
Comparator Reset
Fast reset is just as as important as fast regeneration
The design below ping-pongs between two comparators to
increase the available reset time
[Kull, ISSCC 2013]
Aside: Counter/Single-Slope ADC
[Harpe, ASSCC 2010]
One of the oldest ADC architectures

Simply measure time it takes for a ramp to reach input voltage
Ramp can be generated using a counter + DAC or current
source+capacitor
Slow, because counter range increases exponentially with bit-
resolution

Pipeline ADCs
Boris Murmann
Stanford University
Outline
Background
History and state-of the art performance
Derivation from SAR architecture
Pipeline ADC basics
Ideal block diagram and operation, impact of block
nonidealities
Ways to deal with nonidealities
Redundancy, calibration
CMOS implementation details
Stage scaling, MDAC design
Architectural options
OTA sharing, SHA-less front-end
Research topics

Pipeline ADCs An Old Idea (1956)
B.D. Smith, An Unusual Electronic Analog-Digital Conversion Method, IRE Transactions on

Instrumentation, vol. PGI-5, pp. 155-160, June 1956.
Todays Pipeline ADC Performance Range
10
Flash
10 Folding
Two-Step
Pipeline

8 SAR
10 Other
[Hz]
1000fs Jitter
rms
in,hf
100fs Jitter
f
rms
6
10
4
10
20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
hf

SAR ADC
x bk

- - -
1 -1 -2
b0 b1 b2 b3
Register
1 -1 -2 -3
Output x
SAR Pipeline (1)
x -2 bk

- - -
b0 b1 b2 b3
Register
1 -1 -2 -3
Output x

SAR Pipeline (2)
x bk

- - -
b0 b1 b2 b3
Register
1 -1 -2 -3
Output x
SAR Pipeline (3)
x

- - -
b0 b1 b2 b3
1 -1 -2 -3
Output x

Observation
Pipeline and SAR ADCs are mathematically equivalent

(considering ideal components)
Therefore, not surprisingly, all variants of redundancy can also
be incorporated in a pipeline ADC
It is just less obvious, and usually explained quite differently
More later
General Pipeline ADC Block Diagram
Align & Combine Bits

Dout
Vin
SHA Stage 1 Stage n-1 Stage n
Vin1 Vres1
G11
G Each stage contains a T/H
- (not shown)
ADC DAC
D1

Concurrent Stage Operation
CLK Align & Combine Bits

D
V
SHA Stage 1 Stage 2 Stage 3
ACQUIRE CONVERT ACQUIRE CONVERT

BUFFER ACQUIRE CONVERT ACQUIRE
Stages operate on the input signal like a shift register

New output data every clock cycle, but each stage introduces
clock cycle latency
Pipelining An Old Idea

Data Alignment
Digital shift register aligns sub-conversion results in time

Digital output is taken as weighted sum of stage bits
Latency
[Analog Devices, AD9226 Data Sheet]

Pipeline ADC Characteristics
Number of components grows linearly with resolution

Unlike flash ADC, where components ~ 2B
Pipeline ADC trades latency for conversion speed
Throughput limited by speed of one stage
Enables high-speed operation
Latency can be an issue in some applications
E.g. in feedback control loops
Pipelining only possible with good analog "memory elements"
Calls for implementation in CMOS using switched-capacitor
circuits
Stage Analysis
Ignore timing/clock delays for simplicity
D = Q(Vin ) Vres = G [Vin Vdac ]

Unity Gain Quantizer Model
1 1 2
LSB =
2 2 2B
Stage Model with Ideal DAC
D = Vin + q Vres = G q
Residue of pipeline stage (Vres) is equal to (-gain) times sub-

ADC quantization error

"Residue Plot" (2-bit Sub-ADC)
{-3/4, -1/4, 1/4, 3/4}
Sub-ADC
Decision
Levels
Pipeline Decomposition
Often convenient to look at pipeline as single stage plus

backend ADC

Resulting Model
in res
1
qb
out b
G qb
Dout = Vin + q 1 +
Gd Gd
With Gd=G
Canonical Extension
G q 2 G2 q( n 1) G( n 1) qn
Dout = Vin + q1 1 1 + 1 + ... + n 2 1 + n 1
Gd 1 Gd 1 Gd 2 Gd( n 1)
G
dj
G dj
j =1 j =1
First stage has most stringent precision requirements
Note that above model assumes that all stages use same reference
voltage (same full scale range)
This is true for most designs, one exception is [Limotyrakis 2005]
General Result Ideal Pipeline ADC
With ideal DACs and ideal digital weights (Gdj=Gj)
qn n 1
Dout = Vin + n 1 BADC = Bn + log 2G j
j =1
G j
j =1
The only error in Dout is that of last quantizer, divided by

aggregate gain
Aggregate ADC resolution is independent of sub-ADC
resolutions in stage 1...n-1 (!)
Makes sense to define "effective" resolution of jth stage as
Rj=log2(Gj)
Questions
How to pick stage gain G for a given sub-ADC resolution?

Impact and compensation of nonidealities?
Sub-ADC errors
Amplifier offset
Amplifier gain error
Sub-DAC error
Begin to explore these questions using a simple example
First stage with 2-bit sub-ADC, followed by 2-bit backend

Upper Bound for Stage Gain
Vin Vres
G1
G
-
qb
D Db
q
{-1/2 1/2B}
B
+1
G/2B
Vres 2G/2B 2
-G/2B
-1
-1 0 +1
qb
Vin
qb
Dout = Vin + Grows out of LSB bounds for G>2B
G
Issue with G=2B

in res
1
qb
b
q
B B
Overrange!
res
qb
in
Any error in sub-ADC decision levels will overload backend ADC and
thereby deteriorate ADC transfer function

Idea #1: G slightly less than 2B
Effective stage resolution can be non-integer (R=log2G)

E.g. R = log23.2 = 1.68 bits
See e.g. [Karanicolas 1993]
Idea #2: G < 2B, but Power of Two
Effective stage resolution is an integer

E.g. R = log22 = 1 = B-1
Digital hardware requires only a few adders, no need to
implement fractional weights (see appendix)
See e.g. [Mehr 2000]

Idea #3: G=2B, Extended Backend Range
No redundancy in stage with errors

Extra decision levels in succeeding stage used to bring
residue "back into the box"
See e.g. [Opris 1998]
Variant of Idea #2: "1.5-bit stage"
Sub-ADC decision levels placed to minimize comparator count

Can accommodate errors up to
B = log2(2+1) = 1.589 (sub-ADC resolution)
R = log22 = 1 (effective stage resolution)
See e.g. [Lewis 1992]

Summary on Sub-ADC Redundancy
We can tolerate sub-ADC errors as long as
The residue stays "inside the box", or
Another stage downstream returns the residue "into the box"
before it reaches last quantizer
This result applies to any stage in an n-stage pipeline
Can always decompose pipeline into single stage + backend
ADC
In literature, sub-ADC redundancy schemes are often called
"digital correction" a misnomer in my opinion
There is no explicit error correction!
Sub-ADC errors are absorbed in the same way as their
inherent quantization error
As long as there is no overranging
Amplifier Offset
Push
Amplifier offset can be referred toward stage input and results in

Global offset
Usually no problem, unless "absolute ADC accuracy" is required
Sub-ADC offset
Easily accommodated through redundancy

Gain Errors
G + qn
Dout = Vin + q1 1 1 + ... + n 1
Gd 1
G dj
j =1
Want to make Gd1 = G1+
Digital Gain Calibration (1)

Error in analog gain is not a problem as long as "digital gain
term" is adjusted appropriately
Problem
Need to measure analog gain precisely
Example
Digital calibration of a 1-bit first stage with 1-bit redundancy
(R=1, B=2)
Note
Even if all Gdj are perfectly adjusted to reflect the analog gains, the ADC will have non-
zero DNL and INL, bounded by 0.5LSB. This can be explained by the fact that the
residue transitions may not correspond to integer multiples of the backend-LSB. This
can cause non-uniformity in the ADC transfer function (DNL, INL) and also non-
monotonicity (see [Markus, 2005]).
In case this cannot be tolerated
Add redundant bits to ADC backend (after combining all bits, final result can be truncated back)
Calibrate analog gain terms

Vres = G [Vin Vdac ]
Db = Vres + qb
Step1:
Db( 1) = G [Vin + 0.25] + (qb
1)
Step2: Db( 2 ) = G [Vin 0.25] + (qb

2)
Db( 1) Db( 2 ) = 0.5 G + (qb

1)
(qb
2)
Can minimize impact of quantization error using

Averaging (thermal noise dither)
Extra backend resolution

DAC Calibration
Essentially same concept as gain calibration

Step through DAC codes and use backend to measure errors
Store coefficients for each DAC transition in a look-up table
Recursive Stage Calibration
First few stages have most stringent accuracy requirements

Errors of later stages are attenuated by aggregate gain
Commonly used algorithm [Karanicolas 1993]
Take ADC offline
Measure least significant stage that needs calibration first
Move to next significant stage and continue toward stage 1

Calibration Hardware Example
[Chuang 2002]
Alternative Schemes
Other foreground calibration schemes

Calibrate ADC starting from first stage [Singer 2000]
Connect stages in a circular loop [Soenen 1995]
Background calibration
See e.g. [Ming 2001]
Makes sense primarily when calibration parameters are
expected to drift
Capacitor ratios do not drift!
Background calibration is justifiable e.g. when drift in OTA
open-loop gain is an issue

Nonlinearity Compensation with
Background Calibration
[Murmann 2003]
Combining the Bits (1)

Example1: Three 2-bit stages, no redundancy
1 1
Dout = D1 + D2 + D3
4 16

D1 XX
D2 XX Only bit shifts
D3 XX No arithmetic circuits needed
------------
Dout DDDDDD
Example2: Three 2-bit stages, one bit redundancy in stages 1

and 2 (6-bit aggregate ADC resolution)
B1=3 B2=3 B3=2

R1=2 R2=2
Vin Stage 1 Stage 2 Stage 3
8 Wires
???
6 Wires
Dout[5:0]

D1 XXX Bits overlap
1 1 D2 XXX
Dout = D1 + D2 + D3 Need adders (Still, no
4 16 D3 XX
good reason for calling
------------
this "digital correction"...)
Dout DDDDDD
For fractional weights (e.g. radix <2), there is no need to

implement complex multipliers
Can still use simple bit shifts; push actual multiplication into low-
resolution output
E.g. a 1x10 bit multiplication needs only one adder
See e.g. [Karanicolas 1993]

Outline
Background
History and state-of the art performance
General idea of multi-step A/D conversion
Pipeline ADC basics
Ideal block diagram and operation, impact of block
nonidealities
Ways to deal with nonidealities
Redundancy, calibration
CMOS implementation details
Stage scaling, MDAC design
Architectural options
OTA sharing, SHA-less front-end
Research topics
Stage Implementation
Flash ADC "MDAC"

Switched-
Capacitor
Circuit

Generic Circuit
1: Q = Vin kCs
2 : Q = Vres Cf + Vrefp mCs + Vrefn ( k m ) Cs
Vres =
kCs
Vin
mCs
Vrefp +
( k m ) Cs V
refn
Cf Cf Cf
= G ( Vin Vdac )
Endless List of Design Parameters

Stage resolution, stage scaling factor
Stage redundancy
Thermal noise/quantization noise ratio
OTA architecture
OTA sharing?
Switch topologies
Comparator architecture
Front-end SHA vs. SHA-less design
Calibration approach (if needed)
Time interleaving?
Technology and technology options (e.g. capacitors)
A very complex optimization problem!

Thermal Noise Considerations
Total input referred noise

Thermal noise + quantization noise
Costly to make thermal noise smaller than quantization noise
Example: VFS=1V, 10-bit ADC
Nquant=LSB2/12=(1V/210)2/12=(280Vrms)2
Design for total input referred thermal noise ~280Vrms or
larger, if SNR target allows
Total input referred thermal noise is the sum of noise in all
stages
How should we distribute the total thermal noise budget
among the stages?
Let's look at an example
Stage Scaling (1)
Example: Pipeline using 1-bit (effective) stages (G=2)
Total input referred noise power
1 1 1
Ntot kT + + + ...
C1 4C2 16C3

Stage Scaling (2)
C1/2 C2/2 C3/2
C1 C2 C3
Vin Gm Gm Gm
1 1 1
Ntot kT + + + ...
C1 4C2 16C3
If we make all caps the same size, backend stages contribute

very little noise
Wasteful, because Power ~ Gm ~ C
Stage Scaling (3)

C1/2 C2/2 C3/2
C1 C2 C3
Vin Gm Gm Gm
1 1 1
Ntot kT + + + ...
C1 4C2 16C3
How about scaling caps down by 22=4x per stage?

Same amount of noise from every stage
All stages contribute significant noise
Noise from first few stages must be reduced
Power ~ Gm ~ C goes up!

Stage Scaling (4)
[Cline 1996]
Optimum capacitior scaling lies approximately midway between

these two extremes
Shallow Optimum
[Chiu 2004]
Capacitor scaling factor = 2Rx x=1 scaling exactly by stage gain

Practical Approach to Stage Scaling
Start by assuming caps are scaled precisely by stage gain

E.g. for 1-bit effective stages:
C/2 C/4 C/8
C C/2 C/4
Vin Gm Gm Gm
Refine using first pass circuit information & Excel spreadsheet

Use estimates of OTA power, parasitics, minimum feasible
sampling capacitance etc.
Or, buy a circuit optimization tool
Stage Scaling Examples (1)
[Cline 1996]

Stage Scaling Examples (2)
[Ishii 2005]
How Many Bits Per Stage?
Low per-stage resolution (e.g. 1-bit effective)

Need many stages
+ OTAs have small closed loop gain, large feedback factor
High speed
High per-stage resolution (e.g. 3-bit effective)
+ Fewer stages
OTAs can be power hungry, especially at high speed
Significant loading from flash-ADC
Qualitative conclusion
Use low per-stage resolution for very high speed designs
Try higher resolution stages when power efficiency is most
important constraint

Power Tradeoff is Fairly Flat!
[Chiu 2004]
= parasitic cap at output/total

sampling cap in each stage
(junctions, wires, switches, )
ADC power varies by only ~2x across different stage resolutions!
Examples
Reference [Yoshioka, 2007] [Jeon, 2007] [Loloee 2002] [Bogner 2006]
Technology 90nm 90nm 0.18um 0.13um
Bits 10 10 12 14
Bits/Stage 1-1-1-1-1-1-1-3 2-2-2-4 1-1-1-1-1-1-1-1-1-1-2 3-3-2-2-4
SNDR [dB] ~56 ~54 ~65 ~64
Speed [MS/s] 80 30 80 100
Power [mW] 13.3 4.7 260 224
mW/MS/s 0.17 0.16 3.25 2.24
Low power is possible for a wide range of architectures!

Re-Cap
Choosing the "optimum" per-stage resolution and stage scaling
scheme is a non-trivial task
But optima are shallow!
Quality of transistor level design and optimization is at least as
important (if not more important than) architectural
optimization
Next, look at circuit design details
Assume we're trying to build a 10-bit pipeline
Recent technology, feature size ~0.18m or smaller
Moderate to high-speed ~100MS/s
1-bit effective/stage, using "1.5-bit" stage topology
Dedicated front-end SHA
1.5-Bit Stage Implementation
[Abo 1999] ([Lewis 1992])
Cf is used as sampling cap during acquisition phase, as

feedback cap in redistribution phase
Helps improve feedback factor (max. 1/3 max. 1/2)

Residue Plot
[Abo 1999]
Stage 1 Matching Requirements
Cs C
1+
Cf C
Error in residue transition must be accurate to within a fraction of

9-bit backend LSB
Typically want C/C ~0.1% or better

Capacitor Matching
0.1% "easily" achievable in current technologies
Even with metal sandwich caps, see e.g. [Verma 2006]
Beware of metal density related issues, "copper dishing"
For MIMCap matching data see e.g. [Diaz 2003]
What if we needed much higher resolution than 10 bits?
Digital calibration
Multi-bit first stage
Each extra bit resolved in the first stage alleviates precision
requirements on residue transition by 2x
For fixed capacitor matching, can show that each (effective) bit
moved into the first stage
Improves DNL by 2x
Improves INL by sqrt(2)x
Multi-bit examples: [Singer 1996] [Kelly 2001] [Lee 2007]
Typical Reference Generator
[Brooks 1994]
External decoupling caps provide dynamic currents

Low power reference buffer

Comparators
Can tolerate large offsets and large noise with appropriate

redundancy
Consume negligible power in a good design
50-100W or less per comparator
Lots of implementation options
Resistive/capacitive reference generation
Different pre-amp/latch topologies

Comparator Examples
Vin
[Chiu 2004]
[Mehr 2000]

OTA Design Considerations
Static amplifier error = 1/(DC Loop Gain)
E.g. for 0.1% accuracy in first stage of 10-bit ADC, need loop
gain > 60dB
Dynamic settling error
Typically want to settle outputs to ~1/8 LSB accuracy within
1/2 clock cycle
Thermal noise
Size capacitors to satisfy kT/C noise requirement
Start by picking an OTA topology that will deliver sufficient gain
Or think about ways to compensate finite gain error
General references on OTA design

[Boser 2005], [Murmann, EE315A]
Two-Stage Folded Cascode OTA

1V
[Ishii 2005]
~0.5V
(1Vpp,diff)
Works down to VDD=1V with reasonable output swing

Gain ~ (gmro)3 ~ 103 = 60dB
Use gain boosting to achieve larger gain

How Fast Can We Go? (1)
Non-dominant pole in two-stage amplifier hard to move past fT/5
For 73 degrees phase margin (optimum for fast settling), loop
crossover frequency is 1/3 of non-dominant pole frequency
Settling linearly to 0.1% precision takes 7 loop time constants;
typically budget ~10 time constants
Ideally, we'd have 1/2 clock cycle to settle linearly, but there is
some time needed for slewing and non-overlap clock timing
Assume 60% of half cycle is available for linear settling
In summary
fT 1 1 f
fCLK ,max = 2 0.5 0.6 = T
5 3 10 80
How Fast Can We Go? (2)
NMOS fT
Technology fCLK,max = fT/80
(at moderate VGS-Vt ~150mV)
0.35um 10GHz 125 MHz
0.18um 30GHz 375 MHz
90nm 90GHz 1.125GHz (?)
Sampling speeds of 200-300MHz are "easily" achievable in

today's technologies
fT is no longer a showstopper
Speed ultimately constrained by power, power efficiency
and/or clock jitter

Switches
[Ishii 2005]
Make switch RC ~ 10 times
faster than OTA
Avoids speed degradation
Minimizes switch noise
contribution
See e.g. [Schreier 2005]
Avoids stability issues due to
poles in feedback network
Three choices for switches
Single N or P device
Transmission gate
Bootstrapped NMOS
For high swing nodes that
require constant Ron
Front-End SHA
Need constant RON here to

minimize signal dependent
charge injection from S1N, S1P
Minimize S1P
Jitter! S1N
[Ishii 2005]

Total Integrated OTA Noise (1)
Cf
g m11 + g m 31
N1 = 1 + 2...4
g m1
Cs
g m 61
N2 = 1 + 2
Cc g m51
2 1 kT kT
Vod = 2 N1 + 2( N2 + 1)
Cc CLtot
ignore in first
Stage 1 Stage 2 cut design
Cf
= CLtot = CL + (1 ) Cf + Cparasitic
Cf + Cs + Cgs1
Total Integrated OTA Noise (2)
Assuming =1, N1=N2=2
2 1 kT kT
Vod =4 +6
Cc CLtot
OTA noise partitioning problem

How should we split noise between stage1 and stage2
terms?
In this design example we'll use a 2/3, 1/3 split
This is yet another design/optimization parameter
With this assumption, we have
2 kT CLtot
Vod = 18 Cc =
CLtot 3

Stage 1 Noise
Cs2
Cs1=C1P+C2P
Cs1 / 2 1 2 kT
= Vod ,1 = 18
Cs1 + Cgs1 3 Cs 2 + Cs1 / 3
1C 18 kT
CLtot = Cs 2 + 1 s1 Vid2 ,1 = 2
3 2 2 Cs 2 + Cs1 / 3
SHA Noise
Cs 0 1
=
Cs 0 + Cgs1 2
Cs1
1C
CLtot = Cs1 + 1 s 0
2 2
Cs0 Design choice: Cs0 = Cs1
From sample phase (1)
2 2 kT kT kT
Vod ,0 = Vid ,0 = 18 + 16
Cs1 + Cs 0 / 4 Cs 0 Cs1

Noise Budgeting
Total input referred noise budget, assuming VFS,diff=1V
Nthermal = Nquant=LSB2/12=(1V/210)2/12=(280Vrms)2
Reasonable "first cut" partitioning of input referred noise
SHA 1/2
Stage 1 1/4
All remaining stages 1/4
kT 1 2
Vid2 ,0 = 16 = ( 280Vrms ) Cs1 = 1.66 pF
Cs1 2
9 kT 1 2
Vid2 ,1 = = ( 280Vrms ) Cs 2 = 0.38 pF
2 Cs 2 + Cs1 / 3 4
Capacitor Sizes
Cs0 1.66pF
Cs1 1.66pF
Cs2 0.38pF
/2
Cs3 190fF
/2
Cs4 85fF
Cs5 42.fF (minimum) /2

Cs10 42.fF (minimum)
Now refine these numbers using simulation and Excel spreadsheet

Iterate over assumptions/design choices to optimize design

Reality Check
[Honda 2007]
Not too far off from a practical design
Amplifier Sharing (1)
[Min 2003]
Limited power savings

because amplifiers have
different specs

Amplifier Sharing (2)
[Kurose 2006]
Sharing of amplifiers is most efficiently done in a pair of

converters that process I/Q signals
SHA-Less Architectures (1)

Motivation
SHA can burn up to 1/3 of total ADC power
Removing front-end SHA creates acquisition timing mismatch
issue between first stage MDAC & Flash
Sampler
(MDAC)
[Chiu 2004]

SHA-Less Architectures (2)
Strategies
Use first stage with large redundancy; this can help absorb
fairly large skew errors
Try to match sampling sub-ADC/MDAC networks
Bandwidth and clock timing
[Mehr 2000]
Pipelined SAR
[Lee, JSSC, April 2011]

Pipeline Cyclic ADC (1)
x

- - -
b0 b1 b2 b3
1 -1 -2 -3
Output x
Pipeline Cyclic ADC (2)

x -
Register
b0 b1 b2 b3
-1 -2 -3
1
Output x

Implementation Example
1 C
Vo1 = 1 + 5 Vo 2
Vo1 C6
[Erdogan et al. JSSC 12/99]

2
Vo2
(
Vo 2 = Vip Vref ) CC4
3
Discussion
Advantages
Area efficient
Typically only one or two switched capacitor stages plus
comparator
Easy to calibrate
Need to measure only one coefficient (capacitor ratio)
Disadvantages
Slow
Need many clock cycles for a single conversion
Sub-optimal power efficiency
Cannot scale stages like in a pipeline ADC
Noise and accuracy requirements decrease from MSB to LSB
cycle, but invested circuit energy per cycle is (usually) constant

General
S. Kawahito, "Low-Power Design of Pipeline A/D Converters," Proc. CICC, pp.
505-512, Sep. 2006.
Redundancy & Calibration
S. H. Lewis et al., "A 10-b 20-Msample/s analog-to-digital converter," IEEE
JSSC, pp. 351-358, Mar. 1992.
A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline
ADC," IEEE J. Of Solid-State Circuits, pp. 1207-1215, Dec. 1993.
E. G. Soenen et al., "An architecture and an algorithm for fully digital correction
of monolithic pipelined ADCs," IEEE TCAS II, pp. 143-153, Mar. 1995.
I. E. Opris et al., "A single-ended 12-bit 20 MSample/s self-calibrating pipeline
A/D converter," IEEE JSSC, pp. 1898-1903, Dec. 1998.
L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120
MHz," ISSCC Dig. Techn. Papers, pp. 38-39, Feb. 2000.
I. Mehr et al., "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE
JSSC, pp. 318-325, Mar. 2000.
J. Ming et al., "An 8-bit 80-Msample/s pipelined analog-to-digital converter with
background calibration," IEEE JSSC, pp. 1489-1497, Oct. 2001.
S.-Y. Chuang et al., "A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined
A/D Converter," IEEE JSSC, pp. 674-683, Jun. 2002.
J. Markus et al., "On the monotonicity and linearity of ideal radix-based A/D
converters," IEEE Trans. Instr. and Measurement, pp. 2454-2457, Dec. 2005.

Implementation
T. Cho, "Low-Power Low-Voltage Analog-to-Digital Conversion Techniques
using Pipelined Architecures, PhD Dissertation, UC Berkeley, 1995,
http://kabuki.eecs.berkeley.edu/~tcho/Thesis1.pdf.
L. A. Singer at al., "A 14-bit 10-MHz calibration-free CMOS pipelined A/D
converter," VLSI Circuit Symposium, pp. 94-95, Jun. 1996.
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits,"
PhD Dissertation, UC Berkeley, 1999,
http://kabuki.eecs.berkeley.edu/~abo/abothesis.pdf.
D. Kelly et al., "A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at
Nyquist," ISSCC Dig. Techn. Papers, pp. 134-135, Feb. 2001.
A. Loloee, et. al, A 12b 80-MSs Pipelined ADC Core with 190 mW
Consumption from 3 V in 0.18-um, Digital CMOS, Proc. ESSCIRC, pp.
467-469, 2002
B.-M. Min et al., "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,"
IEEE JSSC, pp. 2031-2039, Dec. 2003.
Y. Chiu, et al., "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB
SFDR, IEEE JSSC, pp. 2139-2151, Dec. 2004.
S. Limotyrakis et al., "A 150-MS/s 8-b 71-mW CMOS time-interleaved
ADC," IEEE JSSC, pp. 1057-1067, May 2005.
T. N. Andersen et al., "A Cost-Efficient High-Speed 12-bit Pipeline ADC in
0.18-um Digital CMOS," IEEE JSSC, pp. 1506-1513, Jul 2005.

P. Bogner et al., "A 14b 100MS/s digitally self-calibrated pipelined ADC in
0.13um CMOS," ISSCC Dig. Techn. Papers, pp. 832-833, Feb. 2006.
D. Kurose et al., "55-mW 200-MSPS 10-bit Pipeline ADCs for Wireless
Receivers," IEEE JSSC, pp. 1589-1595, Jul. 2006.
S. Bardsley et al., "A 100-dB SFDR 80-MSPS 14-Bit 0.35um BiCMOS
Pipeline ADC," IEEE JSSC, pp. 2144-2153, Sep. 2006.
A. M. A. Ali et al, "A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With
100 dB SFDR and 50 fs Jitter," IEEE JSSC, pp. 1846-1855, Aug. 2006.
S. K. Gupta, "A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power
Realized by a High Bandwidth Scalable Time-Interleaved Architecture,"
IEEE JSSC, 2650-2657, Dec. 2006.
M. Yoshioka et al., "A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with
Regulated Overdrive Voltage Biasing," ISSCC Dig. Techn. Papers, pp. 452-
453, Feb. 2007.
Y.-D. Jeon et al., "A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a
Front-End S/H in 90nm CMOS," ISSCC Dig. Techn. Papers, pp. 456-457,
Feb. 2007.
K.-H. Lee et al., "Calibration-free 14b 70MS/s 0.13um CMOS pipeline A/D
converters based on highmatching 3D symmetric capacitors," Electronics
Letters, pp. 35-36, Mar. 15, 2007.
K. Honda et al., "A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline
A/D Converter Using Capacitance Coupling Techniques," IEEE JSSC, pp.
757-765, Apr. 2007.

Per-Stage Resolution and Stage Scaling
D. W. Cline, "Noise, Speed, and Power Tradeoffs in Pipelined Analog to
Digital Converters", PhD Dissertation, UC Berkeley, November, 1995,
http://kabuki.eecs.berkeley.edu/~cline/thesis/thesis.pdf.
D. W. Cline et al., "A power optimized 13-b 5 MSamples/s pipelined analog-
to-digital converter in 1.2um CMOS," IEEE JSSC, Mar. 1996
Y. Chiu, "High-Performance Pipeline A/D Converter Design in Deep-
Submicron CMOS," PhD Dissertation, UC Berkeley, 2004.
H. Ishii et al., "A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS,"
Proc. CICC, pp. 395-398, Sep. 2005.
OTA Design, Noise
B. E. Boser, "Analog Circuit Design with Submicron Transistors,"
Presentation at IEEE Santa Clara Valley, May 19, 2005,
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
R. Schreier et al., "Design-oriented estimation of thermal noise in switched-
capacitor circuits," IEEE TCAS I, pp. 2358-2368, Nov. 2005.
B. Murmann, "Thermal Noise in Track-and-Hold Circuits: Analysis and
Simulation Techniques," IEEE Solid-State Circuits Magazine, vol.4, no.2,
pp. 46-54, June 2012.

Capacitor Matching Data
C. H. Diaz et al., "CMOS technology for MS/RF SoC," IEEE Trans. Electron
Devices, pp. 557-566, Mar. 2003.
A. Verma et al., "Frequency-Based Measurement of Mismatches Between
Small Capacitors," Proc. CICC, pp. 481-484, Sep. 2006.
V. Tripathi and B. Murmann, "Mismatch Characterization of Small Metal
Fringe Capacitors," CICC 2013.
Reference Generator
T. L. Brooks et al., "A low-power differential CMOS bandgap reference,"
ISSCC Dig. Techn. Papers, pp. 248-249, Feb. 1994.

Time Interleaving
Boris Murmann
Stanford University
Time-Interleaved ADC
M times increased throughput!
[Ken Poulton]
M
[W. Black and D. Hodges, JSSC, Dec. 1980]

Typical Timing
Sampling
clocks of each
ADC
Each ADC samples for 1/Mth of the period

Still need very high acquisition bandwidth in each ADC slice
No free lunch
Why Time Interleaving?
70
TI SAR
TI Pipeline
60
TI Flash
Other
50
SNDRHF [dB]
40
30
20
10 8 9 10 11
10 10 10 10
Sampling Rate [Hz]

How Many Channels?
[El-Chammas, PhD Thesis, Stanford University, 2010]
Feasible
Solutions Secondary factors
dominate the power
(e.g. flash resistor ladder)
Shallow power minimum
A complex optimization problem!

Luckily, first order analyses show that the optimum is shallow
Time Interleaving Errors
0
o0
G0 ADC0
Ts+1
o1
G1 ADC1
x(t) y[n]
(N-1)Ts+N-1
oN-1
GN-1 ADCN-1
Timing Skew
Gain Offset

Offset Errors
[Ken Poulton]
Signal independent noise pattern
Impact of Offset Errors
[Gustavsson, p.262]
OS/FS
E.g. FS=1V, OS=1mV ENOB~9bits!

Gain Errors
[Ken Poulton]
Very similar to amplitude modulation
Impact of Gain Errors
[Gustavsson, p.266]
Gain
E.g. Gain=0.1% ENOB~10bits

Timing Errors
Very similar to PM, jitter
[Ken Poulton]
Can be analyzed like jitter, using curvature of signal

autocorrelation (see earlier discussion)
Only difference is that a factor of N/N-1 shows up, since only
N-1 channels are skewed
See [El-Chammas & Murmann, IEEE TCAS 5/2009]
Impact of Timing Errors
[Gustavsson, p.267]
Above chart is for M=4 channels

E.g. fin=100MHz, phase skew=3ps ENOB~9bits!

Compensation of Interleaving Errors
Gain and offset
Several relatively simple techniques exist
Can compensate in analog and/or digital domain
Timing skew
Much more difficult to handle, fully digital compensation
often too complex for practical designs
Popular solutions
Measure errors in digital domain, compensate via
adjustable delay lines typically incur a jitter penalty
Measure errors in digital domain, compensate by
skewing equalizer taps
See overview paper by B. Razavi, CICC 2012
Digital Detection and Correction
y0[n]
ADC0 Correction ~y0[n]
Digital Backend
x(t) Detection
ADC1 Correction ~y1[n]

y1[n]
Sub-ADC Digitally corrected

output sub-ADC output

Digital Detection and Analog Correction
Foreground vs. Background

Calibration
Foreground Calibration
Background Calibration

Example: Fully Digital Gain Error
Background Cal
[Tsai, TCAS1, 2/2009]
A similar approach can be used for digital offset

compensation
Example: Foreground Analog Gain &

Offset Cal
vga comp
gain offset offset
cntrl cntrl cntrl
5-bit
8-bit Interleave 0
C Calibration
Calibration
Decoder
Logic
DAC
G2(0)
6
63
comp
G1(0)
Flash
other
Coarse
interleave
(not shown) nonlinearity
compensation
[Verma, ISSCC 2013] in G2(0)

Sources of Timing Skew
Clock Generator
All traces and all transistors have mismatch, which can easily
result in ~10ps total timing skew for a complex clock tree
[A. Agarwal, CICC 2008]
Minimizing Skew by Design
[Louwsma, JSSC 4/2008]
Global CML master clock times the sampling instants; local phase
gating for each ADC
Skew ~0.5ps (!)

Hiding the Timing Skew Using a Global T/H
Typically not feasible in ultra-high-speed converters

Successfully used in moderately high-speed designs
S. Gupta et al., A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW
Power Realized by a High Bandwidth Scalable Time-Interleaved
Architecture , JSSC 12/2006.
B. Setterberg et al., A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC
with Background Calibration and Digital Dynamic Linearity
Correction, ISSCC 2013.
Global Bottom Plate Sampling
[Gustavsson, TCAS1, 9/2000]
Big issue: parasitics

at node X

Better: Local Re-Timing & Fine Tuning
3.5ps tuning range, 250fs steps
[Kull, VLSI 2013]
Typical Delay Cell
Causes a penalty in supply induced

jitter manageable if delay range is
small
K. Poulton et al., A 4GSample/s 8b ADC in 0.35um CMOS, ISSCC 2002

Delay Control via Varactor DAC
Encoder
Control Bits
Measuring the Skew Using Aux ADC
Auxiliary ADC
[El-Chammas, VLSI 2010]

..
MUX
...

Clocking the Aux ADC
1
t
2
t
3
t
CAL
t
1
3
Period of CAL is e.g. 17/8 period of 1 - 8
Blind Estimation of the Skew
[Haftbaradaran, CICC 2007]
Assuming well-behaved input signal statistics, it also possible to

detect the skew blindly
Key idea: pairwise signal correlations along the array must be
equal, unless there is skew
System-Level Absorption of Skew
[Tsai, TCAS1, 2/2009]
Split equalizer into M paths and adapt coefficients separately

For complex equalizers typically found in ADC-based links, one
must carefully evaluate if the power overhead is justifiable
Can also combine this idea with analog time skew control
Hierarchical Interleaving
[Doris, JSSC 12/2011]

Quadrature Clocking
[Doris, JSSC 12/2011]
Hierarchical interleaving with 4x split in first rank

Drive the samplers directly with QVCO signal
Low jitter, small phase skew (need only small tuning range, if any)
Examples (1)
[Greshishchev, ISSCC 2010]
160 SAR ADCs interleaved to resolve 6 bits at 40GS/s (!)

Examples (2)
[Kull, VLSI 2013]
8 Interleaved SARs,
each running at
1.1GS/s
8.8GS/s, 50mW
Examples (2)
[El-Chammas & Murmann, VLSI 2010]
8x Interleaved 5-bit Flash

12GS/s, 81mW
65nm CMOS

Examples (3)
[Setterberg, ISSCC 2013]
14b, 2.5 GS/s ADC, 80-dB linear up to 1 GHz input

Employs 2 million logic gates for digital correction
Power dissipation = 24 Watts
Examples (4)
[Danesh, VLSI 2011]
128 single slope ADCs interleaved to resolve 7 bits at 1GS/s

Power efficient (~26mW)

Oversampling ADCs and DACs
Boris Murmann
Stanford University
Overview
Oversampling A/D conversion

Decimation filters
Oversampling D/A conversion

Recap
Sampling theorem
fs > 2fsig ,max
One good reason for sampling faster ("oversampling")

Can use lower order anti-alias filter
Anti-Alias Filtering

Quantization Noise
Ne(f)
2/12
fB fs/2
Recall that the "noise" introduced by quantizer is evenly

distributed across all frequencies
Provided that quantization error sequence is "sufficiently
random"
Idea: Let's filter out the noise beyond f=fB!
Digital Noise Filter (1)
f B 2 2

f s / 2 12 12
Total quantization noise at digital output is reduced proportional

to "oversampling ratio" M=(fs/2)/fB

Digital Noise Filter (2)
Increasing M by 2x, means 3-dB reduction in quantization noise
power, and thus 1/2 bit increase in resolution
"1/2 bit per octave"
Is this useful?
Reality check
Want 16-bit ADC, fB=1MHz
Use oversampled 8-bit ADC with digital lowpass filter
8-bit increase in resolution necessitates oversampling by 16
octaves
fs 2 fB M = 2 1MHz 216
131GHz
Noise Shaping
Idea: "Somehow" build an ADC that has most of its quantization

noise at high frequencies
Key: Feedback

Noise Shaping Using Feedback (1)
Y ( z ) = E ( z ) + A ( z ) X ( z ) A ( z )Y ( z )
1 A(z)
= E (z) + X (z)
1+ A ( z ) 1+ A ( z )
= E ( z ) HE ( z ) + X ( z ) H X ( z )
123 123
Noise Signal
Transfer Transfer
Function Function
Noise Shaping Using Feedback (2)
1 A(z)
Y (z) = E (z) + X (z)
1+ A ( z ) 1+ A ( z )
1424 3 1424 3
Noise Signal
Transfer Transfer
Function Function
Objective
Want to make STF unity in the signal frequency band
Want to make NTF "small" in the signal frequency band
If the frequency band of interest is around DC (0fB) we
achieve this by making |A(z)| >>1 at low frequencies
Means that NTF is <<1
Mans that STF 1

Discrete Time Integrator
v ( k ) = u ( k 1) + v ( k 1) V ( z ) = z 1U ( z ) + z 1V ( z )
V (z) z 1 1
= 1
= z = e j T
U (z) 1 z z 1
"Infinite gain" at DC (=0, z=1)
First Order Delta-Sigma Modulator
E(z)
X(z) z-1 Y(z)
+ +
- 1-z-1
DAC
1
1
Y (z) = E (z)
1 1 (
+ X ( z ) z 1 = E ( z ) 1 z 1 + X ( z ) z 1 )
1+ 1+
z 1 z 1
Output is equal to delayed input plus filtered quantization noise

NTF Frequency Domain Analysis
He ( z ) = 1 z 1
e j T / 2 e j T / 2
( )
He ( j ) = 1 e j T = 2e j T / 2
2

T T
j T T j
= 2e 2
j sin = 2 sin e
2
2 2
f
He ( f ) = 2 sin ( fT ) = 2 sin
fs
"First order noise Shaping"

Quantization noise is attenuated at low frequencies, amplified at
high frequencies
In-Band Quantization Noise (1)

Question: If we had an ideal digital lowpass, what would be the
achieved SQNR as a function of oversampling ratio?
Can integrate shaped quantization noise spectrum up to fB and
compare to full-scale signal
fB 2
2 2 f
Pqnoise = 2 sin
12 fs fs
df

0
fB 2
2 2 f

12 fs
2 df
fs
0
3
2 2 2fB 2 2 1
=
12 3 fs 12 3 M 3

In-Band Quantization Noise (2)
Assuming a full-scale sinusoidal signal, we have

2
B
( )
1 2 1
Psig 2 2
= 1.5 2B 1 2 3 M 3
SQNR
Pqnoise
= 2
1 2 ( 2
4
)
1 24 3
12 3 M 3 Due to noise
shaping &
digital filter
1.76 + 6.02B 5.2 + 30 log( M ) [dB ] (for large B)
Each 2x increase in M results in 8x SQNR improvement

9dB (1.5bits) per octave oversampling
SQNR Improvement
Example revisited
Want 16-bit ADC, fB=1MHz
Use oversampled 8-bit ADC, first order noise shaping and
(ideal) digital lowpass filter
SQNR improvement compared to case without oversampling is
-5.2dB+30log(M)
8-bit increase in resolution (48dB SQNR improvement)
would necessitate M60
Not all that bad!
M SQNR improvement
16 31dB (~5 bits)
256 67dB (~11 bits)
1024 85dB (~14 bits)

DAC Requirements
1 A(z)
Y (z) = E (z) + X ( z ) DAC ( z )
1+ A ( z ) 1+ A ( z )
DAC error is indistinguishable from signal

Means that DAC must be precise to within target resolution
For the previous example, this means that we need an 8-bit
DAC whose output levels have 16-bit precision
Solutions
Trimming or calibration
Measure DAC levels during test or at power-up
Apply correction values to each level using auxiliary DAC
Dynamic Element Matching Algorithms
Shuffle DAC unit elements to obtain fairly precise "average"
output levels
Two ways
Data independent shuffling
Data dependent shuffling
Data dependent shuffling algorithms allow to push most of
the DAC "noise" outside the signal band
See e.g. [Carley, JSSC 4/1989], [Galton, TCAS II 10/1997],
[Vleugels, JSSC 12/2001]
Single bit DAC

Data Independent Shuffling (1)
Carley, L.R., "A noise-shaping coder topology for 15+ bit converters,"
IEEE JSSC, vol.24, no.2, pp.267-273, Apr. 1989.
Data Independent Shuffling (2)
Carley, L.R., "A noise-shaping

coder topology for 15+ bit
converters," IEEE JSSC, vol.24,
no.2, pp.267-273, Apr. 1989.

Data Dependent Shuffling (1)
Select elements such that

each one is used (on Code 3
average) the same number
of times
DAC errors quickly sum to
zero; errors are pushed to Code 4
high frequencies
R.T. Baird, and T.S. Fiez, "Improved

DAC linearity using data weighted Code 2
averaging ," IEEE ISCAS, pp.13-16,
May 1995.
Data Dependent Shuffling (2)

Single-Bit DAC
A single bit DAC has only two output levels

Even if these two levels are imprecise, the errors will only affect
gain and offset of the DAC and modulator
Tolerable in many applications
Modulator with Single-Bit Quantizer (1)

Model
1-bit
code
Expected SQNR (from slide 15 with B=1)

2
1
Psig
= 2 2
2 2 9
SQNR = 2 M3
Pqnoise 1 2
3
12 3 M
= 3.4 + 30 log(M ) [dB ]
E.g. M=128 SQNR=60dB

Modulator with Single-Bit Quantizer (2)
Implementation example
[Schreier, p. 31]
Not all that great in terms of achievable SQNR, but sufficient for
some applications
E.g. digital voltmeter
See [van de Plassche, pp. 469]
Simulated Response

Spectrum
[Schreier, p. 39]
f/fs
Looks like there is some noise shaping, but SQNR=55dB is

lower than the expected 60dB
Amplitude and Frequency Dependence
[Schreier, p. 40]
[M=256]
Erratic dependence on amplitude and frequency

Simple linear model fails to predict this behavior
Issue: Quantization error sequence is not "sufficiently random",
as assumed in the beginning of this discussion

Quantization Error in 1st Order Modulator
0.5
Input x(n) 0
-0.5
0 200 400 600 800 1000
Quantization error e(n)
0.5
-0.5
0 200 400 600 800 1000
Sample index n
A complicated, but deterministic function of the input
Aside: Quantizer Gain

Another issue is that the gain of the single bit quantizer is ill-
defined, but we assumed it to be unity in our analysis
The actual quantizer gain can be found from simulations, and
then plugged back into the linear model for better agreement
(and stability analysis using root locus, etc.)
References
Schreier, Sections 3.2 and 4.2
S. Ardalan, and J. Paulos, "An analysis of nonlinear behavior
in delta - sigma modulators," IEEE TCAS, vol.34, no.6, pp.
593-603, June 1987.
T. Ritoniemi, T. Karema, and H. Tenhunen, "Design of stable
high order 1-bit sigma-delta modulators," Proc. IEEE ISCAS,
pp. 3267-3270, May 1990.

Tones
Since the quantization error is correlated with the input, the
shaped quantization noise contains spurious tones, some of
which lie in the signal band
The linear model cannot predict these tones
It is generally difficult to predict tonal behavior for arbitrary
inputs, even with a nonlinear model
Analytical results exist for DC and sine inputs, see e.g.
R.M. Gray "Spectral analysis of quantization noise in a single-
loop sigma-delta modulator with DC input," IEEE Trans.
Comm., pp. 588-599, June 1989.
R.M. Gray et al., Quantization noise in single-loop sigma-delta
modulation with sinusoidal inputs," IEEE Trans. Comm., pp.
956-968, Sept 1989.
Interesting and intuitive to look at DC input as a worst case
DC Input (1)
E.g. x(n)=0
Modulator generates an alternating sequence of 1s and 0s
Single tone at fs/2; no low frequency component
E.g. x(n)=0.001/2
Compared to previous example, only one in 1000 outputs
will change
Output has period of 1000T, and hence contains a low
frequency, in-band component

DC Input (2)
For a DC input, the modulator output consists of discrete tones
("idle tones") with power and frequency given by
2
sin ( fkT )
Pk =
k
x
fk = k DC + 0.5 fs

where k is an integer, and <r> represents the fractional part of r

(r modulo 1)
Strongest tones occur for small k, due to reciprocal dependence
The plot on the following slide shows the total mean square
error due to in-band idle tones as a function of DC input (M=16)
MSE due to Idle Tones
X/

Idle Tone Considerations
Idle tones are known to be a significant issue in audio applications
The human ear can detect tones ~20dB below the
thermal/quantization noise floor
If idle tones are an issue, there are several options for mitigating their
impact
Larger oversampling ratio
Multi-bit quantizer and DAC
Dither
Superimpose a pseudorandom signal at the quantizer input to "whiten"
quantization noise
See e.g. Chapter 3 of Delta-Sigma Data Converters by Norsworthy, Schreier & Temes.
Overdesign by making quantization noise much smaller than

electronic noise from integrators
Noisy integrator(s) help randomize quantization error sequence
Higher order modulators
Naturally produce "more random" quantization error sequences
Higher Order Modulators
Motivation: better SQNR for a given oversampling ratio, plus

improved idle tone performance as a side benefit
Commonly used architectures
Single quantizer loop with higher order filtering
Essentially a logical extension to the first order noise shaping
concept discussed previously
Cascaded, multi-stage modulators
Contain a separate quantizer in each stage

Higher Order Noise Shaping
Lth order noise transfer function
L
(
HE ( z ) = 1 z 1 )
In-Band Quantization Noise
fB 2L
2 2 f
Pqnoise = 2 sin
12 fs fs
df
0
fB 2L
2 2 f

12 fs
2
fs
df
0
2L +1
2 2L 2fB

12 2L + 1 fs
2L +1
2 2L 1

12 2L + 1 M
For an Lth order modulator, every doubling of M results in an

increase in SQNR of 6L+3dB (L+0.5bits)

SQNR with Single Bit Quantizer
SQNR [dB]
Building a Second-Order Modulator (1)
General idea: Start with a first order modulator and replace

quantizer by another first order loop
-1 -1
-1 -1

Building a Second-Order Modulator (2)
More general structure
E(z)
X(z) z z Y(z)
+ a1 + a2 +
- 1-z - 1-z
2
a a z 2
HX (z ) = 1 2 HE (z ) =
(1 z )
1
D (z) D (z)
2 a = a2 = 1 and b = 2
(
D( z ) = 1 z 1 ) ( )
+ a2bz 1 1 z 1 + a1a2 z 2 = 1 e.g. for 1
a1 = 0.5,a2 = 2 and b = 1
Boser-Wooley Modulator (1)

(Single-bit)
[Boser & Wooley, JSSC 12/1988]
a1=0.5 and b=1, but a2=0.5 (instead of 2)

Since the integrator is followed by a single-bit quantizer, a2 can
be scaled to reduce swing requirements in second integrator

Boser-Wooley Modulator (2)
Performance of 2nd Order Modulator
[Schreier, p.70]
Compared to first
order modulator,
SQNR is in "better"
agreement with
simple linear model
-20
-30 O
-40
O
O
1st order Improved idle tone
O
-50
X O performance
-60 O
X
-70
-80 X
-90 2nd order X

-100 X
-110
X
-120
8 16 32 64 128 256 512 1024
Oversampling Ratio

Single Quantizer Modulators with Order >2
Most general (mathematical) filter decomposition
1 L0 ( z )
He ( z ) = Hx ( z ) =
1 L1( z ) 1 L1( z )
Hx ( z ) 1
L0 ( z ) = L1( z ) = 1
He ( z ) He ( z )
Stability
Having more than two integrators in a feedback loop means that
the loop can be unstable (criterion = BIBO)
From the diagram of the previous slide, it is clear that the
stability of the loop mostly depends on L1(z), and therefore the
characteristics of the NTF
How about the nonlinear transfer characteristic of the quantizer?
Unfortunately, there is no crisp mathematical result that
would address this question for all possible configurations
One important, and general aspect of having a nonlinearity
in the loop is that the stability becomes dependent on the
signal (and also L0)!
In practice, designers rely on a combination of stability analyses
using the linear model (!), established heuristics, and time
domain simulations of the nonlinear model

Stability Heuristics
Single-bit
First order modulator is stable (bounded integrator output)
with arbitrary inputs of less than /2 in magnitude
Second order modulator is known to be stable with arbitrary
inputs of less than /20 in magnitude, and for "reasonable",
slow varying inputs of magnitude <0.8/2, integrator outputs
are "likely" to stay within bounds
Lee's criterion: modulator is "likely" to be stable if
max[He()]<1.5
Multi-bit
A modulator with Nth order differentiation using an N+1 bit
quantizer is stable for arbitrary inputs with amplitude less
than half the quantizer input range (Schreier, p. 104)

The Cost of Stability (Single-bit)
[Norsworthy, pp.156]
Max. Input [/2]
M=40, L=6
max[He()] max[He()]
Higher out of band gain means higher attenuation in the signal

band and hence better SQNR
Unfortunately modulator becomes "less stable"

Achievable SQNR
Diminishing return for order greater 5-6
Topology Example: Single Feedback Loop
1 A( z )
He ( z ) = Hx ( z ) = 1 in band of interest
1 + A( z ) 1 + A( z )

Topology Example: CIFB Architecture
[Schreier, p. 115]
Cascade of Integrators with Feedback

All zeros of NTF lie at DC for this structure, i.e. HE(z) = (1-z-1)N
Can create complex conjugate zeros by adding feedback paths
around pairs of integrators (cascade of resonators, CRFB
structure)
Typical Design Procedure

"Cookbook design"
See e.g. Delta-Sigma Data Converters, by Norsworthy,
Schreier & Temes, Sections 4.4 and 5.6
Choose order based on desired SQNR and M
Design NTF using filter approximations (e.g. Chebyshev2)
Make sure to obey Lee's criterion
Determine loop-filter transfer function and evaluate
performance and stability using simulations
Determine implementation-specific coefficients
Scale coefficients to restrict integrator outputs to stay within
available range (dynamic range scaling")
Delta-Sigma Toolbox for MATLAB (by Richard Schreier)
http://www.mathworks.com/matlabcentral/fileexchange
Look under "Controls" and find "Delsig" toolbox
"Cookbook" NTF Design Example (1)
% design parameters
L=4; % order
M=64; % oversampling ratio
% stop-band attenuation; reduce if needed to make max(|He(w)|<1.5)

Rstop = 80;
[b,a] = cheby2(L, Rstop, 1/M, 'high');
% normalize to make He(z->inf)=1; needed for realizability

% makes first sample of impulse response of He equal to 1
% makes first sample of impulse response of A equal to 0
% (must have at least one delay around quantizer)
b = b/b(1);
% check Lee's rule; want max(|He(w)|<1.5 )

NTF = filt(b, a, 1)
[mag] = bode(NTF, pi)

Transfer function:
1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4
------------------------------------------------------
1 - 3.247 z^-1 + 4.013 z^-2 - 2.231 z^-3 + 0.4699 z^-4
mag = 1.459
0
-20
He [dB]
-40
-60
-80
-100 -3 -2 -1
10 10 10
Frequency [f/f s]

% Loop filter transfer function
A = inv(NTF) - filt(1,1,1)
Transfer function:
0.7505 z^-1 - 1.982 z^-2 + 1.766 z^-3 - 0.5301 z^-4
---------------------------------------------------
1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4
% Check realizability
a = impulse(A);
a(1)
ans = 0
Commercial Example

Cascaded Modulators
Analog + Digital
x y DELAY
In Out

e
DIGITAL
x y DIFFERENCE
Concept
Cascade of two or more stable (low order) modulators
Quantization error of each stage is quantized by the
succeeding stages and subtracted in digital domain
Second Order (1-1) Cascade
Y1(z) = z1X(z) + (1 z1)E1(z)
Y2(z) = z1E1(z) + (1 z1)E2(z)
Y(z) = z1Y1(z) (1 z1)Y2(z)
= z2X(z) + z1(1 z1)E1(z) z1(1 z1)E1(z) (1 z1)2E2(z)
Y(z) = z2X(z) (1 z1)2E2(z)
Second order noise shaping using two first order loops!

Properties
Order of overall noise shaping is equal to sum of modulator
orders
No stability issues
Improved idle tone performance
Input of second stage is "noise like"
Remaining quantization error from second stage is very
close to white noise
Cancellation of first stage quantization noise depends on
matching between analog and digital signal paths
Hard to suppress first stage quantization error by more than
40dB
Mismatch will affect idle tone performance
1-1-1 Cascaded Modulator (MASH)
1
z-1
1
z-1
1
z-1

Mismatch Sensitivity
2-1 Cascade

Mismatch Sensitivity
Circuit Level Considerations

Finite OTA gain
Integrator leak
Dead zones
Nonlinearity
Electronic noise
OTA dynamic settling error, nonlinearity due to slewing
Capacitor voltage coefficients
Comparator hysteresis
Usually not a problem; simulations show that up to a few %
hysteresis can be tolerated
Unwanted mixing effects
E.g. if Vref contains fs/2, out of band noise will be mixed down
into signal band

Integrator Analysis (1)
t/Ts Qs QI
n-1 CsVi(n-1) CIVo(n-1)
n-1/2 0 CIVo(n-1/2) = CIVo(n-1) + CsVi(n-1)
n CsVi(n) CIVo(n) = CIVo(n-1) + CsVi(n-1)
n+1/2
Integrator Analysis (1)

Assuming that Vo is sampled during 1, we have
CIVo ( n ) = CIVo ( n 1) + CsVi ( n 1)
CIVo ( z ) = z 1CIVo ( z ) + z 1CsVi ( z )
Vo ( z ) Cs z 1
=
Vi ( z ) CI 1 z 1
Unfortunately, this ideal expression holds only for infinite

amplifier gain
Let's look at impact of finite gain

Finite Gain (1)
t/Ts Qs QI
n-1 CsVi(n-1) CIVo(n-1)[1+1/A]
n-1/2 CsVo(n-1/2)/A CIVo(n-1/2)[1+1/A] = CIVo(n-1)[1+1/A] +
CsVi(n-1) - CsVo(n-1/2)/A
n CsVi(n) CIVo(n)[1+1/A] = CIVo(n-1)[1+1/A] +
CsVi(n-1) - CsVo(n)/A
n+1/2
Finite Gain (2)

Again, assuming that Vo is sampled during 1, we have
1 1 C
CIVo ( z ) 1 + = z 1CIVo ( z ) 1 + + z 1CsVi ( z ) s Vo ( z )
A A A
1 C
z 1 1 1 + s
Vo ( z ) Cs A CI g z 1
=
Vi ( z ) CI 1 Cs 1 1 [1 ] z 1
1 1 z
A CI
Vo ( z ) = [1 ] z 1Vo ( z ) + g z 1Vi ( z )
Finite gain results in "leaky integrator"

Some fraction of previous output is lost in new cycle

Frequency Domain View
Limited gain at low frequencies (0, z 1)
g g
H0 = H( z ) z =1 = = A
1 [1 ]
But noise shaping relies on high integrator gain at low frequencies
Required DC Gain
[Boser & Wooley, JSSC 12/1988]
Good practice to make OTA gain at least a few times larger than
oversampling ratio

Integrator Noise
Noise splits into an input referred and output referred component

The two noise components are correlated
Luckily, only the input referred component is relevant
Well see that output noise is first-order shaped by the modulator
[Schreier, TCAS1, 2005]
Integrators Input Referred Noise
2 kT kT 1 kT 1
v in,tot = + + x = gm 2Ron
Cs Cs 1 + 1 Cs 1 + x
{
1 1444 x424444 3 [Schreier, TCAS1, 2005]
Analysis of phi2 noise:

Calculate noise charge left behind
at Y after switch has turned off.
Charges at X and Y are equal and
opposite, so calculating charge on
Cs accomplishes the task.

Second-Order Modulator
2 2
v in,tot1 v in,tot2
PSD(f) PSD(f)
f f
fs/2 fs/2
Y(z) Y(z)
N1(z)
= z 2
N2(z)
= 2 1 z 1 z 1( )
In-Band Noise
PSD(f)
PSD(f)
Digital filter
f f
fs/2 fb fs/2
+ f
+
PSD(f) fb fs/2
PSD(f)
fs / 2
OSR =
f
fb f
fs/2 fb fs/2

In-Band Noise
PSD(f) PSD(f)
+
f f
fs/2 fs/2
2 1 2 2 1
vin,tot1 v in,tot2
OSR 3 OSR3
Total in-band thermal noise at modulator input:
2 2 1 2 2 1
v in,tot = vin,tot1 + vin,tot2
OSR 3 OSR3
Example of a Continuous Time Modulator
[Mitteregger, ISSCC 2006]
4-stage amplifier with

feedforward compensation
Impractical for SC circuits
Great for CT delta-sigma
modulators

Multi-Mode Modulator
[Ouzounov, ISSCC 2007]
Delta-sigma ADCs are

more amenable to BW
and DR reconfiguration
Very hard to
reconfigure pipelined
ADCs
Great for flexible, multi-
standard wireless
receivers
Decimation Filters
References
J. Candy, "Decimation for Sigma-Delta Modulation," IEEE
Trans. Communications, pp. 72-76, Jan. 1986.
Chapters 1 and 13 of Delta-Sigma Data Converters, by
Norsworthy, Schreier, Temes.
B.P. Brandt and B.A. Wooley, "A low-power, area-efficient
digital filter for decimation and interpolation," IEEE J. Solid-
State Circuits, pp. 679-687, June 1994.
E. Hogenauer, "An economical class of digital filters for
decimation and interpolation," IEEE Trans. Acoustics,
Speech and Signal Processing, pp. 155-162, Apr 1981.
Objectives
Remove out-of band quantization noise
Re-sample at lower frequency
Ideally at Nyquist rate

Example
Decimation Filter (M = 256)
fS fN
Analog Modulator 1-Bit Digital
Input Output
11.3 (2nd-Order) 11.3 44.1 (16 Bits)
MHz MHz kHz
Quantization
Signal Noise
Noise
Frequency Frequency Frequency
Filter must attenuate spectral components around NfN,

Otherwise they will alias onto signal after re-sampling
Filter Requirements
Pass band 020kHz, transition band 2024.1kHz (f=4.1kHz),

stop band 24.1kHz5.65MHz
A digital FIR filter that meets these requirements would require
more than fs/f = 11.3MHz/4.1kHz 2800 coefficients
Impractical!

Multi-Step Decimation
Key idea: Dont try to decimate down to fN in one step
Perform a gradual reduction of sampling rate + some filtering
E.g. Two-step decimation
Example: M1=64, fs/M1=176.4kHz
Sinc Filter (1)

A popular, low complexity choice for stage 1 is the so-called
sinc-filter
From a time domain perspective, this filter simply computes the
average of several samples
1 N 1
y( n ) = x (n i )
N i =0
Frequency domain
f
N sin N j f ( N 1)
1 1 z 1 fs e fs
H( z ) = H( ) =
N 1 z 1 N f

fs
Zeros at multiples of fs/N
Make N=M1 to attenuate alias components!

Cascade of K Sinc Filters
0
-10
-20
-30
-40
-50
-60 K=1
K=2
-70
K=3
-80
-90
-100
0 f B fN fs1 2f s1 3f s1
M1 M1 M1
Frequency
Higher order means better rejection

But also more in-band droop
Can show that for Lth order noise shaping, an (L+1)th order sinc
filter is the best choice
Sinc Filter Performance

Noise penalty relative to "brick wall" filter Droop
[Norsworthy, p.30]
[Norsworthy, p.31]
Only about 0.14 dB increase in baseband noise for decimation

to an intermediate oversampling ratio of 4
If droop is undesired, it can be corrected downstream, using a
separate post-emphasis filter
Sinc Filter Performance (2)
In addition to suppressing quantization noise, the filter must
attenuate out-of-band signals present at the modulator input
Worst case freqeuncy is fs/M1-fB
E.g. 50dB for sinc3, and intermediate oversampling of 4x
Any additional desired rejection must come from analog filter
at modulator input
[Norsworthy, p.31]
Sinc Filter Implementation
Numerator Section:
X Y X + Y
1 z -1
Delay
Denominator Section:
X 1 Y X + Y
1 z -1
Delay

Complete Filter Implementation
1 THIRD- 20 FIRST 22 SECOND 22 DROOP 16

IN ORDER HALFBAND HALFBAND CORRECTION OUT
SINC FILTER FILTER FILTER
11.3 FILTER 176.4 (R=18) 88.2 (R=110) 44.1 (R=8) 44.1
MHz kHz kHz kHz kHz
M 1 = 64 M2 = 2 M3 = 2
0
Passband Ripple
-10 = 0.01 dB
-20
-30 [Brandt & Wooley, JSSC 6/1994]

-40
Second First Third-Order
-50 Halfband Halfband Sinc Filter
Filter Filter
-60
-70
-80
-90
-100
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
Droop Correction
0.6
0.5
0.4
0.3 Droop-Correction
0.2 Filter
First Halfband
0.1 Filter
0.0
-0.1
Second
-0.2
Third-Order Halfband
-0.3 Sinc Filter Filter
-0.4
-0.5
-0.6
0 2 4 6 8 10 12 14 16 18 20 22
FREQUENCY (kHz)

Implementation
43 multiplications and
SINC FILTER
INTEGRATORS 20 20 20 20 20 20 Modulator 84 additions per output
Output
sample
CLK (11.3 MHz)
Processor
Input
Virtual Addr.
Logic
Can use serial
7
Addr
7 arithmetic to minimize
8
7 hardware area
Data RAM
Addr
PROCESSOR
(128 x 22)
Coefficient/
Since output rate is
R/W
Control ROM
(256 x 22)
usually fairly low
Dout Din
22 13 Ctrl.
22
22-Bit Arithmetic Unit (AU) Filter

Output
D/A Conversion Revisited
TS
yH (t)
Time
N-Bit Digital lnput Word x(kT) y(t)
b1 b2 b3 bN Time

x*(t) yH (t) Lowpass y(t) Analog

Digital-to-Analog Interface Zero-Order
Hold Filter Output

Frequency Spectra
Magnitude
Baseband Signal SpectralImage
Spectral Images
Bands (Dirac Reconstruction)
|X*(f)|
0 fS/2 fS 2fS 3fS
|P Z (f)|
0 fS/2 fS 2fS 3fS
|YH (f)|
0 fS/2 fS 2fS 3fS

Frequency
Oversampling
Magnitude Analog Filter Spectral Image

Spectral Bands
Images
|X(f)|

fB fN 2 fN (a) (M-2) fN (M-1) fN M fN
|XM (f)| Analog Filter
fB (b) fS = M f N
Frequency
Oversampling greatly reduces reconstruction filter requirements

How to create oversampled DAC input from a Nyquist rate signal?

Interpolation (1)
Can increase the sampling rate of a discrete time signal by a
factor of M, by inserting M-1 zero-valued samples between the
actual Nyquist rate samples ("zero stuffing")
Causes an M-fold periodic repetition of the baseband
spectrum
Image Bands
Spectral Images
Nyquist-rate
Input
fB fS =fN 2 fN (M-2) fN (M-1) fN M fN
After
Zero
Insertion
fB fN 2 fN (M-2) fN (M-1) fN fS =M fN
Interpolation (2)
Why is this a good idea?
Can remove images and get wide transition band to play with
Simple reconstruction filter
Possibility of noise shaping
Build a high resolution DAC using a low resolution D/A interface
B N N N N S N
Digital M
Lowpass
Filter
fB fS =M fN
Interpolator
Output
fB fS =M fN

Example
DIGITA L ANALOG
Digital Analog
Digital 16 Digital 16 1 Analog
Noise Reconstruction
Input Interpolator M f Output
fN N Shaper M fN Filter
1-bit D/A Interface
Digital noise shaper is essentially a digital sigma-delta loop

Shapes "truncation noise" that results from truncating 16-bit
word to a 1-bit output
Spectra
Spectral Images
Digital
Input
fN 2 fN (M-2) fN (M-1) fN M fN
Interpolator Baseband Signal

Output
M fN
Truncation Noise
Quantization Noise
Noise
Shaper
Output
M fN
Analog
Output
Frequency

Example
E(z)
16 + + 18 + 19 1
X(z) z1 z1 Y(z) To 1-bit D/A Interface
+ +
18
Clipper
+

[Su &Wooley, JSSC 12/94]
2
Y(z) = z 2 X(z) + (1 z 1 ) 2 E(z)
Clipper prevents second integrator from overflowing

Digital "wrap around" would cause large errors
Semi-Digital Reconstruction (1)
Digital n -Bit Shift Register

Input 1
DIN z 1 z 1 ... z 1
DIGITA L
ANALOG
a1 a2 ... an
[Su &Wooley, JSSC 12/94]

Analog Output, A OUT
HFIR (z) = a1 z1 + a2 z2 + ... + an zn
Attractive alternative to fully analog reconstruction filter

Build FIR filter with weighted analog outputs

Semi-Digital Reconstruction (2)
Digital
Input 128-Bit Shift Register
DIGITA L
ANALOG
Weighted
Current
Sources
a a ... a 128
1 2
Current-to-Voltage
Conversion
I
out
Analog
I out + Output
1 2 3 n
A OUT ( z ) = a1 z + a2 z + a3 z + + an z DIN ( z )
H (z)
Linear if H(z) is independent of DIN(z)
Measurement Results
Reconstruction Filter Output

0
Noise Shaper Output

20
Analog Output
Power Spectrum (dB)
40
60
80
100
120
140
160
1k 10k 100k 1M
Frequency (Hz)

Energy Limits in A/D Converters
Boris Murmann
Stanford University
ADC Landscape in 2005

-6
10
-8
10
P/f s [J]
-10
10
-12
10
20 30 40 50 60 70 80 90 100 110
SNDR [dB]

-6
10
-8
10
P/f s [J]
-10
10
-12
10 ISSCC & VLSI 2006-2013
20 30 40 50 60 70 80 90 100 110
SNDR [dB]
Questions
How much more improvement can we hope for? What is the

fundamental energy limit?
Will certain architectures continue to improve faster than others?

Are there any architecture-specific limits?
Will CMOS process technology scaling play a significant role in

future improvements?
How does absolute conversion speed affect energy

consumption and the projected limits?

Fundamental Limit
2
1 VFS
2 2
SNR = Pmin = CVFS fs VDD VDD = VFS
kT
C
Pmin
Emin = = 8kT SNR
fs
[Hosticka, Proc. IEEE 1985; Vittoz, ISCAS 1990]

-6
10
-8
10
Energy [J]
-10
10
-12 4x/6dB
10
-14 ISSCC & VLSI 1998-2005

10
Emin
20 30 40 50 60 70 80 90 100 110
SNDR [dB]

-6
10
-8
10
Energy [J]
-10
10
-12 4x/6dB
10

-14 ISSCC & VLSI 1998-2005
10
Emin
20 30 40 50 60 70 80 90 100 110
SNDR [dB]
Normalized Plot
8
10
6
10
EADC/Emin
4
10
2
10
~10,000 ~100
100x in 8 years ~2x in 8 years
0
10
20 30 40 50 60 70 80 90 100 110
SNDR [dB]

Aside: Figure of Merit Considerations
There are (at least) two widely used ADC figures of merit (FOM)
used in literature
Walden FOM
Power
Energy increases 2x per bit (ENOB) FOM = ENOB
2 fsnyq
Empirical
Schreier FOM
Energy increases 4x per bit (DR)
Thermal
BW
Ignores distortion FOM = DR(dB) + 10log
P
FOM Lines
-6
10
-8
10
Energy [J]
-10
10
-12 ISSCC & VLSI 1998-2005

10
Emin
10
-14 Walden FOM = 10fJ/conv-step
Schreier FOM = 170dB
20 30 40 50 60 70 80 90 100 110
SNDR [dB]
Best to use thermal FOM for designs with SNDR > 60dB

Energy by Architecture
-6
10
-8
10
P/f s [J]
-10
10
Flash
Pipeline
SAR
-12
10
Other
20 30 40 50 60 70 80 90 100
SNDR [dB]
Flash ADC
Ecomp Eenc

Encoder
Assume a Wallace encoder (ones counter)
Uses ~2BB full adders, equivalent to ~ 5(2BB) gates
(
Eenc 5 2B B Egate )
Matching-Limited Comparator
A 2VT C
2VOS = A 2VT c Offset
WL Cox
A 2VT Cox Required
Cc = + Cc min capacitance
Cc Cc 2VOS
1 Vinpp Confidence
3 VOS = interval
Simple Dynamic Latch 4 2B
Assuming Ccmin = 5fF 3dB penalty
for wires, clocking, etc. SNR[dB] + 3
B accounts for
6 DNL noise
2
VDD
Ecomp 144 2 Cox A VT 2 + Cc min VDD
2B 2 2
2B 1 ( )
1424 3 Vinpp
Matching

Energy

Typical Process Parameters
Process AVT Cox

AVT2Cox /kT Egate [fJ]
[nm] [mV-m] [fF/m2]
250 8 9 139 80
130 4 14 54 10
65 3 17 37 3
32 1.5 43 23 1.5
Comparison to State-of-the-Art
-6
10
Flash ISSCC & VLSI 1997-2012
Eflash65nm
-8
10 Ecomp65nm
Emin
-10 [6]
10
P/f snyq [J]
[5]
[2] [3] [4]
10
-12 [1]
-14
10
-16
10
15 20 25 30 35 40
[1] Van der Plas, ISSCC 2006
SNDR [dB]
[4] Daly, ISSCC 2008
[2] El-Chammas, VLSI 2010 [5] Chen, VLSI 2008
[3] Verbruggen, VLSI 2008 [6] Geelen, ISSCC 2001 (!)
Impact of Scaling
-6
10
Flash ISSCC & VLSI 1997-2012
Eflash250nm
-8
Eflash130nm
10 Eflash65nm
Eflash32nm
P/f snyq [J]
Emin
-10
10
-12
10
-14
10
15 20 25 30 35 40
SNDR [dB]
SC Delta-Sigma Modulator
Model of first Assumptions

integrator Closed-loop gain =
C
Infinite transistor fT (Cgs=0)
C /2 Thermal noise factor ()

1 2 equals 1
Bias device has same
noise as amplifier device
Linear settling only
(no slewing)
Ci 2 1 2
= = Ceff = Ci (1 ) + CL = Ci + CL Ci
Ci 3 3 3
Ci +
2
SC Integrator Constraints
2
1 Vinpp

2 2 Thermal noise
SNR
kT 1 sets Ceff
4
Ceff OSR
Ceff T /2 Ts / 2
= = s Settling time
gm 1 ln SNR ( )
ln sets gm
d
gm
P = VDD gm sets power
gm

ID
Pulling It All Together
VDD
Settling
penalty
Number
6474of 8 2 }
VDD 1 1
Eint DT = 64
{ kT SNR ln ( SNR )
V V
gm
14inpp DD
Excess noise 24 3
ID
Finite Supply {
utilization Transconductor
efficiency
For settling with ~10 time constants and VDD=1V,

gm/ID=1/(1.5kT/q), Vinpp=0.5V, we have
E 200kT SNR

Comparison to State-of-the-Art
-6
10
[8]
-8
10 [7]
P/f snyq [J]
[6]
[4] [5]
-10 [3]
10 [1] [2] DT ISSCC & VLSI 1997-2012
CT ISSCC & VLSI 1997-2012
First Integrator
EintCT
-12
10 EintDT
Emin
60 65 70 75 80 85 90 95 100 105 110

[1] Kauffman, ISSCC 2011 SNDR [dB] [5] Chae, ISSCC 2008
[2] Witte, ISSCC 2012 [6] Pena Perez, ISSCC 2011
[3] Shettigar, ISSCC 2012 [7] Park, VLSI 2008
[4] Gealow, VLSI 2011 [8] Brewer, ISSCC 2005
Overall Picture
-6
10
-8
10
Flash
Pipeline
SAR
P/f s [J]
-10
10 Other
E
flash32nm,cal
E
pipe
-12
10 E
sar
E
CT
E
min
-14
10
20 30 40 50 60 70 80 90 100 110
SNDR [dB]

Discussion
Todays designs are very close to the predicted limits

The limit lines at high resolution are set by fundamental thermal
noise and architectural circuit overhead
Technology scaling wont help much
Sometimes it is even argued that technology scaling will
deteriorate efficiency, due to low VDD
Lets have a closer look at this
A Closer Look at the Impact of

Technology Scaling
As shown previously:
2
1 VDD 1
E
VDD Vinpp gm

ID
Low VDD hurts, but this is not the only factor

Designers have worked hard to maintain (if not improve)
Vinpp/VDD in low-voltage designs
How about gm/ID?

gm/ID Considerations (1)
30
180nm
25 90nm
20
gm/ID [S/A]
15
10
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
VGS-Vt [V]
Largest value occurs in weak inversion ~(1.5kT/q)-1

Range of gm/ID does not scale (much) with technology
120 180nm
100 90nm
80
fT [GHz]
60
40
20
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
VGS-Vt [V]
fT is small in weak inversion region

Must look at gm/ID for given fT requirement to compare technologies

30 Example
180nm
90nm fT = 30GHz
25 45nm 90nm: gm/ID = 18S/A
180nm: gm/ID = 9S/A
gm/ID [S/A]
20 For a given fT, 90nm device

takes less current to produce
15 same gm
Helps mitigate, if not
eliminate penalty due to
10 lower VDD (!)
5
0 20 40 60 80 100
fT [GHz]
ADC Energy for 90nm and Below

-6
10
-8
10
P/f snyq [J]
-10
10
-12
10 ISSCC & VLSI 1997-2013
90nm and below
20 30 40 50 60 70 80 90 100 110
SNDR [dB]

Efficiency versus Absolute Speed

=
2

6
10
2006-2013
1998-2005
FOM W [fJ/conv-step]
4
10
2
10
0
10 4 5 6 7 8 9 10
10 10 10 10 10 10 10
f s [Hz]
Analysis
1 Energy efficiency reduces with larger

gate overdrive

3 But, large gate overdrive is needed for

= high transistor fT
2
fT is usually chosen as a multiple of the

=
sampling rate

Conclusions (1)
No matter how you look at it, todays ADCs are extremely well
optimized
The main trend is that the thermal knee shifts very rapidly toward
lower resolutions
Thanks to process scaling and creative design
At high resolution, we seem to be stuck at E/Emin~100

The factor 100 is due to architectural complexity and
inefficiency: excess noise, signal < supply, non-noise limited
circuitry, class-A biasing,
This will be very hard to change

Scaling wont help (much)
Some of the recent data points already use class-B-like
amplification
Can we somehow recycle charge?
Conclusions (2)
At low resolutions, scaling will continue to help lower ADC
energy
Scaling will especially help improve the efficiency of GS/s A/D
converters
This is badly needed for high-speed data links
(electrical and optical)
For non-incremental improvements, we must explore new ideas
in signal processing that tackle ADC inefficiency at the system
level
Compressed sensing
Finite innovation rate sampling
Other ideas?

Example: Finite Innovation Rate
Sampling of Ultrasound Signals
High BW Low BW after filtering
Analog Recon-
Filter struction
[Inspired by theoretical work of Prof. Yonina Eldar]
~100x reduction in sampling rate

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EE315B

VLSI Data Conversion Circuits

B. Murmann EE315B - Chapter 1 1

B. Murmann EE315B - Chapter 1 2

Benefits of digital signal processing

B. Murmann EE315B - Chapter 1 3

A/D Converter ca. 1954

B. Murmann EE315B - Chapter 1 4

B. Murmann EE315B - Chapter 1 5

Data Converter Applications (2)

Computing and Control

B. Murmann EE315B - Chapter 1 6

[Poulton, ISSCC 2003]

B. Murmann EE315B - Chapter 1 7

Schvan, ISSCC 2008

B. Murmann EE315B - Chapter 1 8

A typical cell phone contains:

A total of 19 data converters!

B. Murmann EE315B - Chapter 1 9

Low-cost, single chip solutions require embedded data

B. Murmann EE315B - Chapter 1 10

B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html

B. Murmann EE315B - Chapter 1 11

Acquire a thorough understanding of the basic principles and

B. Murmann EE315B - Chapter 1 12

B. Murmann EE315B - Chapter 1 13

B. Murmann EE315B - Chapter 1 14

B. Murmann EE315B - Chapter 1 15

B. Murmann EE315B - Chapter 1 16

Please remember you are bound by the honor code

B. Murmann EE315B - Chapter 1 17

Tools and Technology

B. Murmann EE315B - Chapter 1 18

M. Pelgrom, Analog-to-Digital Conversion, Springer, 2010

B. Razavi, Data Conversion System Design, IEEE Press, 1995

B. Murmann EE315B - Chapter 1 19

Ideal sampling, reconstruction and quantization

B. Murmann EE315B - Chapter 1 20

B. Murmann EE315B - Chapter 2 1

The Data Conversion Problem

Real world signals

B. Murmann EE315B - Chapter 2 2

We'll fist look at these building blocks from a functional, "black

B. Murmann EE315B - Chapter 2 3

Uniform Sampling and Quantization

Most common way of performing A/D

B. Murmann EE315B - Chapter 2 4

B. Murmann EE315B - Chapter 2 5

Aliasing Example (2)

899 899 101

B. Murmann EE315B - Chapter 2 6

1101 1101 101

B. Murmann EE315B - Chapter 2 7

The frequencies fsig and Nfs fsig (N integer), are

B. Murmann EE315B - Chapter 2 8

In order to prevent aliasing, we need

The sampling rate fs=2fsig,max is called the Nyquist rate

B. Murmann EE315B - Chapter 2 9

Brick Wall Anti-Alias Filter

B. Murmann EE315B - Chapter 2 10

0 B fs/2 fs-B fs ... f

0 B/fs 0.5 f/fs

Need to sample faster than Nyquist rate to get good attenuation