IMPACT OF PROCESS VARIATION ON RF STABILITY PERFORMANCE OF

JUNCTIONLESS FinFET
V.GOVARTHANAN AND Dr.K.SIVASANKARAN
VLSI DIVISION, SENSE, VIT UNIVERSITY

ABSTRACT
In this paper, we investigate the RF stability Performance of Junctionless FinFET using Sentaurus Process with Advanced Calibration and the 3D
MGOALS module. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and
threshold voltage roll-off, on the various fin angle and fin height are investigated. The optimized JL FinFET shows good RF stability Performance.

BACKGROUND METHODOLOGY RESULTS AND DISCUSSION

VARIABLE DESCRIPTION RANGE(m) Step-1: Structure of Junctionless FinFET:
NAME Designing of Junctionless FinFET as
Polypitch The poly pitch 0.044 per ITRS requirements using
Sentaurus Process with MGOALS.
Gatethick Thickness of the 0.0006
Gate Step-2:
The small signal parameters are
FinPitch The Fin pitch 0.024
extracted using TCAD and that
HFin Height of the Fin 0.030 parameters are used to develop RF
STI depth Shallow Trench 0.100
stability model.
Isolation depth Step-3:
The above extracted RF model is
Wfin Fin width 0.006
validated for better device
performance and operation.
Current-Voltage Characteristics:
Lg Gate Length 0.015

In order to keep up with Moores law,

we are supposed to reduce the channel
length, but after reducing the channel
length, short channel effects (SCE) arise
and gate loses control over the channel and
hence short channel effects come into
account. In order to avoid them and
improve the gate controllability over the
channel, multigate devices are proposed.
In this work RF stability performance
of JLTGT was studied which is an important
parameter in Radio Frequency integrated
circuit design (RFIC). This paper gives
optimized device structure in terms of
geometric and voltage biasing parameters.
The correction approach of the
gate oxide permittivity and the
workfunction is used for the channel
quantum correction. The quantum
correction density gradient model is
switched on in the source/drain and
the channel stop regions to
compensate for the Channel direction
quantum correction.
CONCLUSION
The RF stability performance of Junctionless
FinFET is studied at optimized geometric and
biasing conditions. We observed that by increasing
the spacer length up to optimized value we get an
improved value of ft. The proposed Junctionless
FinFET is having the threshold voltage of 0.455.