CSE 370 Spring 2006 Binary full adder

Introduction to Digital Design 1-bit full adder

A B Cin S Cout
Computes sum, carry-out 0 0 0 0 0
Lecture 12: Adders Carry-in allows cascaded 0 0 1 1 0
adders 0 1 0 1 0
0 1 1 0 1
Sum = Cin xor A xor B 1 0 0 1 0
Last Lecture Cout = ACin + BCin + AB 1 0 1 0 1
1 1 0 0 1
PLAs and PALs XOR
A
XOR
1 1 1 1 1
B 32
Sum
Cin
Today 33

Adders AND2
B A Sum
Cin Full
B
11

AND2 OR3
Adder Cout
A
Cin 12 14
Cout Cin
AND2
A
B 13

Full adder: Alternative Implementation

2-bit ripple-carry adder
Multilevel logic
A B Cin S Cout Cout A B
Slower 0 0 0 0 0 0 A1 B1 A2 B2
0 0 1 1 0 0
Less gates 0 1 0 1 0 0 XOR
1-Bit Adder
2 XORs, 2 ANDs, 1 OR 0 1 1 0 1 1 A
B 32
XOR

1 0 0 1 0 0 Cin
Sum
0 Cin Cout Cin Cout
Sum = (A B) Cin
33
1 0 1 0 1 1
Cout = ACin + BCin + AB 1 1 0 0 1 1 AND2
B

= (A B)Cin + AB 1 1 1 1 1 1 Cin
Cin 11

AND2 OR3
Cout
A
Cout Sum1 Sum2
Cin 12 14

Half Adder Half Adder AND2

A xor B A xor B xor Cin A

A Sum Sum Sum B 13

B AB (A xor B)Cin
Cout Cout
Cin Overflow
Cout
Sum
4-bit ripple-carry adder/subtractor Problem: Ripple-carry delay
Circuit adds or subtracts
2s complement: A B = A + (B) = A + B' + 1 Carry propagation limits adder speed
Cin
XOR

A3 B3B3' A2 B2B2' A1 B1B1' A0 B0B0' @0 A

@0 B 32
XOR
A0 S0 @2
B0 C1 @2
Sel Sum
0 1 0 1 Sel 0 1 Sel 0 1 Sel @2N Cin 33
@2N+1
AND2 A1 S1 @3
@0 B B1 C2 @4
A B A B A B A B @2N Cin 11
0 Add
Cout Cin Cout Cin Cout Cin Cout Cin 1 Subtract
AND2 OR3
S2 @5
@2N+2 A2
@0 A
Sum Sum Sum Sum Cout B2 C3 @6
@2N Cin 12 14

AND2
S3 S2 S1 S0 @0 A A3 S3 @7
@0 B B3 Cout @8
Cout takes two gate delays
13
Overflow Note: Can replace 2:1
muxes with XOR gates Cin arrives late

Ripple-carry adder timing One solution: Carry lookahead

diagram logic
Critical delay Compute all the carries in parallel
Carry propagation Derive carries from the data inputs Cin
S0 @2
Not from intermediate carries A0
1111 + 0001 = 10000 is worst case B0
Use two-level logic C1 @3
S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid
Compute all sums in parallel A1 S1 @4
B1
Cascade simple adders to make large C2 @3
adders A2 S2 @4
B2
Speed improvement
C3 @3
16-bit ripple-carry: ~32 gate delays A3 S3 @4
16-bit carry-lookahead: ~8 gate B3

delays C4 @3 C4 @3

T0 T2 T4 T6 T8 Issues
Complex combinational logic
 Full adder again Carry-lookahead logic
Carry generate: Gi = AiBi
Half Adder Half Adder
A xor B A xor B xor Cin Generate carry when A = B = 1
A Sum Sum Sum
B AB Cin(A xor B) Carry propagate: Pi = Ai xor Bi
Cout Cout
Cin Cout Propagate carry-in to carry-out when (A xor B) = 1
Sum and Cout in terms of generate/propagate:
XOR XOR
Ai Pi
Si
Bi 36 38 Si = Ai xor Bi xor Ci
AND2 AND2
= Pi xor Ci
Ai Gi
Bi 37 39
OR2 Ci+1= AiBi + Ci(Ai xor Bi)
Ci
Ci+1 = Gi + CiPi
40

Implementing the carry-

Carry-lookahead logic (contd)
lookahead logic
Re-express the carry logic in terms of G and P Ai Pi @ 1 gate delay Logic complexity
Bi
C1 = G0 + P0C0 Si @ 2 gate delays
increases with
Ci
adder size
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 Gi @ 1 gate delay
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + C0
C0
P0
P0 C1 C0 P1
P3P2P1P0C0 G0
P0
P1
P2
P2 P3
G0
G0 P1
C0 P1
Implement each carry equation with two-level logic P0 P2 P2
P1 P3
G0 G1 C3 G1
Derive intermediate results directly from inputs P1 C2 P2 P2
P3
G2 G2 C4
Rather than from carries G1
P3
G3
Allows "sum" computations to proceed in parallel
 Cascaded carry-lookahead Another solution: Carry-select
adder adder
4 four-bit adders with internal carry lookahead Redundant hardware speeds carry calculation
Second level lookahead extends adder to 16 bits Compute two high-order sums while waiting for carry-
in (C4)
4 4 4 4 4 4 4 4
Select correct high-order sum after receiving C4
A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]
C12 C8 C4 C0
4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder
@0 C8 0
P G P G P G P G
4-bit adder adder
[7:4] low
4 4 4 4

S[15-12] S[11-8] S[7-4] S[3-0]

@8 @3 @8 @7 @4
@2 @2 @3 @2 @3 @2 @3 C8 1
@5 @5 @4 4-bit adder adder
[7:4] high
P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0

C16 C0 C0
C4 Lookahead Carry Unit
@4 @0
five 1 0 1 0 10 1 0 1 0 C4 4-Bit Adder C0
P3-0 G3-0
2:1 muxes [3:0]
@3 @5

C8 S7 S6 S5 S4 S3 S2 S1 S0

We've finished combinational Sequential versus

logic... combinational
What you should know A
C
Twos complement arithmetic
B
Truth tables
clock
Basic logic gates
Schematic diagrams
Apply fixed inputs A, B
Timing diagrams Wait for clock edge
Minterm and maxterm expansions (canonical, minimized) Observe C
de Morgan's theorem Wait for another clock edge
AND/OR to NAND/NOR logic conversion Observe C again
K-maps, logic minimization, don't cares
Combinational: C will stay the same
Multiplexers/demultiplexers
Sequential: C may be different
PLAs/PALs
ROMs
Adders
 Sequential versus
Sequential logic
combinational (again)
Combinational systems are memoryless
Two types
Outputs depend only on the present inputs
Synchronous = clocked
Asynchronous = self-timed
Has state Inputs System Outputs

State = memory
Employs feedback
Sequential systems have memory
Assumes steady-state signals
Outputs depend on the present and the previous inputs
Signals are valid after they have settled
Inputs
State elements hold their settled output System Outputs
values

Feedback

Synchronous sequential systems Steady-state abstraction

Memory holds a systems state Outputs retain their settled values
Changes in state occur at specific times The clock period must be long enough for all voltages
A periodic signal times or clocks the state changes to settle to a steady state before the next state
The clock period is the time between state changes change
A A
C C
B B
State changes occur
clock at rising edge of clock clock Clock hides transient
behavior
pulsewidth duty cycle = pulsewidth/period
(here it is 50%) clock
clock
C
period
Settled value
Example: A sequential system
Door combination lock
Enter 3 numbers in sequence and the door opens
If there is an error the lock must be reset
After the door opens the lock must be reset
Inputs: Sequence of numbers, reset
Outputs: Door open/close
Memory: Must remember the combination