3EC1105 HDL Based Design with

Programmable Logic
 Teaching Scheme

Course Examination Scheme

code Course Name
Hours Component
Weightage
SEE SEE CE LPW
3.00 0.4 0.6 NA
HDL Based Design with
3EC1105
programmable logic

Class Test Sessional Term/ Total CE

Exam Sp. Assign
ment
30 40 30 100
 Text /Reference Books
A Verilog HDL Primer by J. Bhasker,
BS Publications
Verilog HDL by Samir Palnitkar,
Pearson Education
A VHDL Primer by Bhasker, Pearson
Education
VHDL programming by examples by
Douglas L.Perry, Tata McGraw Hill
 Text /Reference Books
C. H. Roth, Digital System Design with VHDL,
PWS/Brookscole
Stiphen M Trimberger, Field Programmable Gate Array
Technology, Springer
Brown Vranesic, Fundamentals of Digital Logic with Verilog
Design. Tata McGrawHill
Stephen Brown and Zvonko Vranesic, Fundamentals of
Digital Logic with VHDL Design. Tata McGrawHill
Sudhakar Yalamanchi, Introductory VHDL From Simulation
to Synthesis, Pearson Education
Mark Zwolinski, Digital System Design with VHDL, Pearson
Education
Peter J Ashenden, The Designers Guide to VHDL, Elsevier
Kevin Skahil, VHDL for Programmable Logic, Pearson
Wyane Wolf, FPGA Based System Design, Pearson
 Other References
https://sites.google.com/a/nirmauni.
ac.in/3ec1105-hdl-based-design-
with-programmable-logic/
https://3ec1105usm.wordpress.com/
http://textofvideo.nptel.iitm.ac.in/vid
eo.php?courseId=106105083
Typical Design Flow
 What will we learn?
Hardware Description Languages
(HDLs)
Verilog
VHDL
 What is HDL?
Hardware Description Language is
used to model a digital system at
different level of abstraction
 HDL History
The first HDL was ISP (Instruction-set
Processor language), invented by C.
Gordon Bell and Alan Newell at
Carnegie Mellon University

This language was also the first to

use the term register transfer level
 Why HDLs?
The complexity of logic circuits has
increased dramatically in the past few
decades
Other forms of EDAs are no longer
effective
HDLs offer a consistent and efficient
method for both design and synthesis
HDLs are relatively easy to learn
 Why HDLs?
Technology independent
Technology changes- no need to redesign
circuit/ system
Functional verification (simulation)
Can be done early in design cycle
Optimization
Since designer work at RTL level
Designer can modify RTL description until
functionality satisfy
Library support for reuse and previously
verified components
Timing Information
 Why not C or other?
Timing information
Sequential and Concurrent
Synthesis
 History
Verilog HDL originated in 1983 at
Gateway Design Automation
1995 Original standard IEEE 1364-
1995 was approved
IEEE 1364-2001 is latest standard
VHDL was developed under the
contract from DARPA
Verilog
Popularity of Verilog HDL
Easy to learn and easy to use
Syntaxes are similar to C programming
Verilog HDL allows different level of
abstraction to be mixed in same model
Most popular logic synthesis tools
support Verilog HDL
All fabrication vendors provide Verilog
HDL libraries
Programming Language Interface (PLI)
 Verilog
Synthesizable
Non-Synthesizable (simulation based)
Verilog Basics
 Verilog Vs VHDL
VHDL was designed to support system
level design and Specifications
Verilog is Preliminary for Digital
Hardware Design (FPGA, ASIC)
VHDL provides some high level
constructs (user defined types like
integer , Boolean etc.)
Verilog
all the gates are available provides
comprehensive to gate level design
Not available in VHDLincludes as
Pacakages
 Verilog
Synthesizable
Non-Synthesizable (simulation based)
 Design Methodologies
Top Down
Bottom Up
Top Down
Bottom Up
4-bit Ripple Carry Counter
4-bit Ripple Carry Counter
4-bit Ripple Carry Counter
Design at Different Level
Behavioural
Dataflow
Structural
Design at Different Level:
Behavioural
Behavioral: Algorithmically specify the
behavior of the design
Example: a
Black Box out
if (select == 0) begin
b 2x1 MUX

out = b;
end sel

else if (select == 1) begin

out = a;
end
Design at Different Level:
Dataflow
Dataflow: Specify output signals in
terms of input signals
Example:
assign out = (sel & a) | (~sel
& b); b

sel_b
sel
sel_n
out
sel_a

a
Design at Different Level:
Structural
Structural: Logic is described in
terms of Verilog gate primitives
Example: b
not n1(sel_n, sel); sel n1
a1
sel_b

sel_n
and a1(sel_b, b, sel_b); o1 out
a
and a2(sel_a, a, sel); a2 sel_a

or o1(out, sel_b, sel_a);

Module in Verilog
 Modules
The basic hardware unit is called module
Syntax
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule
Example:
module T_ff(q, clock, reset);
...
<functionality of T_flipflop>
endmodule
 Modules
Module can not contains definition of
other module
A module can be instantiate in
module
Allows the creation of hierarchy in
Verilog description
Instance in Verilog
 Instances
module ripple_carry_counter(q, clk,
reset);

output [3:0] q;
input clk, reset;
//4 instances of the module TFF are
created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);

endmodule
 T flip-flop
module TFF(q,clk,reset);
output q;
input clk, reset;
wire d;

DFF dff0(q,d,clk,reset);
not n1(d, q); // not is a Verilog provided primitive.

endmodule
 D flip-flop
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;

always @(posedge reset or negedge clk)

if (reset)
q = 1'b0;
else
q = d;
endmodule
 Illegal instantiation
example
Nested module definition not allowed
Note the difference between module definition and module
instantiation

// Define the top level module called ripple carry

// counter. It is illegal to define the module T_FF inside
// this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING

endmodule
 Exercise (Half Adder)
module HalfAdder(A,B,Sum,Carry);
input A,B;
output Sum,Carry;
assign Sum = A ^ B;
//^ denotes XOR

assign Carry = A & B;

// & denotes AND

endmodule
 Lexical Conventions
Number Specifications

<Size><Base format><Number>

4b111 //This is a 4-bit binary number

12habc //This is a 12-bit hexadecimal number
16d255 //This is 16-bit decimal number
23456 //This is a 32-bit decimal number by default
hc3 //This is a 32-bit hexadecimal number
o21 //This a 32-bit octal number
1bx // 1 bit unknown number
1bZ // 1 bit high impedance number
12b1111_1100_1010 //underscore is just for readability
 Lexical Conventions

Comments
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment
*/ This is an illegal comment
/* end with this is also illegal
 Data Types
Value set
Verilog supports 4 values and 8
strengths to model the functionality of
real hardware
Value Level Condition in Hardware Circuits

0 Logic zero, false condition

1 Logic one, true condition

X Unknown logic value

Z High impedance, floating state

 Data Types
Nets
Net represents connections between
hardware elements

Nets are primarily declared by keyword

wire
Syntax
wire a;
wire b, c;
wire d=1b0;
(default it is considered as 1 bit)
 Data Types
Register
Register represents the data storage
elements
Register retains until another values are
placed into them
A variable which can hold the value
Syntax
reg reset;
 Data Types
Vectors
Nets and register can be declared as vectors
(multiple bit width)
If not mentioned , the default is scalar (1-
bit)
wire a; // scalar net variable
reg reset; // scalar reg variable
wire [7:0] a;
reg [0:40] virtual_add;
Vector can be defined as [#high:#low] or
[#low:#high]- first is MSB
 Data Types
Vector
Example
wire [0:3] a;

wire [3:0] a;

a 0011

First value defined in square bracket is MSB

 Array
<array_name> [<subscript>]

integer count[0:7]; //An array of 8 count

variables
reg bool[31:0];// Array of 32 one-bit boolean
register variables
time chk_point[1:100];//Array of 100 time
checkpoint variables
reg[4:0] port_id[0:7];//Array of 8 port_ids and
each port_id is 5 bits wide
{interger matrix[4:0][0:255];//Illegal
declaration of Multidimensonal array}
Count[5]//5th element of array of count variables
Chk_point[100]//100th time check point value
Port_id[3]//3rd element if port_id array. This is
a 5-bit value
 String
reg [8*18:1] string_value;//Declare a
variable that is 18 bytes wide

string_value=hello verilog world;

//String can be stored in variable
Components of Verilog
Modules
Components of SR Latch
SR Latch
 SR Latch
//This example illustrates the different components of a
module
//Module name and port list
//SR_latch module
module SR_latch(Q,Qbar,Sbar,Rbar);
//portdeclarations
output Q,Qbar;
input Sbar,Rbar;
//Instantiate lower-level modules
//In this case, instantiate verilog primitive nand gates
//Note, how the wires are connected in a cross-coupled
fashion.
nand n1(Q,Sbar,Qbar);
nand n2(Qbar,Rbar,Q);
//endmodule statement
endmodule
 Observations
Components of Module
variable declaration, dataflow (assign)
statements, behavioral block (always or
initial)
Module contains all except port list, port
declaration and data flow (assign)
All components except module, module
name, and endmodule are optional
Verilog allows multiple modules to be
defined in a single file
 Ports
Port provides the interface by which
module can communicate
 Port Declaration

Verilog Keyword Type of Port

input Input Port

output Output Port

inout Bidirectional Port

Port Connection Rules
 Port Connection Rules
Inputs
Outputs
Inouts
Width Matching
Unconnected Ports
Fulladd4 fa0(SUM, , A, B, C_IN)//output port
C_out is unconnected
 Port Connection Rules
Illegal Port Connection
Module Top;
//Declare connection variables
reg[3:0]A,B;
reg C_IN;
reg [3:0]SUM;
wire C_out;
//Instantiate fulladd4,call it fa0
Fulladd4 fa0(SUM,C_OUT,A,B,C_IN);
//Illegal connection because output port sum in
module fulladd4
//is connected to a register variable SUM in module
Top.
 Connecting Port to
external Signal
Connections between signals
specified in the module instantiations
and the port in the module definition
Connecting by ordered list
Connecting Ports by name
 Connecting Port to
external Signal
Connecting by ordered list: It should be
in same order
module Top;
//Declare connection variables
reg[3:0]A,B;
reg C_IN;
wire[3:0]SUM;
wire C_OUT;
//Instantiate fulladd4,call it fa_ordered.
//signals are connected to port in order(by
position)
Fulladd4 fa_ordered(SUM,C_OUT,A,B,C_IN);
endmodule
 Connecting Port to
external Signal
module fulladd4(sum,c_out,a,b,c_in);
output[3:0] sum;
output c_out;
input[3:0] a,b;
input c_in;

<module internals>

endmodule
 Connecting Port to
external Signal
Connecting Ports by name

//Instantiate module fa_byname and

connect signals to ports by name fulladd4
fa_name(.c_out(C_OUT),.sum(SUM), .b(B),
.c_in(C_IN), .a(A));

//Instantiate module fa_byname and

connect signals to ports by name fulladd4
fa_byname(.sum(SUM),.b(B), .c_in(C_IN),
.a(A));