M.TECH.

ETRX Part II CMOS design

Microwind Lab
M.TECH. ETRX Part II CMOS design

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M.TECH. ETRX Part II CMOS design

Microwind 3.1
M.TECH. ETRX Part II CMOS design

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M.TECH. ETRX Part II CMOS design

Process Technology

This showing technology using in

current design.
The lambda units is fixed to half of the
minimum
available lithography of the technology.
Currently is showing 5 lambda skill,
zoom in to
change to 1 lambda skill.
To change the technology process,
click File Select
Foundry, and select the design that
you
M.TECH. ETRX Part II CMOS design

Palette
.
The palette is located in the lower right corner of the screen. A red color indicates the
current laye
M.TECH. ETRX Part II CMOS design

NMOS Transistor

Click on the polysilicon on palette first to

make sure in polysilicon
layer.

Than, fix the first corner of the box with

the mouse. While keeping the mouse
button pressed, move the mouse to opposite
corner of the box. Release the button. This
creates a box in polysilicon layer as shown.
The box width should not be inferior to 2,
which is the minimum width of the
polysilicon box.
Next to draw the n+ diffusion. Change the
current layer into n+ diffusion by a click
on the palette of the Diffusion n+ button.
Make sure that the red layer is now the n+
diffusion. Draw a n-diffusion box at the
bottom of the drawing.
N-diffusion box is represented in green.
The intersection between diffusion and
polysilicon creates the channel of the
nMOS device.

2D view of the transistor.

M.TECH. ETRX Part II CMOS design

Click on icon to access process

simulation.(Simulation
Process section in 2D ). The cross
section is given by a click
of the mouse at the first point and
the release of the mouse
at the second point.

In the example, three nodes

appear in the cross section of the n-channel MOS device: The gat
(red), the left diffusion called source (green) and the right
diffusion called drain (green),
over a substrate (gray). A thin
oxide called the gate oxide
isolated the gat
M.TECH. ETRX Part II CMOS design

MOS characteristic

Click on the MOS characteristic icon. It appear Id/Vd static Characteristic of the
nMOS
device. The MOS size (width and Length) has a strong influence on the value of the
current.
A High gate voltage (Vg=1.2V) corresponds to the highest Id/Vd curve. For Vg =0; no
current flow.
M.TECH. ETRX Part II CMOS design

Dynamic MOS behavior

M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

Analog simulation
Click on Simulate Start Simulation the timing diagram of the nMOS device appear as
shown below.
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

Procedure to draw layout in MICROWIND

M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

Drawn physical layout

M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

AND gate

Aim: Design and implementation of two input AND gate

Tools: Microwind 3.1 layout editor

Logic symbol and truth table:

M.TECH. ETRX Part II CMOS design

AND GATE LAYOUT:

M.TECH. ETRX Part II CMOS design

Simulation result
M.TECH. ETRX Part II CMOS design

Experiment no 7

Aim: Layout implementation of MUX Transmission gate.

Tools: Microwind 3.1 layout editor

Theory:

Multiplexers are key components in CMOS memory elements and data manipulation
structures.
A Multiplexer chooses the output from among several inputs based on a select signal. A 2-
input, or
2:1 Multiplexer, chooses input D0 when the select is 0 and input D1 when the select is 1.

The truth table is given in Table 1.6; the logic function Y = S D0 + S D1. Two transmission
gates
can be tied Together to form a compact 2-input multiplexer, as shown in Figure 1.28(a). The
select
and its Complement enable exactly one of the two transmission gates at any given time. The
Complementary Select S is often not drawn in the symbol, as shown in Figure 1.28(b).

Symbol of transmission gate multiplexer

M.TECH. ETRX Part II CMOS design

Table: Multiplexer Truth table

Mux layout using transmission gate

M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

OUTPUT:
M.TECH. ETRX Part II CMOS design

Experiments no 8

Aim: Layout implementation (any one) Half adder

Toos used: Microwind 3.1

Theory:

HALF ADDER USING MICROWIND

M.TECH. ETRX Part II CMOS design

OUTPUT WAVEFORMS:
M.TECH. ETRX Part II CMOS design

Experiment 6

Aim: Layout implementation xor gate

Toos used: Microwind 3.1

Theory:
M.TECH. ETRX Part II CMOS design
M.TECH. ETRX Part II CMOS design

Experiments no 7

Aim: The aim of this experiment is to design and plot the characteristics of a 4x1 digital
multiplexer using pass transistor and transmission gate logic.

Introduction

A multiplexer or mux is a combinational circuits that selects several analog or digital input
signals and forwards the selected input into a single output line. A multiplexer of 2n inputs
has n selected lines, are used to select which input line to send to the output.

Fig.1: The schematic diagram, boolean equation and the truth table of a 2:1 multiplexer with
inputs A and B, select input S and the output Z.

Figure 2 shows how a 4:1 MUX can be constructed out of two 2:1 MUX
M.TECH. ETRX Part II CMOS design

Design using pass-transistor logic

A multiplexer can be designed using various logics. Fig.3 shows how a 2:1 MUX is
implemented using a pass-transistor logic.

Fig.3. Design of a 2:1 MUX using pass-transistor logic

The pass-transistor logic attempts to reduce the number of transistors to implement a logic by
allowing the primary inputs to drive gate terminals as well as source-drain terminals. The
implementation of a 2:1 MUX requires 4 transistors (including the inverter required to invert
S), while a complementary CMOS implementation would require 6 transistors. The reduced
number of devices has the additional advantage of lower capacitance.

Design using transmission gate logic

A transmission gate is an electronic element and good non mechanical relay built with CMOS
technology. It is made by parallel combination of nMOS and pMOS transistors with the input
at the gate of one transistor (C) being complementary to the input at the gate () of the other.
The symbol of a transmission gate is shown below in fig.4.

Fig.4: Symbol for tranmission gate

The transmission gate acts as a bidirectional switch controlled by the gate signal C. When
C=1, both MOSFETs are on, allowing the signal to pass through the gate. In short, A=B, if
C=1. On the other hand, C=0, places both transistors in cut-off, creating an open circuit
between nodes A and B. Fig.5 shows the implementation of a 2:1 MUX using transmission
gate logic.
M.TECH. ETRX Part II CMOS design

Fig.5: Circuit diagram of a 2:1 MUX using transmission gate logic

Here, the transmission gates selects input A or B on the basis of the value of the control signal
S. When S=0, Z=A and when S=1, Z=B.