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Essentials Oak 14 Schematic


Chief River

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2012-09-05

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C C

REV : A00

B B

A
DY : None Installed M14 DIS A

Wistron Corporation
UMA: UMA only installed 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OPS: DISCRTE OPTIMUS installed Title

Cover Page
Size Document Number Rev
A3
OAK14 Chief River DIS A00
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
1 of 105
5 4 3 2 1

CHARGER
BQ24727 40
Project code: 91.4WT01.001 INPUTS OUTPUTS
91.4XP01.001
PCB P/N : 12204
Oak14 Block Diagram AD+
BT+
DCBATOUT

SYSTEM DC/DC
Revision: A00 TPS51225 41
INPUTS OUTPUTS
3D3V_AUX_S5
D 5V_AUX_S5 D
DCBATOUT 5V_S5
3D3V_S5
DDR3
CPU Core/NB Power
Intel CPU DDR3 1333/1600MHz Channel A
1333/1600
ISL95833 42~44
33
SODIMM A INPUTS OUTPUTS
Nvidia Ivy Bridge 14
VRAM(DDR3) *8 VCC_CORE
128Mx16bx4(1GB) N13P - GS - OP PCIe x 8 17W (DC)
DCBATOUT
VCC_GFXCORE
26
256Mx16bx4(2GB) DDR3
DDR3
N13M- GSR 1333/1600
128Mx16bx8(2GB)
25W DDR3 1333/1600MHz Channel B DDR3 SUS
BGA1023

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88,89,90,91 TPS51216 46
83,84,85,86,87
SODIMM B

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INPUTS OUTPUTS
15
4,5,6,7,8,9,10

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Switchable Graphic only DCBATOUT 1D5V_S3
DDR3 VTT

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TPS51216 46

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FDIx4x2 DMIx4 INPUTS OUTPUTS
DCBATOUT 0D75V_S0

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CPU VCCP_CPU

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10/100 NIC TPS51219 45
HDMI V1.4a HDMI

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C
RJ45 INPUTS OUTPUTS C
51 PCIE x 1 Realtek
DCBATOUT 1D05V_S0
RTL8105E-VD Conn.
Intel PCH 31
59 Intel PCH 1D8V_S0
14.0" LCD SYW231 47
LVDS (2channel)
Panther Point INPUTS OUTPUTS
(16:9) 49
PCIE x 1
BGA989 Mini-Card 3D3V_S5 1D8V_S0

802.11 b/g/n Intel CPU_VCCSA


TPS51463 48
Camera HM76 USB2.0 x 1 BT V4.0 combo
USB2.0 x 1 65 INPUTS OUTPUTS
49 12 USB 2.0/1.1 ports
Digital MIC 5V_S5 0D85V_S0
4 USB 3.0 ports Left side Nvidia VGA_CORE
High Definition Audio USB3.0 x 2 ADP3211MNR2G 92
6 SATA ports USB3.0 Port x 2 INPUTS OUTPUTS
8 PCIE ports DCBATOUT VGA_CORE
USB2.0 x 2
HDA LPC I/F 61,62,63
MIC_IN/GND Switches 36 93
CODEC ACPI 4.0a
USB Board
HDA INPUTS OUTPUTS
HP_R/L Realtek Right side
58 1D5V_S3 1D5V_S0
B Combo Jack ALC3221 29 B
5V_S5 5V_S0
USB2.0 x 1 USB2.0 Port x 1 3D3V_S5 3D3V_S0
2CH SPEAKER
(2CH 2W/4ohm) VCCP_CPU 1D05V_VGA_S0
3D3V_S0 3D3V_VGA_S0
1D5V_S3 1D5V_VGA_S0

58
LPC debug port LPC BUS CardReader SD/SDHC/MS/MS Pro
USB2.0 x 1 Realtek
71
RTS5170
Slot
74
PCB LAYER
32
L1:Top L4:Signal
Thermal 17,18,19,20,21,22,23,24,25
L2:VCC L5:GND
NUVOTON SMBUS
L3:Signal L6:Bottom
NCT7718W 28 KBC
NUVOTON SPI SATA(Gen3) x 1 HDD
Fan Control NPCE885P 56
NUVOTON 27
NCT3940S-A 28

PS2 Flash ROM


Int. 8MB SATA(Gen1) x 1 ODD
60
FAN 28
A
KB 69 56 A

Touch PAD SMBUS


Profile/Image sensor M14 DIS

69
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev

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03-05-1512:40:57 PM
C OAK14 Chief River DIS A00
5 4
03-05-151:22:21 PM 3 2
Date: Wednesday, September 05, 2012
1
Sheet 2 of 105
A B C D E
PCH Strapping Chief River Schematic Checklist Revision 1.5

Name Schematics Notes Power Plane


Processor Strapping Chief River Schematic Checklist Revision 1.5
The signal has a weak internal pull-down. Configuration (Default value for each bit is Default Voltage Rails
Pin Name Strap Description POWER PLANE VOLTAGE DESCRIPTION
Note: the internal pull-down is disabled after PLTRST# deasserts. 1 unless specified otherwise) Value ACTIVE IN
SPKR
If the signal is sampled high, this indicates that the system is strapped to the 5V_S0 5V
No Reboot mode (Panther Point will disable the TCO Timer system reboot 3D3V_S0 3.3V
CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0] 1D8V_S0 1.8V
feature). 1D5V_S0 1.5V
trace in a manner which does not introduce any stubs to 1D05V_VTT 1.05V
This signal has a weak internal pull-up.
INIT3_3V# CFG[0] trace. Route as needed from the opposite side of 0D85V_S0 0.95 - 0.85V
Note: The internal pull-up is disabled after PLTRST# deasserts. 0D75V_S0 0.75V
this series isolation resistor to the debug port. ITP
NOTE: This signal should not be pulled low. Leave as "No Connect".
4 INTVRMEN Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high
will drive the net to GND.
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
0.35V to 1.5V
0.4 to 1.25V
1.8V
S0

CPU Core Rail


4
CFG[2] PCIe Static x16 Lane 1: Normal Operation; Lane # definition 3D3V_VGA_S0 3.3V Graphics Core Rail
NOTE: This signal should always be pulled high 1V_VGA_S0 1V
Numbering Reversal. matches socket pin map definition 1
External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low.
NOTE: This signal should be pulled down to GND through 330 kOhms resistor 0:Lane Reversed
5V_USBX_S3 5V
1:Disabled - No Physical Display Port attached to 1D5V_S3 1.5V S3
CFG[4] Display Port Presence DDR_VREF_S3 0.75V
Embedded DisplayPort No connect for disable
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. strap 0:Enabled - An external Display Port device is connected 1
GNT2#/GPIO53 Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they BT+ 6V-14.1V AC Brick Mode only
to the Embedded Display Port Pull-down to GND through a
GNT1#/GPIO51 should be tied to the Vcc3_3 power rail. DCBATOUT 6V-14.1V
1K 5% resistor to enable port 5V_S5 5V All S states
5V_AUX_S5 5V
This signal is a strap for selecting DMI and FDI termination voltage. 3D3V_S5 3.3V
PCIE Port Bifurcation 00 = 1 x 8, 2 x 4 PCI Express 3D3V_AUX_S5 3.3V
For Ivy Bridge processor only implementation:
CFG[6:5] Straps 01 = reserved
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms 5% resistor. 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
For future processor compatibility: 10 = 2 x 8 PCI Express 1
It needs to be connected to PROC_SELECT through a 11 = 1 x 16 PCI Express

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1.0 kOhms 5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms 5% pull-up resistor 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
to

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PCH VccDFTERM. Reserved configuration
CFG[17:7] lands. A test point may

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Bit11 Bit 10 Boot BIOS Destination Powered by Li Coin Cell in G3
be placed on the board 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
0 1 Reserved

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1 0 PCI for these lands.
SATA1GP/ 1 1 SPI
GPIO19 0 0 LPC

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NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther
Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor

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in order to boot.
NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS
Destination Select to LPC/PCI by functional strap or via Boot BIOS

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Destination Bit will not affect SPI accesses initiated by Management
3 Engine or Integrated GbE LAN.
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NOTE: PCI Boot BIOS destination is not supported on mobile.
Reserved.
SATA2GP/
GPIO36
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
Sandy Bridge + Ivy Bridge Compatibility Requirements
Chief River Schematic Checklist Revision 1.5
PCIE Routing USB Table
NOTE: This signal should not be pulled high when strap is sampled.
Pair Device
Reserved Pin Name Configuration Schematic Notes LANE1 X
SATA3GP/ This signal has a weak internal pull-down. 0 USB3.0 port1
GPIO37 NOTE: The internal pull-down is disabled after PLTRST# deasserts. DDR3 VREF M1 and M3 Guidelines are required. LANE2 X 1 USB3.0 port2, with Debug Port
NOTE: This signal should not be pulled high when strap is sampled. DDR3 VREF Note: The M3 traces are routed to the Sandy Bridge Processor
Sandy Bridge + Ivy Bridge 2 USB2.0 port3
HDA_DOCK_EN# High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking reserved pins.
/GPIO33 isolation logic. This is an active-low-signal. When deasserted the external docking switch is in
LANE3 Mini Card1(WLAN) 3 X
isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio Ivy Bridge No change. 4 X
dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33. LANE4 x
5 Touch Panel
Signal has a weak internal pull-down. LANE5 X
If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect Connect DF_TVS signal of the PCH to PROC_SELECT# of the 6 HM76 NC
HDA_SDO Sandy Bridge + Ivy Bridge processor through a 1K5% series resistor. PROC_SELECT#
(default).If sampled high, the Flash Descriptor Security will be overridden. PROC_SELECT#
also needs a 2.2K5% pull up resistor to PCH VccDFTERM LANE6 Onboard LAN 7 HM76 NC
This strap should only be asserted high via external pull-up in manufacturing/debug environments &
ONLY. rail. 8 X
DF_TVS
Note: The weak internal pull-down is disabled after PLTRST# deasserts. Ivy Bridge No change. LANE7 X 9 X
Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine
after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode LANE8 X 10 CARD READER
and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down The POR for Ivy Bridge mobile parts is now 1.05 V. There is no 11 Mini Card (WLAN)
resistor. Sandy Bridge + Ivy Bridge longer a requirement for a separate VCCIO VR for Sandy Bridge
This signal has a weak internal pull-down. VCCIO VR 12 X
+ Ivy Bridge compatibility.
On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled Implementation
HDA_SYNC 13 CAMERA
low.
Needs to be pulled High for Chief River platform. Ivy Bridge No change.
Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is
2 sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND),
the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to Sandy Bridge + Ivy Bridge VCCSA_SELECT[0:1] which should be connected to SATA Table 2
isolate this signal from the codec during the strap phase. Refer to the example circuits provided in VCCSA_SEL VID[1:0] of the System Agent (SA) VR controller.
the latest Chief River platform design guide. connection to
VCCSA_VID[1:0] SATA
TLS Confidentiality
GPIO15 Low (0) Intel ME Crypto Transport Layer Security (TLS) cipher suite with no lines Ivy Bridge No change. Pair Device
confidentiality
High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality 0 HDD1
This signal has a weak internal pull-down.
NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. 1 X
Sandy Bridge + Ivy Bridge The total motherboard length for a pair of consecutive PCI
NOTE: A strong pull-up may be needed for GPIO functionality Layout Requirement Express Tx lanes be length matched within 100 mils (2.54 mm) 2 X
on PCI Express
LVDS Detected. 3 X
Gen3 Ivy Bridge No change.
When '1'- LVDS is detected; When '0'- LVDS is not detected.
L_DDC_DATA 4 ODD1
This signal has a weak internal pull-down.
NOTE:The internal pull-down is disabled after PLTRST# deasserts. 5 X
GT Core VR Sandy Bridge + Ivy Bridge Depending on the PDDG specifications, some IVB GT2 SKUs may
Implementation require a new VR controller and 2 phase VCC GT core VR.
Port B Detected
When '1'- Port B is detected; When '0'- Port B is not detected
SDVO_CTRLDATA Ivy Bridge No change.
This signal has a weak internal pull-down.
NOTE:The internal pull-down is disabled after PLTRST# deasserts.
Processor PCI Sandy Bridge + Ivy Bridge To support Gen 3 PCI Express Graphic, the value of the AC
Port C Detected. Express (PCIe Gen3): coupling capacitor should be 180 - 265 nF.
When '1'- Port C is detected; When '0'- Port C is not detected Graphics
DDPC_CTRLDATA
This signal has a weak internal pull-down. Guidelines Ivy Bridge No change.
NOTE:The internal pull-down is disabled after PLTRST# deasserts.
Port D Detected.
When '1'- Port D is detected; When '0'- Port D is not detected
DDPD_CTRLDATA
This signal has a weak internal pull-down.
NOTE:The internal pull-down is disabled after PLTRST# deasserts.
The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL
1 GPIO28 Voltage Regulator is disabled.If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap
1
setting when use as the chipset test interface.Refer to the latest platform debug design guide and
platform design guide for more details.
NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# M14 DIS
deasserts.
Wistron Corporation
GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). Taipei Hsien 221, Taiwan, R.O.C.
GPIO29/
If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. Title
SLP_LAN#
A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default,
the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable Table of Content
Size Document Number Rev
GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can

http://vinafix.vn
A2
OAK14 Chief River DIS A00
03-05-1512:40:57 PM
be used as a normal GPIO (default to GPI).
Wednesday, September 05, 2012
03-05-151:22:21 PM
Date: Sheet 3 of 105

A B C D E
5 4 3 2 1
SSID = CPU

Layout Note:
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
VCCP_CPU
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_CPU_RXN_PCH_TXN[3:0] PEG_ICOMPO G1
DMI_CPU_RXN_PCH_TXN0 M2 G4
DMI_CPU_RXN_PCH_TXN1 DMI_RX#0 PEG_RCOMPO
P6 DMI_RX#1
DMI_CPU_RXN_PCH_TXN2 P1
DMI_CPU_RXN_PCH_TXN3 DMI_RX#2
P10 DMI_RX#3 PEG_RX#0 H22
Layout Note: 19 DMI_CPU_RXP_PCH_TXP[3:0]
DMI_CPU_RXP_PCH_TXP0 N3
PEG_RX#1 J21
B22
DMI_RX0 PEG_RX#2
DMI trace length 2000~8000mil DMI_CPU_RXP_PCH_TXP1 P7 DMI_RX1 PEG_RX#3 D21

DMI
DMI_CPU_RXP_PCH_TXP2 P3 A19
DMI_CPU_RXP_PCH_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17

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19 DMI_CPU_TXN_PCH_RXN[3:0] PEG_RX#6 B14
DMI_CPU_TXN_PCH_RXN0 K1 D13
DMI_TX#0 PEG_RX#7

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DMI_CPU_TXN_PCH_RXN1 M8 A11 CPU_RXN_C_dGPU_TXN7
DMI_CPU_TXN_PCH_RXN2 DMI_TX#1 PEG_RX#8 CPU_RXN_C_dGPU_TXN6
N4 B10

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DMI_CPU_TXN_PCH_RXN3 DMI_TX#2 PEG_RX#9 CPU_RXN_C_dGPU_TXN5
R2 DMI_TX#3 PEG_RX#10 G8

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A8 CPU_RXN_C_dGPU_TXN4
19 DMI_CPU_TXP_PCH_RXP[3:0] DMI_CPU_TXP_PCH_RXP0 PEG_RX#11 CPU_RXN_C_dGPU_TXN3
K3 DMI_TX0 PEG_RX#12 B6
DMI_CPU_TXP_PCH_RXP1 M7 H8 CPU_RXN_C_dGPU_TXN2

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DMI_CPU_TXP_PCH_RXP2 DMI_TX1 PEG_RX#13 CPU_RXN_C_dGPU_TXN1
P4 DMI_TX2 PEG_RX#14 E5 CPU_RXN_C_dGPU_TXN[7..0] 83
DMI_CPU_TXP_PCH_RXP3 T3 K7 CPU_RXN_C_dGPU_TXN0
DMI_TX3 PEG_RX#15

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PEG_RX0 K22

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PEG_RX1 K19 CPU_RXP_C_dGPU_TXP[7..0] 83
19 FDI_CPU_TXN_PCH_RXN[7:0] PEG_RX2 C21

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C FDI_CPU_TXN_PCH_RXN0
FDI_CPU_TXN_PCH_RXN1
U7
W11
FDI0_TX#0 PEG_RX3 D19
C19
C
FDI_CPU_TXN_PCH_RXN2 FDI0_TX#1 PEG_RX4
W1 FDI0_TX#2 PEG_RX5 D16
FDI_CPU_TXN_PCH_RXN3 AA6 C13
FDI_CPU_TXN_PCH_RXN4 FDI0_TX#3 PEG_RX6
Layout Note: FDI_CPU_TXN_PCH_RXN5
W6
V4
FDI1_TX#0 PEG_RX7 D12
C11 CPU_RXP_C_dGPU_TXP7 dGPU_RXN_C_CPU_TXN[8..15] 83
FDI1_TX#1 PEG_RX8
FDI trace length 2000~6500mil FDI_CPU_TXN_PCH_RXN6 CPU_RXP_C_dGPU_TXP6

PCI EXPRESS -- GRAPHICS


Y2 FDI1_TX#2 PEG_RX9 C9
FDI_CPU_TXN_PCH_RXN7 AC9 F8 CPU_RXP_C_dGPU_TXP5
FDI1_TX#3 PEG_RX10

Intel(R) FDI
C8 CPU_RXP_C_dGPU_TXP4
PEG_RX11 CPU_RXP_C_dGPU_TXP3 dGPU_RXP_C_CPU_TXP[8..15] 83
19 FDI_CPU_TXP_PCH_RXP[7:0] PEG_RX12 C5
FDI_CPU_TXP_PCH_RXP0 U6 H6 CPU_RXP_C_dGPU_TXP2
FDI_CPU_TXP_PCH_RXP1 FDI0_TX0 PEG_RX13 CPU_RXP_C_dGPU_TXP1
W10 FDI0_TX1 PEG_RX14 F6
FDI_CPU_TXP_PCH_RXP2 W3 K6 CPU_RXP_C_dGPU_TXP0
FDI_CPU_TXP_PCH_RXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_CPU_TXP_PCH_RXP4 W7 G22
FDI_CPU_TXP_PCH_RXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_CPU_TXP_PCH_RXP6 AA3 D23
FDI_CPU_TXP_PCH_RXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
FDI_FSYNC0 AA11 C17
19 FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 AC12 K15
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 F17
19 FDI_INT
FDI_INT U11 FDI_INT PEG_TX#8 F14 CPU_TXN_dGPU_RXN7 1OPS 2 C401 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN8
PEG_TX#9 A15 CPU_TXN_dGPU_RXN6 1OPS 2 C402 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN9
19 FDI_LSYNC0
FDI_LSYNC0 AA10
FDI0_LSYNC PEG_TX#10 J14 CPU_TXN_dGPU_RXN5 1OPS 2 C403 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN10
19 FDI_LSYNC1
FDI_LSYNC1 AG8
FDI1_LSYNC PEG_TX#11 H13 CPU_TXN_dGPU_RXN4 1OPS 2 C404 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN11
PEG_TX#12 M10 CPU_TXN_dGPU_RXN3 1OPS 2 C405 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN12
PEG_TX#13 F10 CPU_TXN_dGPU_RXN2 1OPS 2 C406 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN13
PEG_TX#14 D9 CPU_TXN_dGPU_RXN1 1OPS 2 C407 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN14
J4 CPU_TXN_dGPU_RXN0 1OPS 2 C408 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN15
B VCCP_CPU R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
PEG_TX#15 B
AD2 EDP_ICOMPO PEG_TX0 F22
AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
Layout Note: AG4
AF4
EDP_AUX# PEG_TX4 G19
B18
EDP_AUX PEG_TX5
Signal Routing Guideline: PEG_TX6 K17
eDP

EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_TX7 G17
AC3 E14 CPU_TXP_dGPU_RXP7 1OPS 2 C409 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP8
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. AC4
EDP_TX#0 PEG_TX8
C15 CPU_TXP_dGPU_RXP6 1OPS 2 C410 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP9
EDP_TX#1 PEG_TX9
AE11 EDP_TX#2 PEG_TX10 K13 CPU_TXP_dGPU_RXP5 1OPS 2 C411 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP10
AE7 EDP_TX#3 PEG_TX11 G13 CPU_TXP_dGPU_RXP4 1OPS 2 C412 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP11
PEG_TX12 K10 CPU_TXP_dGPU_RXP3 1OPS 2 C413 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP12
AC1 EDP_TX0 PEG_TX13 G10 CPU_TXP_dGPU_RXP2 1OPS 2 C414 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP13
AA4 EDP_TX1 PEG_TX14 D8 CPU_TXP_dGPU_RXP1 1OPS 2 C415 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP14
AE10 EDP_TX2 PEG_TX15 K4 CPU_TXP_dGPU_RXP0 1OPS 2 C416 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP15
AE6 EDP_TX3
Note:
IVY-BRIDGE-GP-NF PEG with reversal type.
71.00IVY.A0U

A M14 DIS
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU(PCIE/DMI/FDI)
Size Document Number Rev

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03-05-1512:40:57 PM
A3 A00
OAK14 Chief River DIS
03-05-151:22:21 PM Date: W ednesday, September 05, 2012 Sheet 4 of 105
5 4 3 2 1
SSID = CPU

D CPU1B 2 OF 9
D
J3 CLK_EXP_P CLK_EXP_P 20
BCLK CLK_EXP_N
BCLK# H2 CLK_EXP_N 20

MISC

CLOCKS
22 H_SNB_IVB# H_SNB_IVB# F49 RN503
PROC_SELECT# CLK_DP_P_R1
DPLL_REF_CLK AG3 4
CLK_DP_N_R2
TPAD14-OP-GP TP501 1 SKTOCC#_R C57
DPLL_REF_CLK# AG1 3 VCCP_CPU Layout Note:
PROC_DETECT# SRN1KJ-7-GP Checking the connector pin's LAYOUT

VCCP_CPU
TPAD14-OP-GP TP502 1 H_CATERR# C49 R507
R501 CATERR# 4K99R2F-L-GP

THERMAL
w
1 2 H_PROCHOT# 1 2

w
62R2J-GP H_PECI A48 AT30 SM_DRAMRST# SM_DRAMRST# 37
22,27 H_PECI PECI SM_DRAMRST#

w
.ro
R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP
SM_RCOMP0

DDR3
MISC
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 R508 1 2 25D5R2F-GP
27,38,40,42 H_PROCHOT# PROCHOT# SM_RCOMP1
BG43 SM_RCOMP_2 R511 1 2 200R2F-L-GP

se
56R2J-4-GP SM_RCOMP2

fix
H_THERMTRIP#
22 H_THERMTRIP# D45 THERMTRIP# Layout Note:
Signal Routing Guideline:

.c
Layout Note: N53 XDP_PRDY# XDP_PRDY# 71 SM_RCOMP keep routing length less than 500 mils.
PRDY#

om
C R501, R513 place near to CPU PREQ# N55 XDP_PREQ# XDP_PREQ# 71 Trace width = 15mil C
L56 XDP_TCLK
TCK XDP_TMS VCCP_CPU
TMS L55

PWR MANAGEMENT
J58 XDP_TRST#
TRST#

JTAG & BPM


19 H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
PM_SYNC TDI XDP_TDO RN501
TDO L59
R504 XDP_TDI 1 8
0R0402-PAD XDP_TMS 2 7
1 2 H_CPUPW RGD_R B46 XDP_TDO 3 6
22 H_CPUPW RGD UNCOREPWRGOOD
K58 XDP_DBRESET# XDP_DBRESET# 19 4
XDP 5
DBR#
1 R503 2
10KR2J-3-GP SRN51J-1-GP
37 VDDPW RGOOD VDDPW RGOOD BE45 G58 XDP_BPM0 XDP_BPM0 71
SM_DRAMPWROK BPM#0 XDP_BPM1 RN502
BPM#1 E55 XDP_BPM1 71
E59 XDP_BPM2 XDP_BPM2 71 XDP_TRST# 1 4
BPM#2 XDP_BPM3 XDP_TCLK
G55 2 3
BPM#3
G59 XDP_BPM4
XDP_BPM3
XDP_BPM4
71
71
XDP
BUF_CPU_RST# BPM#4 XDP_BPM5 SRN51J-GP
18,27,31,65,71,83 PLT_RST# 1 2 D44 RESET# BPM#5 H60 XDP_BPM5 71
J59 XDP_BPM6 XDP_BPM6 71
BPM#6
1

R510 J61 XDP_BPM7 XDP_BPM7 71


BPM#7
1

1K5R2F-2-GP
R509 C501
698R2F-GP DY SC220P50V2KX-3GP
2
2

IVY-BRIDGE-GP-NF
71.00IVY.A0U
B Layout Note:
B
C501 place near to CPU

H_CPUPW RGD PLT_RST# XDP_DBRESET#


1

EC501 EC502 EC503


SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
DY DY DY
2

reserve for EMI Request

A M14 DIS
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU(THERMAL/CLOCK/PM)
Size Document Number Rev

http://vinafix.vn
03-05-1512:40:57 PM
A3 A00
OAK14 Chief River DIS
03-05-151:22:21 PM Date: W ednesday, September 05, 2012 Sheet 5 of 105
5 4 3 2 1

SSID = CPU

CPU1D 4 OF 9
CPU1C 3 OF 9
M_B_DQ[63:0]
M_A_DQ[63:0] 15 M_B_DQ[63:0]
M_B_DQ0 AL4
14 M_A_DQ[63:0] SB_DQ0
D M_A_DQ0 AG6 M_B_DQ1 AL1 BA34 D
M_A_DQ1 SA_DQ0 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 15
AJ6 SA_DQ1 SA_CK0 AU36 M_A_DIMA_CLK_DDR0 14 AN3 SB_DQ2 SB_CK#0 AY34 M_B_DIMB_CLK_DDR#0 15
M_A_DQ2 AP11 AV36 M_B_DQ3 AR4 AR22
M_A_DQ3 SA_DQ2 SA_CK#0 M_A_DIMA_CLK_DDR#0 14 M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIMB_CKE0 15
AL6 SA_DQ3 SA_CKE0 AY26 M_A_DIMA_CKE0 14 AK4 SB_DQ4
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ4 M_B_DQ6 SB_DQ5
AJ8 SA_DQ5 AN4 SB_DQ6
M_A_DQ6 AL8 M_B_DQ7 AR1
M_A_DQ7 SA_DQ6 M_B_DQ8 SB_DQ7
AL7 SA_DQ7 AU4 SB_DQ8
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36
M_A_DQ9 SA_DQ8 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIMB_CLK_DDR1 15
AP6 SA_DQ9 SA_CK1 AT40 M_A_DIMA_CLK_DDR1 14 AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIMB_CLK_DDR#1 15
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27
M_A_DQ11 SA_DQ10 SA_CK#1 M_A_DIMA_CLK_DDR#1 14 M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIMB_CKE1 15
AV9 SA_DQ11 SA_CKE1 BB26 M_A_DIMA_CKE1 14 AU3 SB_DQ12
M_A_DQ12 AR6 M_B_DQ13 AR3
M_A_DQ13 SA_DQ12 M_B_DQ14 SB_DQ13
AP8 SA_DQ13 AY2 SB_DQ14
M_A_DQ14 AT13 M_B_DQ15 BA3
SA_DQ14 SB_DQ15

w
M_A_DQ15 AU13 M_B_DQ16 BE9
M_A_DQ16 SA_DQ15 M_B_DQ17 SB_DQ16
BC7 SA_DQ16 BD9 SB_DQ17 SB_CS#0 BE41

w
M_A_DQ17 M_B_DQ18 M_B_DIMB_CS#0 15
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIMA_CS#0 14 BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIMB_CS#1 15
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12

w
M_A_DQ19 SA_DQ18 SA_CS#1 M_A_DIMA_CS#1 14 M_B_DQ20 SB_DQ19
BB11 SA_DQ19 BF8 SB_DQ20

.ro
M_A_DQ20 BA7 M_B_DQ21 BD10
M_A_DQ21 SA_DQ20 M_B_DQ22 SB_DQ21
BA9 SA_DQ21 BD14 SB_DQ22
M_A_DQ22 BB9 M_B_DQ23 BE13

se
M_A_DQ23 SA_DQ22 M_B_DQ24 SB_DQ23
AY13 SA_DQ23 BF16 SB_DQ24 SB_ODT0 AT43 M_B_DIMB_ODT0 15
M_A_DQ24 AV14 AY40 M_B_DQ25 BE17 BG47
SA_DQ24 SA_ODT0 M_A_DIMA_ODT0 14 SB_DQ25 SB_ODT1 M_B_DIMB_ODT1 15

fix
M_A_DQ25 AR14 BA41 M_B_DQ26 BE18
M_A_DQ26 SA_DQ25 SA_ODT1 M_A_DIMA_ODT1 14 M_B_DQ27 SB_DQ26
AY17 SA_DQ26 BE21 SB_DQ27
M_A_DQ27 M_B_DQ28

.c
AR19 SA_DQ27 BE14 SB_DQ28
M_A_DQ28 BA14 M_B_DQ29 BG14
SA_DQ28 SB_DQ29

om
C M_A_DQ29 AU14 M_B_DQ30 BG18 M_B_DQS#[7:0] 15
C
M_A_DQ30 SA_DQ29 M_B_DQ31 SB_DQ30 M_B_DQS#0
BB14 SA_DQ30 M_A_DQS#[7:0] 14 BF19 SB_DQ31 SB_DQS#0 AL3
M_A_DQ31 BB17 AL11 M_A_DQS#0 M_B_DQ32 BD50 AV3 M_B_DQS#1
M_A_DQ32 SA_DQ31 SA_DQS#0 M_A_DQS#1 M_B_DQ33 SB_DQ32 SB_DQS#1 M_B_DQS#2
BA45 SA_DQ32 SA_DQS#1 AR8 BF48 SB_DQ33 SB_DQS#2 BG11
M_A_DQ33 AR43 AV11 M_A_DQS#2 M_B_DQ34 BD53 BD17 M_B_DQS#3
M_A_DQ34 SA_DQ33 SA_DQS#2 M_A_DQS#3 M_B_DQ35 SB_DQ34 SB_DQS#3 M_B_DQS#4
AW48 SA_DQ34 SA_DQS#3 AT17 BF52 SB_DQ35 SB_DQS#4 BG51
M_A_DQ35 BC48 AV45 M_A_DQS#4 M_B_DQ36 BD49 BA59 M_B_DQS#5
M_A_DQ36 SA_DQ35 SA_DQS#4 M_A_DQS#5 M_B_DQ37 SB_DQ36 SB_DQS#5 M_B_DQS#6
BC45 SA_DQ36 SA_DQS#5 AY51 BE49 SB_DQ37 SB_DQS#6 AT60

DDR SYSTEM MEMORY B


M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ38 BD54 AK59 M_B_DQS#7
SA_DQ37 SA_DQS#6 SB_DQ38 SB_DQS#7
DDR SYSTEM MEMORY A

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53


M_A_DQ39 SA_DQ38 SA_DQS#7 M_B_DQ40 SB_DQ39
AY48 SA_DQ39 BF56 SB_DQ40
M_A_DQ40 BA49 M_B_DQ41 BE57
M_A_DQ41 SA_DQ40 M_B_DQ42 SB_DQ41
AV49 SA_DQ41 BC59 SB_DQ42
M_A_DQ42 BB51 M_B_DQ43 AY60
M_A_DQ43 SA_DQ42 M_B_DQ44 SB_DQ43
AY53 SA_DQ43 BE54 SB_DQ44
M_A_DQ44 BB49 M_A_DQS[7:0] 14 M_B_DQ45 BG54 M_B_DQS[7:0] 15
M_A_DQ45 SA_DQ44 M_A_DQS0 M_B_DQ46 SB_DQ45 M_B_DQS0
AU49 SA_DQ45 SA_DQS0 AJ11 BA58 SB_DQ46 SB_DQS0 AM2
M_A_DQ46 BA53 AR10 M_A_DQS1 M_B_DQ47 AW59 AV1 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS1 M_A_DQS2 M_B_DQ48 SB_DQ47 SB_DQS1 M_B_DQS2
BB55 SA_DQ47 SA_DQS2 AY11 AW58 SB_DQ48 SB_DQS2 BE11
M_A_DQ48 BA55 AU17 M_A_DQS3 M_B_DQ49 AU58 BD18 M_B_DQS3
M_A_DQ49 SA_DQ48 SA_DQS3 M_A_DQS4 M_B_DQ50 SB_DQ49 SB_DQS3 M_B_DQS4
AV56 SA_DQ49 SA_DQS4 AW45 AN61 SB_DQ50 SB_DQS4 BE51
M_A_DQ50 AP50 AV51 M_A_DQS5 M_B_DQ51 AN59 BA61 M_B_DQS5
M_A_DQ51 SA_DQ50 SA_DQS5 M_A_DQS6 M_B_DQ52 SB_DQ51 SB_DQS5 M_B_DQS6
AP53 SA_DQ51 SA_DQS6 AT56 AU59 SB_DQ52 SB_DQS6 AR59
M_A_DQ52 AV54 AK54 M_A_DQS7 M_B_DQ53 AU61 AK61 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS7 M_B_DQ54 SB_DQ53 SB_DQS7
AT54 SA_DQ53 AN58 SB_DQ54
M_A_DQ54 AP56 M_B_DQ55 AR58
M_A_DQ55 SA_DQ54 M_B_DQ56 SB_DQ55
AP52 SA_DQ55 AK58 SB_DQ56
M_A_DQ56 AN57 M_B_DQ57 AL58
M_A_DQ57 SA_DQ56 M_B_DQ58 SB_DQ57
AN53 SA_DQ57 AG58 SB_DQ58
B M_A_DQ58 M_B_DQ59 B
AG56 SA_DQ58 AG59 SB_DQ59
M_A_DQ59 AG53 M_B_DQ60 AM60
M_A_DQ60 SA_DQ59 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AN55 SA_DQ60 M_A_A[15:0] 14 AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AG55 SA_DQ62 SA_MA1 BB34 AH60 SB_DQ63 SB_MA2 BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ63 SA_MA2 M_A_A3 SB_MA3 M_B_A4
SA_MA3 BD35 SB_MA4 BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA4 M_A_A5 SB_MA5 M_B_A6
SA_MA5 AU34 SB_MA6 BG30
BB32 M_A_A6 15 M_B_BS0 BG39 BD29 M_B_A7
SA_MA6 M_A_A7 SB_BS0 SB_MA7 M_B_A8
14 M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 15 M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
14 M_A_BS1 BF36 AY32 M_A_A8 15 M_B_BS2 AT22 BE28 M_B_A9
SA_BS1 SA_MA8 M_A_A9 SB_BS2 SB_MA9 M_B_A10
14 M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 SB_MA10 BD43
BE37 M_A_A10 AT28 M_B_A11
SA_MA10 M_A_A11 SB_MA11 M_B_A12
SA_MA11 BA30 SB_MA12 AV28
BC30 M_A_A12 15 M_B_CAS# AV43 BD46 M_B_A13
SA_MA12 M_A_A13 SB_CAS# SB_MA13 M_B_A14
14 M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 15 M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
14 M_A_RAS# BD39 AY28 M_A_A14 15 M_B_W E# BD45 AU22 M_B_A15
SA_RAS# SA_MA14 M_A_A15 SB_WE# SB_MA15
14 M_A_W E# AT41 SA_WE# SA_MA15 AU26

IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF 71.00IVY.A0U
71.00IVY.A0U

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
A3 A00
OAK14 Chief River DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
Date: W ednesday, September 05, 2012 Sheet
1
6 of 105
5 4 3 2 1

SSID = CPU

CFG2
CPU1E 5 OF 9
D D

1
PEG Static Lane Reversal
R702
1KR2J-1-GP 1: Normal Operation; Lane #
71 CFG0 CFG0 B50 N59 BCLK_ITP 1 TP721 OPS CFG[2] definition matches socket pin map definition
TP701 CFG1 CFG0 BCLK_ITP BCLK_ITP# TP722
1 C51 N58 1

2
CFG1 BCLK_ITP#
CFG2 B54 0:Lane Reversed
TP702 CFG3 CFG2
1 D53 CFG3
TP703 1 CFG4 A51 N42
CFG5 CFG4 RSVD30
C53 CFG5 RSVD31 L42
CFG6 C55 L45
CFG6 RSVD32
H49 CFG7 RSVD33 L47
A55 CFG8
H51 CFG9
K49 CFG10 RSVD34 M13

w
K53 CFG11 RSVD35 M14 Display Port Presence Strap
F53 CFG12 RSVD36 U14

w
G53 W14 1: Disabled; No Physical Display Port
CFG13 RSVD37
L51 P13 CFG[4] attached to Embedded Display Port

w
CFG14 RSVD38
F51 CFG15

.ro
D52 0: Enabled; An external Display Port device is
CFG16
L53 CFG17 RSVD39 AT49 connected to the Embedded Display Port
K24

se
RSVD40
H43

RESERVED
VCC_VAL_SENSE

fix
K43 VSS_VAL_SENSE RSVD41 AH2
RSVD42 AG13

.c
RSVD43 AM14
H45 VAXG_VAL_SENSE RSVD44 AM15

om
C K45 CFG5 C
VSSAXG_VAL_SENSE

RSVD45 N50 CFG6 PCIE Port Bifurcation Straps


TP719 1VCC_DIE_SENSE F48 VCC_DIE_SENSE

1
G48 RSVD47 R701 R704 CFG[6:5] 11: 1x16 PCI Express
H48
K48
RSVD6 DY 1KR2J-1-GP OPS 1KR2J-1-GP 10: 2 x8 - PCI Express
RSVD7
A4

2
DC_TEST_A4
DC_TEST_C4 C4 01: Reserved
BA19 D3 DC_TEST_C4_D3
RSVD8 DC_TEST_D3
AV19 RSVD9 DC_TEST_D1 D1 00: 1x8, 2x4 PCI Express
AT21 RSVD10 DC_TEST_A58 A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 C59 TP_DC_TEST_A59_C59
RSVD12 DC_TEST_C59
AY21 RSVD13 DC_TEST_A61 A61
BA22 C61 TP_DC_TEST_A61_C61
RSVD14 DC_TEST_C61
AY22 RSVD15 DC_TEST_D61 D61
AU19 RSVD16 DC_TEST_BD61 BD61
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59 TP_DC_TEST_BE59_BE61
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG59_BG61
BD26 RSVD21 DC_TEST_BG58 BG58
BG22 RSVD22 DC_TEST_BG4 BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3 DC_TEST_BE3_BG3
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 BE1 DC_TEST_BE1_BG1
B RSVD26 DC_TEST_BE1 B
BE24 RSVD27 DC_TEST_BD1 BD1

IVY-BRIDGE-GP-NF
71.00IVY.A0U

M14 DIS
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RESERVED)
Size Document Number Rev
A3 A00
OAK14 Chief River DIS

http://vinafix.vn
03-05-1512:40:57 PM
Date: W ednesday, September 05, 2012 Sheet 7 of 105

5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1

SSID = CPU
VCC_CORE
CPU1F POWER 6 OF 9

VCCP_CPU

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1
VCC_CORE
VCCIO1
AF46 8.5A

1
C801

C803

C804

C805

C806

C807

C808

C809

C810

C811

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AG48
ULV 33A VCCIO3
VCCIO4
AG50
A26 AG51
2

2
VCC1 VCCIO5

1
C830

C831

C832

C833

C835

C834

C836

C838
A29 AJ17
VCC2 VCCIO6
A31 AJ21
VCC3 VCCIO7
A34 AJ25 DY

2
VCC4 VCCIO8
A35 AJ43
VCC5 VCCIO9
D A38 AJ47 D
VCC6 VCCIO10
A39 AK50
VCC7 VCCIO11
A42 AK51
VCC8 VCCIO12
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C26 AL14
VCC9 VCCIO13
C27 AL15
1

VCC10 VCCIO14
C812

C813

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C32 AL16
VCC11 VCCIO15
C34 AL20
VCC12 VCCIO16
C37 AL22
2

VCC13 VCCIO17

1
C843

C845

C844

C837

C840

C839

C841

C842
C39 AL26
VCC14 VCCIO18
C42 AL45
VCC15 VCCIO19
D27 AL48 DY DY DY DY

2
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37 AM21
VCC19 VCCIO23
D39 AM43

PEG IO AND DDR IO


VCC20 VCCIO24
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP
D42 AM47
VCC21 VCCIO25
E26 AN20
VCC22 VCCIO26
E28 AN42
VCC23 VCCIO27
1

1
C814

C815

C816

C817

C819

C818

C820

C821

C822

C823

C894

C896

C892

C888

C884
E32 AN45
VCC24 VCCIO28
E34 AN48
VCC25 VCCIO29
DY DY E37 DY
2

2
VCC26
E38
VCC27

w CORE SUPPLY
F25
VCC28
F26
VCC29 VCCP_CPU
F28

w
VCC30
F32
VCC31
F34

w
VCC32
F37 AA14
VCC33 VCCIO30

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
F38 AA15
VCC34 VCCIO31

.ro
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

F42 AB17
VCC35 VCCIO32
G42 AB20
VCC36 VCCIO33

1
C887

C891

C890

C846

C848

C847

C881

C882

C883

C886
H25 AC13
1

VCC37 VCCIO34
C824

C825

C826

C827

C828

C829

H26 AD16

se
VCC38 VCCIO35
H28 AD18 DY DY DY DY

2
VCC39 VCCIO36
DY DY DY H29 AD21
2

VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38

fix
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
H38 AF20

.c
VCC45 VCCIO42
H40 AG15
VCC46 VCCIO43
C J25 AG16 C

1
VCC47 VCCIO44

om

C895

C897

C893

C889

C885
J26 AG17
VCC48 VCCIO45
J28 AG20
VCC49 VCCIO46
J29 AG21 DY DY DY

2
VCC50 VCCIO47
J32 AJ14
VCC51 VCCIO48
J34 AJ15
VCC52 VCCIO49
J35
VCC53
J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62
K35
VCC63
K37
VCC64
K39
VCC66 H_SNB_IVB#_PWRCTRL TP801
K42
VCC67 VCCIO_SEL
BC22 1 VCCPQ Output Decoupling CAP Recommendation:
L25
VCC68
L28
VCC69
1 x 1 uF (0402)
L33
VCC70
L36
VCC71 +V1.05S_VCCPQE_R R812 VCCP_CPU VCCP_CPU
L40
VCC72 0R0402-PAD
N26
VCC73

QUIET
RAILS
N30 AM25 2 1
VCC74 VCCPQE1
N34 AN22
Layout Note:

1
VCC75 VCCPQE2
N38

1
VCC76 C802 R803, R804, R805 need close to CPU
SC1U6D3V2KX-GP R805 R804
Alert# signal must be routed between the Clock and Data

2
75R2F-2-GP 130R2F-1-GP
lines to reduce the cross talk between them
R803

2
43R2J-GP
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALERT# 42
H_CPU_SVIDCLK
VIDSCLK
B43 H_CPU_SVIDCLK 42 Need place Pull Hi

SVID
C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT 42
at IMVP page
VCC_CORE
B B
Layout Note:

1
R801 1. PH/PL resisors place close CPU
100R2F-L1-GP-U 2. SENSE signal recommend differential routing

2
F43 VCCSENSE VCCSENSE 43

SENSE LINES
VCC_SENSE VSSSENSE
G43 VSSSENSE 43
VSS_SENSE

1
VCCP_CPU
R802
100R2F-L1-GP-U

1
AN16
VCCIO_SENSE R807
AN17

2
VSS_SENSE_VCCIO
10R2F-L-GP

VCCIO_SENSE 45

2
VSSIO_SENSE 45

1
IVY-BRIDGE-GP-NF
71.00IVY.A0U R806
10R2F-L-GP
Layout Note:

2
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing
Voltage Rail Voltage(V) Iccmax(A)
VCC_CORE 0.3~1.52 33
VAXG 0~1.52 29 (GT2)
VCCIO 1.05 8.5
VDDQ 1.5 5
VCCSA 0.675~0.9 4
VCCPLL 1.8 1.2

A A

Refer to CPU EDS V.1.7.5


M14 DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)
Size Document Number Rev
A2 A00
OAK14 Chief River DIS

http://vinafix.vn
03-05-1512:40:57 PM
Date: Wednesday, September 05, 2012 Sheet 8 of 105

03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1

SSID = CPU
Voltage Rail Voltage(V) Iccmax(A)
VCC_CORE 0.3~1.52 33
Layout Note: VAXG 0~1.52 29 (GT2)
CPU1G POWER 7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width
VCCIO 1.05 8.5
+V_SM_VREF_CNT VDDQ 1.5 5
VCC_GFXCORE ULV GT2 33A
SM_VREF
AY43 VCCSA 0.675~0.9 3
AA46

VREF
VAXG1 RN902
AB47
VAXG2
VCCPLL 1.8 1.2
D AB50 BE7 DDR_WR_VREFA 3 2 D
VAXG3 SA_DIMM_VREFDQ

1
SC22U6D3V5MX-2GP
C901

C902
SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP
C903

C904
SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP
C905

SC22U6D3V5MX-2GP
C906
AB51 BG7 DDR_WR_VREFB 4 1
AB52
VAXG4 SB_DIMM_VREFDQ DY
AB53
VAXG5
Refer to CPU EDS V2.0

2
VAXG6 SRN1KJ-7-GP
AB55
VAXG7
AB56
VAXG8
AB58
VAXG9
AB59
VAXG10
AC61
VAXG11 1D5V_S0
AD47
VAXG12
AD48
VAXG13 5A

C938
SC10U6D3V3MX-GP

C939
SC10U6D3V3MX-GP

C940
SC10U6D3V3MX-GP

C941
SC10U6D3V3MX-GP

C942
SC10U6D3V3MX-GP

C943
SC10U6D3V3MX-GP
AD50

1
VAXG14
AD51 AJ28

- 1.5V RAILS
VAXG15 VDDQ1
AD52 AJ33
VAXG16 VDDQ2
AD53 AJ36
DY

2
VAXG17 VDDQ3
AD55 AJ40
VAXG18 VDDQ4

1
C927
SC1U6D3V2KX-GP

C928
SC1U6D3V2KX-GP

C929
SC1U6D3V2KX-GP

C930
SC1U6D3V2KX-GP

C931
SC1U6D3V2KX-GP

C932
SC1U6D3V2KX-GP

C933
SC1U6D3V2KX-GP

C934
SC1U6D3V2KX-GP

C935
SC1U6D3V2KX-GP

C936
SC1U6D3V2KX-GP
AD56 AL30
VAXG19 VDDQ5
AD58 AL34
VAXG20 VDDQ6
AD59 AL38 DY DY

2
VAXG21 VDDQ7
AE46 AL42
VAXG22 VDDQ8
N45 AM33
VAXG23 VDDQ9
P47 AM36
VAXG24 VDDQ10

w
P48 AM40
VAXG25 VDDQ11
P50 AN30
VAXG26 VDDQ12

C944
SC1U6D3V2KX-GP

C945
SC1U6D3V2KX-GP

C946
SC1U6D3V2KX-GP

C947
SC1U6D3V2KX-GP

C948
SC1U6D3V2KX-GP

C949
SC1U6D3V2KX-GP
P51 AN34

w
1

1
VAXG27 VDDQ13
P52 AN38
VAXG28 VDDQ14
P53 AR26

DDR3
w
VAXG29 VDDQ15
DY DY P55 AR28

GRAPHICS
2

2
VAXG30 VDDQ16

1
C919
SC10U6D3V3MX-GP

C920
SC10U6D3V3MX-GP

C921
SC10U6D3V3MX-GP

C922
SC10U6D3V3MX-GP

C923
SC10U6D3V3MX-GP

C924
SC10U6D3V3MX-GP

C925
SC4D7U6D3V3KX-GP

C926
SC10U6D3V3MX-GP
P56 AR30
VAXG31 VDDQ17

.ro
P61 AR32
VAXG32 VDDQ18
T48 AR34

2
VAXG33 VDDQ19 DY
T58 AR36
VAXG34 VDDQ20
T59 AR40

se
VAXG35 VDDQ21
T61 AV41
VAXG36 VDDQ22
U46 AW26
C953 VAXG37 VDDQ23
SC1U6D3V2KX-GP

C951
SC1U6D3V2KX-GP

C952
SC1U6D3V2KX-GP

C954
SC1U6D3V2KX-GP

C950
SC1U6D3V2KX-GP
V47 BA40
VAXG38 VDDQ24
1

fix
V48 BB28
VAXG39 VDDQ25
V50 BG33
VAXG40 VDDQ26
DY DY V51
2

2
VAXG41
V52

.c
VAXG42
V53
VAXG43
C V55 C
VAXG44

om
V56
VAXG45
V58
VAXG46
V59
VAXG47
W50
VAXG48
W51
VAXG49
W52
VAXG50
W53
VAXG51
W55
VAXG52
W56
VCC_GFXCORE VAXG53
W61
VAXG54
Y48
VAXG55
Y61
VAXG56
Layout Note:

1
1. PH/PL resisors place close CPU R901 +V1.5S_VCCD_Q 1D5V_S0
100R2F-L1-GP-U
2. SENSE signal recommend differential routing R903
0R0402-PAD

QUIET RAILS
AM28 2 1

SENSE
LINES
2
VCC_AXG_SENSE VCCDQ1
44 VCC_AXG_SENSE F45 AN26
VSS_AXG_SENSE VAXG_SENSE VCCDQ2
44 VSS_AXG_SENSE G45

1
VSSAXG_SENSE

C937
SC1U6D3V2KX-GP
1
R902

2
100R2F-L1-GP-U

1.8V RAIL
2
BB3
VCCPLL1
BC1
1D8V_S0 VCCPLL2
BC4
1.2A VCCPLL3
C907
SC1U6D3V2KX-GP

C908
SC1U6D3V2KX-GP

C955
SC10U6D3V5KX-1GP
BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP
1

1
VDDQ_SENSE TP_VDDQ_VSS TP902 TPAD14-OP-GP
BA43 1
VSS_SENSE_VDDQ

SENSE LINES
L17
DY
2

VCCSA1
L21
VCCSA2
N16
VCCSA3
N20
0D85V_S0 VCCSA4
N22
ULV 4A

SA RAIL
B VCCSA5 B
P17
VCCSA6 VCCSA_SENSE
P20 U10
VCCSA7 VCCSA_SENSE VCCSA_SENSE 48
R16
1

VCCSA8
C913
SC10U6D3V3MX-GP

C912
SC10U6D3V3MX-GP

C911
SC10U6D3V3MX-GP

C910
SC10U6D3V3MX-GP

C909
SC10U6D3V3MX-GP

R18
VCCSA9
VCCSA Power Select
R21
VCCSA10
U15

VCCSA VID
2

VCCSA11
DY DY V16 Voltage(ULV) VID[0] VID[1]
VCCSA12 VCCSA_SEL0
V17 D48
VCCSA13 VCCSA_VID0 VCCSA_SEL0 48

lines
V18 D49 VCCSA_SEL1
VCCSA14 VCCSA_VID1 VCCSA_SEL1 48
V21 0.9 0 0

2
1
VCCSA15
W20
VCCSA16 RN901
1

1
C918
SC1U6D3V2KX-GP

C917
SC1U6D3V2KX-GP

C916
SC1U6D3V2KX-GP

C915
SC1U6D3V2KX-GP

C914
SC1U6D3V2KX-GP

SRN1KJ-7-GP 0.85 0 1

DY DY
2

IVY-BRIDGE-GP-NF 0.775 1 0

3
4
71.00IVY.A0U
0.75 1 1

A A

M14 DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)
Size Document Number Rev
A2 A00
OAK14 Chief River DIS

http://vinafix.vn
03-05-1512:40:57 PM
Date: Wednesday, September 05, 2012 Sheet 9 of 105

03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1

SSID = CPU
CPU1H 8 OF 9
CPU1I 9 OF 9

A13 VSS1 VSS91 AM38 BG17 VSS181 VSS250 M4


A17 VSS2 VSS92 AM4 BG21 VSS182 VSS251 M58
A21 VSS3 VSS93 AM42 BG24 VSS183 VSS252 M6
A25 VSS4 VSS94 AM45 BG28 VSS184 VSS253 N1
D A28 VSS5 VSS95 AM48 BG37 VSS185 VSS254 N17 D
A33 VSS6 VSS96 AM58 BG41 VSS186 VSS255 N21
A37 VSS7 VSS97 AN1 BG45 VSS187 VSS256 N25
A40 VSS8 VSS98 AN21 BG49 VSS188 VSS257 N28
A45 VSS9 VSS99 AN25 BG53 VSS189 VSS258 N33
A49 VSS10 VSS100 AN28 BG9 VSS190 VSS259 N36
A53 VSS11 VSS101 AN33 C29 VSS191 VSS260 N40
A9 VSS12 VSS102 AN36 C35 VSS192 VSS261 N43
AA1 VSS13 VSS103 AN40 C40 VSS193 VSS262 N47
AA13 VSS14 VSS104 AN43 D10 VSS194 VSS263 N48
AA50 VSS15 VSS105 AN47 D14 VSS195 VSS264 N51
AA51 VSS16 VSS106 AN50 D18 VSS196 VSS265 N52
AA52 VSS17 VSS107 AN54 D22 VSS197 VSS266 N56
AA53 VSS18 VSS108 AP10 D26 VSS198 VSS267 N61
AA55 VSS19 VSS109 AP51 D29 VSS199 VSS268 P14

w
AA56 VSS20 VSS110 AP55 D35 VSS200 VSS269 P16
AA8 VSS21 VSS111 AP7 D4 VSS201 VSS270 P18

w
AB16 VSS22 VSS112 AR13 D40 VSS202 VSS271 P21
AB18 AR17 D43 P58

w
AB21
VSS23
VSS24
VSS113
VSS114 AR21 D46
VSS203
VSS204 VSS VSS272
VSS273 P59

.ro
AB48 VSS25 VSS115 AR41 D50 VSS205 VSS274 P9
AB61 VSS26 VSS116 AR48 D54 VSS206 VSS275 R17
AC10 AR61 D58 R20

se
VSS27 VSS117 VSS207 VSS276
AC14 VSS28 VSS118 AR7 D6 VSS208 VSS277 R4
AC46 VSS29 VSS119 AT14 E25 VSS209 VSS278 R46

fix
AC6 VSS30 VSS120 AT19 E29 VSS210 VSS279 T1
AD17 VSS31 VSS121 AT36 E3 VSS211 VSS280 T47

.c
AD20 VSS32 VSS122 AT4 E35 VSS212 VSS281 T50
AD4 AT45 E40 T51
VSS33
VSS VSS123 VSS213 VSS282

om
C AD61 AT52 F13 T52 C
VSS34 VSS124 VSS214 VSS283
AE13 VSS35 VSS125 AT58 F15 VSS215 VSS284 T53
AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55
AF1 VSS37 VSS127 AU11 F29 VSS217 VSS286 T56
AF17 VSS38 VSS128 AU28 F35 VSS218 VSS287 U13
AF21 VSS39 VSS129 AU32 F40 VSS219 VSS288 U8
AF47 VSS40 VSS130 AU51 F55 VSS220 VSS289 V20
AF48 VSS41 VSS131 AU7 G51 VSS221 VSS290 V61
AF50 VSS42 VSS132 AV17 G6 VSS222 VSS291 W13
AF51 VSS43 VSS133 AV21 G61 VSS223 VSS292 W15
AF52 VSS44 VSS134 AV22 H10 VSS224 VSS293 W18
AF53 VSS45 VSS135 AV34 H14 VSS225 VSS294 W21
AF55 VSS46 VSS136 AV40 H17 VSS226 VSS295 W46
AF56 VSS47 VSS137 AV48 H21 VSS227 VSS296 W8
AF58 VSS48 VSS138 AV55 H4 VSS228 VSS297 Y4
AF59 VSS49 VSS139 AW13 H53 VSS229 VSS298 Y47
AG10 VSS50 VSS140 AW43 H58 VSS230 VSS299 Y58
AG14 VSS51 VSS141 AW61 J1 VSS231 VSS300 Y59
AG18 VSS52 VSS142 AW7 J49 VSS232
AG47 VSS53 VSS143 AY14 J55 VSS233
AG52 VSS54 VSS144 AY19 K11 VSS234
AG61 AY30 K21


VSS55 VSS145 VSS235
AG7 VSS56 VSS146 AY36 K51 VSS236

A5,A57,BC61,BG5
AH4 AY4 K8 A5

BG57,C3,E1,E61
VSS57 VSS147 VSS237 VSS_NCTF_1#A5

NCTF TEST PIN


AH58 VSS58 VSS148 AY41 L16 VSS238 VSS_NCTF_2#A57 A57
AJ13 VSS59 VSS149 AY45 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ16 VSS60 VSS150 AY49 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ20 VSS61 VSS151 AY55 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ22 VSS62 VSS152 AY58 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ26 VSS63 VSS153 AY9 L34 VSS243 VSS_NCTF_13#E1 E1
AJ30 VSS64 VSS154 BA1 L38 VSS244 VSS_NCTF_14#E61 E61

NCTF
AJ34 VSS65 VSS155 BA11 L43 VSS245
AJ38 VSS66 VSS156 BA17 L48 VSS246
AJ42 VSS67 VSS157 BA21 L61 VSS247 VSS_NCTF_4 BD3
AJ45 VSS68 VSS158 BA26 M11 VSS248 VSS_NCTF_5 BD59
AJ48 VSS69 VSS159 BA32 M15 VSS249 VSS_NCTF_6 BE4
AJ7 VSS70 VSS160 BA48 VSS_NCTF_7 BE58
AK1 VSS71 VSS161 BA51 VSS_NCTF_11 C58
AK52 VSS72 VSS162 BB53 VSS_NCTF_12 D59
AL10 VSS73 VSS163 BC13
AL13 VSS74 VSS164 BC5
AL17 VSS75 VSS165 BC57
AL21 BD12 IVY-BRIDGE-GP-NF
VSS76 VSS166
AL25 VSS77 VSS167 BD16 71.00IVY.A0U
AL28 VSS78 VSS168 BD19
AL33 VSS79 VSS169 BD23
AL36 VSS80 VSS170 BD27
AL40 VSS81 VSS171 BD32
AL43 VSS82 VSS172 BD36
AL47 VSS83 VSS173 BD40
AL61 VSS84 VSS174 BD44
AM13 VSS85 VSS175 BD48
AM20 VSS86 VSS176 BD52
AM22 VSS87 VSS177 BD56
AM26 VSS88 VSS178 BD8
AM30 VSS89 VSS179 BE5
AM34 VSS90 VSS180 BG13
A M14 DIS A

Wistron Corporation
IVY-BRIDGE-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
71.00IVY.A0U Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A3 A00
OAK14 Chief River DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
10 of 105
5 4 3 2 1

D D

w
w
w
.ro
se
fix
.c
om
C C

(Blanking)

B B

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XDP
Size Document Number Rev
A3 A00
OAK14 Chief River DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
11 of 105
5 4 3 2 1

D D

w
w
w
.ro
se
fix
.c
om
C C

(Blanking)

B B

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
OAK14 Chief River DIS A00
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
12 of 105
5 4 3 2 1

D D

w
w
w
.ro
se
fix
.c
om
C C

(Blanking)

B B

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
OAK14 Chief River DIS A00
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
13 of 105
5 4 3 2 1

SSID = MEMORY
DM1
6 M_A_A[15:0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# 6
M_A_A4 A3 RAS# SA0_DIMA
M_A_A5
92
A4 WE#
113 M_A_WE# 6
SA1_DIMA
Note:
91 115 M_A_CAS# 6
M_A_A6 A5 CAS# SA0 DIM0 = 0, SA1_DIM0 = 0
90
A6

1
M_A_A7 86 114 M_A_DIMA_CS#0 6 SO-DIMMA SPD Address is 0xA0

1
M_A_A8 A7 CS0# R1402
89 121 M_A_DIMA_CS#1 6
A8 CS1#
M_A_A9 85
A9
R1401 0R0402-PAD SO-DIMMA TS Address is 0x30
M_A_A10 107 73 0R0402-PAD
A10/AP CKE0 M_A_DIMA_CKE0 6
M_A_A11 84 74 M_A_DIMA_CKE1 6

2
M_A_A12 A11 CKE1
83

2
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 6
M_A_A14 A13 CK0
D 80 103 M_A_DIMA_CLK_DDR#0 6 D
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 6
6 M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 6
CK1#
109
6 M_A_BS0 BA0
108 11
DDR_VREF_S3 6 M_A_BS1 BA1 DM0
6 M_A_DQ[63:0] 28
M_A_DQ0 DM1
5 46
Layout Note: M_A_DQ1 7
DQ0 DM2
63
1

M_A_DQ2 DQ1 DM3


Place these caps 15
DQ2 DM4
136
R1405 M_A_DQ3 17 153
0R0402-PAD
close to VREF_CA M_A_DQ4 DQ3 DM5
4 170
M_A_DQ5 DQ4 DM6
6 187
M_VREF_CA_DIMMA M_A_DQ6 DQ5 DM7
16
2

M_A_DQ7 DQ6
18 200 PCH_SMBDATA 15,20,69
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK 15,20,69
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 3D3V_S0
33 198
DQ10 EVENT#
1

M_A_DQ11 35
M_A_DQ12 DQ11
C1427

C1428

C1426

22 199
DY
SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

M_A_DQ13 DQ12 VDDSPD


24
2

M_A_DQ14 DQ13 SA0_DIMA


34 197

1
DQ14 SA0

w
M_A_DQ15 36 201 SA1_DIMA C1401
M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP
39
M_A_DQ17 DQ16
41 77

w
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125

w
M_A_DQ20 DQ19 NC#/TEST
40
DQ20 Close to DIMM1.199
M_A_DQ21 42 75
DQ21 VDD1

.ro
M_A_DQ22 50 76
DDR_VREF_S3 M_A_DQ23 DQ22 VDD2
52 81
Layout Note: M_A_DQ24 57
DQ23 VDD3
82
M_A_DQ25 DQ24 VDD4
Place these caps 59 87

se
DQ25 VDD5
1

M_A_DQ26 67 88
R1404
close to VREF_DQ M_A_DQ27 DQ26 VDD6
69 93
0R0402-PAD M_A_DQ28 DQ27 VDD7
56 94
DQ28 VDD8 1D5V_S3

fix
M_A_DQ29 58 99
M_VREF_DQ_DIMMA M_A_DQ30 DQ29 VDD9
68 100
2

M_A_DQ31 DQ30 VDD10


70 105
M_A_DQ32 DQ31 VDD11
129 106

.c
ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U10V5ZY-1GP
M_A_DQ33 DQ32 VDD12

TC1401

C1403

C1404

C1405

C1406

C1407

C1408
131 111
DQ33 VDD13

1
C M_A_DQ34 141 112 C
1

DQ34 VDD14

om
M_A_DQ35 143 117
M_A_DQ36 DQ35 VDD15 DY DY DY DY DY
C1411

C1423

C1429

130 118
DY
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP

2
M_A_DQ37 DQ36 VDD16
132 123
2

M_A_DQ38 DQ37 VDD17


140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
146 13
M_A_DQ45 DQ44 VSS
148 14

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_A_DQ46 DQ45 VSS

C1414

C1415

C1416

C1417
158 19

1
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
Layout Note: 165 26

2
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
Place these caps 177
DQ51 VSS
32
M_A_DQ52 164 37
0D75V_S0 close to VTT1 and M_A_DQ53 DQ52 VSS
166 38
VTT2. M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
176 44
M_A_DQ56 DQ55 VSS
181 48
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
Layout Note:
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_A_DQ59 DQ58 VSS


C1419

C1420

C1418

193 55
1

M_A_DQ60 DQ59 VSS


180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ61 182 61
DY M_A_DQ62 192
DQ61 VSS
65
2

M_A_DQ63 DQ62 VSS


194 66
DQ63 VSS
6 M_A_DQS#[7:0] 71
M_A_DQS#0 VSS 1D5V_S0 1D5V_S3
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133 1 2
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 152
DQS4# VSS
138
DY
M_A_DQS#6 DQS5# VSS C1421
169 139
M_A_DQS#7 DQS6# VSS SCD1U10V2KX-5GP
186 144
DQS7# VSS
6 M_A_DQS[7:0] 145
M_A_DQS0 VSS
12 150 1 2
B M_A_DQS1 DQS0 VSS B
29 151
M_A_DQS2 47
DQS1 VSS
155 DY
M_A_DQS3 DQS2 VSS C1424
64 156
M_A_DQS4 DQS3 VSS SCD1U10V2KX-5GP
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188
DQS7 VSS
168
172
Layout Note:
VSS
6 M_A_DIMA_ODT0
116
ODT0 VSS
173 For S3 reduction circuit's 1D5V return pass.
120 178
6 M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should 15,37 DDR3_DRAMRST#
30
RESET# VSS
190
EC1401 1 2 195
have width=20mil; SCD1U10V2KX-5GP VSS
196
spacing=20 mil
0D75V_S0
DY 203
VSS
205
VTT1 VSS
204 206
VTT2 VSS

DDR3-204P-119-GP-U
62.10017.Z81

A A

M14 DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
DNE40 14 CR DIS

http://vinafix.vn
03-05-1512:40:57 PM
Date: Wednesday, September 05, 2012 Sheet 14 of 105

03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1

SSID = MEMORY DM2


6 M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 6
M_B_A4 A3 RAS#
92 113 M_B_WE# 6
M_B_A5 A4 WE#
M_B_A6
91
A5 CAS#
115 M_B_CAS# 6 Note:
90
M_B_A7 A6 SO-DIMMB SPD Address is 0xA4
86 114 M_B_DIMB_CS#0 6
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 6 SO-DIMMB TS Address is 0x34
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIMB_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIMB_CKE1 6
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 6
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 6
DDR_VREF_S3 M_B_A15 A14 CK0#
D 78 D
A15
79 102 M_B_DIMB_CLK_DDR1 6
6 M_B_BS2 A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 6
CK1#
109
1

6 M_B_BS0 BA0
108 11
R1505 6 M_B_BS1 BA1 DM0
6 M_B_DQ[63:0] 28
0R0402-PAD M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_VREF_CA_DIMMB M_B_DQ2 DQ1 DM3
15 136
2

M_B_DQ3 DQ2 DM4


17 153
M_B_DQ4 DQ3 DM5
4 170
Layout Note: M_B_DQ5 6
DQ4 DM6
187
M_B_DQ6 DQ5 DM7
Place these caps 16
DQ6
1

M_B_DQ7 18 200
close to VREF_CA M_B_DQ8 DQ7 SDA PCH_SMBDATA 14,20,69
C1523

C1524

C1522

21 202
DY
SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

M_B_DQ9 DQ8 SCL PCH_SMBCLK 14,20,69


23
2

M_B_DQ10 DQ9 3D3V_S0


33 198
M_B_DQ11 DQ10 EVENT# 3D3V_S0
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD R1507
24

1
M_B_DQ14 DQ13 SA0_DIMB SA1_DIMB
34 197 1 2
M_B_DQ15 DQ14 SA0 SA1_DIMB C1501
36 201
DQ15 SA1

w
M_B_DQ16 39 SCD1U10V2KX-5GP 10KR2J-3-GP

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 R1506
51 122

w
M_B_DQ19 DQ18 NC#2 1D5V_S3 SA0_DIMB
53 125 1 2
DDR_VREF_S3 M_B_DQ20 DQ19 NC#/TEST
40

w
M_B_DQ21 DQ20
42
DQ21 VDD1
75 Close to DIMM1.199 0R0402-PAD
M_B_DQ22 50 76
DQ22 VDD2

.ro
M_B_DQ23 52 81
1

M_B_DQ24 DQ23 VDD3


57 82
R1503 M_B_DQ25 DQ24 VDD4
59 87
0R0402-PAD M_B_DQ26 DQ25 VDD5
67 88
Layout Note:

se
M_B_DQ27 DQ26 VDD6
69 93
M_VREF_DQ_DIMMB M_B_DQ28 DQ27 VDD7
Place these caps 56 94
2

M_B_DQ29 DQ28 VDD8


close to VREF_DQ 58 99
DQ29 VDD9

fix
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10 1D5V_S3
70 105
M_B_DQ32 DQ31 VDD11
129 106
1

M_B_DQ33 DQ32 VDD12


131 111

.c
M_B_DQ34 DQ33 VDD13
C1515

C1516

C1517

141 112
DY
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP

M_B_DQ35 DQ34 VDD14


C 143 117 C
2

DQ35 VDD15

om
M_B_DQ36 130 118

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
M_B_DQ37 DQ36 VDD16

C1503

C1504

C1507

C1509

C1510
132 123

SC10U6D3V5KX-1GP
1

1
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18

C1508
142
M_B_DQ40 147
DQ39
2
DY DY DY DY

2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
0D75V_S0 M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
Layout Note:

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_B_DQ49 DQ48 VSS

C1511

C1512

C1513

C1514
165 26
DQ49 VSS

1
Place these caps M_B_DQ50 175 31
M_B_DQ51 DQ50 VSS
177 32
close to VTT1 and M_B_DQ52 DQ51 VSS DY
C1518

C1519

C1521

164 37
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2
1

VTT2. M_B_DQ53 DQ52 VSS


166 38
M_B_DQ54 DQ53 VSS
174 43
DY M_B_DQ55 176
DQ54 VSS
44
2

M_B_DQ56 DQ55 VSS


181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 192
DQ61 VSS
65
Layout Note:
M_B_DQ63 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
6 M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
B M_B_DQS2 DQS1 VSS B
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_B_DIMB_ODT0 ODT0 VSS
120 178
6 M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
14,37 DDR3_DRAMRST# RESET# VSS
All VREF traces should EC1501 1 2
VSS
195
have width=20mil;
0D75V_S0
DY SCD1U10V2KX-5GP
203
VSS
196
205
spacing=20 mil VTT1 VSS
204 206
VTT2 VSS

DDR3-204P-90-GP
62.10017.U81

A A

M14 DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2
Size Document Number Rev
A2 A00
OAK14 Chief River DIS

http://vinafix.vn
03-05-1512:40:57 PM
Date: Wednesday, September 05, 2012 Sheet 15 of 105

03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1

D D

w
w
w
.ro
se
fix
.c
om
C C

(Blanking)

B B

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
OAK14 Chief River DIS A00
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
16 of 105
5 4 3 2 1

SSID = PCH

D D

3D3V_S0

RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA 27 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45

SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

3
4
SDVO_STALLP AM40
LVDS_DDC_CLK_R RN1706
49 LVDS_DDC_CLK_R
49 LVDS_DDC_DATA_R
T40
LVDS_DDC_DATA_R K47 L_DDC_CLK
AP39 SRN2K2J-1-GP
Layout Note:
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40 Close HDMI port

w
RN1702 L_CTRL_CLK T45
L_BKLT_EN L_CTRL_DATA L_CTRL_CLK
2 3 P39

2
1
L_CTRL_DATA

w
1 4 LVDS_VDD_EN
LVDS_IBG AF37 P38

w
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
SRN100KJ-6-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51

.ro
1
AE48 LVD_VREFH
R1701
Layout Note: AE47 AT49

se
2K37R2F-GP LVD_VREFL DDPB_AUXN
DDPB_AUXP AT47
Place near PCH; DDPB_HPD AT40 HDMI_PCH_DET 51

fix
trace to trace spacing=20mil 49 LVDSA_CLK# AK39

2
LVDSA_CLK#

LVDS
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51

.c
DDPB_0P AV40 HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51

om
C AM47 AV46 C
49 LVDSA_DATA1# LVDSA_DATA#1 DDPB_1P HDMI_DATA1_R 51

Digital Display Interface


49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
Layout Note: AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P42
Layout Note:
DDPC_CTRLDATA
LVDS signal trace HDMI trace length to DC CAP. max 10000mil
length max 4000mil 49 LVDSB_CLK# AF40 LVDSB_CLK#
49 LVDSB_CLK AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
49 LVDSB_DATA0# AH45 LVDSB_DATA#0 DDPC_HPD AT38
49 LVDSB_DATA1# AH47 LVDSB_DATA#1
49 LVDSB_DATA2# AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
3D3V_S0 AH43 AY45
49 LVDSB_DATA0 LVDSB_DATA0 DDPC_1P
49 LVDSB_DATA1 AH49 LVDSB_DATA1 DDPC_2N BA47
49 LVDSB_DATA2 AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
3
4

RN1707
SRN2K2J-1-GP N48 CRT_BLUE DDPD_CTRLCLK M43
P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
2
1

B B
DDPD_AUXN AT45

CRT
CRT_DDCCLK T39 AT43
CRT_DDCDATA CRT_DDC_CLK DDPD_AUXP
M40 CRT_DDC_DATA DDPD_HPD BH41

DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1

Layout Note: R1702 DDPD_3P BG42

Place near PCH; 1KR2J-1-GP PANTHER-GP-NF


trace to trace spacing=30mil 71.0HM76.A0U
2

A M14 DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)
Size Document Number Rev
A3 A00
OAK14 Chief River DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
Date: W ednesday, September 05, 2012 Sheet
1
17 of 105
5 4 3 2 1

SSID = PCH

PCH1E 5 OF 10
3D3V_S0 AY7
RN1803 RSVD1
RSVD2 AV7
SRN10KJ-6-GP BG26 AU3
PCH_GPIO50 TP1 RSVD3
8 1 BJ26 TP2 RSVD4 BG4
7 2 PCH_GPIO54 BH25
PCH_GPIO02 TP3
6 3 BJ16 TP4 RSVD5 AT10
D 5 4 BOARD_ID1 BOARD_ID1 20 BG16 BC8 D
TP5 RSVD6
AH38 TP6
AH37 TP7 RSVD7 AU2
3D3V_S0 AK43 AT4
RN1804 TP8 RSVD8
AK45 TP9 RSVD9 AT3
SRN10KJ-6-GP C18 AT1
INT_PIRQD# TP10 RSVD10
8 1 N30 TP11 RSVD11 AY3
7 2 KB_LED_BL_DET H3 AT5
INT_PIRQC# TP12 RSVD12
6 3 AH12 TP13 RSVD13 AV3
5 4 PCH_GPIO04 AM4 AV1
TP14 RSVD14
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
3D3V_S0 K24 BB5
RN1805 TP17 RSVD17
L24 TP18 RSVD18 BB3
SRN10KJ-6-GP AB46 BB7
TP19 RSVD19

w
8 1 PCH_GPIO52 AB45 BE8
TP20 RSVD20

RSVD
7 2 INT_PIRQB# BD4
RSVD21

w
6 3 SATA_ODD_DA# BF6
INT_PIRQA# RSVD22
5 4
Layout Note:

w
B21 AV5
TP21 RSVD23 USB Table

.ro
Trace Length : M20 TP22 RSVD24 AV10
PCH ~~9000mil~~Cap~~1000mil~~CONN AY16 TP23
BG46 AT8 Pair Device

se
TP24 RSVD25

RSVD26 AY5 0 USB3.0 port2

fix
RSVD27 BA2
USB3_RX1_N BE28 1 USB3.0 port1, with Debug Port
USB3.0/2.0 Mapping Table 62 USB3_RX1_N USB3_RX2_N USB3RN1

.c
62 USB3_RX2_N BC30 USB3RN2 RSVD28 AT12
BE32 USB3RN3 RSVD29 BF3 2 USB2.0 port3

om
C USB 3.0 Port USB 2.0 port BJ32 USB3RN4
C

62 USB3_RX1_P
USB3_RX1_P BC28 USB3RP1 3 NC
Port 1 Port 0 USB3_RX2_P BE30
62 USB3_RX2_P
BF32
USB3RP2
USB3RP3
USB2.0 Signal Group 4 NC
Port 2 Port 1 BG32 USB3RP4 USBP0N C24 USB_PN0 62
62 USB3_TX1_N USB3_TX1_N AV26 USB3TN1 USBP0P A24 USB_PP0 62 5 Touch Panel
Port 3 Port 2 62 USB3_TX2_N USB3_TX2_N BB26 USB3TN2 USBP1N C25 USB_PN1 62
AU28 USB3TN3 USBP1P B25 USB_PP1 62 6 HM76 NC
Port 4 Port 3 AY30 USB3TN4 USBP2N C26 USB_PN2 82
62 USB3_TX1_P USB3_TX1_P AU26 USB3TP1 USBP2P A26 USB_PP2 82 7 HM76 NC
62 USB3_TX2_P USB3_TX2_P AY26 K28
USB3TP2 USBP3N
AV28 USB3TP3 USBP3P H28 8 NC
AW30 E28 USB_PN4 1 TP1803
USB3TP4 USBP4N
USBP4P D28 USB_PP4 1 TP1804 9 NC
USBP5N C28 USB_PN5 49
USBP5P A28 USB_PP5 49 10 Card reader
USBP6N C29
USBP6P B29 11 WLAN
INT_PIRQA# K40 N28
PIRQA# USBP7N
INT_PIRQB# K38 PIRQB# USBP7P M28 12 NC

PCI
INT_PIRQC# H38 L30
Boot Bios Strap PIRQC# USBP8N
INT_PIRQD# G38 PIRQD# USBP8P K30 13 CAMERA
USBP9N G30
PCH_GPIO50 C46 E30
REQ1#/GPIO50 USBP9P

USB
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location PCH_GPIO52 C44 REQ2#/GPIO52 USBP10N C30 USB_PN10 32 1. USB Ext. port 9 (HS) External debug port
3D3V_S0 PCH_GPIO54 E40 A30
REQ3#/GPIO54 USBP10P USB_PP10 32 use on Chief River platform.
USBP11N L32 USB_PN11 65
0 0 LPC R1808 1 2 10KR2J-3-GP BBS_BIT1 D47 K32 USB_PP11 65
2. 2011 July; Microsoft will support USB3.0
GNT1#/GPIO51 USBP11P
B
TP1801 1 PCH_GPIO53 E42 GNT2#/GPIO53 USBP12N G32 debug--> Port1 useable. B
PCI_GNT3# F46 E32
0 1 Reserved DY GNT3#/GPIO55 USBP12P
USBP13N C32 USB_PN13 49
USBP13P A32 USB_PP13 49
PCH_GPIO02 G42
1 0 PIRQE#/GPIO2
Reserved 56 SATA_ODD_DA# G40 PIRQF#/GPIO3
PCH_GPIO04 C33 USB_RBIAS
C42
KB_LED_BL_DET D44 PIRQG#/GPIO4 USBRBIAS# 1
R1811
2
Layout Note:
PIRQH#/GPIO5
1 1 SPI(Default) 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended impedance
USBRBIAS B33 spacing to other signal=15mil
TP1802 1 PCI_PME# K10 PME# 2. Length < 500mil
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 61
PLTRST# OC0#/GPIO59
OC1#/GPIO40 K20
2 1 PCI_GNT3# B17 USB_OC#4_5
DY 71 CLK_PCI_LPC R1807 1 LPC 2 22R2J-2-GP CLK_PCI_LPC_R H49
OC2#/GPIO41
C16
USB_OC#4_5 61
R1801 R1805 CLKOUT_PCI0 OC3#/GPIO42
20 CLK_PCI_FB 1 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16
4K7R2J-2-GP 27 CLK_PCI_KBC R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16 R1812
CLKOUT_PCI2 OC5#/GPIO9 8K2R2J-3-GP
K42 CLKOUT_PCI3 OC6#/GPIO10 D14
H40 C14 OC# 1 2 3D3V_S5
CLKOUT_PCI4 OC7#/GPIO14
2

A16 Swap Override jumper EC1802


DY DY EC1804DY EC1805 PANTHER-GP-NF RN1802
SC4D7P50V2CN-1GP

1
SC4D7P50V2CN-1GP

71.PANTH.00U USB_OC#0_1 1 4
SC10P50V2JN-4GP

3D3V_S5
PCI_GNT#3 Low = A16 swap override/Top-Block USB_OC#4_5 2 3
Swap Override enabled
High = Default SRN10KJ-5-GP

A M14 DIS A

R1823
5,27,31,65,71,83 PLT_RST# 1 2 PCI_PLTRST# Wistron Corporation
0R0402-PAD 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.


1

R1816 C1801
100KR2J-1-GP SC220P50V2KX-3GP Title
DY DY
PCH (PCI/USB/NVRAM)
2
2

Size Document Number Rev


A3 A00
DNE40 14 CR DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
Date: W ednesday, September 05, 2012 Sheet
1
18 of 105
5 4 3 2 1

SSID = PCH

PCH1C 3 OF 10
4 DMI_CPU_TXN_PCH_RXN[3:0] FDI_CPU_TXN_PCH_RXN[7:0] 4
DMI_CPU_TXN_PCH_RXN0 BC24 BJ14 FDI_CPU_TXN_PCH_RXN0
DMI_CPU_TXN_PCH_RXN1 DMI0RXN FDI_RXN0 FDI_CPU_TXN_PCH_RXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_CPU_TXN_PCH_RXN2 BG18 BE14 FDI_CPU_TXN_PCH_RXN2
DMI_CPU_TXN_PCH_RXN3 DMI2RXN FDI_RXN2 FDI_CPU_TXN_PCH_RXN3
BG20 DMI3RXN FDI_RXN3 BH13
D BC12 FDI_CPU_TXN_PCH_RXN4 D
4 DMI_CPU_TXP_PCH_RXP[3:0] FDI_RXN4
DMI_CPU_TXP_PCH_RXP0 BE24 BJ12 FDI_CPU_TXN_PCH_RXN5
DMI_CPU_TXP_PCH_RXP1 DMI0RXP FDI_RXN5 FDI_CPU_TXN_PCH_RXN6
BC20 DMI1RXP FDI_RXN6 BG10
DMI_CPU_TXP_PCH_RXP2 BJ18 BG9 FDI_CPU_TXN_PCH_RXN7
DMI_CPU_TXP_PCH_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_CPU_TXP_PCH_RXP[7:0] 4
BG14 FDI_CPU_TXP_PCH_RXP0
4 DMI_CPU_RXN_PCH_TXN[3:0] DMI_CPU_RXN_PCH_TXN0 FDI_RXP0 FDI_CPU_TXP_PCH_RXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_CPU_RXN_PCH_TXN1 AW20 BF14 FDI_CPU_TXP_PCH_RXP2
DMI_CPU_RXN_PCH_TXN2 DMI1TXN FDI_RXP2 FDI_CPU_TXP_PCH_RXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_CPU_RXN_PCH_TXN3 AV18 BE12 FDI_CPU_TXP_PCH_RXP4
DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CPU_TXP_PCH_RXP5
4 DMI_CPU_RXP_PCH_TXP[3:0] DMI_CPU_RXP_PCH_TXP0 FDI_RXP5 FDI_CPU_TXP_PCH_RXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_CPU_RXP_PCH_TXP1 AY20 BH9 FDI_CPU_TXP_PCH_RXP7
DMI_CPU_RXP_PCH_TXP2 DMI1TXP FDI_RXP7
Layout Note: DMI_CPU_RXP_PCH_TXP3
AY18
AU18
DMI2TXP
DMI3TXP

w
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT FDI_INT 4
routing length less than 500 1D05V_PCH DSWODVREN - On Die DSW VR Enable

w
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 4
mils. DMI_ZCOMP FDI_FSYNC0

w
DMI_IRCOMP keep W=4 mils and HIGH Enabled (DEFAULT)
R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1

.ro
routing length less than 500 LOW Disabled
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0

se
BB10 FDI_LSYNC1 FDI_LSYNC1 4
FDI_LSYNC1

fix
RTC_AUX_S5

DSW ODVREN RTC_AUX_S5

.c
DSWVRMEN A18
DSW ODVREN R1917 1 2 330KR2J-L1-GP

om
C R1911 1 2 10KR2J-3-GP C
DY

System Power Management


3D3V_S0 TP1907 1 SUSACK# C12 E22 PCH_DPW ROK R1927 1 2 PM_RSMRST#
SUSACK# DPWROK 0R0402-PAD
R1905 1 2 10KR2J-3-GP
5 XDP_DBRESET# K3 B9 PCH_W AKE#
SYS_RESET# WAKE# 3D3V_S0

36 SYS_PW ROK P12 N3 PM_CLKRUN# 1 R1929 2 PM_CLKRUN#_EC 27


SYS_PWROK CLKRUN#/GPIO32 0R0402-PAD PM_CLKRUN# R1919 1 2 8K2R2J-3-GP

27,36 S0_PW R_GOOD 1 R1921 2 PW ROK L22 PWROK SUS_STAT#/GPIO61 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
0R0402-PAD 1 R1916 2
0R0402-PAD
1 2 MEPW ROK L10 N14 SUS_CLK 1 R1925 2
45,46,47,93 RUNPW ROK
R1907 DY 0R2J-2-GP APWROK SUSCLK/GPIO62 0R0402-PAD
PCH_SUSCLK_KBC 27
PCH_SUSCLK_KBC

37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP


DRAMPWROK SLP_S5#/GPIO63

2
R1924 EC1901
27 RSMRST#_KBC 1 2 PM_RSMRST# C21 H4 PM_SLP_S4# PM_SLP_S4# 27,46 SC4D7P50V2CN-1GP DY

1
0R0402-PAD RSMRST# SLP_S4#

SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# 27,36,37,47


SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3#

27 PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903


PWRBTN# SLP_A#

27,86 AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904


B ACPRESENT/GPIO31 SLP_SUS# B

27 BATLOW # BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC 5


BATLOW#/GPIO72 PMSYNCH

PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905


RI# SLP_LAN#/GPIO29

PANTHER-GP-NF
Sequence: 71.PANTH.00U
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

3D3V_S5
SYS_PW ROK S0_PW R_GOOD RUNPW ROK
RN1901
8 1 BATLOW #
1

7 2 PM_RI# EC1907 EC1902 EC1903


6 3 SUS_PW R_ACK SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
5 4 PCH_W AKE#
DY DY DY
2

SRN10KJ-6-GP

R1909 1 2 100KR2J-1-GP AC_PRESENT


R1920 2 1 10KR2J-3-GP PM_SLP_LAN# PM_DRAM_PW RGD RSMRST#_KBC AC_PRESENT
DY
A M14 DIS A
1

EC1904 EC1905 EC1906


SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
DY DY DY Wistron Corporation
2

R1908 2 1 10KR2J-3-GP PM_RSMRST#


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R1926 1 2 100KR2J-1-GP SYS_PW ROK
R1904 1
DY 2 100KR2J-1-GP PW ROK Title

reserve for EMI Request PCH (DM I/FDI/PM)


Size Document Number Rev
A3 A00
DNE40 14 CR DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
Date: W ednesday, September 05, 2012 Sheet
1
19 of 105
5 4 3 2 1

SSID = PCH S5 power rail CLKREQ#: 3D3V_S5

PCIECLKRQ[0]# SMB_CLK 4 1 RN2003


SMB_DATA 3 2 SRN2K2J-1-GP
3D3V_S5 PCIECLKRQ[7:3]#
RN2001
1 8 PCIE_CLK_REQ6# PCIE_CLK_RQ6# SML0_DATA 1 8 RN2004
2 7 PCIE_CLK_REQ3# PCIE_CLK_RQ3# PCH1B 2 OF 10 SML0_CLK 2 7 SRN2K2J-2-GP
3 6 PCIE_CLK_REQ0# PCIE_CLK_RQ0# SML1_CLK 3 6
4 5 PCIE_CLK_REQ4# PCIE_CLK_RQ4# BG34 SML1_DATA 4 5
PERN1 EC_SW I#
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# 27
SRN10KJ-6-GP
RN2002
AV32
AU32
PETN1 NC H14 SMB_CLK
EC_SW I# PETP1 SMBCLK PCH_GPIO74 R2011 1 10KR2J-3-GP
D 1 8 2 D
2 7 PCIE_CLK_LAN_REQ# PCIE_CLK_RQ5# BE34 C9 SMB_DATA
CLK_PCIE_REQ7# PERN2 SMBDATA DRAMRST_CNTRL_PCH 1
3 6 PCIE_CLK_RQ7# BF34 PERP2 2
CLK_PEG_B_REQ# R2009 1KR2J-1-GP
4 5 BB32
AY32
PETN2 NC
PETP2

SMBUS
SRN10KJ-6-GP A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 37
SML0ALERT#/GPIO60 3D3V_S0
65 PCIE_RXN3 BG36 PERN3
65 PCIE_RXP3 BJ36 C8 SML0_CLK RN2007
C2005 1 PERP3 SML0CLK
65 PCIE_TXN3 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34 PETN3 NC 2 3
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP3_C SML0_DATA
65 PCIE_TXP3 AU34 PETP3 SML0DATA G12
Layout Note: 1 4

BF36 PERN4
Can Place Far away PCH SRN2K2J-1-GP
BE36 PERP4 PCH_GPIO74
AY34
BB34
PETN4 WLAN SML1ALERT#/PCHHOT#/GPIO74 C13
PETP4

w
E14 SML1_CLK
SML1CLK/GPIO58 SML1_CLK 27,28,86

PCI-E*
BG37 PERN5

w
BH37 M16 SML1_DATA SMB_DATA 6 1
PERP5 SML1DATA/GPIO75 SML1_DATA 27,28,86 PCH_SMBDATA 14,15,69
AY36 NC

w
PETN5
BB36 PETP5 5 2

.ro
84.2N702.A3F
31 PCH_RXN_C_LAN_TXN6 BJ38 PERN6 4 3 2nd = 84.DM601.03F
31 PCH_RXP_C_LAN_TXP6 BG38 3rd = 84.2N702.E3F

se
C2001 1 PERP6
2 SCD1U10V2KX-5GP PCH_TXN_LAN_RXN6 LAN

Controller
31 LAN_RXN_C_PCH_TXN6 AU36 PETN6 CL_CLK1 M7 Q2001 4th = 84.2N702.F3F
31 LAN_RXP_C_PCH_TXP6 C2002 1 2 SCD1U10V2KX-5GP PCH_TXP_LAN_RXP6 AV36 2N7002KDW -GP
PETP6

fix
PCH_SMBCLK 14,15,69

Link
BG40 PERN7 CL_DATA1 T11
SMB_CLK

.c
BJ40 PERP7 NC
Layout Note: AY40 PETN7

om
C BB40 P10 C
PETP7 CL_RST1#
Layout trace < 14000mil XTAL25_IN 1 2
X2001
BE38 PERN8 Layout Note: C2008
BC38
AW38
PERP8 NC CLKOUT termination 1 4 SC15P50V2JN-2-GP
PETN8

2
S0 power rail CLKREQ#: AY38 PETP8 place close to PCH <500mil
R2006
PCIECLKRQ[2:1]# M10 PEG_CLKREQ# 83 1M1R2J-GP
3D3V_S0 PEG_A_CLKRQ#/GPIO47 C2007
Y40 CLKOUT_PCIE0N 2 3
RN2018 RN2016 SC15P50V2JN-2-GP
Y39 NC

1
CLK_PCIE_W LAN_REQ# CLKOUT_PCIE0P CLKOUT_PEG_A_N
1 4 PCIE_CLK_RQ2# CLKOUT_PEG_A_N AB37 1 4 CLK_PCIE_VGA# 83
CLK_PCIE_REQ1# PCIE_CLK_RQ1# PCIE_CLK_REQ0# CLKOUT_PEG_A_P XTAL25_OUT XTAL-25MHZ-155-GP1

CLOCKS
2 3 J2 AB38 2 3 2
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P OPS CLK_PCIE_VGA 83
SRN10KJ-5-GP SRN0J-6-GP
AB49 AV22 CLKOUT_DMI_N R1930 1 2 CLK_EXP_N 5 82.30020.D41
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P R1931 10R0402-PAD
AB47 CLKOUT_PCIE1P NC CLKOUT_DMI_P AU22 2
0R0402-PAD
CLK_EXP_P 5 2nd = 82.30020.G61
CLK_PCIE_REQ1# M1 PCIECLKRQ1#/GPIO18
CLKOUT_DP_N AM12
AM13 3D3V_S0
R1918 1 CLK_PCH_SRC2_N CLKOUT_DP_P
65 CLK_PCIE_W LAN# 2 AA48 CLKOUT_PCIE2N
R1922 10R0402-PAD CLK_PCH_SRC2_P
65 CLK_PCIE_W LAN 2 AA47 CLKOUT_PCIE2P WLAN CLK

1
0R0402-PAD BF18 CLK_BUF_EXP_N 2 3 3D3V_S5
CLKIN_DMI_N CLK_BUF_EXP_P RN2019 1 R2014
65 CLK_PCIE_W LAN_REQ# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 4

1
SRN10KJ-5-GP 10KR2J-3-GP
OPS
R2004
Y37 BJ30 CLK_BUF_CPYCLK_N 2 3 10KR2J-3-GP

2
CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P RN2008 1
Y36 CLKOUT_PCIE3P NC CLKIN_GND1_P BG30
SRN10KJ-5-GP
4
Layout Note:

2
B PCIE_CLK_REQ3# PEG_CLKREQ# B
A8 PCIECLKRQ3#/GPIO25 22 BOARD_ID2
G24 CLK_BUF_DOT96_N 2 3
CLKIN_DOT_96N

1
CLKOUT termination CLKIN_DOT_96P E24 CLK_BUF_DOT96_P RN2020 1 4
place close to PCH <500mil Y43 SRN10KJ-5-GP R2010
CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P NC CLK_BUF_CKSSCD_N
UMA 10KR2J-3-GP
CLKIN_SATA_N AK7 2 3
PCIE_CLK_REQ4# L12 AK5 CLK_BUF_CKSSCD_P RN2021 1 4

2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P SRN10KJ-5-GP

31 CLK_PCIE_LAN# R1923 1 2 CLK_PCH_SRC5_N V45 K45 CLK_BUF_REF14 R2008 1 2


R1928 10R0402-PAD CLK_PCH_SRC5_P CLKOUT_PCIE5N REFCLK14IN 10KR2J-3-GP
31 CLK_PCIE_LAN 2
0R0402-PAD
V46 CLKOUT_PCIE5P LAN CLK
31 PCIE_CLK_LAN_REQ# L14 H45 CLK_PCI_FB CLK_PCI_FB 18
Layout Note: BIOS UMA/DIS Strap pin
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
1500mil < Layout trace < 10000mil
AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN BOARD_ID1 BOARD_ID2
XTAL25_OUT
AB40 CLKOUT_PEG_B_P NC XTAL25_OUT V49

CLK_PEG_B_REQ# PX(AMD) 0 0
Layout Note: E6 PEG_B_CLKRQ#/GPIO56 R2007
Layout trace < 14000mil XCLK_RCOMP Y47 XCLK_RCOMP 1 2 +VCCDIFFCLKN
V40 CLKOUT_PCIE6N
DIS 0 1
90D9R2F-1-GP
V42 CLKOUT_PCIE6P NC
PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
UMA 1 0
V38 K43 JTAG_TCK 1 TP2004
FLEX CLOCKS

CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37 CLKOUT_PCIE7P NC Optimus(NV) 1 1
A F47 CARD_READER_48M 1 TP2005 M14 DIS A
CLK_PCIE_REQ7# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
CLKOUTFLEX2/GPIO66 H47 CLK_27M_VGA_R 1 TP2006
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 BOARD_ID1 BOARD_ID1 18
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PANTHER-GP-NF
Title
71.PANTH.00U
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
A3 A00
OAK14 Chief River DIS
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
Date: W ednesday, September 05, 2012 Sheet
1
20 of 105
5 4 3 2 1

SSID = PCH
RTC_AUX_S5

R2127 1 220KR2F-L-GP
R2128 1 220KR2F-L-GP Integrated SUS 1V VRM Enable

1
C2104 Low = External VRs
INTVRMEN Layout Note:

SC1U6D3V2KX-GP
High = Internal VRs*
Place near PCH

2
D D
PCH1A 1 OF 10 LPC_AD[3..0]
LPC_AD[3..0] 27,71
RN2101 SRN0J-7-GP
RTC_X1 A20 C38 LPC_LAD0_PCH 1 8 LPC_AD0
RTCX1 FWH0/LAD0 LPC_LAD1_PCH LPC_AD1
FWH1/LAD1 A38 2 7

LPC
RTC_X2 C20 B37 LPC_LAD2_PCH 3 6 LPC_AD2
RTCX2 FWH2/LAD2 LPC_LAD3_PCH LPC_AD3
FWH3/LAD3 C37 4 5
RTC_RST# D20 RTCRST#
FWH4/LFRAME# D36 LPC_LFRAME#_PCH 1 R2136 2 LPC_FRAME# 27,71
SRTC_RST# G22 0R0402-PAD
R2104 SRTCRST#
84.07002.I31