Horia Cucu

Speech & Dialogue Research Laboratory

Faculty of Electronics, Telecommunications and Information Technology
University POLITEHNICA of Bucharest
1.1 Example #1
 Overview of a CISC, General Purpose
Microprocessor Core

General Purpose Registers (GPRs) Arithmetic and Logic Unit (ALU)

Memory Data Register (DR) Memory Addressing Control Unit
Memory Address Registers (AR) Timing and Control Unit (TCU)
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 Instruction Execution Timing
Premises
Busses
8-bit internal and external data bus
16-bit external address bus
Memory
Linear memory organization
16-bit physical addresses
8-bit memory locations
Registers
8-bit, general purpose registers: R1, , R6; can be concatenated
8-bit special function registers: A (accumulator), F (flags), DR
(data reg), IR (instruction reg), ATEMP, TEMP, AUX1, AUX2
16-bit special function registers: PC, SP, IX, RA

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 Instruction Execution Timing Example
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result

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 Machine Cycle 1: Fetch
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: addrlow addrhigh data
code
6 machine cycles: (00h) (20h) (50h)

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result

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 Machine Cycle 1: Fetch

T1. (AR) <- (PC), MEM-READ

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 Machine Cycle 1: Fetch

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

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 Machine Cycle 1: Fetch

T3. (IR) <- (DR)

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 Machine Cycle 1: Fetch

T4. decode instruction code

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 Machine Cycle 2: Read Address
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX2) <- (DR)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result

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 Machine Cycle 2: Read Address

T1. (AR) <- (PC), MEM-READ

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 Machine Cycle 2: Read Address

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

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 Machine Cycle 2: Read Address

T3. (AUX2) <- (DR)

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 Machine Cycle 3: Read Address
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX1) <- (DR)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result

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 Machine Cycle 3: Read Address

T1. (AR) <- (PC), MEM-READ

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 Machine Cycle 3: Read Address

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

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 Machine Cycle 3: Read Address

T3. (AUX1) <- (DR)

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 Machine Cycle 4: Read Operand 1
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (A) <- (DR)
M5. Read operand 2 and Execute
M6. Write result

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 Machine Cycle 4: Read Operand 1

T1. (AR) <- (PC), MEM-READ

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 Machine Cycle 4: Read Operand 1

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

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 Machine Cycle 4: Read Operand 1

T3. (A) <- (DR)

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 Machine cycle 5: Read operand 2 and Execute
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
T1. (AR) <- (AUX1, AUX2), MEM-READ
T2. (DR) <- ((AR))
T3. (A) <- (A) + (DR)
M6. Write result

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 Machine cycle 5: Read operand 2 and Execute

T1. (AR) <- (AUX1, AUX2), MEM-READ

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 Machine cycle 5: Read operand 2 and Execute

T2. (DR) <- ((AR))

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 Machine cycle 5: Read operand 2 and Execute

T3. (A) <- (A) + (DR)

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 Machine Cycle 6: Write Result
Instruction example: (2000h) <- (2000h) + 50h
Instruction format: code
addrlow addrhigh data

(00h) (20h) (50h)
6 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand 1
M5. Read operand 2 and Execute
M6. Write result
T1. (DR) <- (A)
T2. (AR) <- (AUX1, AUX2), MEM-WRITE

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 Machine Cycle 6: Write Result

T1. (DR) <- (A)

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 Machine Cycle 6: Write Result

T2. (AR) <- (AUX1, AUX2), MEM-WRITE

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1.2 Example #2
 Instruction Execution Timing Example
Instruction example: (R1) <- (R3)
Instruction format: code

1 machine cycle:
M1. Fetch and Decode
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
Execute
T1. (TEMP) <- (R3)
T2. (R1) <- (TEMP)

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1.3 Example #3
 Instruction Execution Timing Example
Instruction example: (A) <- (A) + (R1)
Instruction format: code

1 machine cycle:
M1. Fetch and Decode
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
Execute
T1. (TEMP) <- (R1), (ATEMP) <- (A)
T2. (A) <- (ATEMP) + (TEMP)

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1.4 Example #4
 Instruction Execution Timing Example
Instruction example: (A) <- (A) + ((R5, R6))
Instruction format: code
3 machine cycles:
M1. Fetch and Decode
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
M2. Read operand
T1. (AR) <- (R5, R6), MEM-READ

T2. (DR) <- ((AR))
T3. (TEMP) <- (RD), (ATEMP) <- (A)
M3. Execute
(A) <- (ATEMP) + (TEMP)

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1.5 Example #5
 Instruction Execution Timing Example
Instruction example: (A) <- (2000h)
Instruction format: code
addrlow addrhigh

(00h) (20h)
4 machine cycles:
M1. Fetch and Decode
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand

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 Instruction Execution Timing Example
Instruction example: (A) <- (2000h)
Instruction format: code
addrlow addrhigh

(00h) (20h)
4 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX2) <- (RD)
M3. Read address (most significant byte)
M4. Read operand

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 Instruction Execution Timing Example
Instruction example: (A) <- (2000h)
Instruction format: code
addrlow addrhigh

(00h) (20h)
4 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX1) <- (RD)
M4. Read operand

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 Instruction Execution Timing Example
Instruction example: (A) <- (2000h)
Instruction format: code
addrlow addrhigh

(00h) (20h)
4 machine cycles:
M1. Fetch and Decode
M2. Read address (least significant byte)
M3. Read address (most significant byte)
M4. Read operand
T1. (AR) <- (AUX1, AUX2), MEM-READ
T2. (DR) <- ((AR))
T3. (A) <- (RD)

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1.6 Example #6
 Instruction Execution Timing Example
Instruction example: (PC) <- 0100h
Instruction format: code
datalow datahigh

(00h) (01h)
3 machine cycles:
M1. Fetch and Decode
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (IR) <- (DR)
T4. decode instruction code
M2. Read data (least significant byte)
M3. Read data (most significant byte) and Execute

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 Instruction Execution Timing Example
Instruction example: (PC) <- 0100h
Instruction format: code
datalow datahigh

(00h) (01h)
3 machine cycles:
M1. Fetch and Decode
M2. Read data(least significant byte)
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX2) <- (RD)
M3. Read data (most significant byte) and Execute

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 Instruction Execution Timing Example
Instruction example: (PC) <- 0100h
Instruction format: code
datalow datahigh

(00h) (01h)
3 machine cycles:
M1. Fetch and Decode
M2. Read data (least significant byte)
M3. Read data (most significant byte) and Execute
T1. (AR) <- (PC), MEM-READ
T2. (PC) <- (PC) + 1, (DR) <- ((AR))
T3. (AUX1) <- (RD)
T4. (PC) <- (AUX1, AUX2)

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