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domain faults
Gao Qiang
Himanshu Kukreja
Jovin Basil Roy J
www.lantiq.com
ABSTRACT
High transition delay coverage is utmost priority in current complex designs to improve the test
quality. Conventionally the faults between two OCC domains are not considered for the
transition delay test. The default OCC structure and ATPG flow support faults which belong to
only one clock domain. When there is a timing requirement between different clock domains,
those faults must be tested. This requires some modification for OCC structure or insertion of
synchronous OCC IP. The paper describes this novel DFT concept used to test the inter clock
domain faults using the asynchronous OCC IP and modification of ATPG. This approach also
enabled us to target the critical paths across clock domains using path delay fault model
Table of Figures
Figure 1 Design before OCC insertion ................................................................................... 5
Figure 2 Design after OCC insertion ...................................................................................... 5
Figure 3 at-speed clock pulse generation ................................................................................ 6
Figure 4 waveform of clock pulse generation......................................................................... 6
Figure 5 Example of 2 clock domains with divider ................................................................ 7
Figure 6 Two synchronous clocks with two OCC .................................................................. 8
Figure 7 2 OCCs start to run at different time ........................................................................ 8
Figure 8 2 OCCs start to run at the same time ........................................................................ 8
Figure 9 Proposed Enhancement in OCC connection............................................................. 9
Figure 10 Launch by CLK_A(clk_500), captured by CLK_B(clk_250) .............................. 11
Figure 11 Launched by CLK_B(clk_250), captured by CLK_A(clk_500) .......................... 12
Figure 12 Launch and captured by CLK_A(clk_500) .......................................................... 13
Figure 13 Launch and captured by CLK_B(clk_250) .......................................................... 13
Figure 14 coverage comparison between 2 types of OCC .................................................... 14
One common methodology for at-speed testing is to leverage existing on-chip clock (OCC)
generation circuitry. This approach uses the active controller (OCC) to generate the high-speed
launch and capture clock pulses.
High transition delay coverage is utmost priority in current complex designs to improve the test
quality. Conventionally the faults between two OCC domains are not considered for the
transition delay test. The OCC structure and ATPG flow support faults which belong to the clock
domain. When there is a timing requirement between different clock domains, those faults must
be tested. This requires some modification for OCC structure or insertion of synchronous OCC
IP. The paper describes this novel DFT concept used to test the inter clock domain faults using
the asynchronous OCC IP and modification of ATPG procedure (spf) file.
This paper will describe the principle of OCC, analyze its limitation for cross clock domain test
and propose a solution to test cross clock domain faults.
The following figures show an example design with and without OCC.
FUNC_CLK
CGU
ATE_CLK
Fucntion logic
ATE_CLK
Test_SE
PLL_bypass
Scan_mode
NOTE: Figure 2 is just a simplified logical view to understand OCC easily, not a real
implementation.
Functionality of OCC:
1. scan shift mode, shift configuration value (how many fast clock pulses will be generated)
to OCC clock_chain.
2. scan capture mode, the one-hot counter will run based on func_clk frequency. It enables
at_speed clock pulse based on the value of OCC clock_chain.
occ_si occ_so
shift shift shift
scan_clk reg reg reg
clk_enable
scan_enable clk_out
One-hot counter fast
Sync0 Sync1 Sync2 & pipe clk Clk_gating
fast_clk Compare logic en
The following figure shows how the fast clock pulse is generated when clk_enable[0] is set to 1.
enable pulse if
clk_enable[0]=1
pipe reg
3 synchronization cycles fastclk_enable reg
fast_clk
scan_enable
clk_out
7th clock pulse after
scan_enable falling
Description:
1. The whole flow is triggered by detecting falling edge of scan_enable.
2. After scan_en is captured by rising edge of fast_clk, it needs the following steps to
generate final clock pulse.
1) Three synchronous cycles
2) Synchronized falling edge of internal scan_enable will trigger counter to run:
So after scan_enable falling edge , the 3+n+1+1+1 fast_clk pulse will be sent out on clk_out of
OCC.
500MHz 250MHz
Divider
1/2
After inserting OCC, the clock structure would look like the one shown below.
A
OCC_A Block A
Based on the description of 2.2, we know that falling edge of scan_en will trigger the OCC to
start the operation. For the example shown above, scan_en is asynchronous with internal at-
speed clocks (CLK_A and CLK_B), so there will be two scenarios for OCC to start running.
OCC_A start
scan_en OCC_B start
CLK_A
CLK_B
Figure 7 Both OCCs start to run at different time
OCC_A start
scan_en OCC_B start
CLK_A
CLK_B
Figure 8 Both OCCs start to run at the same time
To generate patterns for cross clock domains, we need to make 2 OCCs run in same way
regardless the relationship between internal clock and scan_en. Now the following modification
needs to be done for OCC_A and OCC_B.
For OCC_B, we created a new output from the internal scan_en synchronized by CLK_B.
For OCC_A, we use the new output of OCC_B to enable one-hot counter of OCC_A.
occ_si occ_so
shift shift shift
scan_clk reg reg reg
OCC_B clk_enable
scan_enable clk_out
One-hot counter fast
Sync0 Sync1 Sync2 & pipe clk Clk_gating
fast_clk Compare logic en
occ chain
occ_si occ_so
shift shift shift
scan_clk reg reg reg
OCC_A clk_enable
scan_enable clk_out
One-hot counter fast
Sync0 Sync1 Sync2 & pipe clk Clk_gating
fast_clk Compare logic en
As we have mentioned in the earlier explanation the clocks are 500 and 250 MHz, so the
Period_A = 2ns and Period_B = 4ns
If n=1 (clk_chain[0]=1) for both clock, then the time of first clock pulse for two internal clocks
are shown below.
OCC_A: 4 * 2 = 8 ns
OCC_B: 4 * 4 = 16 ns
So based on same clock configuration settings (clock_chain[0]=1), clock pulse of OCC_B will
be 8ns (2 clock_B cycles) later than that of OCC_A.
Pattern AB : launched by CLK_A and captured by CLK_B (target cross clock domain faults)
Pattern BA : launched by CLK_B and captured by CLK_A (target cross clock domain faults)
Pattern A : launched by CLK_A and captured by CLK_A
SNUG 2014 10 Using Synopsys Asynchronous OCC IP
to target cross clock domain faults
Pattern B : launched by CLK_B and captured by CLK_B
Result of simulation:
Result of simulation:
Result of simulation:
4. Conclusion
By default, cross clock domain faults are not targeted during at-speed test.. The falling edge of
scan_enable triggers OCC to start. As scan_enable is asynchronous with internal at-speed clock,
the different relationship between scan_enable and internal clock will make 2 OCC clock outputs
asynchronous to each other. This is the reason why the default OCC does not support cross clock
domain fault detection.
The paper described an innovative methodology to update certain connectivity in asynchronous
OCCs to achieve deterministic behavior between two OCCs which can help in targeting the
critical inter clock domain faults. The change in OCC connectivity along with corresponding
change in SPF helps us achieve the test coverage for the inter clock domain paths which
enhances the test quality and thus the reliability of the chip. The methodology has been
implemented in one of our devices and is silicon proven.
5. References
[ 1 ] Lantiq DFT Standard, Mandatory Design for Testability (DFT) Features for Infineon Technologies SOC
Products
[ 2 ] DFT Compiler User Guide
[ 3 ] TetraMax ATPG User Guide