`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.03.2017 01:27:13
// Design Name:
// Module Name: final
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// Description:
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// Revision:
// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.03.2017 01:06:54
// Design Name:
// Module Name: push_button
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module rom_read(
input switch,
input clk,
input reset,
output [6:0] out,
output en_1,
output en_2,
output en_3,
output en_4
);
wire [3:0] adr;

wire [7:0] data;

wire [3:0] data1;
wire [7:0]address;
wire clk1,clk2;
 push_button m3 (switch,clk2,adr,reset);
clk_1ms u1(clk,clk1);
clk_2_ms u2(clk1,clk2);
binary_bcd p1( adr,address);//convert binary address of rom into bcd address
for diplay
rom_16x8 m1(adr,1'b1,1'b1,data);
assign data1= clk2 ? (clk1 ? address[7:4]: address[3:0]):(clk1 ?
data[7:4]:data[3:0]);
assign en_1= ~((~clk1) & (~clk2));//enable ist seven segment for 0.5ms(lower
nibble data)
assign en_2= ~((clk1) & (~clk2));//enable 2nd seven segment for next
0.5ms(upper nibble data)
assign en_3= ~((~clk1) & (clk2));//enable 3rd seven segment for next
0.5ms(lower bcd address)
assign en_4= ~((clk1) & (clk2));// enable 4th seven segment for next
0.5ms(upper bcd address)
seven_seg_decoder m2(data1,out);// give data to seven segment decoder
endmodule
module push_button(
input switch,
input clk,
output [3:0] count,
input reset
);
reg [3:0] count=4'b0000;
always@(posedge clk)
begin
if(reset)
begin
if(switch &(&count))
count=0;

else if(switch)
count=count+1;
else
count=count;
end
else
count=4'bzzzz;
end
endmodule

module rom_16x8(
input [3:0] adr,
input cs,
input read_en,
output [7:0] data
);
reg [7:0] data;
reg [7:0] mem [15:0];//define memory
initial
begin
mem[0]=8'h15;
mem[1]=8'h14;
mem[2]=8'h13;
mem[3]=8'h12;
mem[4]=8'h11;
mem[5]=8'h10 ;
 mem[6]=8'h09;
mem[7]=8'h08;
mem[8]=8'h07;
mem[9]=8'h06;
mem[10]=8'h05;
mem[11]=8'h04;
mem[12]=8'h03;
mem[13]=8'h02;
mem[14]=8'h01;
mem[15]=8'h00;
end
always@(adr,cs,read_en)
begin
if (cs&read_en)
data=mem[adr];
else
data=8'hzz;
end
endmodule

module seven_seg_decoder(
input [3:0] data,
output reg [6:0] out

);
//abcdefg output to seven segment
parameter blank =7'hff;
parameter zero =7'h01;
parameter one =7'h4f;
parameter two =7'h12;
parameter three =7'h06;
parameter four =7'h4c;
parameter five =7'h24;
parameter six =7'h20;
parameter seven =7'h0f;
parameter eight =7'h00;
parameter nine =7'h04;
always@(data)
begin

case(data)
4'b0000 : out=zero;
4'b0001: out=one;
4'b0010: out=two;
4'b0011: out=three;
4'b0100: out=four;
4'b0101:out=five;
4'b0110:out=six;
4'b0111:out=seven;
4'b1000:out=eight;
4'b1001:out=nine;
default: out=blank;
endcase
end

endmodule
/// geneation of clk of period 1ms
module clk_1ms(
input clk,
output clk_out
);
wire c2,c3;
clk_div_100 m1(clk,c2);
clk_div_100 m2(c2,c3);
clk_div_10 m3 (c3,clk_out);
endmodule

//generation of clk
module clk_2_ms(
input clk,
output clk_out
);
reg clk_out=0;
always@(posedge clk)
clk_out=~clk_out;
endmodule

module clk_div_100(
input clk,

output clk_out1
);
wire cl, c2;
clk_div_10 u1(clk,cl);
clk_div_10 u2(cl,clk_out1);
endmodule

module clk_div_10(
input clk,
output reg clk_out
);
reg [2:0] count;
initial
begin
count=3'b000;
clk_out=0;
end
always@(posedge clk)

begin
if (count[2]&(~count[0]) &(~count[1]))
begin
clk_out=~clk_out;
count=0;
end
else
count=count+1;
end
endmodule
module full_adder_4_bit(
input [3:0] a,
input [3:0] b,
input c,
output [3:0] sout,
output cout
);
wire c1,c2,c3,c4;
full_adder m1(a[0],b[0],c,sout[0],c1);
full_adder m2(a[1],b[1],c1,sout[1],c2);
full_adder m3(a[2],b[2],c2,sout[2],c3);
full_adder m4(a[3],b[3],c3,sout[3],c4);
assign cout=c4;
endmodule