17 BIT IMPLEMENTATION FOR DUAL CORE RISC ARCHITECTURE

AKSHATHA RAI K
M.tech,Department of ECE,VTU University, MITE ,Moodabidri, Karnataka, INDIA

VENKATE GOWDA
Assistant professor, Department of ECE,VTU university, MITE, Moodabiri, Karnataka . INDIA

ABSTRACT: The main objective of this project is simulate and synthesis the 17bit RISC
processor based on MIPS. RISC is a family of processor architecture that has been designed to
perform a small set of instructions and it performs the operations in very simple manner . The
major feature of the RISC processor is that this processor is very simple to design and implement
and also support load and store architectures only. The design uses simple Harvard architecture,
which means it has distinct program memory space and data memory space so the memory access
speed will be increased . The proposed processor design consists mainly of four stage pipelining,
which are instruction fetch, instruction decode, execute and store result stages. In this project the
simulation is done by modelsim simulator to perform logical verification and further synthesizing
the code on Xilinx-ISE tool using target technology and performing place & routing operation for
system verification. The verilog language used in this project.

KEYWORDS: MIPS, RISC, Harvard architecture, CISC, Pipelining, Instruction sets, Dual core,
modelsim, verilog,Xilinx.

INTRODUCTION

Processors are mainly used for the arithmetic calculations. Whenever we are going to buy a
processor we will mainly concentrate on the features such as memory and speed etc. Memory and
speed are interrelated ,when the memory access is done faster the speed will be increased. While
coming to the processor there are two kinds of processor ,they are RISC and CISC and also there
is two types of architecture- Harvard and Von-numan. Von-numan is older architecture so most of
the processor uses the Harvard architecture.

Comparing to CISC CPU, RISC have more advantages, such as simplified structure easier
implementation and faster speed. RISC processors has wide use in embedded system. In RISC
CPU we have a important feature called pipelining, and the pipelining is done by in one machine
cycle. One machine cycle means it is equal to 6 states , two clocks will form the one state, so there
is totally 12 cycles required to perform pipelining. There are many varieties of processors are
available. In this mostly used one is MIPS RISC processor. MIPS processor is abbreviated as
microprocessor without interlocked pipeline stage. It is a very simple processor design used to
remove the hardware interlocks between the each pipelining stages.. Here presented project uses
the 17 bit instruction set width , where 5bit opcode and rest operands are 4bit each. MIPS
implementations are primarily used in embedded systems such as Routers ,Windows CE devices
and residential gateway.
PROPOSED MIPS RISC ARCHITECTURE

The proposed architecture aims to implement four stage pipeline RISC processor based on MIPS
format. It emphasizes on speed and cost of the processor implementation. Pipelining is the
standard feature of the all RISC processor. It can process the different steps of the instruction at
the same time so that more instructions can be executed at the same time. Today CPUs are getting
cheaper, faster and more advanced and day by day the cores are doubling to make the processor
more powerful. Such processors perform multitasking. The cores may implemented or
communicated by using shared memory or message passing inter-core communication method. If
each core in the processor uses the individual memory then the chip area will be increases, further
more the latency and power consumption also increases. In order to overcome these drawbacks
shared memory architecture is designed in this project. The processors are connected in star
topology and share common memory for data and program. Any processor can write/read from the
memory at the same time. If collision occurs they are handled by priority method.

Pipelining
The important feature of RISC CPU is pipelining. In this paper 4-stage pipelining is designed ,
with the aim of increasing operating speed as well as performance of processor. The four stages of
pipelining are fetch, decode, execute and store result stage .Pipelining allows the processor to work
on different instruction at the same time, thus more number of instruction can be executed in a
shorter interval of time. The basic architecture of MIPS RISC pipelined processor is shown in the
bellow figure 1.

CPU Register

IF ID & IE ST
Block Operan block block
d fetch (ALU)
block

Program memory Data memory result

Figure 1.. Basic architecture of MIPS RISC Pipelined processor.

The 4 stages of pipelining are

Instruction Fetch (IF):

The Instruction Fetch stage is where a program counter (8 bit) will pull the next instruction from
the correct location in program memory and obtain next instruction from memory location . Based
on the PC value loads the instruction into instruction register IR and the MAR is loaded with
instruction pointer. Here the instruction is loaded through the MDR. Once the instruction is
fetched the program counter will be incremented and it updates instruction pointer address while
reading instruction from memory.

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Instruction Decode (ID):
The Instruction Decode stage examines op code of the instruction. Depending on the opcode it
will determine which operation to perform . Output line signals a circuit which implements the
corresponding operation.

Execute Unit (EX):

The Execute stage is where the instruction is actually sent to the ALU and executed. Branch
locations are calculated in this stage if it is necessary. Initially it computes the address of the
memory location of the instruction operand, and then Loads MAR with address calculated. later
Reads memory into MDR, making data available as input to the processing unit. The Microcode
for the instruction, selected by the decoder output and instructions are executed by the ALU.

Store result (ST):

If the instruction is a load , memory does a read operation using the effective address computed in
the previous cycle that can be stored . Instruction Cycle begins anew.
The figure 2. shows how instructions are executed using the pipelining technique.

At any given time there are 4 instructions in different stages of execution.

IF ID IE ST

IF ID IE ST

IF ID IE ST

IF ID IE ST

Figure 2.. Instruction execution using Pipelining technique.

RISC specifications
Architecture contains total 23 instructions (6arthmetic+5 branching + 8 logical + 4 data
path instruction)
Four stage instruction execution (IF, ID,IE,ST).
8Bit data and 8bit address bus.
Harvard memory architecture.
1 Special purpose status register
8 Bit memory mapped input / output register..
13 General purpose registers uniform instruction width of 4bit for all the instruction

Dual core RISC architecture

Core is a processing unit of the system. A dual-core processor is a CPU with two processors or
"execution cores" in the same integrated circuit. To design a dual core first we have to design
simple RISC core processor and its replication into 2 times. Here all the 2 cores are identical to
each other and based on the instructions it performs the operation. Finally all the 2 cores are

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instantiated in to a single top module called dual core. The below figure will shows the simple dual
core processor block diagram.

CORE CORE
1 2

Individual Individual
memory memory

Shared memory

Bus interface

Off-chip component

Fig 3. Simple dual core RISC architecture.

Instruction set
ISA(Instruction Set Architecture) of every processor is composed of number of instruction sets and
corresponding registers.. The instruction set used in this architecture consists of arithmetic
instructions, logical instructions, data path instructions, branch instructions and memory
instructions. The different addressing modes in an instruction set architecture define how machine
language instructions in that architecture identify the operand (or operands) of each instruction.
The addressing mode used in present architecture is : Register addressing mode. It uses 17 bit
address with opcode of five bit and rest three fields operands each of 4 bits. The data width,
program counter, status register are of 8 bit. Totally 23 instructions are used in this processor .
The instruction format is of register type and is shown in Figure 3. Instruction of 17 bit width with
opcode 5bit and three operands fields of each 4 bit.
17 bit
opcode operand 3 operand 2 operand 1

5 bit 4bit 4 bit 4 bit

Fig 4. Instruction set of RISC processor.

SIMULATION RESULTS

The single core RISC processor or CPU is simulated by using pipeline concept and using Xilinx
ISE and Modelsim simulator is used to get results. The Verilog HDL language is used for
designing the dual core processor. The RTL schematic for single RISC processor obtained in
Xilinx ISE is shown in Figure5. Initially the simulation waveform for Single core CPU is
obtained by using Modelsim is shown in Figure 6 and the outputs are verified. Here there is a five
input such as reset(1bit), clock (1bit),input1 (4 bit), input2 (4 bit), ram datain(4 bit). The data read
from ram memory by using load instruction. The output are out put(4 bit), ram write (4 bit).

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Finally output of the dual core RISC is obtained the simulation waveform of dual core RISC core
processor is shown in Figure 7.

Figure 5. Obtained RTL Schematic of RISC processor.

Figure 6.Obtained simulation waveform for single RISC processor.

Figure 7. Simulation waveform of dual core RISC processor

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The design summery shows that the device utilization out of available devices. The utilization of
registers, flip-flops, latches etc. are shown in terms of percentage.

register
Device utilization flip flops
latches
4 input luts
occupied slices
slices containing related logic
slices containg unrelated logic
Bonded IOBs
RAMB 16s
BUFGMUXs
MULT18X18SIOs

Figure 8. Design summary of CPU.

CONCLUSION

17 bit instruction set width dual core RISC Processor has been designed and simulated in Xilinx
ISE 14.1 tool. The design has been achieved using Verilog language and simulated with Modelsim
simulator. After synthesis got the less no of logic resource utilization comparing the available
resources this can be show in the device utilization summery table. It shows that the speed and
performance of the presented processor is increased.

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