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Combinational Logic
INVERTER: A Z=A 0 1
1 0
€ € A B Z
A 0 0 0
AND: Z = A⋅ B
B 0 1 0
1 0 0
€ 1 1 1
€
€
A B Z
A 0 0 0
OR: Z = A+ B
B 0 1 1
1 0 1
€ 1 1 1
€
€
6.004 Computation Structures L4: Logic Synthesis, Slide #4
Straightforward Synthesis
We can implement Y = CBA + CBA + CBA + CBA
SUM-OF-PRODUCTS
with just three levels of
logic:
1. Inverters
2. ANDs
-it’s systematic!
3. OR -it works!
-it’s easy!
-are we done yet???
Propagation delay --
No more than 3 gate delays? *
€
More Building Blocks
NAND (not AND) A B Z NOR (not OR) A B Z
0 0 1 0 0 1
A 0 1 1 A 0 1 0
Z = A⋅ B Z = A+ B
B 1 0 1 B 1 0 0
1 1 0 1 1 0
€ €
In a CMOS gate, rising inputs lead to falling €
€ outputs and vice-versa, so
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CMOS gates are naturally inverting. Want to use NANDs and NORs in
CMOS designs… But NAND and NOR operations are not associative, so
wide NAND and NOR gate can’t use a chain or tree strategy. Stay tuned
for more on this!
XOR is very useful when
XOR (exclusive OR) A B Z implementing parity and arithmetic
0 0 0 logic. Also used as a “programmable
A inverter”: if A=0, Z=B; if A=1, Z=~B
Z=A⊕B 0 1 1
B
1 0 1 Wide fan-in XORs can be created with
1 1 0 chains or trees of 2-input XORs.
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€
6.004 Computation Structures L4: Logic Synthesis, Slide #7
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Universal Building Blocks
NANDs and NORs are universal:
= =
= =
= =
Any logic function can be implemented using only NANDs
(or, equivalently, NORs). Good news for CMOS
technologies!
AND4:
tPD = 160 ps, size = 20μ2
NAND4 + INV:
tPD = 90 ps, size = 27μ2
Demorgan’s A ⋅ B = A + B
Laws: A + B = A ⋅ B
2*NAND2 + NOR2:
tPD = 80 ps, size = 30μ2
8-input 8-input
NAND NOR
A A
B
Y
≡ B
Y
AC + AB + BC
AB=A+B
NOR-NOR
C C
A A
B
Y
≡ B
Y
Reduction: ab + ab = b, (a + b)(a + b) = b
DeMorgan’s Law: a + b = ab, ab = a + b
6.004 Computation Structures L4: Logic Synthesis, Slide #12
Boolean Minimization
Can’t he come up
with a new example???
Let’s (again!) simplify
Y = C B A + CB A + CBA + C BA
Y = C A + CB
6.004 Computation Structures L4: Logic Synthesis, Slide #13
Truth Tables with “Don’t Cares”
One way to reveal the opportunities for a more compact
implementation is to rewrite the truth table using “don’t
cares” (-- or X) to indicate when the value of a particular input is
irrelevant in determining the value of the output.
C B A Y C B A Y
0 0 0 0 0 X 0 0 Note: Some input
combinations (e.g.,
0 0 1 1 000) are matched by
0 X 1 1 CA
0 1 0 0 more than one row in
1 0 X 0 the “don’t care” table.
0 1 1 1 It would be a bug if all
1 0 0 0 1 1 X 1 CB the matching rows
X 0 0 0 didn’t specify the
1 0 1 0
same output value!
1 1 0 1 X 1 1 1 BA
1 1 1 1
It’s cyclic. The left edge is adjacent to the right edge. 000 001
100 101
\AB
CD\ 00 01 11 10
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 1 0 0 1
Again it’s cyclic. The left edge is adjacent to the right edge, and
the top is adjacent to the bottom.
C\AB 00 01 11 10 AC C\AB 00 01 11 10
0 0 0 1 1 0 1 0 0 1
1 1 0 0 0 1 1 1 0 1
ABC AC B
• can be uniquely identified by a single product term. The
larger the implicant, the smaller the product term.
\AB
CD\ 00 01 11 10
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 1 0 0 1
Minimal SOP is
\AB
CD\ 00 01 11 10 not necessarily
unique!
00 0 1 1 1
01 1 1 1 1 Y = D + BC + AC + BC
\AB
00 01 11 10
11 1 1 1 1
CD\
00 0 1 1 1
01 1 1 1 1
10 1 0 0 1
11 1 1 1 1
10 1 0 0 1
Y = D + BC + AB + BC
C\AB 00 01 11 10
A
0 0 0 1 1 B
C
1 0 1 1 0 Y
To make the circuit lenient, include product terms for ALL prime
implicants.
A
C
Y = CA + CB + AB
B
6.004 Computation Structures L4: Logic Synthesis, Slide #21
We’ve Been Designing a Mux
Truth Table
D1
S D1 D0 Y
Y 0 0 0 0
D0 0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
S 1 0 1 0
2-input Multiplexer 1
1
1 0
1 1
1
1
Full-Adder
Carry Out Logic
0 0
A B Cin Cout 0 1
0 0 0 0 0
0 0 1 0
2
1 3 Cout
0 1 0 0 0
0 1 1 1 4
1 5
1 0 0 0
1 6
1 0 1 1
1 1 0 1 1 7
1 1 1 1 A,B,Cin
00 0 A
01 1 MUX 0 0 A Y
10 1
Logic Fn(A,B) B
0
1
1
Y=
B
11 0 S
A
B 0
0 A Y
Generalizing: Y=
1 1
1 B
In theory, we can build any 1-output S
D0 DECODER:
D1 • k SELECT inputs, Have I
mentioned
• N = 2k DATA OUTPUTs. that HIGH
Select inputs choose one of the is a synonym
DN-1 Dj to assert HIGH, all others for ‘1’ and
LOW means
will be LOW. the same
k as ‘0’
Co FA Ci
000
S For K inputs,
Shared 001
A B Ci S Co decoder produces 2K
decoder 010
0 0 0 0 0 signals, only 1 of
011 which is asserted at
0 0 1 1 0
100 a time -- think of it
0 1 0 1 0 as one signal for
101
0 1 1 0 1 each possible
110 product term.
1 0 0 1 0
111
1 0 1 0 1
A
1 1 0 0 1 B
CIN
1 1 1 1 1 One column
S COUT for each
output
6.004 Computation Structures L4: Logic Synthesis, Slide #26
Read-only Memory (ROM)
Each column is large fan-in “NOR.” Note
Full Adder location of pulldowns correspond to a
A B “1” output in the truth table!
Co FA Ci
000
S 1 For K inputs,
Shared 001
A B Ci S Co decoder produces 2K
decoder 010
0 0 0 0 0 signals, only 1 of
011 which is asserted at
0 0 1 1 0
100 a time -- think of it
0 1 0 1 0 as one signal for
101
0 1 1 0 1 each possible
110 product term.
1 0 0 1 0
1 0 1 0 1 0 111
A 0 0 1
1 1 0 0 1 B
CIN 1
1 1 1 1 1 1 0 One column
S COUT for each
output
6.004 Computation Structures L4: Logic Synthesis, Slide #27
Read-only Memory (ROM)
Full Adder LONG LINES slow down propagation
A B times…
The best way to improve this is to build
Co FA Ci square arrays, using some inputs to
drive output selectors (MUXes):
S
A B Ci S Co 00
0 0 0 0 0 01
0 0 1 1 0
10
0 1 0 1 0
11
0 1 1 0 1 A
0 1
1 0 0 1 0 B 0 1
CIN
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1 S COUT