IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO.
6, NOVEMBER/DECEMBER 2016
Characterization and Modeling of a Gallium Nitride
Power HEMT
Kang Peng, Soheila Eskandari, and Enrico Santi
AbstractIn this paper, a simple and accurate circuit-simulator
compact model for gallium nitride (GaN) high electron mobility
transistor is proposed and validated under both static and switch-
ing conditions. A novel feature of this model is that it is valid also
in the third quadrant, which is important when the device operates
as a freewheeling diode. The only measurements required for the
parameter extraction are simple IV static characteristics and
CV characteristics. A detailed parameter extraction procedure
is presented. Furthermore, a double-pulse test-bench is built to
characterize the resistive and inductive switching behavior of the
GaN device. A simulation model is built in Pspice software tool,
considering the parasitic elements associated with the printed
circuit board interconnections and other test-bench components
(load resistor, load inductor, and current shunt monitor). The
Pspice simulation results are compared with experimental results.
The comparison shows good agreement between simulation and
experimental results under both resistive and inductive switching
conditions. Operation in the third quadrant under inductive
switching is also validated.
Index TermsModeling, power conversion, power electronics,
power semiconductor devices, power semiconductor diode
switches, power semiconductor switches, semiconductor device
modeling.
I. INTRODUCTION
ALLIUM NITRIDE (GaN) is considered one of the most
G promising semiconductor material candidates for high-
frequency, high-efficiency, and high-power density power con-
version applications with significant advantages over silicon
because of its excellent electrical properties, such as wider
bandgap, higher thermal conductivity, and higher critical break-
down electric field [1][3]. The GaN high-electron-mobility
transistor (HEMT) is the most promising active device in GaN
and is currently available from various manufacturers, such as
efficient power conversion (EPC), International Rectifier (now
acquired by Infineon), Transphorm, GaN Systems, and others.
GaN HEMT has a better Baliga figure of merit compared to
state-of-the-art Si MOSFETs, because GaN HEMT exhibits low
Manuscript received November 19, 2015; revised May 22, 2016; accepted
June 20, 2016. Date of publication July 7, 2016; date of current version Novem-
ber 18, 2016. Paper 2015-PEDCC-0781.R1, presented at 2014 Energy Conver-
sion Congress and Exposition, Pittsburgh, PA, USA, Sep. 1418, and approved
for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the
Power Electronic Devices and Components Committee of the IEEE Industry
Applications Society. This work was supported by the Office of Naval Research
under Grant N00014-08-1-0080.
The authors are with the Department of Electrical Engineering, University
of South Carolina, Columbia, SC 29208 USA (e-mail: pengk@email.sc.edu;
eskandar@email.sc.edu; santi@engr.sc.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2016.2587766
0093-9994 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
4965
on-state resistance, small parasitic device capacitance, and high
critical electric field [4]. As a result, GaN HEMT can switch at
faster speeds and exhibit lower conduction and switching losses
[5][8]. Since power semiconductor device performance plays
a key role in power electronics applications, power electronics
designers need validated circuit-oriented device models to eval-
uate the performance of GaN HEMTs in different applications.
The objective of this work is to develop a simple and accu-
rate circuit-simulator compact device model, and validate it for
commercially available GaN HEMT devices under static and
switching conditions.
So far several device models have been proposed for GaN
HEMT, most of them based on device physics. These physics-
based device models provide more accuracy but have some
disadvantages: They typically require several device parame-
ters (which are usually unavailable to circuit designers) to apply
the model to a specific device; they are complicated; and they
require long simulation time [9]. Additionally, most of these
models have originally been developed for radio frequency or
microwave applications, which are quite different from power
electronics applications. Very few papers have been published
on the development of a device model for GaN HEMT in the
power conversion area. In [10], a simple GaN power transistor
model for dcdc converters has been proposed, and it is shown
to have good static characteristics in most respects. However,
this paper does not provide switching characteristics and does
not consider the reverse channel current conduction behavior
of GaN HEMT. The reverse channel current conduction is of
vital importance, because the GaN transistor has no body diode.
When GaN HEMT is required to operate in the third quadrant,
the reverse channel current conduction from source to drain
functions as an equivalent body diode. In [11], a GaN HEMT
model has been developed in SaberRD and static IV and CV
characteristics have been validated, but the validation of switch-
ing characteristics is not provided.
This paper describes the development and validation of a
simple GaN HEMT device model including both forward and
reverse channel current conduction. The device under investi-
gation is the commercially available EPC 2001 (100 V/7 m)
from EPC. The simulation software used in this modeling work
is Pspice. In Section II, the model equations are given. In
Section III, static characterization is performed using a curve
tracer and CV analyzer. A parameter extraction procedure is
proposed to extract device model parameter values. The model
validation is presented in Section IV. For dynamic switch-
ing characterization, a double-pulse tester (DPT) printed cir-
cuit board (PCB) with both a resistive load and an inductive
load is built. The 3-D inductance extraction software program
4966 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 6, NOVEMBER/DECEMBER 2016

TABLE I
OPERATING REGIONS OF VOLTAGE-DEPENDENT CURRENT SOURCE

Operating region Condition Equation

Cut off Vg s < Vth 1 , Vd s Id s = 0

Forward conduction linear
region
Forward conduction
saturation region
Reverse conduction linear
region
Reverse conduction
saturation region
0orV g d < V t h 2 , V s d 0
Vd s < Vg s Vth 1
and V d s > 0
Vd s > Vg s Vth 1 > 0
and V d s > 0
V s d < V g d V t h 2 and
Vsd > 0
V s d > V g d V t h 2 > 0 and
Vsd > 0
Id s =
K p 1 [(V g s V t h 1 )
V d s V d s 2 /2]
Id s =
K p 1 (V g s V t h 1 ) 2
(1 + 1 V d s )/2
I d s = K p 2
[(V g d V t h 2 )V s d
V s d 2 /2]
I d s = K p 2
(V g d V t h 2 ) 2 /2

Fig. 1. Structure of the GaN HEMT model.
FastHenry is used to estimate the parasitic inductances from
DPT circuit PCB layout. The extracted gate drive loop and
drain-to-source main switching loop parasitic inductances from
the PCB layout are used in Pspice simulation circuit together
with the developed GaN HEMT model to accurately simulate
the resistive and inductive switching transient behavior of the
power devices.
II. DEVELOPMENT OF A DEVICE SIMULATION MODEL
The simple circuit-simulator compact GaN HEMT model de-
veloped in this work is shown in Fig. 1. The model comprises
a voltage-dependent current source Ids , two voltage-dependent
capacitances Cgd and Cds , a voltage-independent gatesource
capacitance Cgs , and three parasitic resistances Rg , Rs and Rd .
The voltage-dependent current source Ids is used to model static
current-voltage (IV) characteristics for both forward and re-
verse conduction. The three parasitic capacitances play a vital
role in determining device switching performance. Note that for
simplicity dynamic on-resistance effectsthe so-called current
collapse phenomenonare not considered in this model.
A. Voltage-Dependent Current Source Ids
The voltage-dependent current source Ids is a bidirectional
current source function of internal device node voltages Vds and
Vgs . Since the device has a nearly symmetrical lateral structure, a
positive gate-to-drain voltage will enhance channel conduction
in the third quadrant in the same way as a positive gate-to-source
voltage does in the first quadrant. Therefore, the forward and re-
verse channel conduction modes are both taken into account. In
order to accurately predict power converter performance at dif-
ferent operating temperatures, accurate temperature-dependent
device transconductance parameter Kp is used in the circuit
model.
The voltage-dependent current source Ids determines the
model IV characteristics in the four operating modes: for-
ward linear, forward saturation, reverse linear, and reverse sat-
uration modes. These operating regions and the corresponding
current equations are listed in Table I where Vth1 is the thresh-
old voltage for forward channel conduction, and Vth2 is the
threshold voltage for reverse channel conduction. Notice that
this model neglects the temperature effect on threshold volt-
ages, which can be taken into account in future work. Kp1 is
the temperature-dependent device transconductance parameter
in forward conduction mode. Kp2 is the temperature-dependent
device transconductance parameter in reverse conduction mode.
1 is the channel length modulation parameter for forward chan-
nel conduction.
B. Parasitic Capacitances Cgs , Cgd , and Cds
Since gatesource capacitance is relatively independent of
the voltage potentials applied to the electrodes, a constant gate
source capacitance Cgs is used in this device model. This as-
sumption is justified by device capacitance measurement shown
in Fig. 8. Capacitances Cgd and Cds are nonlinear voltage-
dependent parasitic capacitances, given by
Cgd0
Cgd =  |V g d |
m 1 (1)
1+ PB1
Cds0
Cds =  |V d s |
m 2 (2)
1+ PB2
where Cgd0 is the zero-bias gate-to-drain capacitance, and Cds0
is the zero-bias drain-to-source capacitance. PB1 and PB2 are
the junction built-in potentials for gatedrain capacitance Cgd
and drainsource capacitance Cds , respectively. The parameters
m1 and m2 are the junction grading coefficients for gatedrain
capacitance Cgd and drainsource capacitance Cds , respectively.
C. Parasitic Resistances Rg , Rs , and Rd
The internal gate resistance Rg is assumed to be zero, com-
pared with the external gate resistance typically introduced to
dampen transient oscillations during switching transients. Re-
sistances Rd and Rs are assumed to be constant and represent
the distributed nature of terminal contact mesh.
PENG et al.: CHARACTERIZATION AND MODELING OF A GALLIUM NITRIDE POWER HEMT 4967

TABLE II
GAN HEMT MODEL PARAMETERS

Kp 1 Forward conduction device transconductance parameter at room

temperature
Kp 2 Reverse conduction device transconductance parameter at room
temperature
Vth 1 Forward conduction gate threshold voltage
Vth 2 Reverse conduction gate threshold voltage
1 Forward conduction channel length modulation coefficient
Cgs Gatesource capacitance
Cgd 0 Zero-bias gatedrain capacitance
PB 1 Built-in potential for gatedrain capacitance
m1 Junction grading coefficient for gatedrain capacitance
Cd s0 Zero-bias drainsource capacitance
PB 2 Built-in potential for drainsource capacitance
m2 Junction grading coefficient for drainsource capacitance
Rd Drain parasitic resistance
Rs Source parasitic resistance Fig. 3. Measured reverse output IV characteristics at room temperature 25C
T c 1 1 T c 2 1 Temperature coefficients for forward conduction device constant for EPC 2001.
T c 1 2 T c 2 2 Temperature coefficients for reverse conduction device constant

Fig. 4. Measurement of forward temperature-dependent output characteristics

at 25C (solid) and 125C (dashed).

Fig. 2. Measured forward output IV characteristics at room temperature 25C

for EPC 2001.
tracer, and capacitance CV characteristics with a Keithley
590 CV analyzer.
D. Temperature Dependence of the Device Transconductance
Parameter Kp A. Static Characteristics of GaN HEMT

In order to accurately estimate the device conduction loss
versus temperature, the device model should include the
temperature dependence of the device transconductance param-
eter Kp , which determines the voltage drop across the device as
a function of current. A quadratic fit for the temperature depen-
dence of the device transconductance parameter Kp is proposed
 
Kp = Kp0 / 1 + Tc1 (T T0 ) + Tc2 (T T0 )2 (3)
where Kp0 is the nominal device transconductance parameter
at room temperature, T0 is nominal room temperature, and Tc1
and Tc2 are temperature coefficients.
The complete list of the needed parameters for the considered
device model is shown in Table II.
The forward output characteristic family of curves is mea-
sured under different gatesource voltage bias conditions (from
2 V up to 5 V) in Fig. 2. The reverse output characteristic curves
under different gatesource voltage bias conditions (from 3 V
up to 2 V) are shown in Fig. 3. It is interesting to notice that
the reverse characteristic curves do not exhibit saturation char-
acteristics similar to the forward characteristics curves. This is
due to the fact that these characteristics are measured with a
curve tracer under constant gatesource voltage Vgs = const.,
but for reverse conduction the controlling voltage is the gate
drain voltage Vgd . As sourcedrain voltage Vsd increases, gate
drain voltage also increases according to
Vgd = Vgs + Vsd = const + Vsd . (4)

III. STATIC CHARACTERIZATION AND PARAMETER

EXTRACTION
The parameter extraction approach used in this paper is based
on static characterization of the semiconductor device. Static IV
characteristics are measured with a Tektronix 371A curve
The measured forward output characteristic curves
(Vgs = 2/3/4/5 V) under operating temperatures 25 and
125C are shown in Fig. 4. As seen, the slope of the IV
curve decreases with increasing temperature, indicating the
decreasing channel conductivity. This is due to the lower
4968 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 6, NOVEMBER/DECEMBER 2016

Fig. 7. Measurement of transfer characteristic at room temperature.

Fig. 5. Measured on resistance of GaN HEMT at 5 V gatesource voltage as

a function of junction temperature.

Fig. 8. Measured capacitances versus drain-to-source voltage for EPC 2001.

Fig. 6. Measurement of reverse temperature-dependent output characteristics

at 25C (solid) and 125C (dashed).

channel carrier mobility under higher operating temperatures.

This device characteristic is potentially beneficial to device par-
alleling. Fig. 5 shows the measured on-resistance at maximum
gatesource voltage (Vgs = 5 V) as a function of junction tem-
perature. The measured on-resistance of GaN HEMT increases
from 6.01 to 10.01 m, as device junction temperature rises
from 25 to 125C.
The measured reverse output characteristics curves
(Vgs = 3/ 2/ 1/0/2 V) under operating temperatures 25
and 125C show a similar behavior in Fig. 6.
Fig. 9. Plot of the square root of Id s versus gatesource voltage.
The measured transfer characteristic of GaN HEMT at room
temperature is shown in Fig. 7, which describes drain current
Ids as a function of gatesource voltage Vgs at a constant drain
source voltage Vds . 1) Forward Conduction Device Transconductance Parame-
A plot of measured device parasitic capacitances is shown ter Kp1 and Threshold Voltage Vth1 : A curve of the square
in Fig. 8. These measurements justify the choice of having a root of Ids versus gatesource voltage Vgs shown in Fig. 9 is
constant gatesource capacitance Cgs , since from Fig. 8 one plotted to extract the forward conduction device transconduc-
can see that Cgs = Ciss Crss approximately constant. tance parameter Kp1 and threshold voltage Vth1 . The parameter
(Kp1 /2)0.5 is extracted from the slope of an operating point
on the curve, when the GaN HEMT operates in the saturation
B. Parameter Extraction
region of forward conduction. The threshold voltage Vth1 is ex-
The parameter extraction process for GaN HEMT is devel- tracted from the point of intersection of the tangent line to the
oped using only measured static IV and CV characteristics. curve with the x-axis.
The parameter extraction process using static characterizations 2) Forward Conduction Channel Length Modulation Co-
is described as follows. efficient 1 : The channel-length modulation coefficient 1 is
PENG et al.: CHARACTERIZATION AND MODELING OF A GALLIUM NITRIDE POWER HEMT
Fig. 10. Plot of the square root of Isd versus gatedrain voltage.
Fig. 11. Loglog plot of C g d versus drain-gate voltage.
extracted from the slope of forward output IV characteristics
in the saturation region.
3) Reverse Conduction Device Transconductance Parameter
Kp2 and Threshold Voltage Vth2 : A curve of the square root of
Isd versus gatedrain voltage Vgd shown in Fig. 10 is plotted to
extract the reverse conduction device transconductance param-
eter Kp2 and threshold voltage Vth2 . The parameter (Kp2 /2)0.5
is extracted from the slope of an operating point on the curve,
when the GaN HEMT operates in the saturation region of re-
verse conduction. The threshold voltage Vth2 is extracted from
the point of intersection of the tangent line to the curve with the
x-axis.
4) GateSource Capacitance Cgs : The gatesource capaci-
tance Cgs is approximately constant. The parameter Cgs is ex-
tracted from Ciss and Crss measurements.
5) Zero-Bias GateDrain Capacitance Cgd0 , Built-in Poten-
tial PB1 , and Junction Grading Coefficient m1 : The zero-bias
gatedrain capacitance Cgd0 is extracted from Crss measure-
ment at low gatedrain bias. As shown in Fig. 11, the junction
grading coefficient m1 is extracted from the slope of gatedrain
capacitance curve at high drain bias. The built-in potential PB1
is extracted from a linear interpolation of the curve. The accu-
4969
Fig. 12. Loglog plot of C d s versus drainsource voltage.
Fig. 13. Forward conduction output characteristics and on-resistance
extraction.
racy could be improved by using a higher order interpolation at
the cost of increased model complexity.
6) Zero-Bias DrainSource Capacitance Cds0 , Built-in Po-
tential PB2 , and Junction Grading Coefficient m2 : The zero-
bias gatedrain capacitance Cds0 is extracted from Coss and Crss
measurements at low drainsource bias. As shown in Fig. 12,
the junction grading coefficient m2 is extracted from the slope
of drainsource capacitance curve at high drain bias. The built-
in potential PB2 is extracted from a linear interpolation to the
curve.
7) Drain Parasitic Resistance Rd and Source Parasitic Re-
sistance Rs : The total forward conduction on-resistances at
varied gatesource voltages are extracted from output charac-
teristics shown in Fig. 13. In the linear IV region, the parasitic
resistances Rd and Rs are connected in series with the internal
channel resistance.
With on-resistances extracted from Fig. 13, a curve of total
on-resistance as a function of 1/(Vgs Vth1 ) is given in Fig. 14
to estimate the sum of parasitic resistances Rd and Rs . The
sum of Rd and Rs is extracted from the point of intersection of
tangent line to the curve with the y-axis [12].
4970 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 6, NOVEMBER/DECEMBER 2016

Fig. 14. Plot of on-resistance R o n versus 1/(V g s V th 1 ).

Fig. 15. Forward IV characteristic comparison between simulation (dashed)

TABLE III and measurement (solid) at room temperature 25C.
EXTRACTED MODEL PARAMETER VALUES FOR EPC 2001

Parameter Value Source

Kp 1 103.664 A/V2 DC transfer characteristics

Kp 2 102.259 A/V2 DC transfer characteristics
Vth 1 1.155 V DC transfer characteristics
Vth 2 1.285 V DC transfer characteristics
1 0.241 A/V DC output characteristics
Cgs 0.804 nF CV characteristics
Cgd 0 0.151 nF CV characteristics
PB 1 1.216 V CV characteristics
m1 0.451 CV characteristics
Cd s0 1.299 nF CV characteristics
PB 2 1.805 V CV characteristics
m2 0.302 CV characteristics
Rd 2.400 m DC output characteristics
T c 1 1 0.013 Temperature
T c 2 1 1.906 10 5 Temperature
T c 1 2 0.002 Temperature
T c 2 2 6.241 10 5 Temperature Fig. 16. Forward I--V characteristics comparison between simulation (dashed)
and measurement (solid) in linear region (zoom-in of prior figure) at room
temperature 25C.

Considering the lateral device structure of GaN HEMT, drain

parasitic resistance Rd is much larger than source parasitic resis-
tance Rs . Therefore, source parasitic resistance Rs is assumed
to be zero in this model.
8) Temperature Coefficients Tc11 , Tc12 , Tc21 and Tc22 :
Only parameters Kp1 and Kp2 have temperature dependence.
The nominal device transconductance parameters at room tem-
perature Kp0 1 and Kp0 2 are extracted at room temperature
(25C). To extract the temperature coefficients, the same ex-
traction procedure for parameters Kp1 and Kp2 is performed at
several higher temperatures (50, 75, 100, and 125C). Only the
temperature-dependent parameters are extracted at each temper-
ature, while the temperature-independent parameters are fixed
at their room temperature values. Values for parameters Kp1 and
Kp2 are obtained at several temperature points. Using tempera-
ture dependence (3), the temperature coefficients are extracted
using the parameter values as a function of temperature.
IV. MODEL VALIDATION
The parameter extraction method of a GaN HEMT model
is described in Section III. Table III lists the extracted model
parameter values for EPC 2001 (100 V/7 m) GaN HEMT. In
this section, the developed GaN HEMT model is validated under
static and switching conditions.
A. Validation of Static Characteristics
Fig. 15 shows the comparison of simulated (dash lines) IV
characteristics of GaN HEMT in forward conduction mode
based on the extracted parameters with experimental (solid
lines) static characteristics. The simulation IV curves are in
good agreement with experimental data under different gate
bias conditions; however, some discrepancies can be observed
in the saturation region. In order to capture the device on-state
behavior, accurate modeling of the output characteristics in the
linear region is crucial. Fig. 16 shows the comparison of sim-
ulated (dash lines) IV characteristics of GaN HEMT in the
forward linear region based on the extracted parameters with
experimental (solid lines) static characteristics. Good agree-
ment between measured and simulated results is shown. Fig.
17 shows the comparison between simulation (dash lines) IV
curves and experimental IV characteristics (solid lines) in re-
verse conduction mode. The simulation results have very good
matching with experimental results.
PENG et al.: CHARACTERIZATION AND MODELING OF A GALLIUM NITRIDE POWER HEMT 4971

Fig. 17. Reverse IV characteristic comparison between simulation (dashed)

and measurement (solid) at room temperature 25C. Fig. 19. Reverse IV characteristic comparison between simulation (dashed)
and measurement (solid) at 125C.

Fig. 20. On-resistance comparison between simulation (dashed) and measure-

ment (solid) at 5 V gatesource voltage.

Fig. 18. Forward IV characteristic comparison between simulation (dashed)

and measurement (solid) at 125C.

The measured and simulated IV characteristics in forward

conduction mode at 125C are shown in Fig. 18. Fig. 19
shows the measured and simulated IV characteristics in reverse
conduction mode. Excellent agreement is observed between
simulation and measurement in IV characteristics at 125C.
The comparison of on-resistance at maximum gate voltage
(Vgs = 5 V) between simulations and experiments is shown in
Fig. 20. The simulated on-resistance is in agreement with the
measured result over the temperature ranging from 25 to 125C.
Fig. 21. Comparison of CV characteristic between simulation (dashed) and
Fig. 21 shows the plot of measured and simulated capaci- measurement (solid).
tances of GaN HEMT, showing a discrepancy in the Coss volt-
age dependence at low drain voltages. This is probably due to
the specific geometry of the gatesource region.
PCB layout is carefully designed to minimize parasitic elements.
The current waveforms are measured by a coaxial shunt resis-
B. Validation of Switching Characteristics tor (0.1 ) with high bandwidth and low parasitics from T&M
A PCB DPT circuit has been built to verify the accuracy Research Products, Inc. The gate driver is driver IC LM5113
of the proposed GaN HEMT device model under switching from Texas Instruments, which is designed to drive both high
conditions. Figs. 22 and 23 show the double-pulse test circuit side and low side enhancement mode GaN HEMTs in a half-
schematic and PCB prototype. The double-pulse test circuit has bridge configuration. The gate driver LM5113 has separate turn-
a phase leg structure with a GaN HEMT EPC 2001 pair. The ON and turn-OFF driving pins, so that different gate resistances
4972 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 6, NOVEMBER/DECEMBER 2016

Fig. 22. Double-pulse test circuit schematic.

Fig. 24. Simulated (dashed) and experimental (solid) turn-ON voltage wave-
forms of resistive switching.

Fig. 23. Picture of DPT PCB board.

Fig. 25. Simulated (dashed) and experimental (solid) turn-OFF voltage wave-
can be used for turn-ON and for turn-OFF. Switching characteri- forms of resistive switching.
zation is done under resistive load conditions and inductive load
conditions at room temperature.
The 3-D inductance extraction software program FastHenry TABLE IV
RESISTIVE SWITCHING RESULTS
is used to estimate parasitic inductances in the DPT circuit PCB
layout [13]. The circuit components in the DPTincluding load
Turn-on gate Turn-off Turn-on Drainsource Turn-off Drainsource
inductor, load resistor, and current shuntare modeled on the resistance gate dv/dt (V/ns) voltage falling dv/dt (V/ns) voltage rising
basis of frequency domain measurements performed using the R o n () resistance time (ns) time (ns)
R o f f ()
Agilent 4395A network analyzer. These parasitics are included
in circuit simulations, in order to predict voltage and current 15 10 5.42 8.9 2.84 16.9
15 7.5 5.42 8.7 3.29 14.6
transient slopes, ringing, and spikes [14].
15 3 5.51 8.7 4.98 9.6
1) Resistive Switching Validation: For the resistive switch- 10 3 7.42 6.5 5.00 9.6
ing experiments the resistive load is 12 . Switching speeds and 7.5 3 9.34 5.2 5.17 9.3
0 0 16.2 3.0 26.6 1.78
energy losses are dependent on gate resistance values. Different
gate driver turn-ON and turn-OFF resistance values are tested.
The top GaN HEMT device is OFF in this testing. The compar-
ison between simulation and experiment is performed at room
temperature. Comparisons between experimental and simulated 16.2 V/ns and dv/dt(off) = 26.6 V/ns. Fig. 26 shows the turn-
waveforms are shown in Fig. 24 for turn-ON transient and in ON speed dependence on turn-ON resistance, while Fig. 27 shows
Fig. 25 for turn-OFF transient. The gate driver turn-ON resis- the turn-OFF speed dependence on turn-OFF resistance. As the
tance is 7.5 , and turn-OFF resistance is 3 . As seen from the gate resistance increases, switching speeds reduces as expected.
figures, the simulation results are in good agreement with the As turn-ON gate resistance varies from 7.5 to 15 , the corre-
experimental results. sponding turn-ON dv/dt drops from 9.34 to 5.42 V/ns. As turn-
Table IV shows EPC 2001 turn-ON and turn-OFF resistive OFF gate resistance increases from 3 to 10 , the corresponding
switching performance with different gate resistance values. The turn-OFF dv/dt is reduced from 5.17 to 2.84 V/ns. The simulated
fastest switching speeds obtained for the DPT are dv/dt(on) = results show a good matching with the experiment.
PENG et al.: CHARACTERIZATION AND MODELING OF A GALLIUM NITRIDE POWER HEMT
Fig. 26. Simulated (dashed) and experimental (solid) turn-ON dv/dt and drain
source voltage falling time dependence on turn-ON gate resistance.
Fig. 27. Simulated (dashed) and experimental (solid) turn-OFF dv/dt and drain
source voltage rising time dependence on turn-OFF gate resistance.
Fig. 28. Simulated (dashed) and experimental (solid) turn-ON transient under
inductive switching.
2) Inductive Switching Validation: For the inductive switch-
ing test a 250 H ferrite EE core inductor is used as an inductive
load in the phase-leg tester topology. The inductor is modeled by
adding to the main inductance an equivalent series resistance, an
equivalent parallel capacitance, as well as an equivalent parallel
resistance. By curve fitting, the measured inductor impedance
measured with the network analyzer, these parameters of the
load inductor can be extracted. Figs. 28 and 29 show the in-
ductive switching transient for the turn-ON and turn-OFF of the
4973
Fig. 29. Simulated (dashed) and experimental (solid) turn-OFF transient under
inductive switching.
Fig. 30. Simulated (dashed) and experimental (solid) turn-ON current wave-
forms under inductive switching.
Fig. 31. Simulated (dashed) and experimental (solid) turn-OFF current wave-
forms under inductive switching.
low-side device under 48 V dc voltage and 10 A load current,
with turn-ON resistance 15 and turn-OFF resistance 7.5 .
A good matching between simulation and measurement voltage
waveforms is observed.
Figs. 30 and 31 show the drain current waveforms during
turn-ON and turn-OFF transient under 10 A inductive switch-
ing condition. Both turn-ON and turn-OFF drain current tran-
sient comparisons show fairly good agreement. A discrepancy
between simulated and experimental results is found in drain
4974 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 6, NOVEMBER/DECEMBER 2016
Fig. 32. (a) Double-pulse test schematic. (b) Gate drive signals showing the
dead time introduced to prevent cross-conduction.
current ringing shown in Fig. 30. This might be due to the un-
derestimated capacitances Cgd and Cds at low voltage bias in
device model parameter extraction shown in Figs. 11 and 12.
There is a slight difference in ringing resonant frequency be-
tween simulated and experimental waveforms in Fig. 31. This
is probably caused by the nonlinear capacitance model in the
GaN HEMT model or the extracted parasitic inductances.
3) Validation of Third Quadrant Operation: Considering
the double-pulse test circuit under inductive load, shown in
Fig. 32(a), the top side GaN HEMT Q1 operates as a free-
wheeling diode. One main difference between a GaN HEMT
and a silicon MOSFET is that the GaN HEMT does not have
a built-in body diode. When the GaN HEMT is used as a free-
wheeling diode, it actually operates in the third quadrant. With
zero gatesource voltage bias, the GaN HEMT has a voltage
drop of almost 1.7 V for 10 A current as shown in Fig. 3. There-
fore, it is desirable to reduce this conduction loss by turning ON
the top HEMT similarly to synchronous rectifier operation for
a MOSFET circuit [15]. A short 100 ns dead time between the
two gate drive signals is introduced to avoid cross-conduction,
as shown in Fig. 32(b).
Fig. 33. Comparison of simulated (dashed) and experimental (solid) drain
source voltage waveforms of Q2 at turn-ON transition.
Fig. 34. Comparison of simulated (dashed) and experimental (solid) drain
source voltage waveforms of Q2 during dead time (zoom-in of prior figure).
Fig. 33 shows the drainsource voltage of the Q2 switch at
turn-ON. From the figure it can be seen that the drainsource
voltage increases by about 1.7 V during the 100 ns dead time.
This is due to the increased voltage drop across switch Q1 during
the dead time. Fig. 34 shows a zoom-in of the voltage during the
dead time interval. Note that the simulation captures this effect
and shows excellent agreement with the experiment.
V. CONCLUSION
In this paper, a simple and accurate circuit-simulator compact
model for a normally off GaN HEMT device is developed. The
model parameters can be easily extracted from static IV char-
acteristics and CV characteristics. This model captures reverse
channel conduction, which is a very important feature for cir-
cuit designers. To the authors knowledge, this is the first GaN
HEMT model that describes the complete static IV character-
istics for power electronics applications. A parameter extraction
method is provided to allow easy extraction of model param-
eters using static IV characteristics and CV characteristics.
The device model is validated under static conditions over a
wide temperature range of 25 to 125C. A double-pulse test-
bench is built to test the switching behavior of GaN HEMT. In
PENG et al.: CHARACTERIZATION AND MODELING OF A GALLIUM NITRIDE POWER HEMT
order to simulate the parasitic ringing during very fast switch-
ing transient, gate-to-source driving loop and drain-to-source
main switching loop parasitic elements of the PCB layout are
extracted using a 3-D impedance extraction program. The ex-
tracted parameters are used with the GaN HEMT device models
for resistive and inductive hard switching simulations in Pspice.
The simulation results are compared with experimental results.
The comparison shows good matching between simulated and
experimental results under both resistive and inductive switch-
ing. The dynamic performance of the GaN HEMT in its reverse
conduction region is also verified. However, some future work
can be done to improve the proposed GaN HEMT model, such
as dynamic Rds (on), which is not captured in this model.
REFERENCES
[1] E. Santi, K. Peng, H. A. Mantooth, and J. L. Hudgins, Modeling of
wide-bandgap power semiconductor devices-part II, IEEE Trans. Elec-
tron Devices, vol. 62, no. 2, pp. 434442, Feb. 2105.
[2] U. K. Mishra, P. Parikh, and Y. Wu, AlGaN/GaN HEMTsAn overview
of device operation and applications, in Proc. IEEE vol. 90, no. 6,
pp. 10221031, Jun. 2002.
[3] M. A. Khan, G. Simin, S. Pytel, A. Monti, E. Santi, and J. L. Hudgins,
New developments in gallium nitride and the impact on power
electronics, in Proc. IEEE Power Electron. Spec. Conf., Jun. 2005,
pp. 1526.
[4] A. Lidow, J. Strydom, M. de Rooij, and Y. Ma, GaN Transistors for
Efficient Power Conversion. El Segundo, CA, USA, Power Conversion
Publications, 2012.
[5] R. Mitova, R. Ghosh, U. Mhaskar, D. Klikic, M. Wang, and A. Dentella,
Investigations of 600 V GaN HEMT and GaN diode for power converter
applications, IEEE Trans. Power Electron., vol. 29, no. 5, pp. 24412452,
May 2014.
[6] X. Huang, Z. Liu, Q. Li, and F. C. Lee, Evaluation and application of
600 V GaN HEMT in cascode structure, IEEE Trans. Power Electron.,
vol. 29, no. 5, pp. 24532461, May 2014.
[7] B. Wang, M. Riva, J. D. Bakos, and A. Monti, Integrated circuit im-
plementation for a GaN HFET driver circuit, IEEE Trans. Ind. Appl.,
vol. 46, no. 5, pp. 20562067, Sep./Oct. 2010.
[8] T. Ishibashi et al., Experimental validation of normally-on GaN HEMT
and its gate drive circuit, IEEE Trans. Ind. Appl., vol. 51, no. 3, pp.
24152422, May/Jun. 2015.
[9] T. Yu and K. Brennan, Theoretical study of a GaN-AlGaN high electron
mobility transistor including a nonlinear polarization model, IEEE Trans.
Electron Devices, vol. 50, no. 2, pp. 315323, Feb. 2003.
[10] K. Shah and K. Shenai, Simple and accurate circuit simulation model for
gallium nitride power transistors, IEEE Trans. Electron Devices, vol. 59,
no. 10, pp. 27352741, Oct. 2012.
[11] R. Khanna, W. Stanchina, and G. Reed, Effects of parasitic capacitances
on gallium nitride hetero-structure power transistors, in Proc. IEEE En-
ergy Convers. Congr. Exhib., 2012, pp. 14891495.
[12] F. J. Garcia-Sanchez, A. Oritz-Conde, and J. J. Liou, Extraction of the
source and drain series resistance of MOSFETs, Microelectron. Reliab.,
vol. 39, no. 8, pp. 11731184, Aug. 1999.
[13] R. Fu, A. Grekov, K. Peng, and E. Santi, Parasitic modeling for accurate
inductive switching simulation of converters using SiC devices, in Proc.
IEEE Energy Convers. Congr. Expo., 2013, pp. 12591265.
4975
[14] Z. Liu, X. Huang, F. C. Lee, and Q. Li, Package parasitic inductance
extraction and simulation model development for the high-voltage cascode
GaN HEMT, IEEE Trans. Power Electron., vol. 29, no. 4, pp. 19771985,
Apr. 2014.
[15] D. Han and B. Sarlioglu, Dead-time effect on GaN-based synchronous
boost converter and analytical model for optimal dead-time selection,
IEEE Trans. Power Electron., vol. 31, no. 1, pp. 601612, Jan. 2016.
Kang Peng received the bachelors degree in elec-
trical engineering from Hunan University, Changsha,
China, in 2008; the M.S. degree in electrical engi-
neering from the Huazhong University of Science and
Technology, Wuhan, China, in 2011; and the Ph.D.
degree in electrical engineering from the University
of South Carolina, Columbia, SC, USA, in 2016.
His research interests include modeling and sim-
ulation of semiconductor power devices, and power
converter design, control, and simulation.
Soheila Eskandari received the M.Sc. degree in elec-
trical engineering from Clemson University, Clem-
son, SC, USA, in 2013. She is currently working
toward the Ph.D. degree in the Department of Elec-
trical Engineering, University of South Carolina,
Columbia, SC.
Her research interests include switched-mode
power converters, simulation and design of semi-
conductor power devices and circuits, and control
of power electronics systems.
Enrico Santi received the bachelors degree in elec-
trical engineering from the University of Padua,
Padua, Italy, and the Ph.D. degree in power electron-
ics from Caltech University, Pasadena, CA, USA, in
1988 and 1994, respectively.
Since 1998, he has been with the Department of
Electrical Engineering, University of South Carolina,
Columbia, SC, USA, where he is currently an As-
sociate Professor. He has published more than 150
papers on power electronics, and modeling and sim-
ulation in international journals and conference pro-
ceedings. His research interests include switched-mode power converters, ad-
vanced modeling and simulation of power systems, modeling and simulation of
semiconductor power devices, and control of power electronic systems.