Verilog Introduction

What is Verilog ?

Verilog is powerful HDL that was created to perform chip design at a higher level rather than
doing it through schematic capture.

It is textual format for describing electronic circuits and systems. Applied to electronic design,
Verilog is intended to be used for verification through simulation, for timing analysis, for test
analysis (testability analysis and fault grading) and for logic synthesis.

-Synthesis Tools that could convert the verilog HDL in to synthesize net list.

Histry of Verilog HDl :

Verilog was invented by Phil Moorby & Prabhu Goel at Gateway Design Automation Systems in
1983/84.

Verilog was started initially as a proprietary hardware modeling language by Gateway Design
Automation Inc. around 1984. It is rumored that the original language was designed by taking
features from the most popular HDL language of the time, called HiLo, as well as from
traditional computer languages such as C. At that time, Verilog was not standardized and the
language modified itself in almost all the revisions that came out within 1984 to 1990.

Verilog simulator was first used beginning in 1985 and was extended substantially through 1987.
The implementation was the Verilog simulator sold by Gateway. The first major extension was
Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which
was a very efficient method for doing gate-level simulation.

The time was late 1990. Cadence Design System, whose primary product at that time included
Thin film process simulator, decided to acquire Gateway Automation System. Along with other
Gateway products, Cadence now became the owner of the Verilog language, and continued to
market Verilog as both a language and a simulator. At the same time, Synopsys was marketing
the top-down design methodology, using Verilog. This was a powerful combination.

In 1990, Cadence recognized that if Verilog remained a closed language, the pressures of
standardization would eventually cause the industry to shift to VHDL. Consequently, Cadence
organized the Open Verilog International (OVI), and in 1991 gave it the documentation for the
Verilog Hardware Description Language. This was the event which "opened" the language.

OVI did a considerable amount of work to improve the Language Reference Manual (LRM),
clarifying things and making the language specification as vendor-independent as possible.

Soon it was realized that if there were too many companies in the market for Verilog, potentially
everybody would like to do what Gateway had done so far - changing the language for their own
benefit. This would defeat the main purpose of releasing the language to public domain. As a
result in 1994, the IEEE 1364 working group was formed to turn the OVI LRM into an IEEE
standard. This effort was concluded with a successful ballot in 1995, and Verilog became an
IEEE standard in December 1995.

When Cadence gave OVI the LRM, several companies began working on Verilog simulators. In
1992, the first of these were announced, and by 1993 there were several Verilog simulators
available from companies other than Cadence. The most successful of these was VCS, the
Verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed
to an interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but
simulation execution speed was much faster.

In the meantime, the popularity of Verilog and PLI was rising exponentially. Verilog as a HDL
found more admirers than well-formed and federally funded VHDL. It was only a matter of time
before people in OVI realized the need of a more universally accepted standard. Accordingly, the
board of directors of OVI requested IEEE to form a working committee for establishing Verilog
as an IEEE standard. The working committee 1364 was formed in mid 1993 and on October 14,
1993, it had its first meeting.

The standard, which combined both the Verilog language syntax and the PLI in a single volume,
was passed in May 1995 and now known as IEEE Std. 1364-1995.

After many years, new features have been added to Verilog, and the new version is called
Verilog 2001. This version seems to have fixed a lot of problems that Verilog 1995 had. This
version is called 1364-2001.

How Verilog is Used :

Verilog may be used to model and simulate aspects of the complete system containing one or
more ASICs or FPGAs.

This may be a fully functional description of the system allowing the specification to be
validated prior to commencing detailed design.

Alternatively, this may be a partial description that abstracts certain properties of the system,
such as a performance model to detect system performance bottle-necks.

Verilog performs Simulated to check functionality.

Synthesized (net list generated). Static timing analysis.

This may be a fully functional description of the system allowing the specification to be
validated prior to commencing detailed design.

Alternatively, this may be a partial description that abstracts certain properties of the system,
such as a performance model to detect system performance bottle-necks.
Levels of Abstraction:

Verilog is both the structural and functional language. Internals of each module can be defined
at four levels of abstraction, depending on the need of the design. The module behaves
identically with the external environment irrespectively of the level of abstraction at which the
module is described. Internals of the module are hidden from the environment. Thus, the level of
abstraction to describe the module can be changed without any change in the environment.

The levels are described below:

Behavioral Level

Dataflow Level

Gate Level

Switch level

Behavioral model:

Verilog provides the designer the ability to describe the design functionality in an algorithmic
manner. In other words the designer describes the behavior of the circuit. The abstraction in this
modeling is as simple as writing the logic in C language. Verilog behavioral models contain
procedural statements that control the simulation and manipulate variables of the data types
previously described. The activity starts at the control constructs initial and always. Each initial
statement and each always statement starts a separate activity flow. All of the activity flows are
concurrent, allowing the user to model the inherent concurrence of hardware.

Behavioral Level is used to model the behavior of a design without describing its actual
Hardware structure.

If we know the algorithm or process of design we can use this type of Modeling.
 Procedural assignments:

Procedural assignments are used for updating reg, integer, time, real, realtime, and memory data
types.

The left hand side of a procedural assignment could be:

1. reg, integer, real, realtime, or time data type.

2. Bit-select of a reg, integer, or time data type, rest of the bits are untouched
3. Part-select of a reg, integer, or time data type, rest of the bits are untouched.
4. Memory word.

Syntax: wire out= in1 & in2;

Blocking assignments
Non-blocking assignments
Conditional (if-else) statement
Case statement
Loop statements : There are four types of looping statements in Verilog:

for loop,while,forever,repeat

Data Flow model:

For small circuits, the gate level modeling approach works very well because the number of
gates is limited and designer can instantiate and connects every gate individually. However in
complex design the number of gates is very large. Thus implementing the function at a level
higher than gate level is good choice. Dataflow modeling has become a popular design approach
as logic synthesis tools have become sophisticated. This approach allows the designer to
concentrate on optimizing the circuit in terms of data flow.

I. Continuous Assignments:
It is the most basic statement in dateflow level, used to drive a value onto a net. It replaces gates
in the description of the circuit and describes the circuit at a higher level of abstraction.

A continuous assignment statement starts with the keyword assign.

Syntax : assign [ delay ] net = expression;

Example : assign sum = a ^ b;

II. Implicit Continuous Assignment:

Instead of declaring a net and then writing a continuous assignment on the net. Verilog provides
a shortcut by which a continuous assignment can be placed on a net when it is declared. There
can be only one implicit declaration assignment per net because a net is declared only once.

Example: wire out= in1 & in2;

Data Flow Level is Describes the flow of data between registers and how a design processes
that data.

If we know the final equation of the design we can use this modeling

Gate Level :

A slightly higher level of abstraction would be the gate level, which refers to the ability to
describe the circuit as a netlist of primitive logic gates and functions. The gates have one scalar
output and multiple scalar inputs.

Gate Primitives:

AND,

OR,

XOR,

XNOR,
NAND,

NOR

Gate level is used to model the design from the basic instances .here basic building blocks are
logic .

Gates so Gate Level Describes the logic gates and the connections between logic gates in a
Design.

Switch Level :

The lowest level of abstraction for a digital HDL would be the switch level, which refers to the
ability to describe the circuit as a netlist of transistor switches. A more detailed modeling scheme
that can catch some additional electrical problems when transistors are used in this
way. Now, little-used because circuits generally arent built this way.

Switch Level Describes the transistors and storage nodes in a device and the connections
between Them.

RTL(Register Transfer Level):

A combination of both Behavioral & Dataflow constructs.

Acceptable to logic synthesis tool.

RTL on the other hand is a way of describing a circuit.

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations
and the transfer of data between the registers.

An explicit clock is used. RTL design contains exact timing bounds: operations are scheduled to
occur at certain times.

Modern RTL code definition is "Any code that is synthesizable is called RTL code".
Design Methodologies :

Verilog, like any other hardware description language, permits a design in either

Bottom-up or

Top-down methodology.

Top Down Design Methodology :

The desired design-style of all designers is the top-down one. A real top-down design allows
early testing, easy change of different technologies, a structured system design and offers many
other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most
designs are a mix of both methods, implementing some key elements of both design styles.

Bottom Up Design Methodology :

The traditional method of electronic design is bottom-up. Each design is performed at the gate-
level using the standard gates (refer to the Digital Section for more details). With the increasing
complexity of new designs this approach is nearly impossible to maintain. New systems consist
of ASIC or microprocessors with a complexity of thousands of transistors. These traditional
bottom-up designs have to give way to new structural, hierarchical design methods. Without
these new practices it would be impossible to handle the new complexity.

Modules :

module is the basic building block in Verilog.

Elements are grouped into modules to provide the common functionality that is used at many

places in the design.

A module provides the necessary functionality to the higher-level block through its port
interface

(inputs and outputs).

In Verilog a module is declared by the keyword module .

A corresponding keyword endmodule must appear at the end of the module definition.
 Modules CAN NOT be nested.

Rather,one module can instantiate another module.

Module instantiation is like creating actual objects (Instances) from the common
template(module definition).

Each instance of module has all the properties of that module.

Module instantiations are used for:

connecting different parts of the designs,and

connecting testbench to the design.

Structure of module

The <module name> is an identifier that uniquely names the

module.
 The <port list> is a list of input, inout and output ports which are used to connect to other
modules.

The <declares> section specifies data objects as registers, memories and wires as wells as
procedural constructs such as functions and tasks.

The <statements> may be initial constructs, always constructs, continuous assignments or

instances of modules.

module and_1(a,b,c) //module declerations

input a,b; //directions

output c;

assign c = a & b; //statements

endmodule // end of module .