Verilog Basic Concepts :

overall lexical conventions of Verilog, and how the language defines and interprets various
elements such as white space, strings, numbers, and keywords. Verilog consists of lexical tokens
(one or more characters) of the form:

Comments

Operators

Strings

Numbers

Keywords

Identifiers

System Tasks and Functions

Compiler Directives

Identifiers :

Identifiers are names given to objects so that they can be referenced in the design.

Identifiers can start with an alpha character (a-z, A-Z) or an underscore (_).

identifiers contain alphanumeric, dollar signs ($), and underscores.

Names of instances, modules, nets, ports, and variables are identifiers.

Verilog is case sensitive, sel and SEL are different identifiers.

Examples of legal identifiers

Data_in
Master_clk

Data_out

Escaped Identifiers:

Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped
identifiers provide a means of including any of the printable ASCII characters in an identifier
(the decimal values 33 through 126, or 21 through 7E in hexadecimal)

Escaped identifiers begin with the back slash ( \ )

Entire identifier is escaped by the back slash.
Escaped identifier is terminated by white space (Characters such as commas, parentheses,
and semicolons become part of the escaped identifier unless preceded by a white space)
Terminate escaped identifiers with white space, otherwise characters that should follow
the identifier are considered as part of it.

Examples of escape identifiers

Verilog does not allow to identifier to start with a numeric character. So if you really want to use
a identifier to start with a numeric value then use a escape character as shown below.

// There must be white space after the

// string which uses escape character

module \1dff (

q, // Q output

\q~ , // Q_out output

d, // D input

cl$k, // CLOCK input

\reset* // Reset input

);

input d, cl$k, \reset* ;

output q, \q~ ;

endmodule

Keywords :

Keywords are special identifiers reserved to define the language constructs.

Keywords are lowercase letters.

Keywords cannot be used as Identifiers that is module is a keyword but MODULE can be an
Identifier, though it is better not to use them so as to avoid confusion.
Verilog_Keywords:

always endmodule large reg

and endprimitive macromodule release
tranif0
assign endspecify nand repeat
tranif1
attribute endtable negedge rnmos
tri
begin endtask nmos rpmos
tri0
buf event nor rtran
tri1
bufif0 for not rtranif0
triand
bufif1 force notif0 rtranif1
trior
case forever notif1 scalared
trireg
casex fork or signed
unsigned
casez function output small
vectored
cmos highz0 parameter specify
wait
deassign highz1 pmos specparam
wand
default if posedge strength
weak0
defparam ifnone primitive strong0
weak1
disable initial pull0 strong1
while
edge inout pull1 supply0
wire
else input pulldown supply1
wor
end integer pullup table
xnor
endattribute join rcmos task
xor
endcase medium real time
endfunction module realtime tran

Comments :

Comments can be inserted in the code for readability and documentation.

Begin a single-line comment with // and end it with the new- line character.
 Begin a multi-line comment with /* and end it with */.

Examples:

// Single line comment

/* Begins multi-line (block) comment All text within is ignored

Line below ends multi-line comment */

Number Specification:

They are of two types

- Sized Numbers

- Un-sized Numbers

Sized Numbers :

Syntax : <size>'<baseformat><number>

Size of the number is calculated in binary format only. If dont mention any size by default it
takes as 32 bit integer .

After this we need to mention the format of number system if it is binary represent as B or b .

If it is decimal represent as D or d .

If it is Octal represent as O or o.

If it is Hexadecimal represent as H or h.
.then write the respective value .

4b1111 => this is a 4-bit binary number

12habc => this is a 12-bit hexadecimal number

Negative numbers: put minus sign before size.

Format : -<size><base><number>

<size> field is always +ve.

Represented by 2s complement internally.

Often _ (Underscore) is used in between digits of the number

for readability.

Ex :

Num = -6; // negative number

Num = -8d4; // 8 bit -ve number

Num = d-12; // // Illegal !!

Verilog numbers may have x or z as part of numbers.

x ? unknown value, z ? high impedance value

A question mark ? can also be used as an alternative to z.

Ex :

reg [5:0] Num;

Reg [31:0] data;

Num = 6b_100x; // Num = 6b00100x

data = 32bx; // 32 bit no with all x bits

Num = bz01; // Num = 6bzzzz01

Num = b11??1; // Num = 6b011zz1

data = 32h_x5f3_2693; // data = 32hX5f32693

If we going to represent the Negative numbers just put minus sign before size.

Format is -<size><base><number>

<size> field is always +ve.

Represented by 2s complement internally.

Often _ (Underscore) is used in between digits of the number for readability.

For example to represent the 8 bit negative decimal number - 8 d 4.

Verilog expands to fill given working from LSB to MSB.

If size is smaller than value MSBs of value are truncated with warning (tool dependent)

If size is larger than value

MSBs of value are filled with zeros. Regardless of MSB being 0 or 1, 0 filling is done

Verilog numbers may have x or z as part of numbers.

x ? Unknown value, z ? high impedance value

A question mark ? can also be used as an alternative to z.

module Verilog_number;

reg [7:0] Num;

wire status;
Num = 16; // 8b0001_0000

Num = -8d4; // twos complement of 4

Num = bx; // 8bxxxx_xxxx

Num = b0x; // 8b0000_000x

Num = b10x; // 8b0000_010x

if (status == 1) // status == 32h0001

Num = 8b1010_0101;

if (status == 1b1) // status == 1b1

endmodule

Values used in verilog :

Values used in verilog are : 0 1 X Z

0- Represents a logic Zero , or a false condition.

1-Represnts a logic ONE, or a True Statement.

X- Represents an Unknown logic value.

Z-Represents a High Impedance state.

Strengths:

Strongest signal Prevails.

Useful for gate level modeling and not for RTL.

Data Types:

There are two major data types

reg,

net,

by default these data types are 1 bit values scalr.

All can be vectors (multi-bit signal or bus) The default is scalar.

Nets:

Nets represent the connections between hardware elements.

They are always driven by some source.

Default value for any net type variable is "z.

Usually, declared by the keyword wire.

Different types: wire, wand, wor, tri, triand, trior, trireg, etc.

A wire connecting one driver to other gates input. Types wire and tri are identical. Two different
names are used as hint to intent. Type tri implies a tri-state buffer is driving the line.

tri0 - Like tri but when the resultant value is to be Z, it resolves to resistive pulldown.

tri1 - Like tri but when the resultant value is to be Z, it resolves to resistive pullup.

wand (triand) - Type indicates this wire has multiple drivers. (tri-state) The drivers are
configured in a wired-and configuration.

wor (trior) - Type indicates this wire has multiple drivers. (tri-state) The drivers are configured
in a wired-or configuration.

Supply0 Vss - , the circuit ground.

Supply1 Vdd - , the circuit Vdd power supply.

Trireg - A tri-state capacitive wire. It holds its old value when resultant value is Z. You can
specify how long the value is held.

Here interconnects(light blue color ) between combinational blocks is called wires.

Registers :

These correspond to variables in the C language.

Register data types always retain their value until another value is placed on them.

DO NOT confuse with hardware registers built with flip-flops.

A reg type variable is the one that can hold a value.

Unlike nets, register do not need any drivers.

Reg data type A reg data type represents a variable in Verilog

Type reg variable stores values,

but not necessarily a FF (register) Are only assigned in an always block task or function

If a reg data type is assigned a value in an always block that has a clock edge expression, a flip-
flop is inferred.

In synthesis, the compiler will generate latches or flip-flops for them. However, if it can be
sure their output does not need to be stored it will synthesize them into wires.

It can be sure they do not have to store if their outputs is based only on their present inputs.

Rules for Reg and Wire :

The common rule in Verilog :

A variable on the Left Hand Side (LHS) of a procedural block assignment is always declared
as a register data type.All other variables are of net type.

Verilog register data types: reg / time / integer / real / realtime / event (reg is the most common
of all.)

So , reg is assigned with in always or initial blocks.

A variable is declared of type wire if it appears on the left side ofan continuous assignment
statement.

Structural code continuous assignment statements start with the keyword assign.

Data Types:

Integer & Real Data Types

Declaration syntax is

integer i, k;

real r;

Use as registers (inside procedures)

i = 1;
 r = 2.9;

k = r; // k is rounded to 3

Integers are not initialized in Verilog!!

Reals are initialized to 0.0

Integer :

A general purpose register data type with default value having all x bits.

Declared with keyword integer.

Usually preferred for arithmetic manipulations over reg.

Default width: host machine word size(minimum32bits).

Differs from reg type as it stores signed quantities as opposed to reg storing unsigned
quantities.

Real Numbers:

Real number constants declared with a keyword real.

Real constants have default value of 0.

Real numbers CANNOT have arrange declaration.

Two notations: Decimal& Scientific notation.

When a real value is assigned to an integer, the real number is rounded off to the nearest
integer.

Time and real time Data types:

time A special register data type used mainly to store simulation time.

time is an unsigned 64-bit by default. Usually, it is used to store the simulation time.
 real time is similar to time except that it has initial value of 0.

Depending upon the timescale specified, real time provides the simulation time with the
fractional part with given precision.