International Journal of Electronics Letters

ISSN: 2168-1724 (Print) 2168-1732 (Online) Journal homepage: http://www.tandfonline.com/loi/tetl20

Approximate adder for low-power computations

Irina Alam & K T Lau

To cite this article: Irina Alam & K T Lau (2016): Approximate adder for
low-power computations, International Journal of Electronics Letters, DOI:
10.1080/21681724.2016.1138507

To link to this article: http://dx.doi.org/10.1080/21681724.2016.1138507

Accepted author version posted online: 11

Jan 2016.
Published online: 05 Feb 2016.

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 INTERNATIONAL JOURNAL OF ELECTRONICS LETTERS, 2016
http://dx.doi.org/10.1080/21681724.2016.1138507

Approximate adder for low-power computations

Irina Alam and K T Lau
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

ABSTRACT ARTICLE HISTORY

In present-day VLSI technology, errors cannot be avoided and it is Received 25 November 2014
not always feasible to overcome all errors. An attempt to get rid of Accepted 1 November 2015
all errors results in excessive power consumption and also slows KEYWORDS
down the system. In this article, a novel adder circuit has been Adders; approximate
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presented (Imprecise Adder Circuit) that produces imperfect computation; low power;
results but consumes lower power and is faster than traditional high speed circuit; error
adders. The 16-bit adder designed has been divided into four 4-bit tolerance
full adder blocks. All the adder circuits were designed with a 65-
nm CMOS technology. The software CADENCE was used for
designing and later for the post design simulations.

1. Introduction
Digital circuits are an important part in the present-day society. The basic principle
behind the MOSFET (Metal Oxide Semiconductor Field Eect Transistor) transistor
was proposed in a patent by J. Lilienfeld (Canada) as early as 1925 (Rabaey, 2003).
The advantage of CMOS technology over bipolar logic is its low power consump-
tion. Energy eciency is gaining more and more importance as power dissipation
aects feasibility, cost and reliability. For much of the history of CMOS design,
power was a secondary consideration behind speed and area for many chips (Weste
& Harris, 2004). However, with rapid increase in transistor counts and density,
power consumption is becoming a dominant concern and techniques to consider-
ably reduce it are gaining more attention. In recent years, the desirability of
portable operation of all types of electronic systems has become clear and a
major factor in the weight and size of portable devices is the amount of batteries
which is directly impacted by the power dissipated by the electronic circuits
(Chandrakasan & Brodersen, 1995).
In most multimedia applications, the nal output is interpreted by human senses,
which are not perfect (Gupta, Mohapatra, Park, Raghunathan, & Roy, 2011). Hence,
absolutely correct results are not always needed. Analog computation that yields
good enough results instead of totally accurate results (Breuer, 2005) is mostly
acceptable. All digital systems might not be able to employ the error tolerant circuit.
It is mostly used in digital signal processing systems such as image processing
system or communication system which are capable of absorbing errors. However,

CONTACT K T Lau EKTLAU@ntu.edu.sg School of Electrical and Electronic Engineering, Nanyang Technological
University, Singapore, Singapore
2016 Taylor & Francis
 2 I. ALAM AND K. T. LAU

Figure 1. Full adder cell.

Table 1. Truth table of a full adder.

A B Cin S C0
0 0 0 0 0
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0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

in some digital systems, such as a control system, the correctness of the output
signals is extremely important and hence eliminating the use of error-tolerant circuit
(Zhu, Goh, & Yeo, 2009).
Addition is one of the most fundamental and signicant operations used in electro-
nics and hence, most VLSI systems contain adder circuits. It is not only used for addition
and subtraction, but forms the rst step for more complex arithmetic operations. The
basic structure of a full adder cell is depicted in Figure 1.
The outputs generated by a 3-input full adder is shown in Table 1.
The remaining article rst discusses some important terms required to study the
performance of an approximate circuit. The next section then focusses on the design of
the novel 16-bit Imprecise Adder Circuit (IAC). Finally, a detailed comparison is provided
in results followed by conclusion.

2. Important terminologies
Following are some terms that are important in determining the performance of any
approximate digital circuit. The denitions of the terminologies are as follows:
Overall error (OE): The overall error is the dierence between the obtained
or experimental result Re and the original theoretical correct result Ro. Thus,
OE = | Ro Re|.
Accuracy (ACC): The accuracy of a circuit shows the extent to which the result is
correct. It is generally expressed in percentage form. ACC = (1 OE/Ro).
Minimum acceptable accuracy (MAA): It is the threshold accuracy. The minimum
accuracy of any approximate circuit must be higher than this threshold value.
 INTERNATIONAL JOURNAL OF ELECTRONICS LETTERS 3

3. Detailed design of the approximate adder circuit

The structure of the 16-bit adder (IAC) has been discussed in this section. The 16-bit
adder is divided into four 4-bit adder blocks as can be seen in Figure 2. Only the last two
4-bit adder blocks used for computing the lower 8 bits (8 LSBs) consist of approximate
adder cells. The rst two 4-bit adder blocks, used for computing the higher 8 bits (8
MSBs), are ensured to provide correct output by using conventional adder cells. Thus,
the 8 MSBs are more accurate than the lower 8 bits as they play a more signicant role in
representing a number. In short, it is done to reduce the overall error and ensure a
reasonable output quality.

3.1. Imprecise block one

In this 4-bit adder block, the last two bits (the two least signicant bits) are set to HIGH
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or logic 1 and these two output bits remain unchanged irrespective of the input. The
last two bits do not quite aect the overall output of the 16-bit adder circuit as they are
the least signicant bits. Hence, the need for a separate adder cell to compute these two
bits is not much and can be eliminated.
For the next two bits, the adder cells are an approximate version of the conventional
adder cell with lesser number of transistors. In this approximate adder cell, the carry
circuit is rst simplied. The rst part of the circuit in Figure 3 is the simplied carry
circuit. After the simplication of the carry circuit, one out of eight C0 outputs turned
out to be incorrect as shown in the truth Table 2. The output computed in this rst half
of the circuit is C0 .
From the truth table of a conventional full adder cell (Table 1), it can be seen that for
6 out of 8 cases, S =C0 . Thus the adder cell was further reduced by completely removing
the sum circuit and the sum S was directly set to C0 as seen in Figure 3.

Figure 2. Overall block diagram of the 16-bit novel adder circuit (IAC).
 4 I. ALAM AND K. T. LAU

Figure 3. The approximate full adder cell used in imprecise block one.
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Table 2. Truth table of the approximate full adder cell used in

imprecise block one.
A B Cin S C0
0 0 0 1 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1

Overall, 3 errors are introduced in the sum S output and 1 error is introduced in the
carry C0 output. This can be seen in Table 2.

3.2. Imprecise block two

In this 4-bit adder block, all the 4 bits are computed the same way unlike imprecise
block one. The approximate carry circuit used in the previous block is also used in this
adder block. The major change brought about in this block as compared to the previous
one is in the second part of the sum circuit. Instead of directly setting sum S to C0 , a
more detailed sum circuit, somewhat similar to the second half of a conventional adder,
is used and no approximation is done in this part of the circuit. The overall circuit can be
seen in Figure 4.
The overall errors introduced in the sum S output is reduced from 3 in the previous
block to 1 and the 1 error in the carry C0 output remains same as before. It can be seen
in Table 3.

3.3. Conventional 4-bit adder block

The conventional 4-bit adder block is built by cascading four conventional 28-transistor
1-bit full adder cells shown in Figure 5.
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Figure 4. The approximate full adder cell used in imprecise block two.

Table 3. Truth table of the approximate full adder cell used in

imprecise block two.
A B Cin
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
S C0
0 0 0
1 0 1
0 1 0
1 0 1
0 1 0
1 0 1
0 0 1
1 1 1

4. Results and discussion

The novel 16-bit IAC designed is compared with few previously designed 16-bit
approximate adder circuits and also with a conventional 16-bit ripple carry adder.
The software CADENCE was used to design all the 16-bit adder circuits. A set of 50
random input combinations were generated using the Math.random() function in
JAVA and used for this comparison. The previously designed approximate adder
circuits, with which the novel adder was compared, are as follows:

(1) Type II Error Tolerant Adder (ETAII) designed by Ning Zhu, Wang Ling Goh, and
Kiat Seng Yeo (Zhu et al., 2009).
(2) Modied ETAII (ETAIIM), also designed by Ning Zhu, Wang Ling Goh, and Kiat
Seng Yeo (Zhu et al., 2009).
 6 I. ALAM AND K. T. LAU
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Figure 5. The 1-bit conventional full adder circuit used in conventional 4-bit adder block.

(3) Almost Correct Adder (ACA) designed by Verma, Brisk and Ienne (Verma, Brisk, &
Ienne, 2008).
(4) Imprecise adders for low-power approximate computing (IMPACT) designed by
Kaushik Roy et al. (Gupta, et al., 2011).

In total, six 16-bit adder circuits were compared. The comparison was done based on
power, average accuracy, maximum error, delay and transistor count. The results
obtained are shown in Table 4.
For each input combination, the accuracy, error and power consumed were calcu-
lated. With 50 sets of results, the average accuracy and power and maximum and
minimum error were determined. The novel circuit designed in this project has achieved
the most important criterion, low power consumption. The power consumption of this
circuit (both static and total) is the least amongst those compared and can be used in

Table 4. Simulation results obtained (at 1.2 V).

Figure of merit
Figure of merit (delay (delay transistor
Power Accuracy Max. Delay Transistor transistor count count power)/
Type of Adder (W) (%) error (s) count power) (W-s) (accuracy) (W-s)
Conventional Ripple 3.04E-08 100.00 0 1.47E-03 448 2.006E-08 2.006E-08
Carry Adder
ETAII 9.76E-05 95.362 4096 4.60E-04 686 3.08E-05 3.23E-05
ETAIIM 7.23E-05 96.972 256 4.72E-04 686 2.34E-05 2.42E-05
ACA 5.81E-08 96.020 4096 3.07E-04 1024 1.82E-08 1.90E-08
IMPACT 2.31E-08 89.160 255 8.04E-04 344 6.39E-09 7.17E-09
Novel circuit IAC 2.27E-08 92.478 235 1.08E-03 340 8.33E-09 9.01E-09
 INTERNATIONAL JOURNAL OF ELECTRONICS LETTERS 7

low-power and ultra-low power circuits as it can operate at voltages as low as 1.2 V. It is
26% lower than the conventional adder. This low power consumption can be totally
attributed to the approximations and simplication of logic. The area of this circuit is
also the least (conventional adder has 1.32 times higher transistor count) and thus can
be used in circuits where area is a major consideration. One way to reduce power and
area further will be to extend the approximation to higher order bits. However, that
would result in a decrease in accuracy. Another very interesting feature of this circuit is
that it also has the lowest maximum error amongst all other circuits. The average
accuracy is around 4% higher than IMPACT but 4.6% lower than ETAIIM. So, the overall
quality of the output will be better than IMPACT but not as good as the other three.
Thus, it can be used in circuits whose output is interpreted by human senses and hence
a slightly lower accuracy will not create a huge dierence.
In the process, the delay got aected and the adder circuit designed turned out
to be slower than the previous ones. However, the delay of the novel circuit is
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26.5% lesser than the traditional ripple carry adder. The major reason for increase
in delay is that the carry out signal from the preceding 4-bit blocks were taken in
as the carry-in signal by the succeeding blocks. This was done to reduce the
maximum error and improve the quality of the overall output obtained.
Reducing the transistor count is an achievement as area is one of the primary
concerns in the present-day digital world. However, the most important point is the
ultra-low power consumption of the approximate adder circuit as that was the
primary focus of this research. The gure of merit shows that the performance of
the novel circuit in terms of accuracy, transistor count, delay and power consump-
tion is around 55% better than the conventional adder.

5. Conclusion
A novel 16-bit approximate adder (IAC) was designed. Standard 65 nm TSMC CMOS
technology was used for designing. The performance of the imprecise adder was
compared with that of the previous imprecise adders to highlight the advantages of
the newly designed adder.
The simulation results showed that the power consumed by the novel adder is
lesser than the previously designed approximate adder circuits it was compared
with. Though the average accuracy of the novel circuit is slightly less than the
others, the maximum error is much less compared to that of the others. Thus, the
quality of the output will be signicantly better in the case of the novel adder. In
addition, the transistor count is fewer than the other designs.

Disclosure statement
No potential conict of interest was reported by the authors.

References
Breuer, M. A. (2005). Lets think analog. Proceedings of the IEEE Computer Society Annual Symposium
on VLSI. doi:10.1109/ISVLSI.2005.48
 8 I. ALAM AND K. T. LAU

Chandrakasan, A. P., & Brodersen, R. W. (1995). Minimizing power consumption in digital CMOS
circuits. Proceedings of the IEEE, 83, 498523. doi:10.1109/5.371964
Gupta, V., Mohapatra, D., Park, S. P., Raghunathan, A., & Roy, K. (2011). IMPACT: IMPrecise adders
for low-power approximate computing. International Symposium on low Power Electronics and
Design (ISLPED), 409414. doi:10.1109/ISLPED.2011.5993675
Rabaey, J. M. (2003). Digital integrated circuits, a design perspective (2nd ed.). New Jersey: Prentice-
Hall.
Verma, A. K., Brisk, P., & Ienne, P. (2008). Variable latency speculative addition: A new paradigm for
arithmetic circuit design. Proceedings of Design, Automation, and Test in Europe, 12501255.
doi:10.1109/DATE.2008.4484850
Weste, N. H. E., & Harris, D. (2004). CMOS VLSI design, a circuits and systems perspective. Boston, MA:
Addison-Wesley.
Zhu, N., Goh, W. L., & Yeo, K. S. (2009). An Enhanced low-power high-speed adder for error-tolerant
application. Proceedings of International Symposium on Integrated Circuits, 6972. Retrieved
from http://ieeeexplore.ieee.org
Downloaded by [Laurentian University] at 03:17 01 March 2016