Vous êtes sur la page 1sur 67

A B C D E

COMPAL CONFIDENTIAL
MODEL NAME : PAL50/52
1 1

PCB NO : LA-6591P (DA80000JV10)


LA-6593P HF (DA80000MB10)
BOM P/N : 43192831L01
GPIO MAP:{Macallan} GPIO Map 10102010.xlsx

2
E3 MACALLAN 14" UMA/ATG 2

rPGA Sandy Bridge +


FCBGA PCH Cougar Point-M
2011-1-6
REV : 1.0(A00)
@ : Nopop Component
3
CONN@ : ME controll and stuff by default 3

MB Type BOM P/N

TPM EN/ TCM DIS 43192831L01 1@ 3@ 7@

TPM DIS/ TCM EN 43192831L02 2@ 4@ 7@

TPM DIS/ TCM DIS 43192831L04 2@ 3@ 7@

ATG TPM EN/ TCM DIS 43192831L11 1@ 3@ 7@

ATG TPM DIS/ TCM EN 43192831L12 2@ 4@ 7@

ATG TPM DIS/ TCM DIS 43192831L13 2@ 3@ 7@


4 4
TPM EN/ TCM DIS HF 4319BP31L01 1@ 3@ 8@
7@ MB PCB1
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DA80000JV10 PCB 0FD LA-6591P REV0 M/B UMA Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
8@ MB PCB2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Part Number Description
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
DA80000MB10 PCB 0FD LA-6593P REV0 M/B UMA HF LA-6591P
Date: Monday, January 10, 2011 Sheet 1 of 66
A B C D E
A B C D E

Block Diagram Compal confidential Model: PAL50/52

Memory BUS (DDR3) DDRIII-DIMM X2


1066/1333MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Sandy Bridge PAGE 12,13

4MB (Socket 988B)


1
rPGA CPU 1

On IO board Touch Screen


988 pins PAGE 24
CRT CONN VGA For MB/DOCK
Video Switch BT PAGE 43
PAGE 6-11
VGA PI3V712-AZLE
FDI DMI2 Camera Trough eDP Cable
Lane x 8 Lane x 4
VGA
HDMI CONN DPB SATA Repeater
INTEL USB SATA
MAX4951BE
PAGE 26 E-SATA
PAGE 39 2560
DPC
DPD COUGAR POINT-M USB Port PAGE 39
DOCKING PORT
PAGE 40 BGA
LVDS CONN LVDS USB Port PAGE 38
DAI
2560
PAGE 24
2
USB[8,9] 2

SATA5 PAGE 14-21 USB Port PAGE 38


DOCK LAN 2062
SDXC/MMC/MS Card reader on IO board
PAGE 35 OZ600FJ0LN PCIE x1 USB Port
PAGE 35
PCI Express BUS 100MHz Intel Lewisville
HD Audio I/F
PCI Express BUS 100MHz DOCK LAN 82579LM
Option
SPI S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PCIE3 PCIE5 PCIE2 PCIE1 PAGE 32

EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TPM1.2 LPC BUS SATA
33MHz INT.Speaker LAN SWITCH
Card Flash WLAN WWAN/UWB SSX44B SATA Repeater HDA Codec PI3L720 PAGE 32
W25X64ZE MAX4951BE 92HD90B2 PAGE 30
PAGE 37 PAGE 36 PAGE 36 PAGE 36 PAGE 34
PAGE 14
PAGE 28
USB10 USB6 USB4 USB5 64M 4K sector PAGE 30

USH TPM1.2 HeadPhone & RJ45


3 Smart Card TDA8034HN W25Q16BVSSIG MIC Jack 3

PAGE 33 PAGE 33 BCM5882 HDD MDC


PAGE 14 on IO board
PAGE 33,34 16M 4K sector
CPU XDP Port RFID PAGE 28
Fingerprint DAI
PAGE 7 PAGE 33 FP_USB USB7 To Docking side
CONN PAGE 23 RJ11
PCH XDP Port
PCIE4 E-Module on IO board Dig.
PAGE 14
SMSC SIO
BC BUS PAGE 29
MIC
Thermal PWM FAN ECE5028
GUARDIAN III PAGE 41 Trough eDP Cable
PAGE 22
EMC4022
PAGE 22
SMSC KBC
MEC5055
WiFi ON/OFF &
PAGE 42
Power ON/OFF SW
PAGE 31
4 4

DC/DC Interface
PAGE 44
TP CONN KB CONN DELL CONFIDENTIAL/PROPRIETARY
PAGE 43 PAGE 43
LED Compal Electronics, Inc.
PAGE 45 Title
UMA Block Diagram
Size Document Number Rev
1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 2 of 66
A B C D E
5 4 3 2 1

POWER STATES
USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
0 JUSB2 (Right side 1)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB3 (Right side 2)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
2 JESA1 (Right Side ESATA)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
3 JUSB1 (Ext Left Side )
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCH
6 JMINI3(Flash)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO

8 DOCKING
PM TABLE
9 DOCKING
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C
SATA DESTINATION C
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card
+3.3V_ALW_PCH +1.8V_RUN (M-OFF)
power SATA 0 HDD
+3.3V_RTC_LDO +1.5V_RUN
plane 11 Bluetooth
+0.75V_DDR_VTT
SATA 1 ODD/ E3 Module Bay
+VCC_CORE
12 Camera
+1.05V_RUN_VTT
SATA 2 NA
+1.05V_RUN
State 13 LCD Touch
SATA 3 NA

S0 ON ON ON ON ON SATA 4 ESATA 0 BIO


USH
S3 ON ON OFF ON OFF SATA 5 Dock 1 NA

S5 S4/AC ON OFF OFF ON OFF

B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B

need to update Power Status and PM Table Lane 1 MINI CARD-1 WWAN

Lane 2 MINI CARD-2 WLAN

Lane 3 Express card

Lane 4 E3 Module Bay (USB3)

UMA DP/HDMI Port Connetion Lane 5 1/2vMINI CARD-3 PCIE

Port B MB HDMI Conn Lane 6 MMI

Port C Dock DP port 2 Lane 7 10/100/1G LOM

A
Port D Dock DP port 1 Lane 8 None A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6591P
Date: Monday, January 10, 2011 Sheet 3 of 66
5 4 3 2 1
5 4 3 2 1

MODC_EN
HDDC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21
D D

ADAPTER
SI3456BDV SI3456BDV
(Q27) (Q30)

+PWR_SRC 1.05V_VTTPWRGD
BATTERY ISL95870AH +VCC_SA +5V_HDD +5V_MOD
(PU13)

ALWON

+15V_ALW
C SN0608098 C
CHARGER +5V_ALW RUN_ON
(PU2)

SI4164DY
+3.3V_ALW (Q50)

AUX_EN_WOWL

PCH_ALW_ON
+5V_RUN

AUX_ON
SUS_ON

RUN_ON

M_ON
SN1003055RUWR
SN1003055
MAX17411 RT8209BGQW RT9026GFP TPS51311
(PU9) (PU3) (PU5) (PU4) (PU7) (PU16) SI3456 SI3456 S13456 SI3456 NTMS4920 SI3456
B (Q38) (Q49) (Q54) (Q34) (Q55) (Q58) B
1.05V_0.8V_PWROK

CPU_VTT_ON
0.75V_VR_EN

M_ON
DDR_ON

RUN_ON

+3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M

+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M

Pop option
RUN_ON

CPU1.5V_S3_GATE RUN_ON
Pop option

+1.0V_LAN +3.3V_M

AO4728 NTGS4141N SI4164


A (QC3) (Q59) (Q63) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
+1.05V_RUN BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
+1.5V_CPU_VDDQ +1.5V_RUN NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 4 of 66
5 4 3 2 1
5 4 3 2 1

@ 2.2K
SMBUS Address [0x9a]

@ 2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002
C9 MEM_SMBDATA 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
202
PCH
D
2.2K
+3.3V_LAN 200 DIMMB
SMBUS Address [A4] D

C8 LAN_SMBCLK 28

G12 LAN_SMBDATA 31 LOM SMBUS Address [C8]


M16 E14 53
XDP1 SMBUS Address [TBD]
2.2K 51
SML1_SMBDATA

SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]

3A 3A
2.2K +3.3V_ALW SMBUS Address
2.2K
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
129 MSLICE_EC: 0x72 2.2K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
USB: 0x59
AUDIO: 0x34 14
SLICE_BATTERY: 0x17 13 G Sensor
2.2K SMBUS Address [3B]
SLICE_CHARGER: 0x13
C
+3.3V_ALW C

2.2K
B5 LCD_SMBCLK 30
1B WWAN
A4 LCD_SMDATA 32 SMBUS Address [TBD]
1B
2.2K

KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K

+3.3V_ALW
2.2K
A50 M9
1E USH_SMBCLK
B53 L9 USH SMBUS Address [0xa4]
1E USH_SMBDAT
B B
2.2K

+3.3V_SUS
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT

2.2K
+3.3V_ALW
2.2K
B50 10
1G CHARGER_SMBCLK
A47 9 Charger
1G CHARGER_SMBDAT SMBUS Address [0x12]

2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay
A A7 BAY_SMBCLK SMBUS Address [0xd2] A
2D

2.2K
+3.3V_RUN
2.2K
2A B49 DAI_SMBCLK 8 Compal Electronics, Inc.
DAI_SMBDAT 9
A/D,D/A SMBUS Address [0x30] Title
2A B48
converter SMBUS TOPOLOGY
Size Document Number Rev
1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 5 of 66
5 4 3 2 1
5 4 3 2 1

(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. JCPU1I

(2)PEG_ICOMPO use 12mil connect to RC2


JCPU1A T35 F22
PEG_COMP VSS161 VSS234
PEG_ICOMPI J22 T34 VSS162 VSS235 F19
PEG_ICOMPO J21 T33 VSS163 VSS236 E30
DMI_CRX_PTX_N0 B27 H22 T32 E27
16 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS164 VSS237
16 DMI_CRX_PTX_N1 B25 T31 E24
DMI_CRX_PTX_N2 DMI_RX#[1] VSS165 VSS238
16 DMI_CRX_PTX_N2 A25 T30 E21
D DMI_CRX_PTX_N3 DMI_RX#[2] VSS166 VSS239 D
16 DMI_CRX_PTX_N3 B24 K33 T29 E18
DMI_RX#[3] PEG_RX#[0] VSS167 VSS240
M35 T28 E15
DMI_CRX_PTX_P0 PEG_RX#[1] VSS168 VSS241
16 DMI_CRX_PTX_P0 B28 L34 T27 E13
DMI_CRX_PTX_P1 DMI_RX[0] PEG_RX#[2] VSS169 VSS242
16 DMI_CRX_PTX_P1 B26 J35 T26 E10
DMI_RX[1] PEG_RX#[3] VSS170 VSS243

DMI
DMI_CRX_PTX_P2 A24 J32 P9 E9
16 DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] VSS171 VSS244
DMI_CRX_PTX_P3 B23 H34 P8 E8
16 DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] VSS172 VSS245
H31 P6 E7
DMI_CTX_PRX_N0 PEG_RX#[6] VSS173 VSS246
16 DMI_CTX_PRX_N0 G21 G33 P5 E6
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] VSS174 VSS247
16 DMI_CTX_PRX_N1 E22 G30 P3 E5
DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] VSS175 VSS248
16 DMI_CTX_PRX_N2 F21 F35 P2 E4
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] VSS176 VSS249
16 DMI_CTX_PRX_N3 D21 E34 N35 E3
DMI_TX#[3] PEG_RX#[10] VSS177 VSS250
PEG_RX#[11] E32 N34 VSS178 VSS251 E2
16 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 G22 D33 N33 E1
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] VSS179 VSS252
16 DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31 N32 VSS180 VSS253 D35

PCI EXPRESS* - GRAPHICS


16 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 F20 B33 N31 D32
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] VSS181 VSS254
16 DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32 N30 VSS182 VSS255 D29
N29 VSS183 VSS256 D26
PEG_RX[0] J33 N28 VSS184 VSS257 D20
PEG_RX[1] L35 N27 VSS185 VSS258 D17
PEG_RX[2] K34 N26 VSS186 VSS259 C34
16 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 A21 H35 M34 C31
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] VSS187 VSS260
16 FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32 L33 VSS188 VSS261 C28
16 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 E19 G34 L30 C27
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] VSS189 VSS262
F18 G31 L27 C25
16 FDI_CTX_PRX_N3
Intel(R) FDI
FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] VSS190 VSS263
16 FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33 L9 VSS191 VSS264 C23
16 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 C20 F30 L8 C10
FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] VSS192 VSS265
16 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35 L6 VSS193 VSS266 C1
16 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 E17 E33 L5 B22
FDI1_TX#[3] PEG_RX[10] VSS194 VSS267
F32 L4 B19

16 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 FDI0_TX[0]


PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
D34
E31
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
16 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 L1 B13
C FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] VSS198 VSS271 C
16 FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32 K35 VSS199 VSS272 B11
16 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 G18 K32 B9
FDI_CTX_PRX_P4 FDI0_TX[3] VSS200 VSS273
16 FDI_CTX_PRX_P4 B20 FDI1_TX[0] PEG_TX#[0] M29 K29 VSS201 VSS274 B8
16 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 C19 M32 K26 B7
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] VSS202 VSS275
16 FDI_CTX_PRX_P6 D19 FDI1_TX[2] PEG_TX#[2] M31 J34 VSS203 VSS276 B5
16 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 F17 L32 J31 B3
FDI1_TX[3] PEG_TX#[3] VSS204 VSS277
PEG_TX#[4] L29 H33 VSS205 VSS278 B2
FDI_FSYNC0 J18 K31 H30 A35
16 FDI_FSYNC0 FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS206 VSS279
16 FDI_FSYNC1 J17 K28 H27 A32
FDI1_FSYNC PEG_TX#[6] VSS207 VSS280
J30 H24 A29
FDI_INT PEG_TX#[7] VSS208 VSS281
16 FDI_INT H20 J28 H21 A26
FDI_INT PEG_TX#[8] VSS209 VSS282
H29 H18 A23
FDI_LSYNC0 PEG_TX#[9] VSS210 VSS283
16 FDI_LSYNC0 J19 G27 H15 A20
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] VSS211 VSS284
16 FDI_LSYNC1 H17 E29 H13 A3
FDI1_LSYNC PEG_TX#[11] VSS212 VSS285
F27 H10
PEG_TX#[12] VSS213
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
D28 H9
VSS214
F26 H8
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] VSS215
E25 H7
EDP_COMP PEG_TX#[15] VSS216
A18 H6
eDP_COMPIO VSS217
A17 M28 H5
eDP_ICOMPO PEG_TX[0] VSS218
B16 M33 H4
eDP_HPD PEG_TX[1] VSS219
M30 H3
PEG_TX[2] VSS220
L31 H2
PEG_TX[3] VSS221
C15 L28 H1
eDP_AUX PEG_TX[4] VSS222
D15 K30 G35
eDP_AUX# PEG_TX[5] VSS223
eDP

K27 G32
PEG_TX[6] VSS224
J29 G29
PEG_TX[7] VSS225
C17 J27 G26
eDP_TX[0] PEG_TX[8] VSS226
F16 H28 G23
eDP_TX[1] PEG_TX[9] VSS227
C16 G28 G20
eDP_TX[2] PEG_TX[10] VSS228
G15 E28 G17
eDP_TX[3] PEG_TX[11] VSS229
F28 G11
B PEG_TX[12] VSS230 B
C18 D27 F34
eDP_TX#[0] PEG_TX[13] VSS231
E16 E26 F31
eDP_TX#[1] PEG_TX[14] VSS232
D16 D25 F29
eDP_TX#[2] PEG_TX[15] VSS233
F15
eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

PEG Compensation
DP Compensation
+1.05V_RUN_VTT
+1.05V_RUN_VTT
1
1

RC2
RC1 24.9_0402_1%~D
24.9_0402_1%~D
2
2

PEG_COMP
EDP_COMP

eDP_COMPIO and ICOMPO signals should be shorted near PEG_ICOMPI and RCOMPO signals should be shorted and routed
A A
balls and routed with typical impedance <25 mohms with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (1/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6591P
Date: Monday, January 10, 2011 Sheet 6 of 66
5 4 3 2 1
5 4 3 2 1

Follow DG Rev0.71 SM_DRAMPWROK topology +1.5V_CPU_VDDQ +1.05V_RUN_VTT


+3.3V_ALW_PCH
+3.3V_ALW_PCH

1
+1.05V_RUN_VTT +1.05V_RUN_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC1561 2 1 1

1
RC12

CC65

CC66
UC2 200_0402_5%~D @ RC124 @JXDP1
@ JXDP1
1 B 1K_0402_5%~D 1 2

P
41,42 RUNPWROK

2
RUNPWROK_AND 2 2 GND0 GND1
4 1 2 PM_DRAM_PWRGD_CPU XDP_PREQ# 3 4 CFG16 CFG16 9
O RC28 130_0402_5%~D XDP_PRDY# OBSFN_A0 OBSFN_C0 CFG17
+3.3V_ALW_PCH 1 2 2 5 6 CFG17 9

2
A OBSFN_A1 OBSFN_C1

2
RC18 200_0402_5%~D 7 8
74AHC1G09GW_TSSOP5~D RC64 SYS_PWROK_XDP XDP_OBS0 GND2 GND3 CFG0
16 PM_DRAM_PWRGD 9 10 CFG0 9

3
39_0402_5%~D XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
Place near JXDP1 11
OBSDATA_A1 OBSDATA_C1
12 CFG1 9
13 14
D XDP_OBS2 GND4 GND5 CFG2 D
15 16 CFG2 9

1 1
XDP_OBS3 OBSDATA_A2 OBSDATA_C2 CFG3
17 18 CFG3 9
D OBSDATA_A3 OBSDATA_C3
19 20
QC1 CFG10 GND6 GND7 CFG8
11,44 RUN_ON_CPU1.5VS3# 2 9 CFG10 21 22 CFG8 9
G SSM3K7002FU_SC70-3~D CFG11 OBSFN_B0 OBSFN_D0 CFG9
9 CFG11 23 24 CFG9 9
OBSFN_B1 OBSFN_D1
S 25 26

3
XDP_OBS4 GND8 GND9 CFG4
27 28 CFG4 9
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 30 CFG5 9
OBSDATA_B1 OBSDATA_D1
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33
OBSDATA_B2 OBSDATA_D2
34 CFG6 9
XDP_OBS7 35 36 CFG7 CFG7 9
OBSDATA_B3 OBSDATA_D3
37 GND12 GND13 38
H_CPUPWRGD 1 2 H_CPUPWRGD_XDP 39 40 CLK_XDP
RC51 CFD_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_XDP#
14,16 SIO_PWRBTN#_R 2 1K_0402_5%~D 41 42
RC6 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
43 VCC_OBS_AB VCC_OBS_CD 44
CFG0 1 2 XDP_HOOK2 45 46 XDP_RST#_R
+1.05V_RUN_VTT RC71 SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
16,41 SYS_PWROK 2 1K_0402_5%~D 47 HOOK3 DBR#/HOOK7 48
@ RC9 0_0402_5%~D 49 50
DDR_XDP_WAN_SMBDAT_R1 GND14 GND15 XDP_TDO
12,13,14,15,28,36 DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# RC1251 2 0_0402_5%~D DDR_XDP_WAN_SMBCLK_R1 53 54 XDP_TRST#
12,13,14,15,28,36 DDR_XDP_WAN_SMBCLK SCL TRST# XDP_TDI
@ RC126 56_0402_5%~D RC127 0_0402_5%~D 55 56
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 TCK0 TMS 58
@ RC128 49.9_0402_1%~D 59 60
H_PROCHOT# GND16 GND17
1 2
RC44 62_0402_5%~D JCPU1B Keep R1132, R1133, R1136-R119 SAMTE_BSH-030-01-L-D-A
for slew rate control.
A28 CPU_DMI 1 2
BCLK CLK_CPU_DMI 15

MISC

CLOCKS
C26 A27 CPU_DMI# RC13 1 2 0_0402_5%~D
PROC_SELECT# BCLK# CLK_CPU_DMI# 15
RC15 0_0402_5%~D XDP_RST#_R 2 1 PLTRST_XDP# 17
RC8 1K_0402_5%~D
C C
41 CPU_DETECT# AN34 SKTOCC#
A16 CPU_DPLL 1 2
DPLL_REF_CLK CLK_CPU_DPLL 15
A15 CPU_DPLL# RC16 1 2 0_0402_5%~D
DPLL_REF_CLK# CLK_CPU_DPLL# 15
RC17 0_0402_5%~D
1 2 CLK_XDP 1 2
H_CATERR# CLK_CPU_ITP 15
AL33 @ RC48
@RC48 0_0402_5%~D RH107 0_0402_5%~D
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# 15
RH106 0_0402_5%~D
THERMAL

D
AN33 R8 DDR3_DRAMRST#_CPU 3 1
18 H_PECI PECI SM_DRAMRST# DDR3_DRAMRST# 12
DDR3
MISC
QC2
Max 500mils BSS138W-7-F_SOT323-3~D

G
9 CLK_XDP_ITP 1 2

2
1
42,52,54 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
A5 9 CLK_XDP_ITP# 1 2
Close to JCBU1 SM_RCOMP[1] SM_RCOMP2 4.99K_0402_1%~D DDR_HVREF_RST @ RH108 0_0402_5%~D
A4
SM_RCOMP[2]

22 H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1

2
RC129 0_0402_5%~D THERMTRIP#
SM_RCOMP1/0 --> 20mil CC177
place RC129 near CPU 0.047U_0402_16V4Z~D
2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
AP27
PREQ#
AR26 XDP_TCLK 1 2
TCK 15 DDR_HVREF_RST_PCH
PWR MANAGEMENT

AR27 XDP_TMS RC46 0_0402_5%~D


JTAG & BPM

H_PM_SYNC TMS XDP_TRST#


16 H_PM_SYNC AM34
PM_SYNC TRST#
AP30 42 DDR_HVREF_RST_GATE 1 2 PU/PD for JTAG signals
@RC47
@ RC47 0_0402_5%~D
AR28 XDP_TDI_R +3.3V_RUN
TDI XDP_TDO_R
AP26
TDO
18 H_CPUPWRGD 1 2 VCCPWRGOOD_0_R AP33
B RC25 0_0402_5%~D UNCOREPWRGOOD XDP_DBRESET# B
2 1
RC19 1K_0402_5%~D
AL35 XDP_DBRESET#_R 2 1 XDP_DBRESET# XDP_DBRESET# 14,16
PM_DRAM_PWRGD_CPU DBR# RC26 0_0402_5%~D +1.05V_RUN_VTT
V8
SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0 XDP_TMS RC27 2 1 51_0402_1%~D
BPM#[0] XDP_OBS1_R RC30 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
AR29 1 2 1 2
BPM#[1] XDP_OBS2_R RC31 0_0402_5%~D XDP_OBS2 RC23 0_0402_5%~D XDP_TDI_R RC29 2
BPM#[2]
AR30 1 2 1 51_0402_1%~D
PCH_PLTRST#_R AR33 AT30 XDP_OBS3_R RC33 1 2 0_0402_5%~D XDP_OBS3
RESET# BPM#[3] XDP_OBS4_R RC34 0_0402_5%~D XDP_OBS4 XDP_PREQ# @ RC32 2
BPM#[4]
AP32 1 2 1 51_0402_1%~D
AR31 XDP_OBS5_R RC36 1 2 0_0402_5%~D XDP_OBS5 XDP_TDO_R 1 2 XDP_TDO
BPM#[5] XDP_OBS6_R RC37 0_0402_5%~D XDP_OBS6 RC24 0_0402_5%~D XDP_TDO RC35 2
AT31 1 2 1 51_0402_1%~D
BPM#[6] XDP_OBS7_R RC38 0_0402_5%~D XDP_OBS7
AR32 1 2
BPM#[7] RC39 0_0402_5%~D
For ESD concern, please put near CPU XDP_TCLK RC40 2 1
51_0402_1%~D
Sandy Bridge_rPGA_Rev1p0 XDP_TRST# RC41 2 1
51_0402_1%~D

Buffered reset to CPU +3.3V_RUN VCCPWRGOOD_0_R


+1.05V_RUN_VTT SM_RCOMP2
SM_RCOMP1
1
0.1U_0402_16V4Z~D

SM_RCOMP0
1 RC130
1
75_0402_1%~D

RC4

10K_0402_5%~D

1
CC140

140_0402_1%~D

25.5_0402_1%~D

200_0402_1%~D
RC42

RC43

RC45
2

2
UC1
2

1 5

2
A NC VCC A
14,17 PCH_PLTRST# 2 A
3 4 PCH_PLTRST#_BUF 1 2 PCH_PLTRST#_R
GND Y RC10 43_0402_5%~D Avoid stub in the PWRGD path
SN74LVC1G07DCKR_SC70-5~D while placing resistors RC25 & RC130
DELL CONFIDENTIAL/PROPRIETARY
1

Open drain buffer @ RC11


0_0402_5%~D
Compal Electronics, Inc.
2

Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (2/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6591P
Date: Monday, January 10, 2011 Sheet 7 of 66
5 4 3 2 1
5 4 3 2 1

JCPU1D
JCPU1C

AE2 M_CLK_DDR2
D M_CLK_DDR0 13 DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR#2 M_CLK_DDR2 13 D
12 DDR_A_D[0..63] AB6 M_CLK_DDR0 12 AD2 M_CLK_DDR#2 13
SA_CLK[0] M_CLK_DDR#0 DDR_B_D0 SB_CLK#[0] DDR_CKE2_DIMMB
AA6 M_CLK_DDR#0 12 C9 R9 DDR_CKE2_DIMMB 13
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA DDR_B_D1 SB_DQ[0] SB_CKE[0]
C5 V9 DDR_CKE0_DIMMA 12 A7
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_B_D2 SB_DQ[1]
D5 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 C8
DDR_A_D3 SA_DQ[2] DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D2 A9 AE1 M_CLK_DDR3 13
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D5 SB_DQ[4] SB_CLK[1] M_CLK_DDR#3
D6 AA5 M_CLK_DDR1 12 A8 AD1 M_CLK_DDR#3 13
DDR_A_D5 SA_DQ[4] SA_CLK[1] M_CLK_DDR#1 DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
C6 AB5 M_CLK_DDR#1 12 D9 R10 DDR_CKE3_DIMMB 13
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D7 SB_DQ[6] SB_CKE[1]
C2 V10 DDR_CKE1_DIMMA 12 D8
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D8 SB_DQ[7]
C3 G4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8]
F10 F4
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F8 SA_DQ[9] F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D10 G10 AB4 DDR_B_D11 G1 AA2
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G9 SA_DQ[11] RSVD_TP[2] AA4 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D12 F9 W9 DDR_B_D13 F5
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D14 SB_DQ[13]
F7 SA_DQ[13] F2 SB_DQ[14]
DDR_A_D14 G8 DDR_B_D15 G2
DDR_A_D15 SA_DQ[14] DDR_B_D16 SB_DQ[15]
G7 SA_DQ[15] J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D16 K4 AB3 DDR_B_D17 J8 AB1
DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K5 SA_DQ[17] RSVD_TP[5] AA3 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D18 K1 W10 DDR_B_D19 K9
DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D20 SB_DQ[19]
J1 SA_DQ[19] J9 SB_DQ[20]
DDR_A_D20 J5 DDR_B_D21 J10
DDR_A_D21 SA_DQ[20] DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
J4 SA_DQ[21] K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# 13
DDR_A_D22 J2 AK3 DDR_CS0_DIMMA# DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# 12 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# 13
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D24 M5 AD6
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# 12 DDR_B_D25 SB_DQ[24] RSVD_TP[17]
M8 SA_DQ[24] RSVD_TP[7] AG1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D25 N10 AH1 DDR_B_D26 N2
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D27 SB_DQ[26]
N8 SA_DQ[26] N1 SB_DQ[27]
DDR_A_D27 N7 DDR_B_D28 M4
DDR_A_D28 SA_DQ[27] DDR_B_D29 SB_DQ[28] M_ODT2
M10 SA_DQ[28] N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 13

DDR SYSTEM MEMORY B


DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
C DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 M_ODT0 12 DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 13 C
N9 AG3 M1 AD5
DDR SYSTEM MEMORY A
DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 12 DDR_B_D32 SB_DQ[31] RSVD_TP[19]
M7 SA_DQ[31] RSVD_TP[9] AG2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D32 AG6 AH2 DDR_B_D33 AM6
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D34 SB_DQ[33]
AG5 SA_DQ[33] AR3 SB_DQ[34]
DDR_A_D34 AK6 DDR_B_D35 AP3
DDR_A_D35 SA_DQ[34] DDR_B_D36 SB_DQ[35]
AK5 SA_DQ[35] AN3 SB_DQ[36] DDR_B_DQS#[0..7] 13
DDR_A_D36 AH5 DDR_B_D37 AN2 D7 DDR_B_DQS#0
SA_DQ[36] DDR_A_DQS#[0..7] 12 SB_DQ[37] SB_DQS#[0]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 G6 AP2 K6
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ6 J3 AP5 N3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AJ8 M6 AN9 AN5
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AK8 AL6 AT5 AP9
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AJ9 AM8 AT6 AK12
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AK9 AR12 AP6 AP15
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 AM15 AN8
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D46 SB_DQ[45]
AH9 AR6
DDR_A_D46 SA_DQ[45] DDR_B_D47 SB_DQ[46]
AL9 AR5
DDR_A_D47 SA_DQ[46] DDR_B_D48 SB_DQ[47]
AL8 AR9 DDR_B_DQS[0..7] 13
DDR_A_D48 SA_DQ[47] DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AP11 DDR_A_DQS[0..7] 12 AJ11 C7
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AN11 D4 AT8 G3
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL12 F6 AT9 J6
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM12 K3 AH11 M3
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AM11 N6 AR8 AN6
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AL11 AL5 AJ12 AP8
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AP12 AM9 AH12 AK11
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AN12 AR11 AT11 AP14
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 AM14 AN14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D58 SB_DQ[57]
AH14 AR14
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AL15 AT14 DDR_B_MA[0..15] 13
DDR_A_D59 SA_DQ[58] DDR_B_D60 SB_DQ[59]
AK15 DDR_A_MA[0..15] 12 AT12
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AL14 AN15 AA8
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 AD10 AR15 T7
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AJ15 W1 AT15 R7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 SB_DQ[63] SB_MA[2] DDR_B_MA3
AH15 W2 T6
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
W7 T2
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
V3 T4
SA_MA[4] DDR_A_MA5 SB_MA[5] DDR_B_MA6
V2 T3
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
W3 13 DDR_B_BS0 AA9 R2
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
12 DDR_A_BS0 AE10 W6 13 DDR_B_BS1 AA7 T5
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
12 DDR_A_BS1 AF10 V1 13 DDR_B_BS2 R6 R3
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
12 DDR_A_BS2 V6 W5 AB7
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
AD8 R1
SA_MA[10] DDR_A_MA11 SB_MA[11] DDR_B_MA12
V4 T1
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
W4 13 DDR_B_CAS# AA10 AB10
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
12 DDR_A_CAS# AE8 AF8 13 DDR_B_RAS# AB8 R5
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
12 DDR_A_RAS# AD9 V5 13 DDR_B_WE# AB9 R4
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[15]
12 DDR_A_WE# AF9 V7
SA_WE# SA_MA[15]

Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (3/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6591P
Date: Monday, January 10, 2011 Sheet 8 of 66
5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor

CFG2

1
@RC51
@ RC51
1K_0402_5%~D

2
D JCPU1E D

L7 @ T1 PAD~D
RSVD28 @ T2 PAD~D
AG7
CFG0 RSVD29 @ T3 PAD~D
7 CFG0 AK28 AE7
CFG1 CFG[0] RSVD30 @ T4 PAD~D
7 CFG1 AK29
CFG[1] RSVD31
AK2 PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 AL26 W8 @ T5 PAD~D
7 CFG2 CFG3 CFG[2] RSVD32
7 CFG3 AL27
CFG4 CFG[3]
7 CFG4 AK26
CFG[4] 1:(Default) Normal Operation; Lane #
CFG5 AL29 AT26 @ T6 PAD~D CFG2
7 CFG5 CFG6 AL30
CFG[5] RSVD33
AM33 @ T7 PAD~D
definition matches socket pin map definition
7 CFG6 CFG7 CFG[6] RSVD34
7 CFG7 AM31 CFG[7] RSVD35 AJ27 @ T8 PAD~D 0:Lane Reversed
CFG8 AM32
7 CFG8 CFG9 CFG[8]
7 CFG9 AM30 CFG[9]
CFG10 AM28
7 CFG10 CFG11 CFG[10] CFG4
7 CFG11 AM26 CFG[11]
@ T9 PAD~D CFG12 AN28 CFG[12]

1
@ T10 PAD~D CFG13 AN31 T8 @ T11 PAD~D
@ T12 PAD~D CFG14 CFG[13] RSVD37 @ T13 PAD~D @ RC52
AN26 CFG[14] RSVD38 J16
@ T14 PAD~D CFG15 AM27 H16 @ T15 PAD~D 1K_0402_5%~D
+VCC_GFXCORE CFG16 CFG[15] RSVD39 @ T16 PAD~D
7 CFG16 AK31 CFG[16] RSVD40 G16
CFG17 AN29
7 CFG17

2
RSVD1 CFG[17]
1 2 follow DG0.9 change to 1Kohm 5%
@RC122
@ RC122 49.9_0402_1%~D

AR35 @ T17 PAD~D


+VCC_CORE RSVD1 RSVD41 @ T18 PAD~D
AJ31 VAXG_VAL_SENSE RSVD42 AT34
RSVD2 AH31 AT33 @ T19 PAD~D
RSVD3 RSVD3 VSSAXG_VAL_SENSE RSVD43 @ T20 PAD~D
1 2 AJ33 VCC_VAL_SENSE RSVD44 AP35 Display Port Presence Strap
@RC120
@ RC120 49.9_0402_1%~D RSVD4 AH33 AR34 @ T21 PAD~D
VSS_VAL_SENSE RSVD45
C C
1 : Disabled; No Physical Display Port
1 2 RSVD2 @ T22 PAD~D AJ26 CFG4
RSVD5 attached to Embedded Display Port

RESERVED
@RC123
@ RC123 49.9_0402_1%~D
1 2 RSVD4
@RC121
@ RC121 49.9_0402_1%~D
RSVD46 B34 @ T23 PAD~D 0 : Enabled; An external Display Port device is
1 2 +DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU B4 A33 @ T24 PAD~D
@RC96
@ RC96 1K_0402_5%~D
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU D1 RSVD6 RSVD47
A34 @ T25 PAD~D
connected to the Embedded Display Port
+DIMM0_1_CA_CPU RSVD7 RSVD48
1 2 +DIMM0_1_CA_CPU B35 @ T26 PAD~D
@RC97
@ RC97 1K_0402_5%~D RSVD49 @ T27 PAD~D
C35
RSVD50
@ T28 PAD~D F25 CFG6
@ T29 PAD~D RSVD8
F24
@ T30 PAD~D RSVD9 CFG5
F23
@ T31 PAD~D RSVD10 @ T32 PAD~D
D24 AJ32
RSVD11 RSVD51

1
@ T33 PAD~D G25 AK32 @ T34 PAD~D
@ T35 PAD~D RSVD12 RSVD52 @ RC54 @ RC53
G24
@ T36 PAD~D RSVD13 1K_0402_5%~D 1K_0402_5%~D
E23
@ T37 PAD~D RSVD14
D23
@ T38 PAD~D RSVD15 @ T39 PAD~D
C30 AH27

2
@ T40 PAD~D RSVD16 VCC_DIE_SENSE
A31
@ T41 PAD~D RSVD17
B30
@ T42 PAD~D RSVD18
B29
@ T43 PAD~D RSVD19
D30 AN35 CLK_XDP_ITP 7
@ T44 PAD~D RSVD20 RSVD54
B31 AM35 CLK_XDP_ITP# 7
@ T45 PAD~D RSVD21 RSVD55
A30
@ T46 PAD~D RSVD22
C29
RSVD23
PCIE Port Bifurcation Straps
@ T47 PAD~D J20
@ T48 PAD~D RSVD24 @ T49 PAD~D
B18 AT2
RSVD25 RSVD56
@ T155 PAD~D A19
VCCIO_SEL RSVD57
AT1 @ T50 PAD~D 11: (Default) x16 - Device 1 functions 1 and 2 disabled
AR1 @ T51 PAD~D
B RSVD58 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
@ T52 PAD~D J15
RSVD27 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
KEY 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Sandy Bridge_rPGA_Rev1p0 CFG7

1
@ RC56
1K_0402_5%~D

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately


CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (4/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 9 of 66
5 4 3 2 1
5 4 3 2 1

JCPU1F POWER
+1.05V_RUN_VTT
+VCC_CORE +VCC_CORE

53AAG35 8.5A
VCC1
AG34 VCC2 VCCIO1 AH13

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
1 1 1 1 1 AG33 AH10
VCC3 VCCIO2
AG32 AG10
CC67 CC75 CC76 CC77 VCC4 VCCIO3
CC68 AG31 AC10 1 1 1 1 1 1 1 1 1 1 1
D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC5 VCCIO4 D
AG30 Y10
2 2 2 2 2 VCC6 VCCIO5

CC78

CC69

CC79

CC80

CC81

CC82

CC83

CC84

CC85

CC70

CC86
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7 2 2 2 2 2 2 2 2 2 2 2
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
1 1 1 1 1 AF33 J11
VCC13 VCCIO12
AF32 H14
CC87 CC71 CC72 CC88 CC73 VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D AF30 H11
2 2 2 2 2 VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14 1 1 1
AF28 VCC18 VCCIO17 G13 1 1 1 1 1

PEG AND DDR

@ CC90

@ CC91

@ CC92

@ CC93

CC107

CC108

CC109
AF27 G12 + + + @
VCC19 VCCIO18

CC89
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 F12 2 2 2 2 2 2 2 2
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
+VCC_CORE AC34 C14
VCC32 VCCIO30
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
1 1 1 1 1 AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
C CC110 CC111 CC112 CC113 CC114 C
AC28 VCC38 VCCIO36 A14
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D AC27 A13
2 2 2 2 2 VCC39 VCCIO37
AC26 VCC40 VCCIO38 A12
+1.05V_RUN_VTT
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23

1
AA32 VCC44
AA31 Note: Place the PU resistors close to CPU RC60
VCC45 75_0402_1%~D
1 1 1 1 1 AA30
VCC46 R1555 close to CPU 300 - 1500mils
AA29
CC115 CC116 CC117 CC118 VCC47
CC119 AA28

2
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC48
AA27
2 2 2 2 2 VCC49 H_CPU_SVIDALRT#
AA26 1 2 VIDALERT_N 52
VCC50

CORE SUPPLY
Y35 RC61 43_0402_5%~D
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55 +1.05V_RUN_VTT
1 1 1 1 1 Y30
VCC56
Y29
CC120 CC121 CC122 CC123 CC124 VCC57 CAD Note: Place the PU
Y28
VCC58

1
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D Y27 resistors close to CPU
2 2 2 2 2 VCC59 RC63
Y26 R1558 close to CPU 300 - 1500mils
VCC60 130_0402_1%~D
V35
VCC61

SVID
V34 AJ29 H_CPU_SVIDALRT#
VCC62 VIDALERT# VIDSCLK
V33 AJ30 VIDSCLK 52

2
VCC63 VIDSCLK VIDSOUT Iccmax current changed for PDDG Rev0.7
V32 AJ28 VIDSOUT 52
VCC64 VIDSOUT
V31
VCC65
1 V30
V29
VCC66 CPU Power Rail Table
VCC67
CC125 V28 SVID note: VIDALERT# trace S0 Iccmax
VCC68
22U_0805_6.3VAM~D V27
VCC69 routing need to be routed between Voltage Rail Voltage Current (A)
B 2 V26 B
VCC70 VIDSCLK and VIDSOUT signals
U35
VCC71
U34
VCC72
VCC 0.65-1.3 53
U33
VCC73
U32
VCC74
U31
VCC75
VCCIO 1.05 8.5
U30
VCC76
U29
+VCC_CORE VCC77
U28
VCC78
VAXG 0.0-1.1 26
U27
VCC79
U26
VCC80 +VCC_CORE
R35
VCC81
VCCPLL 1.8 3
R34
VCC82
1 1 1 1 R33
VCC83

1
R32
VCC84
VDDQ 1.5 5
+ @CC129 + @CC130 + CC131 + CC132 RC66
470U_D2_2V-M~D 470U_D2_2V-M~D 470U_D2_2V-M~D 470U_D2_2V-M~D
R31
VCC85 Place RC66, RC70near CPU
R30 100_0402_1%~D
VCC86
R29
VCC87
VCCSA 0.65-0.9 6
2 3 2 3 2 3 2 3
SENSE LINES

R28

2
VCC88 VCCSENSE_R
R27 AJ35 1 2 VCCSENSE 52
VCC89 VCC_SENSE VSSSENSE_R
R26
VCC90 VSS_SENSE
AJ34 RC67 1 2 0_0402_5%~D VSSSENSE 52 +1.5V_MEM 1.5 12-16 *
P35 RC68 0_0402_5%~D
VCC91
P34
VCC92

1
P33
VCC93 VTT_SENSE_R RC70
P32 B10 1 2 VTT_SENSE 51
VCC94 VCCIO_SENSE VSSIO_SENSE_R RC1321
P31
VCC95 VSSIO_SENSE
A10 2 0_0402_5%~D VTT_GND 51 100_0402_1%~D * Description
1 1 P30 RC133 0_0402_5%~D
VCC96
P29 5A to Mem controller(+1.5V_CPU_VDDQ)

2
+ CC133 + CC134 VCC97
P28 5-6A to 2 DIMMs/channel
470U_D2_2V-M~D 470U_D2_2V-M~D VCC98
P27
VCC99 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
P26
2 3 2 3 VCC100
A A

DELL CONFIDENTIAL/PROPRIETARY
Sandy Bridge_rPGA_Rev1p0
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Sandy Bridge (5/6)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6591P
Date: Monday, January 10, 2011 Sheet 10 of 66
5 4 3 2 1
5 4 3 2 1

+1.5V_CPU_VDDQ Source
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +15V_ALW AO4728L_SO8~D
8 1
7 2

1
10U_0805_6.3V6M~D

20K_0402_5%~D
@ RC73
6 3 1

CC135
RC72 5

1
100K_0402_5%~D JCPU1H
RC74

4
100K_0402_5%~D 2 AT35 AJ22

2
VSS1 VSS81
AT32 AJ19
D RUN_ON_CPU1.5VS3 VSS2 VSS82 D
AT29 AJ16

2
VSS3 VSS83

3
AT27 AJ13
VSS4 VSS84
AT25 AJ10
QC4B VSS5 VSS85
1 AT22 AJ7
RUN_ON_CPU1.5VS3# DMN66D0LDW-7_SOT363-6~D VSS6 VSS86
5 AT19 AJ4
CC136 VSS7 VSS87
AT16 AJ3
4700P_0402_25V7K~D +V_DDR_REF QC5 +V_SM_VREF_CNT VSS8 VSS88
AT13 AJ2

4
2 NTR4503NT1G_SOT23-3~D VSS9 VSS89
AT10 AJ1
VSS10 VSS90

6
AT7 AH35
VSS11 VSS91
1 3 AT4 AH34
QC4A VSS12 VSS92
AT3 AH32
DMN66D0LDW-7_SOT363-6~D VSS13 VSS93
37,41,44,49 RUN_ON 1 2 2 AR25 VSS14 VSS94 AH30

1
@ RC77 0_0402_5%~D AR22 AH29
RC78 VSS15 VSS95
AR19 AH28

1
2 100K_0402_5%~D VSS16 VSS96
42 CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# 7,44 AR16 VSS17 VSS97 AH26
RC79 0_0402_5%~D AR13 AH25
VSS18 VSS98
1 2 AR10 AH22

2
@ RC134 0_0402_5%~D VSS19 VSS99
AR7 VSS20 VSS100 AH19
AR4 VSS21 VSS101 AH16
AR2 VSS22 VSS102 AH7
RUN_ON_CPU1.5VS3 AP34 AH4
+VCC_GFXCORE

JCPU1G
POWER AP31
AP28
AP25
VSS23
VSS24
VSS25
VSS103
VSS104
VSS105
AG9
AG8
AG4
VSS26 VSS106
AP22 VSS27 VSS107 AF6
26A AP19 VSS28 VSS108 AF5

SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE 52 AP16 VSS29 VSS109 AF3
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 52 AP13 VSS30 VSS110 AF2
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 1 1 1 1 AT21 VAXG3 AP10 VSS31 VSS111 AE35


CC137

CC138

CC144

CC145

CC146

CC147

CC139

CC148

AT20 VAXG4 AP7 VSS32 VSS112 AE34


AT18 VAXG5 AP4 VSS33 VSS113 AE33
AT17 VAXG6 AP1 VSS34 VSS114 AE32
C 2 2 2 2 2 2 2 2 AR24 AN30 AE31 C
VAXG7 CC1782 VSS35 VSS115
AR23 VAXG8 1 0.1U_0402_10V7K~D AN27 VSS36 VSS116 AE30
AR21 AN25 AE29
AR20
VAXG9
VAXG10
+V_SM_VREF_CNT AN22
VSS37
VSS38 VSS VSS117
VSS118 AE28

VREF
AR18 CC1792 1 0.1U_0402_10V7K~D AN19 AE27
VAXG11 VSS39 VSS119
AR17 VAXG12 AN16 VSS40 VSS120 AE26
AP24 VAXG13 SM_VREF AL1 AN13 VSS41 VSS121 AE9
AP23 CC1492 1 0.1U_0402_10V7K~D AN10 AD7
VAXG14 VSS42 VSS122
AP21 AN7 AC9
VAXG15 VSS43 VSS123
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 AP20
VAXG16
+V_SM_VREF should AN4
VSS44 VSS124
AC8
CC151

CC141

CC152

CC153

AP18 have 10 mil trace width CC1502 1 0.1U_0402_10V7K~D AM29 AC6


VAXG17 VSS45 VSS125
AP17 AM25 AC5
VAXG18 VSS46 VSS126
AN24 AM22 AC3
2 2 2 2 VAXG19 +1.5V_CPU_VDDQ VSS47 VSS127
AN23 AM19 AC2
VAXG20 @ PJP1 VSS48 VSS128
AN21 AM16 AB35
VAXG21 VSS49 VSS129
AN20 1 2 AM13 AB34
VAXG22 DDR3 -1.5V RAILS VSS50 VSS130
AN18 AM10 AB33
VAXG23 PAD-OPEN 4x4m VSS51 VSS131
AN17
VAXG24 5A AM7
VSS52 VSS132
AB32
GRAPHICS

AM24 AF7 +1.5V_MEM AM4 AB31


VAXG25 VDDQ1 @ PJP2 VSS53 VSS133
AM23 AF4 AM3 AB30
VAXG26 VDDQ2 VSS54 VSS134
AM21 AF1 1 2 AM2 AB29
VAXG27 VDDQ3 VSS55 VSS135

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2_2VM_R6M~D
AM20 AC7 1 1 1 1 1 1 1 AM1 AB28
VAXG28 VDDQ4 PAD-OPEN 4x4m VSS56 VSS136
AM18 AC4 AL34 AB27
VAXG29 VDDQ5 VSS57 VSS137

CC161

CC162

CC163

CC164

CC165

CC166

CC167
AM17 AC1 + AL31 AB26
VAXG30 VDDQ6 VSS58 VSS138
AL24 Y7 AL28 Y9
VAXG31 VDDQ7 2 2 2 2 2 2 VSS59 VSS139
AL23 Y4 AL25 Y8
VAXG32 VDDQ8 2 VSS60 VSS140
AL21 Y1 AL22 Y6
VAXG33 VDDQ9 VSS61 VSS141
AL20 U7 AL19 Y5
VAXG34 VDDQ10 VSS62 VSS142
AL18 U4 AL16 Y3
VAXG35 VDDQ11 VSS63 VSS143
AL17 U1 AL13 Y2
VAXG36 VDDQ12 VSS64 VSS144
AK24 P7 AL10 W35
VAXG37 VDDQ13 VSS65 VSS145
AK23 P4 AL7 W34
B VAXG38 VDDQ14 VSS66 VSS146 B
AK21 P1 AL4 W33
VAXG39 VDDQ15 VSS67 VSS147
AK20 AL2 W32
VAXG40 VSS68 VSS148
AK18 AK33 W31
VAXG41 VSS69 VSS149
AK17 AK30 W30
VAXG42 VSS70 VSS150
AJ24 AK27 W29
VAXG43 VSS71 VSS151
AJ23 AK25 W28
VAXG44 VSS72 VSS152
AJ21 AK22 W27
VAXG45 VSS73 VSS153
AJ20 AK19 W26
VAXG46 VSS74 VSS154
AJ18 AK16 U9
VAXG47 VSS75 VSS155
AJ17 AK13 U8
VAXG48 VSS76 VSS156
AH24
6A AK10 U6
SA RAIL

VAXG49 VSS77 VSS157


AH23 AK7 U5
VAXG50 VSS78 VSS158
AH21 M27 +VCC_SA AK4 U3
VAXG51 VCCSA1 VSS79 VSS159
10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D
AH20 M26 AJ25 U2
VAXG52 VCCSA2 VSS80 VSS160
AH18 L26
VAXG53 VCCSA3
AH17 J26 1 1 1 1 1
VAXG54 VCCSA4

@ CC171
J25
VCCSA5
CC168

CC169

CC170
J24 + CC172
VCCSA6 330U_D2_2VM_R6M~D Sandy Bridge_rPGA_Rev1p0
H26
VCCSA7 2 2 2 2
H25
VCCSA8 2
1.8V RAIL

3A 1
RC137
2
0_0402_5%~D
+GND_VCC_SA 55

+1.8V_RUN B6 H23 +VCCSA_SENSE 55


VCCPLL1 VCCSA_SENSE
MISC

A6
VCCPLL2
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

330U_D2_2.5VM_R6M~D

1 1 1 1 A2
VCCPLL3
CC173

CC174

CC175

CC176

+ C22 H_FC_C22
FC_C22
C24 1 2 VCCSA_VID_1 55
2 2 2 VCCSA_VID1
10K_0402_5%~D

RC138 0_0402_5%~D
1

A 2 A
RC83

Sandy Bridge_rPGA_Rev1p0

DELL CONFIDENTIAL/PROPRIETARY
2

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (6/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 11 of 66
5 4 3 2 1
5 4 3 2 1

1
+V_DDR_REF 2 +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel
Note: RD1 0_0402_5%~D JDIMM1
1 2 1 2
Check voltage tolerance of +DIMM0_1_VREF_CPU VREF_DQ VSS
JDIMMA H=5.2

2.2U_0603_6.3V6K~D
@ RD7 0_0402_5%~D 3 4 DDR_A_D4
VSS DQ4
VREF_DQ at the DIMM socket DDR_A_D0 5 DQ0 DQ5 6 DDR_A_D5

0.1U_0402_16V4Z~D
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
1 1 9 VSS DQS0# 10
11 12 DDR_A_DQS0
DM0 DQS0

CD1

CD2
13 VSS VSS 14
DDR_A_D2 15 16 DDR_A_D6 +1.5V_MEM
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
8 DDR_A_DQS#[0..7]
All VREF traces should 19 VSS VSS 20
have 10 mil trace width DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13
8 DDR_A_D[0..63] DQ9 DQ13
25 26 RD27
D DDR_A_DQS#1 VSS VSS 1K_0402_1%~D D
8 DDR_A_DQS[0..7] 27 28
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30
DQS1 RESET#
8 DDR_A_MA[0..15] Populate RD1 for Intel DDR3 31 32

2
DDR_A_D10 VSS VSS DDR_A_D14
VREFDQ multiple methods M1 33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15 DDR3_DRAMRST#_R 1
35 36 13 DDR3_DRAMRST#_R 2 DDR3_DRAMRST# 7
DQ11 DQ15 RD28 1K_0402_1%~D
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS
Layout Note: 45
DQS2# DM2
46
DDR_A_DQS2 47 48
Place near JDIMMA 49
DQS2 VSS
50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
+1.5V_MEM 61 62 DDR_A_DQS#3
VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DQ26 DQ30
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
1 1 1 1 71 VSS VSS 72
CD3

CD4

CD5

CD6

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
2 2 2 2 8 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 8
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
8 DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
C C
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
+1.5V_MEM 93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

M_CLK_DDR0 101 102 M_CLK_DDR1


8 M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 8
8 M_CLK_DDR#0 103 104 M_CLK_DDR#1 8
CK0# CK1#
330U_SX_2VY~D

1 105 106
VDD VDD
@ CD13

1 1 1 1 1 1 1 DDR_A_MA10 107 108 DDR_A_BS1


A10/AP BA1 DDR_A_BS1 8
CD7

CD8

CD9

CD10

CD11

CD12

CD14

+ DDR_A_BS0 109 110 DDR_A_RAS#


8 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 8
111 112
DDR_A_WE# VDD VDD DDR_CS0_DIMMA#
8 DDR_A_WE# 113 114 DDR_CS0_DIMMA# 8
2 2 2 2 2 2 2 2 DDR_A_CAS# WE# S0# M_ODT0
8 DDR_A_CAS# 115 116 M_ODT0 8
CAS# ODT0
117 118
DDR_A_MA13 VDD VDD M_ODT1 +DIMM0_1_VREF_CA
119 120 M_ODT1 8
DDR_CS1_DIMMA# A13 ODT1
8 DDR_CS1_DIMMA# 121 122
S1# NC
123 124
VDD VDD
125 126 1 2 +V_DDR_REF
TEST VREF_CA RD29 0_0402_5%~D
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132 1 2 +DIMM0_1_CA_CPU
DQ33 DQ37 @ RD31 0_0402_5%~D
133 134 1 1
VSS VSS

CD15

CD16
Layout Note: DDR_A_DQS#4 135 136
DDR_A_DQS4 DQS4# DM4
137 138
Place near JDIMMA.203,204 139
DQS4 VSS
140 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_A_D44
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
149 150
B DQ41 VSS DDR_A_DQS#5 B
151 152
VSS DQS5# DDR_A_DQS5
153 154
+0.75V_DDR_VTT DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS VSS DDR_A_D52
163 164
DQ48 DQ52
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D49 165 166 DDR_A_D53


DQ49 DQ53
1 1 1 1 167 168
DDR_A_DQS#6 VSS VSS
169 170
DQS6# DM6
CD17

CD18

CD19

CD20

DDR_A_DQS6 171 172


DQS6 VSS DDR_A_D54
173 174
2 2 2 2 DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
179 180
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
RD21 VSS VSS
2 10K_0402_5%~D 197
SA0 EVENT#
198
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT 7,13,14,15,28,36
VDDSPD SDA
1 2 201 202 DDR_XDP_WAN_SMBCLK 7,13,14,15,28,36
RD3 10K_0402_5%~D SA1 SCL
1 1 203 204 +0.75V_DDR_VTT
VTT VTT
0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT
CD21

CD22

205 206
2 2 GND1 GND2
FOX_AS0A626-U4SN-7F
A CONN@ A

change footprint.

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 12 of 66
5 4 3 2 1
5 4 3 2 1

2-3A to 1 DIMMs/channel
All VREF traces should +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM
have 10 mil trace width JDIMM2
1 VREF_DQ VSS 2
3 4 DDR_B_D4
VSS DQ4
JDIMMB H=9.2

2.2U_0603_6.3V6K~D
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

0.1U_0402_16V4Z~D
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
8 DDR_B_DQS#[0..7] 1 1 9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0

CD23

CD24
8 DDR_B_D[0..63] Populate RD4 for Intel DDR3 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
VREFDQ multiple methods M1 2 2 DDR_B_D3 17
DQ2 DQ6
18 DDR_B_D7
8 DDR_B_DQS[0..7] DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
8 DDR_B_MA[0..15] 21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS VSS
27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R 12
DQS1 RESET#
Note: 31
VSS VSS
32
DDR_B_D10 33 34 DDR_B_D14
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37
VSS VSS
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS
45 DQS2# DM2 46
DDR_B_DQS2 47 48
DQS2 VSS DDR_B_D22
49 VSS DQ22 50
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS 54
Layout Note: 55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 58
Place near JDIMMB DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
+1.5V_MEM
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
8 DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB 8
75 VDD VDD 76
77 78 DDR_B_MA15
NC A15
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_B_BS2 79 80 DDR_B_MA14
8 DDR_B_BS2 BA2 A14
1 1 1 1 81 VDD VDD 82
C DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
CD25

CD26

CD27

CD28

DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD VDD 88
2 2 2 2 DDR_B_MA8 DDR_B_MA6
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD VDD M_CLK_DDR3
8 M_CLK_DDR2 101 102 M_CLK_DDR3 8
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
8 M_CLK_DDR#2 103 104 M_CLK_DDR#3 8
+1.5V_MEM CK0# CK1#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 8
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
8 DDR_B_BS0 109 110
BA0 RAS# DDR_B_RAS# 8
111 112
VDD VDD
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

DDR_B_WE# 113 114 DDR_CS2_DIMMB#


8 DDR_B_WE# DDR_B_CAS# WE# S0# M_ODT2 DDR_CS2_DIMMB# 8
8 DDR_B_CAS# 115 116 M_ODT2 8
CAS# ODT0
1 117 118
VDD VDD +DIMM0_1_VREF_CA
@ CD35

1 1 1 1 1 1 1 DDR_B_MA13 119 120 M_ODT3


A13 ODT1 M_ODT3 8
CD29

CD30

CD31

CD32

CD33

CD34

CD36

+ DDR_CS3_DIMMB# 121 122


8 DDR_CS3_DIMMB# S1# NC
123 124
VDD VDD
125 126
2 2 2 2 2 2 2 2 TEST VREF_CA
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
DDR_B_DQS#4 VSS VSS
135 136
DQS4# DM4

CD37

CD38
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
B DDR_B_D40 VSS DQ44 DDR_B_D45 B
147 148
DDR_B_D41 DQ40 DQ45
Layout Note: 149
DQ41 VSS
150
151 152 DDR_B_DQS#5
Place near JDIMMB.203,204 153
VSS DQS5#
154 DDR_B_DQS5
DM5 DQS5
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
+0.75V_DDR_VTT DDR_B_DQS#6 VSS VSS
169 170
DDR_B_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_B_D54
173 174
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_B_D60


DDR_B_D56 VSS DQ60 DDR_B_D61
1 1 1 1 181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS
CD39

CD40

CD41

CD42

185 186 DDR_B_DQS#7


VSS DQS7# DDR_B_DQS7
187 188
2 2 2 2 DM7 DQS7
189 190
DDR_B_D58 VSS VSS DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
+3.3V_RUN VSS VSS
197 198
SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT 7,12,14,15,28,36
VDDSPD SDA
2 1 201 202 DDR_XDP_WAN_SMBCLK 7,12,14,15,28,36
RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D
RD6

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

1 1 205 GND1 GND2 206


A A
CD43

CD44

FOX_AS0A626-U8SN-7F
2

CONN@
2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6591P
Date: Monday, January 10, 2011 Sheet 13 of 66
5 4 3 2 1
5 4 3 2 1

CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled


at the rising edge of RSMRST# pin.
Can be place in 0 height area. +3.3V_ALW_PCH @ JXDP2
So signal should be PU to the ALWAYS rail. @ RH1 33_0402_5%~D XDP_FN0
Shunt Clear CMOS 17 USB_OC0#_R
1 2
XDP_FN1 +3.3V_ALW_PCH
1 GND0 GND1 2
XDP_FN16
@ RH3 1 2 33_0402_5%~D 3 4
17 USB_OC1#_R @ RH4 33_0402_5%~D XDP_FN2 OBSFN_A0 OBSFN_C0 XDP_FN17
Open Keep CMOS +3.3V_ALW_PCH 17 USB_OC2#
1 2
XDP_FN3
5 OBSFN_A1 OBSFN_C1 6
@ RH5 1 2 33_0402_5%~D 1 7 8
17 USB_OC3# @ RH6 33_0402_5%~D XDP_FN4 XDP_FN0 GND2 GND3 XDP_FN8
1 2 9 OBSDATA_A0 OBSDATA_C0 10
17 USB_OC4# @ RH7 33_0402_5%~D XDP_FN5 @CH1
@CH1 XDP_FN1 XDP_FN9
ME_CLR1 TPM setting 17 USB_OC5#
1 2 11 OBSDATA_A1 OBSDATA_C1 12

1
@ RH8 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_16V4Z~D 13 14
RH66 17 USB_OC6# @ RH9 33_0402_5%~D XDP_FN7 2 XDP_FN2 GND4 GND5 XDP_FN10
Shunt Clear ME RTC Registers 17,42 SIO_EXT_SMI#
1 2
XDP_FN8 XDP_FN3
15 OBSDATA_A2 OBSDATA_C2 16
XDP_FN11
1K_0402_5%~D @ RH10 1 2 33_0402_5%~D 17 18
18,41 SLP_ME_CSW_DEV# @ RH12 33_0402_5%~D XDP_FN9 OBSDATA_A3 OBSDATA_C3
Open Keep ME RTC Registers 18,36 USB_MCARD1_DET# HDD_DET#_R @ RH13
1 2
33_0402_5%~D XDP_FN10
19 GND6 GND7 20
1 2 21 22

2
BBS_BIT0_R @ RH14 33_0402_5%~D XDP_FN11 OBSFN_B0 OBSFN_D0
1 2 23 24
@ RH15 33_0402_5%~D XDP_FN12 OBSFN_B1 OBSFN_D1
1 2 25
GND8 GND9
26
D +RTC_CELL PCH_AZ_SYNC 18 GPIO36 @ RH16 33_0402_5%~D XDP_FN13 XDP_FN4 XDP_FN12 D
18 GPIO37 1 2 27
OBSDATA_B0 OBSDATA_D0
28
@ RH17 1 2 33_0402_5%~D XDP_FN14 XDP_FN5 29 30 XDP_FN13
18 EN_ESATA_RPTR# OBSDATA_B1 OBSDATA_D1

1
@ RH18 1 2 33_0402_5%~D XDP_FN15 31 32
18,41 TEMP_ALERT# GND10 GND11
1

@ RH282 @ RH19 1 2 33_0402_5%~D XDP_FN16 XDP_FN6 33 34 XDP_FN14


RH38 100K_0402_5%~D 18 PCH_GPIO15 @ RH20 33_0402_5%~D XDP_FN17 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15
1 2 35 36
330K_0402_5%~D 18 SIO_EXT_SCI#_R @ RH283 1K_0402_5%~D OBSDATA_B3 OBSDATA_D3
37 38
GND12 GND13 +3.3V_ALW_PCH
16,42 PCH_RSMRST#_Q 2 1 RSMRST#_XDP 42,52 1.05V_0.8V_PWROK 1 2 1.05V_0.8V_PWROK_R 39 40

2
PWRGOOD/HOOK0 ITPCLK/HOOK4
@ RH24 1K_0402_5%~D
7,16 SIO_PWRBTN#_R 1 2 PCH_PWRBTN#_XDP 41 42
2

PCH_INTVRMEN @ RH21 0_0402_5%~D HOOK1 ITPCLK#/HOOK5


43 44
VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
45 46
HOOK2 RESET#/HOOK6
1

47 48 XDP_DBRESET#
HOOK3 DBR#/HOOK7 XDP_DBRESET# 7,16
@ RH39
@RH39 On Die PLL VR is supplied by CH2 @ RH284 0_0402_5%~D 49 GND14 GND15 50
330K_0402_5%~D 18P_0402_50V8J~D 1 2 DDR_XDP_WAN_SMBDAT_R2 51 52 PCH_JTAG_TDO
1.5V when sampled high, 1.8 V 2 1 PCH_RTCX1 7,12,13,15,28,36 DDR_XDP_WAN_SMBDAT
1 2 DDR_XDP_WAN_SMBCLK_R2 53
SDA TD0
54
7,12,13,15,28,36 DDR_XDP_WAN_SMBCLK SCL TRST#
when sampled low @ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
2

YH1 PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS


57 TCK0 TMS 58

1
1 G 2 59 GND16 GND17 60
RH2
INTVRMEN- Integrated SUS 10M_0402_5%~D
UH4A
SAMTE_BSH-030-01-L-D-A
4 3
1.1V VRM Enable G

2
* High - Enable Internal VRs CH3 32.768KHZ_12.5PF_Q13MC1461000~D A20 RTCX1 FWH0 / LAD0 C38 LPC_LAD0 33,34,41,42
18P_0402_50V8J~D A38

LPC
Low - Enable External VRs 2 1 1 2 PCH_RTCX2 C20
FWH1 / LAD1
B37
LPC_LAD1 33,34,41,42
RTCX2 FWH2 / LAD2 LPC_LAD2 33,34,41,42
RH286 0_0402_5%~D C37
FWH3 / LAD3 LPC_LAD3 33,34,41,42
+RTC_CELL 1 2 PCH_RTCRST# D20
RH22 20K_0402_5%~D RTCRST#
FWH4 / LFRAME# D36 LPC_LFRAME# 33,34,41,42
1 2 SRTCRST# G22 +3.3V_RUN
RH23 20K_0402_5%~D SRTCRST#
E36

RTC
INTRUDER# LDRQ0# LPC_LDRQ0# 41
1 2 K22 K36 LPC_LDRQ1# 41
RH11 1M_0402_5%~D INTRUDER# LDRQ1# / GPIO23 IRQ_SERIRQ 2 1
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ RH28 8.2K_0402_5%~D
C INTVRMEN SERIRQ IRQ_SERIRQ 33,34,41,42 PCH_AZ_SYNC_Q 2 C
@ CH100 1
27P_0402_50V8J~D RH37 10K_0402_5%~D
1 2 1 2 AM3 PCH_GPIO33 2 1
1 2 1 2 PCH_AZ_BITCLK SATA0RXN PSATA_PRX_DTX_N0_C 28
1 2 N34 AM1 RH355 100K_0402_5%~D
31 PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C 28

SATA 6G
RH32 33_0402_5%~D AP7 HDD BBS_BIT0_R 2 1
PCH_AZ_SYNC SATA0TXN PSATA_PTX_DRX_N0_C 28 RH51 4.7K_0402_5%~D
L34 HDA_SYNC SATA0TXP AP5
@ @ PSATA_PTX_DRX_P0_C 28
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
30 SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C 29
1 2 1 2 AM8 SATA_ODD_PRX_DTX_P1_C 29
1U_0402_6.3V6K~D PCH_AZ_RST# SATA1RXP
CH5 1U_0402_6.3V6K~D CH4
31 PCH_AZ_MDC_RST# 1 2 K34
HDA_RST# SATA1TXN
AP11
SATA_ODD_PTX_DRX_N1_C 29 ODD/ E Module Bay
CMOS place near DIMM RH34 33_0402_5%~D AP10
SATA1TXP SATA_ODD_PTX_DRX_P1_C 29
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
30 PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
30 PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT 31 PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34
HDA_SDIN1 SATA2TXN
AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
SATA2TXP
30 PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @RH35
@ RH35 10K_0402_5%~D

IHDA
RH26 33_0402_5%~D +3.3V_ALW_PCH HDA_SDIN2
AB8
SATA3RXN
30 PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# 1 2 A34
HDA_SDIN3 SATA3RXP
AB10 No Reboot Strap
RH27 33_0402_5%~D @RH287
@ RH287 1K_0402_5%~D AF3
SATA3TXN
30 PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK SATA3TXP
AF1 Low = Default
1 RH25 33_0402_5%~D RH36 1 2 33_0402_5%~D PCH_AZ_SDOUT A36 SPKR
31 PCH_AZ_MDC_SDOUT

SATA
HDA_SDO
41 ME_FWP RH50 1 2 1K_0402_5%~D Y7 ESATA_PRX_DTX_N4_C 39
High = No Reboot
@ CH101 +3.3V_ALW_PCH SATA4RXN
Y5 ESATA_PRX_DTX_P4_C 39
PCH_GPIO33 SATA4RXP
27P_0402_50V8J~D
2
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
ESATA_PTX_DRX_N4_C 39 E-SATA
AD1
SATA4TXP ESATA_PTX_DRX_P4_C 39
1

USB30_SMI# N32
29 USB30_SMI# HDA_DOCK_RST# / GPIO13
@RH288
@ RH288 Y3
+3.3V_RUN SATA5RXN SATA_PRX_DKTX_N5_C 40
0_0603_5%~D Y1
SATA5RXP SATA_PRX_DKTX_P5_C 40
SATA5TXN
AB3
SATA_PTX_DKRX_N5_C 40 DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2

JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C 40


1

B RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN B

JTAG
@ RH295 JTAG_TMS SATAICOMPO
8.2K_0402_5%~D RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 +SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
+3.3V_ALW_PCH_JTAG RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
2

JTAG_TDO +1.05V_RUN
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

AB12
SATA3RCOMPO
1

1
@ RH48

@ RH49

@ RH47

PCH_SPI_DO
AB13 +SATA3_COMP 1 2
SATA3COMPI
SPI_MOSI RH42 49.9_0402_1%~D

High: Enable Intel


Anti-Theft Technology PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
+3.3V_RUN
2

SPI_CLK SATA3RBIAS RH46 750_0402_1%~D


Left floating: Disable Intel Anti-Theft Technology

1
PCH_SPI_CS0# Y14
SPI_CS0# RH30
PCH_SPI_CS1# T1 10K_0402_5%~D

SPI
17,34,36,37,41,42 PCH_PLTRST#_EC SPI_CS1#
P3 SATA_ACT#
+3.3V_SPI +3.3V_M SATALED# SATA_ACT# 45

2
2
G

PCH_SPI_DO V4 V14 HDD_DET#_R 1 2


SPI_MOSI SATA0GP / GPIO21 HDD_DET# 28
RH290 0_0402_5%~D
1 2 1 2 PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3

S
31 PCH_AZ_MDC_SYNC SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# 42
CONN@ RH350 0_0402_5%~D RH33 33_0402_5%~D
S

JSPI1
1 SPI_PCH_CS1# 1 2 2 1 SSM3K7002FU_SC70-3~D CougarPoint_Rev_1p0 QH1 BSS138W-7-F_SOT323-3~D

G
2
1 PCH_SPI_CS1# RH345 0_0402_5%~D RH31 1M_0402_5%~D
2 QH7 7,17 PCH_PLTRST#
2 SPI_PCH_DO
3 1 2
3 PCH_SPI_DO RH346 0_0402_5%~D
4
4 SPI_PCH_DIN
5 1 2 +3.3V_SPI C745 BBS_BIT0 - BIOS BOOT STRAP BIT 0
5 PCH_SPI_DIN RH347 0_0402_5%~D +3.3V_SPI C746 0.1U_0402_16V4Z~D
6
6 SPI_PCH_CLK 0.1U_0402_16V4Z~D
7 1 2 1 2
7 PCH_SPI_CLK RH348 0_0402_5%~D
8 1 2
8
1

SPI_PCH_CS0#
9
9 1 2
200 MIL SO8
1

PCH_SPI_CS0# RH349 0_0402_5%~D R888


10 10
200 MIL SO8
1

1
A R890 3.3K_0402_5%~D A
11
11 +3.3V_SPI
3.3K_0402_5%~D R891 16Mb Flash ROM R892
12 12
13
+3.3V_M 64Mb Flash ROM 3.3K_0402_5%~D U53 X76@ 3.3K_0402_5%~D
2

13 SPI_PCH_CS1#1
14 U52 X76@ 2 SPI_CS1# 1 8
2

14 SPI_PCH_CS0# /CS VCC


15 1 2 SPI_CS0# 1 8 R935 47_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2

15 /CS VCC 2
16 R933 47_0402_5%~D SPI_PCH_DIN 1 2 SPI_DIN32 2 7
16 SPI_PCH_DIN DO(IO1) /HOLD(IO3)
1 2 SPI_DIN64 2 DO /HOLD 7 R895 33_0402_5%~D
SPI_WP#_SEL SPI_CLK32 1 2 SPI_PCH_CLK
17 SPI_WP#_SEL
R894
1
33_0402_5%~D
2 3 6 SPI_CLK64 1 2 SPI_PCH_CLK @R896
@
1
R896
2
0_0402_5%~D
3 /WP(IO2) CLK 6
R897 33_0402_5%~D Compal Electronics, Inc.
G1 41 SPI_WP#_SEL /WP CLK SPI_DO32 1 Title
G2 18 @ R898 0_0402_5%~D R899 33_0402_5%~D 4 GND DI(IO0) 5 2 SPI_PCH_DO
SPI_DO64 1 SPI_PCH_DO
4 GND DIO 5
R901
2
33_0402_5%~D
R900 33_0402_5%~D
PCH (1/8)
W25Q16BVSSIG_SO8~D Size Document Number Rev
W25Q64BVSSIG_SO8~D 1.0
HRS_FH12-16S-0P5SH(55)~D LA-6591P
Date: Monday, January 10, 2011 Sheet 14 of 66
5 4 3 2 1
5 4 3 2 1

+3.3V_RUN

QH5A

2
DMN66D0LDW-7_SOT363-6~D

MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK 7,12,13,14,28,36

5
MEM_SMBDATA 3 4 DDR_XDP_WAN_SMBDAT 7,12,13,14,28,36
QH5B
D Follow DG0.9 Device down & Express/Mini card UH4B DMN66D0LDW-7_SOT363-6~D D

topology 1 2
BG34 @ RH296 0_0402_5%~D
36 PCIE_PRX_WANTX_N1 PERN1 PCH_SMB_ALERT#
36 PCIE_PRX_WANTX_P1 BJ34 E12
PERP1 SMBALERT# / GPIO11
MiniWWAN (Mini Card 1)---> 36 PCIE_PTX_WANRX_N1
AV32
PETN1 1 2
AU32 H14 MEM_SMBCLK @ RH297 0_0402_5%~D
36 PCIE_PTX_WANRX_P1 PETP1 SMBCLK
BE34 C9 MEM_SMBDATA
36 PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
36 PCIE_PRX_WLANTX_P2 BF34
PERP2
MiniWLAN (Mini Card 2)---> 36 PCIE_PTX_WLANRX_N2
BB32
PETN2
AY32

SMBUS
36 PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
SML0ALERT# / GPIO60 A12
DDR_HVREF_RST_PCH 7 +3.3V_ALW_PCH
37 PCIE_PRX_EXPTX_N3 BG36 PERN3
BJ36 C8 LAN_SMBCLK
37 PCIE_PRX_EXPTX_P3 PERP3 SML0CLK LAN_SMBCLK 32
EXPRESS Card---> 37 PCIE_PTX_EXPRX_N3 AV34 PETN3
AU34 G12 LAN_SMBDATA SML1_SMBCLK 1 2
37 PCIE_PTX_EXPRX_P3 PETP3 SML0DATA LAN_SMBDATA 32
RH298 2.2K_0402_5%~D
BF36 SML1_SMBDATA 1 2
29 PCIE_PRX_EMBTX_N4 PERN4
BE36 RH299 2.2K_0402_5%~D
29 PCIE_PRX_EMBTX_P4 PERP4 GPIO74
E3 Module Bay---> 29 PCIE_PTX_EMBRX_N4 AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13
+3.3V_ALW_PCH
BB34 PETP4
29 PCIE_PTX_EMBRX_P4 SML1_SMBCLK
E14

PCI-E*
SML1CLK / GPIO58 SML1_SMBCLK 42
36 PCIE_PRX_WPANTX_N5 BG37 PERN5
1/2vMINI CARD-3 PCIE BH37 M16 SML1_SMBDATA DDR_HVREF_RST_PCH 2 1
36 PCIE_PRX_WPANTX_P5 PERP5 SML1DATA / GPIO75 SML1_SMBDATA 42
AY36 RH300 1K_0402_5%~D
(Mini Card 3)---> 36 PCIE_PTX_WPANRX_N5
BB36
PETN5 GPIO74 2 1
36 PCIE_PTX_WPANRX_P5 PETP5 RH301 10K_0402_5%~D
BJ38 MEM_SMBCLK 2 1
35 PCIE_PRX_MMITX_N6 PERN6
BG38 RH302 2.2K_0402_5%~D
35 PCIE_PRX_MMITX_P6

Controller
PERP6 PCH_CL_CLK1 MEM_SMBDATA
MMI ---> 35 PCIE_PTX_MMIRX_N6 AU36 PETN6 CL_CLK1 M7 PCH_CL_CLK1 36 2 1
AV36 RH303 2.2K_0402_5%~D
C 35 PCIE_PTX_MMIRX_P6 PETP6 PCH_SMB_ALERT# C
2 1

Link
BG40 T11 PCH_CL_DATA1 RH304 10K_0402_5%~D
32 PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 36
BJ40 PEG_A_CLKRQ# 2 1
32 PCIE_PRX_GLANTX_P7 PERP7
10/100/1G LAN ---> 32 PCIE_PTX_GLANRX_N7 AY40 PETN7
RH80 10K_0402_5%~D
BB40 P10 PCH_CL_RST1#
32 PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# 36
BE38 +3.3V_LAN
PERN8
BC38
PERP8
AW38
PETN8 LAN_SMBCLK
AY38