RESUME

YUVAPRIYA.R
B/178, Reyon Nagar Mobile number : +91-9442755707
Sirumugai (PO)-641302 Email-id : yuvapriya67@gmail.com
Tamilnadu

OBJECTIVE:
Result oriented and dynamic professional with wide exposure in ASIC verification. Sound
knowledge in verification tools and methodologies and logic design. Looking for a position as an ASIC
verification engineer in a prestigious organization.

SKILLS
HDL/HDVL
Verification Methodology
Programming Languages
Scripting Languages
EDA Tools
Operating Systems
: Verilog, System Verilog
: UVM
: C, C++
: PERL, SHELL
: Riviera Pro, Libero IDE
: Windows, Linux

AWARDS AND ACHIVEMENTS:

First rank holder in diploma
Won third prize in state level Tamil speech competition
Selected as one day RJ by hello FM
ACADEMIC PROFILE:
BOARD/ YEAR OF % OF
COURSE INSTITUTION UNIVERSITY PASSING MARKS
Sri Krishna College Of Technology, Anna University,
B.E- ECE Kovaipudur. Chennai 2012 82.8
DIPLOMA IN Nanjiah Lingammal State Board Of Technical Education
ECE Polytechnic College, And Training, 2009 95.9
Mettupalayam. Chennai.
SSLC Govt. Higher Secondary School, State Board Of Tamilnadu.
Pethikuttai. 2006 86

ADVANCED TRAINING: Pursuing design and verification course (QCDVE QSOCS certified design
and verification engineering)in VLSI from Qsocs Technologies, Bangalore.
PROJECTS
1. Verification of AXI to AHB BRIDGE
Platform :Windows/Linux | Language : Verilog HDL and UVM | Tools : Rivera Pro, Libero
Objective: The project focuses on verification of AXI to AHB bridge. Based on AMBA bus, the
Intellectual Property (IP) core of bridge has been verified. The bridge provides interface between the
high performance AXI and AHB domain. It has a slave interface which receives the AXI master
transactions and converts them to AHB master transactions and initiates them on the AHB bus

2. Design and Verification of UART

Platform :Windows/Linux | Language : Verilog HDL and UVM | Tools : Rivera Pro, Libero
Objective: The project focuses on design and verification of UART with AMBA 3 APB
protocol. UART is a serial communication protocol which allows the full duplex communication
in serial link, it is an essential to computers and allows them to communicate with low speed
peripheral devices, such as the keyboard, the mouse, modems etc.

Design

Analyzed the specifications of UART-APB

Prepared micro-architecture for the same
Designed RTL of each sub modules in Verilog HDL
Direct testing of each sub modules was done.
Combined all the sub modules into a final module
Took the RTL of UART-APB and analyzed its functionality
Verification

Prepared the test plan

Prepared the test bench architecture
Created the test environment in System Verilog
Methodology used is UVM

3. Design and Verification of Asynchronous FIFO

Platform :Windows/Linux | Language : Verilog HDL | Tools : Rivera Pro, Libero

Objective: This project focuses on design and verification of Asynchronous FIFO which is used
in preventing meta-stable state when a signal crosses clock domain (Clock Domain Crossing). As
part of the project Asynchronous FIFO with Width 1 byte and Depth 16 is designed in Verilog
HDL and simulated using Rivera Pro and coverage reports are generated.

EXPERIENCE: Nanjiah Lingammal Polytechnic College, Mettupalayam. Lecturer (3 years)

PERSONAL PROFILE:
Fathers Name : Rajasekaran.R
Date of birth : 23.07.1991
Gender : Female
Nationality : India
Languages Known : English, Tamil
DECLARATION
I hereby declare that all the above details are true and correct to best of my knowledge and belief.
Place:
Date:
(R.YUVAPRIYA)