Design of 32-bit RISC Processor

Talal Khaliq

MSEE (DSSP)-7

Reg No: 118396

Supervisor: Dr. Awais M. Kamboh

Date: 22 June 2017

 32-Bit Processor Design Report

Introduction:

The main purpose of this project is to develop simple RISC (Reduced Instruction Set Computer) based
GPP (General Purpose Processor). In this academic project, a simple 32-bit RISC processor will be
designed and tested on an FPGA. For proof of concept, a simple open source 8-bit processor will be
selected to run on FPGA using custom instructions written in C. Thereafter, we shall try to change
specifications and peripherals of the timer like timers, UART, SPI etc.

Selection of 8-bit Processor:

An Open Source Core for 8051 Microcontroller written in VHDL from Oregano Systems was chosen.
Its main features due to which it was chosen are as under:

Instruction set compatible to the industry standard 8051 microcontroller

Active timer/counter and serial interface units selectable via additional special
function register
Parameterizeable via VHDL constants
256 bytes internal RAM
Up to 64 Kbytes ROM and up to 64 Kbytes RAM

Work on FPGA:

Two projects for 8051 were created in Xilinx ISE for synthesis and simulation. Spartan 3E (XC3S500E)
was chosen for both simulation and synthesis. However, due to low IOBs (about 200%) in Spartan 3E
during synthesis, we had to chose Vertex 5 (XC5VFX70T) Evaluation Board to work on.

Top module for 8051 was written in VHDL, which used 8051 Core as well as memories such as 128 x
8 RAM, 64k x 8 ROM and 64k x 8 External RAM. Memories were created from Core Generator in
Xilinx ISE. Configuration for 128 x 8 bit RAM is as follows:

Single Port RAM

Minimum Area
Read / Write Width: 8
Write / Read Depth: 128
Enable (ENA) Pin
Write First
Reset (RSTA)

32 Bit RISC Processor Design 2

 Fig 1: RAM Configuration in Xilinx

Configuration for ROM is as follows:

Single Port ROM

Minimum Area
Read Width: 8
Read Depth: 65536
Always Enabled
Load Init File (COE File)
Use Reset (RSTA) pin

Fig 2: ROM Configuration in Xilinx

Configuration for XRAM (External RAM) is as follows:

Single Port RAM

Minimum Area
Write / Read Width: 8

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 Write / Read Depth: 65536
Write First
Always Enabled
Use Reset (RSTA) Pin

Fig 3: XRAM Configuration in Xilinx

Architecture of Top Module is as follows:

32 Bit RISC Processor Design 4

 Fig 4: Top Module (from Oregano Systems Doc)

Work on Keil C51 (Microcontoller):

For 8051 Core to work on FPGA, we had to create HEX file from C file written for selected
microcontroller. The code used was for BLINKY, an example from Keil C51 after installation. Oregano
System IP Core was already in Keil C51 as shown below:

Fig 5: Target 8051 Microcontroller in Keil

Conversion from HEX to COE:

32 Bit RISC Processor Design 5

HEX file created is loaded into microcontroller ROM as instructions to execute a particular function.
On FPGA, however, ROM created from Xilinx Core does not use HEX file. It rather loads Coefficient
(COE) File into ROM.

To convert HEX to COE file, there are some open source tools available but most are not compatible
with 64 bit Windows. For this purpose, an alternative set to tools were introduced which convert
HEX to bin file and then, bin to COE. These tools used Command Prompt in Windows as shown:

Fig 6: HEX to COE Conversion in Command Prompt

The resulting COE File is referenced by ROM Core during Core Synthesis. These are instructions for
FPGA to perform once it is programmed into FPGA.

Implementation Problems on FPGA:

Before implementation, User Constraints (UCF) file was created in project. On board clock for FPGA
is 100 MHz. Program loaded from HEX file running on default 12 MHz clock. Change in clock domains
caused wrong results in LEDs shown as P0 of 8051 Core.

To deal with this problem, a PLL Core was introduced in between FPGA Clock and 8051 Core Clock.
The resultant clock was matched at: 11.675 MHz. Core Schematic is as follows:

32 Bit RISC Processor Design 6

 Fig 7: Core RTL Schematic in Xilinx

Final Implementation on FPGA:

Once all problems were catered, programming file was generated and loaded into FPGA and was
working smoothly. We tried with different clock speeds to check Timing and Power Utilization of
Synthesis Process. 40MHz was highest clock speed possible achieved by 8051 Core. Comparison for
25 MHz and 40 MHz using different design strategies in given below:

Fig 8: Comparison on different design strategies

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Configuration of IP Core for extra peripherals:

The original microcontroller design offered only 2 timers, one serial and 2 external interrupt units.
These can be changed in VHDL Core using some constants to increase or decrease the said
peripherals. However, to be able to reach all registers of the generated units without changing the
address space of the microcontroller only two 8 bit registers are inferred as additional special
function registers (SFRs). Efforts are being made to be able to infer SFRs in Keil.

Currently, REG51.H is referenced by C File in Keil. SFRs inferred is shown below:

Fig 9: REG51 SFRs

Future Work on 32 Bit Processor:

Taking 8 bit processor 8051 as our initial understanding, we will replicate design strategies for 32 bit
processor. For 32-bit processor, starting with an open source processor design for Leon 3, the study
will involve synthesis of code, compilation of program, and test of pre-configured peripherals on an
FPGA.

Once a decent level of understanding has been achieved, a new peripheral will be integrated into the
processor to enhance the processor's capabilities, and to adapt them for better performance in a given
domain of applications. Also, compiler will be customized as per requirements.

Using study of processor architecture of Leon 3, we will try to design our own processor will custom
instruction set, peripherals, memory management module and custom compiler.

32 Bit RISC Processor Design 8