System Requirements

The keyless auto entry system will be operated by a five- button keypad near the outside door handle.
To keep this project manageable, only four numeric buttons (1, 2, 3, and 4) will be used. The entry code
will be a user-defined sequence of four, five six or seven digits. A Reset button will also be provided, to
be used in the event digits. A Reset button will also be provided, to be used in the event an error is
made while entering the code. After pressing the RESET button, the correct entry code sequence must
be reentered from the beginning.

To make it convenient e for the car owner to set up a custom entry code that can be easily
remembered, a setup panel will be provided inside the car on switch the owner can set switches to
program the digits of the combination and the length of the code.

The system will have a single output. UNLOCK, which activate a mechanism to unlock the door. It is
assumed the electronic signal is overridden by the normal mechanical lock and keys mechanism. A block
diagram of the keyless auto entry system is shown in fig.13.11. It contains the following subsystems:

Code entry keypad. Four push-button switches will be used, representing the digits 1, 2, 3, and 4. A fifth
push-button switch wills active the RESET function. Each switch will generate one logic-high pulse when
pressed. To ensure clean pulse, each switch will be debounced. The signals produced by the four data
switches will be set to an encoder circuit, which will generate a single pulse each time one of the four
numeric buttons is pressed, along with a 2-bit binary code to represent that button. The Reset button
will generate a pulse to reset the system control unit. This button will be disabled for a designated
sleep interval any time three successive incorrect attempts have been made to open the lock.

Setup panel. A panel of 16 DIP switches, shown in fig. 13.12a, will be provided to program the length of
the code sequence and the digits comprising the code. Since valid code sequences can be 4, 5, 6, or 7
digits long, two DIP switches, B7 and B8, will be used to set the code sequence length as defined in
fig.13.12b. Each digit of the code sequence must be one of the four numbers 1, 2,3,or 4. Therefore, two
DIP switches will be assigned to each digit of the code sequence and set as defined in fig.13.12c. Since
the maximum code length is 7 digits, a total of 14 switches are needed to define any possible code
sequence. Signals from the 16 DIP switches will be set to the code checker module, which will determine
if a correct code has been entered.

Code checker:

The checker determines if sequence of digits entered by the keypad is the code sequence defined by
the DIP switches on the setup panel. This module requires a counter to keep track of the number of
digits entered and a circuit to compare each digit to the corresponding pair of switches on the setup
panel. An UNLOCK signal will be generated by the control unit if a correct code sequence has been
detected. An ERROR signal will be generated by the control unit if any entered digit is in error or if too
many digits are entered. Both of these should be reset when the door is opened or when the lock is
reset.
Sleep circuit .

The function of the sleep circuit is to prevent the system from being reset for a period of 3 minutes
following a third consecutive incorrect attempt to open the lock. This circuit will reset the system
automatically after the 3 minutes has elapsed.

Control unit. The control unit will provide all timing and control signal for the other modules. In doing
so, it will determine whether a code sequence is being entered, if a reset is needed following an error in
entering a code sequence, or if the sleep circuit must be activated following three incorrect attempts to
enter the correct code sequence.
Logic Design.

The logic circuit design for the keyless auto entry system will be presented by describing each module
identified in the requirements. Then the modules will be combined to create the complete circuit. The
following paragraphs present the design of the individual modules.

Keypad Interface and Encoder.

The keypad interface comprises five push-button switches, debounce circuitry, and an encoder circuit.
A pair of cross-coupled NAND gates can be used for each switches as debounce circuit, as shown in
fig.13.3 for the previous example. To produce the 2-bit code for each button, a standard 4-to-1 priority
encoder circuit can be used, as described in chapter 4. The circuit diagram is represented in fig.13.13.
Note that there are three outputs: D indicates that at least one digit button is being pressed, and d1d0
is the 2-bit code corresponding to the highest priority button.

For correct operation, the rest of the circuitry will expect the D signal to go high and then low again as
each new button is pressed. If two buttons are pressed at the same time, only the higher numbered
button will be detected.

Setup Panel.

The 16 DIP switches on the setup panel will be set in advance and will be assumed to remain fixed
throughout the operation of the system. Consequently, debounce circuitry is not needed. The DIP
switches are configured as shown in fig.13.14. Each line is pulled up to a logic 1 value when the switch is
OPEN and pulled down to logic 0 when CLOSED.

DIP switches B7 and B8 are routed directly to the circuit that checks the number of digits entered. The
other 14 switches are routed to the circuit that compares them to the entered code.
Code Checker.

The code checker performs two functions. First, it counts the number of digits entered at the keypad.
Since the maximum entry code sequence length is seven digits, a 3-bit binary counter can be used for
the digit counter. The digit counter will be incremented on the falling edge of each pulse on INCD and
cleared whenever a Reset signal is generated on CLRD. In this example, we select a 74LS93 four-bit
binary counter with asynchronous reset, connected as shown in fig.13.15.

The second 74LS93 shown in fig.13.15 counts the number of cod entry attempts. This counter is
incremented after each unsuccessful try on the falling edge of a pulse on INCT and cleared by a pulse on
CLRT. At the counter outputs, a 1 is produced at output T of the AND gate when the count reaches 3,
that is, when QaQb=11. This signals the control unit that there have been three unsuccessful tries to
enter the code.

The second function of the code checker is to compare the 2-bit code for the nth digit of a code
sequence entered by the keypad to the setting of DIP switch pair n on the setup panel. One circuit is
needed to select and route switch pair n to a comparator, to be compared to the code for the entered
digit.

Since there is seven pair of switches, a dual 8-to-1 multiplexer can be used for this purpose. Two
74LS151 8-to-1 multiplexer modules will be used, as shown in fig.13.15. The switch pair is selected by
the digit counter described previously. Pair 0 will be selected immediately after the counter is reset to 0,
pair 1 after the first digit has been entered, and so on. Note that the 74LS93 is incremented on the
falling edge of each pulse on INCD, while the comparison is performed while the pulse is high.

Two comparison circuits are needed, one to compare entered digits to the corresponding pairs of DIP
switches and the second to compare the number of digits entered to the pair of switches that defines
the code sequence length. In the first case, a 2-bit comparator could be used and, for the sequence
length, a 3-bit comparator. Rather than design these circuits, 74LS85 four-bit comparator modules will
be used for each, as shown in fig.13.15. For the first 74LS85, the upper inputs come from the keypad
encoder and the lower inputs from the digit counter, while the lower input the first 74LS85, the upper
inputs come from the keypad encoder and the lower inputs from the digit counter, while the lower
inputs are from DIP switches B& and B8.

Figura 13.15. Diagrama logico de verficador de codigo

Sequence is detected, generating a sleep signal in the form of s pulse with a duration of 3 minutes that
will prevent the control unit from being reset.

Sleep Circuit.

The sleep circuit is to inhibit the operation of the system for a 3-minute period following three incorrect
attempts to enter the combination. This will be done with a 555 timer module configured as shown in
fig. 13.16 for monostable (one-shot) operation. The 555 will be triggered by an active-low pulse from the
control unit on signal SLP whenever a third consecutive incorrect code-entry sequence is detected
generating a SLEEP signal in the form of a pulse with a duration of 3 minutes that will prevent the
control unit from being reset.

Recall from Chapter 6 that the 555 output width is given by tw= 1.1RAC.

Therefore, the values RA = 3 M and C = F produce a pulse of approximately 3 minutes in duration.

Control Unit

In response to entries from the keypad, the control unit is responsible for determining when to active the
UNLOCK mechanism, when to activate the SLEEP circuit, and when to reset the system.
As shown earlier, the keypad encoder produces a pulse on signal D whenever one of the four digit buttons
is pressed, and the RESET button produces a pulse on signal R. Since these are the primary signals that
initiate actions in the system, the control unit will be designed as a pulse mode asynchronous sequential
circuit, as described in Chapter 10.

As pulses are generated on the D and R signals, three other conditions determine what the control unit
should do. These conditions are represented by the C, L and T signal lines as follows.

C=1 if the current digit entered is correct, and 0 if the current digit is incorrect.

L=1 if the number of digits entered is equal to the entry code sequence length, and 0 otherwise.

T=1 if there have been three previous tries at entering the code sequence, and 0 otherwise.

As shown in 13.15, signal C is the output of the 74LS85 comparator that checks for correct digits, signal
L is the output of the 74LS85 that compares the output of the digit counter to the selected code length,
and T is produced by the counter of the three-tries detector.

As discussed in chapter 10, we begin the control unit design by developing a state diagram, which is sown
in fig.13.17. From this state diagram we see that the control unit has three states:

INIT: Initial state, waiting for the first digit to be entered.

ENTRY: Digit entry state; the control unit remains in this state as long as correct digits are entered. This
state is exited when a code input error is detected, when the REST button is pressed, or when an entire
correct entry-code sequence has been entered.

ERROR: Error state, the control unit enters this state if an error is made in the entry-code sequence, and if
there have not been three previous errors. The control unit remains in this state until the RESET button is
pressed, whereupon it returns to the INIT state.

The state table and binary state table for the control unit are given in figs.13.18a and b, respectively. Let
us use JK flip-flops configured to operate as T flip-flops. The T flip-flops excitation table is given in
fig.13.18c. From this table we can derive the T flip-flops excitation equations, and from the transistion
table we can derive the output equations for the pulse mode sequential circuit.