CAREER ENDEAVOUR PUBLICATIONS has taken due care int collecting the data and providing the solutions, before , s, ) Publishing this book. Insite ofthis, if any inaccuracy of printing error occurs then CAREER ENDEAVOUR PUBLICATIONS ‘owes no responsibilty. CAREER ENDEAVOUR PUBLICATIONS willbe gratoful if you. could point out any such error, Your ‘Alright reserved by CAREER ENDEAVOUR PUBLICATIONS. No part of tis book maybe reproduced or tized in any form without the writen permission from the publisher. SE Aunit of Career Endeavour Academy Pvt. Ltd.PREFACE TO THE FIRST EDITION The book is written with the objective of providing an elegant description of fundamental principles of electronics including their applications at a'level.relevant for post-graduate students in different Indian Universities and JRF aspirants. The book: contains a concise description on each topic of Electronics followed by an admirable number of solved and unsolved problems. This book will be extremely fruitful for the candidates preparing for ‘various. competitive examinations at national and state level such as CSIR-UGC-NET, GATE, SLET ete. Invall. competitive examinations such as CSIR-NET, GATE, SLET ete., Electronics carries approximately seven to ten percent weightage of total marks as follows: + Every year GATE paper includes at least 7 to 10 marks from this section + Every session CSIR-UGC-NET paper includes atleast 1010 15 marks from this section. Apart from CSIR-UGC-NET, GATE, SLET, this book will also be very useful to candidates appearing for other examinations such as PSUs, i.e. ONGC, NTPC, HPCL, etc. Students preparing for various competitive examinations are advised to go through each topic for their understanding and conceptual clarity and then get into solving the problems, For the betterment of the students, an excellent number of subjective problems are also provided at the end of every topic in the book. We have taken much care to minimize the typographical errors in the book. In spite of that, if anyone finds any mistake, then your suggestions are graciously invited with a prospect to upgrade the book in future editions. We would tike to thank our respected faculty members for their valuable inputs in the ook: A note of thanks also to Mr. Navin Chandra Pathak for formatting, designing and type- setting the book.CONTENTS Chapter Page Nos. 9s Chaptent/ Network Theory . (24-62) | | My Chapter. Semiconductor Diodes . oL U4 Chapters6/Zener Diode and opto Electronics... Chapter-3 Bipolar Junction Transistors ..... . (63-85) Chapter-A/ Field Effect Transistors (FET) 3» Chapteré/Operational Amplifier. ’ Chapter7/bigital Electronics . (113-139) — | | (140-163) — Chapter-8: Microprocessor . . (164-165)CHAPTER ~— 1: NETWORK THEORY Basie Cireuit Analysis and KVL/KCL, Resistance: It is the property of a resistor to oppose current. fo : . Cased: > —— Conventional curent flow from high to low potential Case: —15— 8 Electron current flow from low to high potential In both case I and case II: =iR ‘Where resistance of Resistor: | R where {= length of conductor, A= Area of conductor, p = resistivity of conductor. 1 So and conductivity ~ Ressivity Current: + The phenomenon of trahsferring charge ftom one point in a circuit fo andther is described by the tem electric current. + Anclectric current may be defined as the time rate of net motion of electric charge across a cross- 4g sectional boundary | =F" | q = Coulombs, «= see, i= Amp Voltage: + Tomove the electrons from one point to other point in particular ditection external force is required. In analytical circuit external force is provided by emf and it is'given by aw dq where a differential amount of charge da is given a differential increase in energy dW Voltage = “Energy per unit charge” = “Work pet unit charge” © Avoltage can exist between a pair of electrical terminal whether a current is flowing or not. An automobile battery, for example, has a voltage of 12V across its terminals even i nothing whatsoever is connected to the terminal. Ohm’s Law: ‘+ Atconstant temperature, the potential difference V across the terminals ofa resistor R as show below, is dicectly proportional to the current i flowing through it, ‘That is Vail|V=R Ml tv ‘Ohm’s law can also be expressed in terms of conductance G as exc G= Conductance {miho or Siemens} NETWORK THEORY14589 ea 5 Field Interpretation of Ohm’s Law: = “At constant temperature current density is directly proportional to electric field intensity.” + _0i it Jak == we [FE OE] I rnnnn Current density (Alm), 6 E vaso Blot Geld intensity (V/m) Linearly test of Resistor: «When resistive element obeys ohms law then the element i called as near fsistor otherwise it is ‘a non-linear resistor: Power Dissipation in a Resistor: .-- Conductivity (Q—m)"'] Practical Voltage Sources: It delivers energy at specified (V) which depends on current delivers by sources. Vs) Current Sources! [deal current source delivers energy at a specified (1), which is independent on voltage. across the source. Internal resistance of ideal current source = o. io ~—— ny Ky Vv 1 v | ideal DE ac Practical Current Sources: Practical current sources delivers energy at specified current I, which is dependent on voltage across the source. in real time system current source does not exist. 1 i@ I gx Vv Log De aC NETWORK THEORYCapacitance: It is the property of capacitor to hold charge q to confined electric field. ae ede EA Ly Coe G Jie v d= distance between plates, A= Area of cross section of each conducting plates Note: When the capacitance of capacitor is independent of current is called as linear capacitor. Q 4 oy, So under steady state ie, at ¢->.00 Capacitor acts as open circuit: Inductance: © Ifthe current “flowing in an element of figure below changes with time, the magnetic flux * * produced by the curtent also changed which causes a voltage to be induced in the cireuit, equal to the rate of flux linkage that is a a ly al '*@ dt where, L is constant of proportionality and is called self inductance. a ie) ve) 0) @ Inductive cireuit ‘Mhutally coupled circuit ‘Therefore, there is an induced emf in coil B, which is equal to © As (dildt) is directly proportional to (a / dt) . Comparison of these two equation gives No=Li NETWORK THEORY@o : From above it may noted that an inductor is a device, while inductance is the quantity L. No i . Asvar%, a And circuit behaves like shots cieuit ‘Active Element: When an element is capable of delivering energy for infinite period of time is called as active a Example: Voltage, source, current source. Passive Element: When an element is not able to deliver energy for infinite time period is called as passive in steady state ie. 100 [V=0 clement, Example: Resistor, inductor and capacitor Active Elements: Voltage Source: Ideal voltage source delivers energy at a specified ‘V’. Internal resistance of ideal voltage source is Zero v co Vv vO vo T t DC source AC source: Voltage Divider Rule: NETWORK THEORYFor capacitor: ¢, Qo CTC, 1, 1, h==—1 l ] 6, 26,4, Gia ae Kirchoft’s Voltage Law (KVL): It states that algebraic sum of all voltages in a closed loop is equal to zero. It is based on conservation of energy. Applying KVL: Vth, VV =0 [Path Q. Calculate values of V, and V, across 4¢ and 502 resistor by KVL. Soin. Qa wk OW dy Applying KVL 6+3+1-5-d-21-2-51=0 = ULI volt Vy Calculate V in the given circuit 2 a yw wh af be jibe a NETWORK THEORYwo : Soln. KVL at loop 1: (Left loop) 41, - 21, + $=0, I, = 5/6 Amp KVL at loop 2: (Right loop) 10 - 21, ~ SI, =0 Applying KVL 8 TE 15 - 51+ 45~ 91-2V =0 36 53-17-21 1=0, 1= 3 [Tet7 Kirchoff Current Law (KCL) © KCL states that algebraic sum of all current meet [Xi=0] NETWORK THEORYLimitations of KVL and KCI Calculate the values of V, and V, by KCL: . 2 Vv, 20 VY, 19 cath 12 Ba 1, =) | w+ Q) | By solving equation (1) and (2); We get V; = 5V and V, = 3V KCL and KVL will fail for the high frequency circuit. KVL and KCL will fail in distritmted elements since in distributed element it is not possible to separate effect of R, L, C. Source Transformation: ve T SIOVR i Series Combination of Batteries: R, R, 2B MA I ove, Parallel combination of current sources: We 1@ FR OL FR Ory, FRR Obtain single current source for network shown A i) Ov 6 5a NETWORK THEORYQ. Convert given circuit into a single voltage source x 0 12A¢ 62 jy x 400 102 @xv Sola. > Olav 0 Qnv Y Linear and non-linear Elements: ‘A linear network shows linear characteristics of vatage versus current. For a non-linear element the current passing through it does not change linearly with the linear change in applied voltage at a particular frequency. Semiconductor devices are usually examples of non-linear element: Tn VL relation if output is zero for zero input and relation is linear then itis called linear network or ‘element obeys ohm’ law. V=ki- linear V=ki? + Nonlinear V=2i+3 — Non-linear . V=i* -» Nonlinear y v r i Linear Non-Linear ‘Simple resistors inductors and print at end capacitors are linear elements and their resistance inductance and capacitances do not change with, change in applied voltage on the cirouit current . Active and Passive Elements: Ifa circuit element has the capability of enhancing the energy level of a signal passing through it then it is called an active element. Vacuum tubes and semicanductor devices are active elements on the other hand resistors, inductors, capacitors, thermistors ete. are passive elements as they do not have any intrinsic mean of signal boosting. ‘ InV- relation if any portion has V-I value as negative then itis active network. Bilateral and Unilateral Element: Ifthe magnitude of the current passing through an element is affected due to change in polarity of polarity of the applied voltage then element is called unilateral element. On the other hand if current ‘magnitude remains the same even if the applied voltage’s polarity is changed then it s called a bibteral elements. Ifby changing variable relation between both dependent variable and independent variable remains ‘same then it is called bilateral network otherwise unilateral network. NETWORK THEORYMesh Analysis: Mesh is a property of a planner circuit and is undefined for a non-planner circuit. We define a mesh as “A loop that does not contain any other loops within it.” Fig. (@) Fig.) [Planner] [Non-Planner] No branch passes over or under any other branch Network Theorem: Superposition Theorem: «The statement of superposition theorem follows as below: “In any linear bilateral network having more than one source, response in any one of the branches equal to algebraic sum of the response caused by individual source while rest of the sources are replaced by their internal impedances. Note: => The principle of superposition is useful for linearly test of the systems. = This is not valid for power relationship. => Sources can be made inoperative by (a) Shot circuiting the voltage sources (©) Open circuiting the current sources => Alinear network comprises independent sources, linear dependent source and linear passive elements like resistor, inductor, capacitor and transformer. Moreover, the components may either be time varying or time invariant. . Other Definition: “The superposition principle states that the voltage across (or current through) on element ina linear circuit is the algebraic sum of the voltage across (or curtent through) that element due to each independent source acting alone. Q _Caleillte value of V for the given circuit by using superposition theorem. 82 vl any 3 Soln. At one time only effect of one source is considered. Voltage source is short circuited and current source is open circuited. Since there are two sources, So, V = Vi +V, NETWORK THEORY} | | Let V, is the voltage across 4 ohm due to 6V voltage source alone (in this case current source is open circuited), 89. 82. So total voltage V is V=V, + V, =2 +8 = 10 volt Q Calculate the value of V, by use of superposition theorem. 32. 2 Soln, Since there are two sources so total voltage due to both sources will be [7 =H, +7, Let V, is the voltage only due to 8A current source, (In this ease 20V source is short circuited) 32. 5 30. 2 Vig20 fH) sa A0v 8x3 _ 34245 Let V, is voltage due to 20V source alone 2,V,=4 volt, Y=, +V,=8+4 volt Thevenin’s Theorem: ‘Any two terminal linear bilateral network can be replaced by a voltage source in series with impedance. A, V,=2x4=8 volt NETWORK THEORY: @ Calculation of Thevenin’s equivalent for independent source:’ For Calculation of R,,: All independent current sources are open circuited and all independent voltage sources are shott circuited. For Calculation of V,,: Voltage across open circuit terminal. Calculation of Thevenin’s equivalent for dependent source: For calculation of V,,: Voltage is calculated across open circuited terminal by assuming current zero in that terminal. For calculation of R,, First Ise is calculated by assuming short-circuited terminal and then R,, is calculated by | Rn =Vin se Q For the given circuit calculate the power loss in the 1 ohm resistor by use of thevenin’s theozem. x i bar ho ag y Soln. For calculation of V,, branch X-Y terminal is assumed as open circuited and let voltage is V,,- xv, at V,=10 Volts, V,-V, =5x2=10 [V, =10 Volt For Calculation of R,,: (If dependent source is present) 2A cuirent ‘source is open circuited and 10V source is short circuited and let resistance is Ry, : 10: 5 Ry 10x5 Fo T045" Ro Vy 10 RytR, 33341 Q. Find the current through the 9 ‘resistor inthe circuit by use of Thevenin’s theorem. 22. 231A 2a 10 2 svSoln. For calculation of V,, = 5 ohm resistor is open circuited dnd so current in 5 ohm will be zero. For Calculating Ry,: 2A current source is open citcuited and 5V source is short circuited, 29 7 Se ee by 30 RytR, 5+10 Norton’s Theorem: Any two terminal linear bilateral network containing active and passive element can be replaced by an equivalent current source in parallel to an equivalent impedance current source. A l—a Nw L, @ Us B Note: Ry 1D i Vn (0) Thevenin'sequvatet circuit. (6) Norton's equivalent circuit . Both of the above circuits are convertible to each other with the relations given as below: Rey = Ry Vg = Ty Ry = Tye Q. Find the Norton’s equivalent circuit actoss a-b for the network shown in figure: a 50: sa 20. we —ob sa Soln, 5a Te na NETWORK. THEORY ie2 2455 +1) =0,1,= 2-5 =04-5 7, 6A SFL I= O01. =F Ry =1A3 Q Find Norton’s equivalent to the right of a-b terminal (across 3V source) Teer Sv 50 iy Soln, The equivalent circuit after shorting ab terminal. 10Q_ iv 100 Esa Oieta 503 ¥ © ® -[To calculate R,} ae 3710!” 10° Reciprocity Theorem: +)”. A linear network is said to be reciprocal or bilateral ifit remains invariant due to the interchang’ of position of cause and effect in the network. + For verification of the recipfocity theorem following conditions must be satisfied. => Circuit should consist of linear, time-invariant bilateral element. => Circuit should consist of only a single independent sources. => — When circuit consist dependent source, reciprocity theorem can not be verified. i Maximum Power Transfer Theorem: Maximum power transferred from source to load is only possible when (i) Source impedance = Load impedance i) Thevenin impedance = Load impedance Ry =10+5=150 For DC Circuits: ; ‘4 x] | pe ' ! Source ic AR ‘Network. | ¥ L ¥ (Load connected to the do source network) (Equivalent source network and load) NETWORK THEORYDifferentiating equation (i) with respect to R,, and equating to zero, We get Hence, it has been provided that power transfer from a de source network to @ resistance network is maximum when the internal resistance of the de source network is equal to the load resistanve. ‘Again value of that maximum power i, p= ako. Ya Rat Ray AR r fe By =R wn [pw ‘The total power supplied is thus: Pade Poo ‘During maximum power transfer the efficiency 1 becomes, Nn =ARa x = 3 ae 100% [n=50% 2Rry So that efficiency in this case is 50% i.e. half of the total power is transferred to the toad R, [Maximum Power Transfer Theorem for ac circuits} ‘Consider the Thevenin’s equivalent cirouit for an ac network as shown below: Za + Nowlet us consider different cases for maximum power transfer. f Case-1: Both R, and X, are variable ‘© When both R, and X, are variable then maximum power from source to load will be transferred if load impedances is complex conjugate of internal impedance of the network. «_Inthis case maximum power (active) will be calculated as | P.,, = 2 NETWORK THEORY. Also during maximum power transfer efficiency will be’50%. Case-2: R, is variable but X, is constant, + Inthis case maximum power willbe transferred when, [ R, -|Zn + or R, = YR Xn +) y { Re x10 + Biiceney can be caleuated as) "=| gm + Efficiency comes out to be greater than 50% [11 >50% Case-3: Load impedance is purely resistive. + Inthis case-maximum power will be transferred when, + Efficiency comes out to be greater than 50%. : R, and X, are variable but the impedance angle is constant ic. , a(X, Z,=R, +X, and Q=tan (2%) scons In this case maximum power will be transferred when, [Z, = Zr Qa Calculate value of R in circuit such that maximum power transfer takes place and also calculate amount of this power, 19 50. we 20, $10 ! re Soln, Above circuit can be solved by Thevenin’s theorem: V 7 1 19 5a i To find Ry, 20 HOR, Ry =[(2I|I) +S] It [Ry = 0.85 Lt jo 50” To find V.,, open load R AVE 20, eati Maximum Power = 7p 64y 0.85 Rw Assuming maximum power transfer from source to load R calculate the value of R and maximum value of power transferred. 19 6-2 52x 100 §R 30 ¥ V3, _ (4090/3) Fou” Fy gas 3 Wa 3 NETWORK THEORYAssignment - Network Theory A segment ofa citcuit is shown in figure V, = SV, Vi =4 sin 2. The voltage V, is given by (@) 3-8 cos 2 (®) 32 sin 2¢ © 16sin2¢ = @ 16 cos 2¢ In the circuit of figure, the magnitudes of V, and_V;, are twice that of Vp. Given that f= 50 Hz, the inductance of col is . Me 3a chy, $00 Lv. @ 2.14 mH & 5308 OUSMU — @132H In the figure value-of R is 140. 12, 10M SA 00 7 40V- (@ 109 & 180 ©@24a @ Ra In figure, the potential dference between points P and Q is, fa) 12V @ lov ov @ 8v In figure, the value of resistance R in gis (a) 10 @ 40aifhe RMS value of the voltage u(#) = 3 + 4 cos (31) © @ viv ov on @ IV Assuming ideal element in the circuit shown below, the voltage V,, will be a 20 at) Me ») sv b @ 3V @® ov ©3v @v The current through the 2k® resistance in the cixeuit shown is 1kQ_c_ 1k ps 1k 1kQ: ov (@) Oma © ima (©) 2ma (@ 6mA ‘The time constant for the given circuit will be HF 39 IPE TIF 30 3A, @ Wes (by 14s (© 4s Og In the circuit given below, the value of R required for the transfer of maximum power to the load having a resistance of 30 is BA. we ws 30] Load @0 ®) 30 © 62 @ o The rms. value of the current i(0) in the circuit shown below is rt 1Q iw [70 (isint)v cy ab i @ 5A . OBA @1A @Ov2A, - NETWORK THEORY12. Inthe given figure, the Thevenin’s equivalent pair (voltage, impedance), as seen at the terminals P Q, is given by 10 mf of woohoo @ @v,say () GV,52) © v.52) @ (2V,750) 13. Inthe circuit shown, the power supplied by the voltage source is 8 10! 10 =)10v 1K 19 2A, if @ ow &) SW @low @-100W 14. The voltage ¢, in the figure is: 20 Tay ft sad fon jo 202, @ 48V (b) 24V ©36V @ 28v 15. Inthe circuit of figure, the value of the voltage source E is Vy ae wy E Hy vAW "Soy i @ -16v ) 4v ov @ 16v | 16. The voltage V in figure is equal to: sv 208 ov 3 a @ wv © =v ov (@) None of these 17. The voltage in figure is + 32 I v Sev @2A @ WV (b) 15V oN @) None of these NETWORK THEORY‘What is the value of R required for maximum power transfer if network shown above? 52 42 @ 20 © 40 © 8a @ 162 The voltage across the terminal a and b in figure is: Brey aw Iv 20% 3A 6 (a) 0.5V (b) 3.0V (©) 3.5V @ 4.0V ‘The nodal method of circuit analysis is based on (@ KVLand ohm’s law () KCL and Ohm's law (© KOL and KVL (@ KCL, KVL and Ohm’s law The current i, in the curreat of figure is equal to: 5A (dea diode Diode Resistance: Diode Resistance’) fc| Davtuste Forward Resistance Reverse Resistance (Loe to 1009) (Rr) IMO) DC Resistance or ACResitame ot 7 gy Static Resistance (R) Dynamic Restanee (r= 4-0) Static 1 DC Resistance: The static resistance of a diode is defined as the ratio V/I of the voltage to the current. + ~ 02 (very less) SEMICONDUCTOR ‘DIODES2. Dynamic / AC Resistance : For small signal operation the dynamic, or incremental, resistance ris defined asthe reciprocal ofthe slope ofthe Vottampere characterise, r= 2. Fora semiconductor diode. 1% ee Wa % we ov ic cond ee eee Dynamic conductance g= 7 is 8p == For a forward bias greater than a few tenths of a volts. 1 >> I,, and r is given approximately by ae rode I Note: DC resistance > AC resistance © ‘The dynamic resistance of Ge diode with a forward current of 26mA is 7mA. «Dynamic resistance in Si diode is more than in Ge diode, Contact Potential: (V,) Wo, KT, (NN; Then =AEn( MX) K~» Bolteman’s constant Depletion Region. . The contact potential V, cannot be read by an voltmeter connected across it because of barrier voltage balance by a metal to semiconductor contact potential at the end of diode. SEMICONDUCTOR DIODEStential barrier and width of depletion layer across P-N junction: barrier potential V, is given by | %=|%p1+I¥a1 Ne e\v je! V, is the potential full in P-region and V, is the potential fall in N-region. Width of depletion layer is given by [7 =, +, Since crystal as a whole is electrically neutral the number of charge carriers on both side must be equal ie. Ww Ww W, Wi= 1K wes Bean To oe Ne Ny Ne So, itis clear that if doping is increased on one side then depletion layer width will increase on other side. In case of P-N, junction diode if doping is increased on P-side width of depletion layer wil increase on N side. llue of Width Depletion Layer: yy, = j 28% and = X, wie Ne q { &) So, total width of depletion layer is given by W =”, ~ Wy SEMICONDUCTOR DIODESForward Biased P-N Junction Diode: 1, Forward current, R, ~» Series resistance > Fy When a PN junction is forward biased the width of depletion layer reduces and barrier height reduces. When a diode is properly forward the effect of barrier voltage becomes zero. =h{e* -1)| 1=2> Si n=1> Ge V-I Characteristic: V,= 0.3V for Ge = 0.7V for Si Note: ¥,—> Cut in voltage or offset Voltage or threshold voltage V, ~> Defined as “minima forward voltage required above which the forward current flow’s through device. In case of reverse biase curent is due to flow of'm of minority carriers. If voltage is further increased in erse direction then reverse current does not increase. At the breakdown of junction, value of current increases abruptly, a Effect of Temperature on Forward Current: | ; _ 7 Forward current is only due to majority carrier concentration is almost independent of temperature, ‘SEMICONDUCTOR ‘DIODESse V, decreases with temperature. For 1°C increase in temperature V, decreases by 2.3 ion in Diode led junction or Abrupt Junction: rupt p-n junction. It refer’s to p* or PN* diode. atively faster than normal diode. n layer will always penetrate more into lightly doped region consider P‘N diode. O= @y +O, at type of Capacitance in P-n Junction: Space Cliarge or Transition Capacitance: When a P-N junction is reversed biased then depletion ion acts like an insulator or dielectric material while P and N regions of either side have low SEMICONDUCTOR DIODESNote: 33, Vz» Knee voltage, V, > Reversed biased voltage | K ~> Depends upon S.C. material n= : for step graded junction (Alloy junction) i for diffused junction / Linearly graded junction "2 _, Step graded / Alloy C.<(V,+¥,)” | > Linearly graded / Diffused Diffusion or Storage Capacitance (C,): Diffusion capacitance dominates in a forward biased diode. It is mainly responsible for storage of minority carriers across the junction. a av Mathematical Value: C, Cate wv (r= dynamic résistance = F-) Where g, = dynamic conductance a, aw, | 80, |% so [C, «I, Diffusion capacitance Cy increase linearly with the forward current. Junction Capacitance) : é Revepse bias bead bias ‘Transition / Depletion Diffusion / Storage ‘Varacter Diode: ‘These are voltage vatiable capacitor, ‘Varacters diode is a linear graded diode. Its principle of operation is transition capacitance (C,). It is always operated under reversed bias condition. ‘Transition capacitance (C,) is given by | Cy 1 Where | "= 5 As reverse bias increases, transition capacitance decreases.Re (Charactetistic Curve) ‘Varacter diode is also known as “Vari-cap diode” or “volt-cap diode” or “epi-cap diode” Equivalent Circuit: & ’——— 4 —_—« w— Boye © ier Where, R, = Reverse resistance (> IMO), R, = Contact resistance (< 100) Boications: ‘Varacter diode is a low noise microwave device. It is fabricated with Ga As, "For direct generation of FM by using varacter diode modulator circuit For fine tuning of Receivers. For self balancing of bridges ‘As a para-armplifer (Parametric amplifier) and iti low noise microwave power amplifier used with satellite communication, Various Diode models in Forward Biasing: 1. Exponential Model: it va ~ Ve Oey V5 of Piece-wire linear Characteristic: vy ~|2 SEMICONDUCTOR DIODES —3. Constant Voltage drop Model: i io Ideal diode: it + ot Vo y. +—_, - Junction Diode Switching Time: In a given P-N junction diode when external voltage is suddenly reversed Q Soln. in a diode circuit which has been! carrying current in forward direction the diode current will not immediately fall to its steady state reverse voltage value until injécted or excess minority cartier density P,—Pyy has dropped normally to zero. The diode will continue to conduct easily and current will be determined by the external resistance in diode circuit, Value of, is generally of the order of 400n Consider again the asymmetrical silicon diode we discussed in the previous two examples. Let the ‘mean lifetime of boles be 10 nS, and let = 1. Ifa forward current of 0.1 mA is flowing in the diode, determine the diffusion capacitance. ath 10n8x0.1nA p= ay, | Vr=0026V, Co=— oa, = 38.5pF 10,026V —SEMICONDUCTOR DIODESConsider an asymmetrical silicon junction, with N, = 10'/em? and N, ~ 10"/em®. If the cross- ‘sectiotial area of the junction is 9.6u1n°, determine its transition capacitance with no applied bias. Q-F wn) ‘ 2 KT Waly, v=n= avy" : al =) ; {10° x10" 5 ons | Or, ¥, =0.94V 2x LL.9x8.85x10"% Hence, W = | gr 094 = 0.11 bt A _ 119x8,85x10"x9.6x10" es O.1tx10% 1 7 draw 0! p On the basis of the connection of the diode - Clipper are again divide in these manner. Clipper Series Parallel _ Positive Negative Positive Negative _SEMICONDUCTOR. DIO)Table ‘Simple Series Clipper (Ideal Diode {a) Positive Biased Series Clipper (Ideal Diodes): (a) Positive SEMICONDUCTOR DIODESSimple Parallel Clipper (Ideal Diode): (a) Positive av, 2 ® vy, v, > vb Ve = v i vo PLY, sed Parallel Clippers (Ideal Diode): (@) Positive Vs £ ® + Y. v vy 74 a Va vf ~ T_. Ni ——xr_ Tt v ¥ V,> jt % poe. N, F t t+ AY y ky» ~e. We Note: In all the above clipper circuit always see carefillly to the connection and polarities of diode and Batteries respectively. SEMICONDUCTOR DIODESAbove circuit is used to convert sinusoidal wave form into a square wave. To generate a symmetrical square wave V,, ard Vp) are adjusted numerically equal but of opposite sign. ‘Above circuit is known as slicer because the output contains a sive of input between two reference level Vp and Vp. ve D, | D, Me Vey OFF) ON \¥j2 SDouble-ended clipper using avalanche diedes: R : ——— v v y, wah yi Y) wy’ Assuming diodes to be ideal describe the transfer characteristic of circuit shown, 10k0 F + D, LD, vs Sv. SV LY, 0K F10KD2 y, for -S +5 . For Level Clipping: SEMICONDUCTOR DIODES ‘iClamper Circuit: ‘A clamper isa network constructed of diode a resistor and a capacitor that shifts a waveform to a different to level without changing the appearance of the applied signal. ‘Addition shift can also be obtained by introducing a do supply to the basic stiticture the chosen resistor and capacitor of the network must be chosen such that the time constafit determined by T=RC is sufficiently large to ensure that the voltage across the capacitor does not discharge significantly during the internal the diode is nonconducting, Clamping network have a capacitor connected directly from input to output with a resistive element in parallel with the output. * Clamping network have a capacitor connected directly fiom input to output with a restive clement in parallel with the output signal. The diode is also in parallel with the output signal but may or may not have a series de supply as an added element. Analysis: Step: ‘Step2: Step3: Step4: |: Start the analysis by examining the response ofthe portion of the input signal that will forward bias the diode. During the period thatthe diode is “On” state, assume that the capacitor will charge up instantaneously to.a voltage level determined by the surrounding network. Rv, [DON stoi Assume that during the period when the diode isin the “off” state the capacitor holds on to its established voltage level. D(OFF)—Oper ‘Through out the analysis, maintained a continual awareness of the location and defined polarity for V, to ensure that the proper levels are obtained. Since V, is in the parallel with diode and resistor, it can also be drawn in the alternative position shown in step (3). Applying KVL in input loops V-V-v,=0 [R=-2V SEMICONDUCTOR: DIODES‘Check thatthe total swing of the output matches that ofthe int. (Very important to check the propex answer in optional questions). = 22OV + V_- SV = Innegative half cycle. 25V- (section of KVL) Teak Check the total swing Input swing = 30V (V; na¢— Vi mig’ Output swing = 300 (Vo max Vo gui) ‘The wave is not start with 0 because of some finite time taken in the discharging. SEMICONDUCTOR DIODESSoln, Find the output waveform of the network. KH — ap v v, 1oK$ |__! Step I: Condition on V, for the diode to be ON and OFF. Applying KVL: -V, - IR - 2V = 0, IR = ~V,~ 2V For D ON: -V,-2V.>0 = V,<-2V Step II: For D to be ON: -V, + V,-2V=0 1 Vy=V, +2 2ov| Doff, Vi>-2V 3 Step 1 : Let D, is ON, D, is OFF; -V,- IR +3V=0, IR=-V,+3 For D, is ON; IR>0 = -V,+3>0 = [V,<3V D, is OFF; IR <0 = [V53V Let D, is ON and D, is OFF; Vi- IR - 5V=0 = IR=V,-5 For D, is ON; IR>0 => V, < SV; D, is OFF = IR<0 = [V,<5V Don | D.-oFF |D.-oNn D,~OFF| D.~OFF | D.-OFF 3V 3v ‘SEMICONDUCTOR DIODESFor V, <3V = V,=3V, 35V = V,=3V ‘A syinmetrical 5 kh squaré wave whose output varies between +10V and ~10V is impressed open clippling circuit shown in figute. If diode has Rj~ 0 and R, = 2mQ arid V) =0: What is output waveform? Kt + Step-I: -V, ~ 2.5 - IR = 0, 2.5 -V,=IR Dis ON; IR > 0, V,<2.5V When D is OFF; IR < 0 V,>2.5V Step-Il: If D is ON, V, <2.5V, then output will be [ Vs = V, IED is off V, > 2.5 V, V,-21-11-2.5V=0 _V,-25V 3 = 3I=V,-25V = |I V,-2.5475 42.5 = Woot Vy=11+25=1 V+5.0 Z| @is oFF) Step-III: Waveform of the output rv, a. 10] ov 25y| 259 >t -10V| SEMICONDUCTOR. DIODESe 2 Soln. Soln. Questions Regarding Diédes Calculate the value of current I in the above circuit. (Assume diode is ideal) Apply KVL, 0 -.1K1+5=0, [1=5mA. ‘The cut in voltage for each diode is 0.6V (Si) each diode current is 0.5mA. Find the value of R,, RyRy Current across Ry = .5 + 5 = ImA, Current across R, = 5 +.5+.5= 1.5 mA Va = 5-06 = 44V, V, = 0-06 =-0.6V 10-06-44 44-(-06) : S30, ImA °. ” 1 > O5mA ~ 10KQ. R= @5405mA ~0.6-(-5V) 44 G4545)mA ~ T5mA? Ps = 293k Calculate the value of current I. Cut in voltage of Si = 0.7V and Ge = 0.3V. Applying KVL in the given circuit 12=0.7+03+1% 56K WL 12-1=1%* 5.6K, 1= sek 1=1,96mA SEMICONDUCTOR DIODES+1, i omy Yoo — £ 2K Find value of V, in the given circuit. Hy Both Si and Ge are in forward bias but Ge will attain cutoff early. So Si will not conduct. +100 Sketch the output waveform ifthe input signal is indicated as: vi When V, <0, D, -> ON, D, -» OFF -V,- IR = IR = 0, 2IR =-V, IR > 0 wa = 5, if v, 0, D conducts, so that V, = 0-and R 100 Vs=——_V,=0.91V, [V, =182V RAR, * 100+10 * ste If V, <0, D blocks, so that V,, = Vs and V, = 0 sketches of V,, and V, are shown in figure, V, i-SEMICONDUCTOR DIODESthe waveform of the following circuit. Examples on Clamper Circuit: YH 3st Zy-Vot 10-0 wv Vy = -25~ 30 Step-IIl: 1" 20¥} Applying KVL in let Side loop Vo =30V V, =-10V easy] ‘Step-I: When diode is OFF (T/2—T) Applying KVL ~25-V,~-V)=9,V, wy} -ssv SEMICONDUCTOR DIODESQ Draw the output waveform of the following circuit? a . toy] v a 100K y, oe sv o+ - — -20V| Son, Step-I: When diode is on; G oT i,t a T~ Apply KVL: -20- V,-5=0 =| Vo =+25 pie + wo fo y Apply KVL: 10 - V.~ Vy = 0; V, = 10 - (25) [V, =35V 10} ~20V| 35v) Total swing of input total swing of output D.C. Power Supply: Step Down Transfer Mr t. Rectifier] | Filter Rena ie oH ‘SEMICONDUCTOR DIODESmportant Terms: , Letus signal X;=Xpe +X qe @ X,(rms) Form factor (F) =~ y + Q) . Xachrms) Ripple factor (1) = ~"y ~-Q) X,(rms) = \Xi.+Xicim, ~@ X,(ms) | (Xbo*Xicim (Zig) ss Form factor (F) = Eo = NOPE Atm), fy 4 | Sac MD eae te Xoo Fave? (5) Or ripple factor (r) = (Form factor)? -1 VF?=-1 + (6) Note: Form factor is always greater than { (F > 1) X ay Means root mean square ofthe signal X,. = Ltye Krenn OY = tt fea} o ‘Theorem (1) : If X)=%(0+ 40+. + X(t) DC values or average value of X() X= HOt KO Ft XO) 2 (8) ‘Theorem (2): If XQ=Asinos, X,(0=Asino,t Xn = yf Xin + Xm | (9) Where | @, #0, Single, Phase Diode Rectifiers: Rectifier is the process of conversion of bi-directional alternating input voltage to uni-directional output voltage. In diode based rectifiers, the output voltage cannot de controlled. ‘A rectifier may half wave type or full wave type. SEMICONDUCTOR :DIQDES.- Gg Single Phase Half Wave Rectifier: This is the unidirectional rectifiet. i lV, sino ate) Vag =—*{-cos or], a -» (10) RMS value of output voltage 7 2 ee ae sin? ot =cos2ot hy x 2 sin’ ovat) Pr d(wt)| = z All) ¥,12 Form factor f=Yme = = _ E elm 2 F=157 (12) Ripple factor (= /F*—-1 = (57-1 =121 ~- (13) Ripple frequency is the same as the input frequericy in this case. Peak Inverse Voltage (PIV): PIV is the rating of diode. It is defined as the maximum reverse voltage, diode can withstand. ne . (14) PIV= v= (15) SEMICONDUCTOR DIODES. igenB, tifier Efficiency: n= + Output d.c. power, Py =Vng Lang (17) E-R.M.S. Output Voltage: . Rectification efficiency () = RMS. value of source current Jays “7 (20) Peak Value Crest factor = Rais Value = w= (21) =2 Single Phiase Full wave Mid-point Rectifier (Centre Tap): D.C. or average output voltage alll) SEMICONDUCTOR DIQDES“D.C. output current 2,2 Tyg =—2- == I, ar ~@) LA Where, 1, = Maximum value of load current = = 4 Output dc. power, P= Vg Lag == Va Ia » QG) RMS output carrent Lime wn 4) Output a.c. power ane ine = (5) ms ms = “Py Rectifier Efficiency: (6) a wW2 (7) we } ] = 03077 Vm (8) x Voltage ripple factor (VRF) = 0.3077 V,, * By = 0.483 . 9) PIV far each diode = 2V,, - (10) (1) Peak value of source current, ( Crest factor of input current = —% 7 en (12) I == CF.=1414 1,/V2 oD SEMICONDUCTOR ‘DIODES :Phase Full Wave Bridge Rectifier: a i Average output voltage: | V4, =——* Average output current: | Jing = B RMS value of output voltage | Vrms = > ty Ipa- RMS value of source current 4s =F Source current waveform for both types are identical, therefore CF=V2 oo i) (ill) a) SEMICONDUCTOR DIODES‘A comparison of three types of 1-phase diode rectifier which are given below: Parameter Half Wave Full Wave (or two Pulse) (orone Pulse) Centré-top Bridge v, Wy wy, 1. DCoutput voltage V,,_ = A 2 Fu as 2. RMS value of output a 7 voltage Vin. 3. Ripple voltage V, 0.3856 V,, 03077 V,, 03077 V,, 4. Voltage ripple factor (VRE) 1.211 0.482 0.482 5. Rectification efficiency (7) 40.53% 81.06% 81.06% 6 TUF 0.2865 0.672 0.8106 7 PV Va Vy iva 8 CE 2 v2 v2 9. No. of diodes 1 2 4 10___ Ripple frequency f 2f 2 Drawback of Centre-topped type Rectifiers: @ This is cosily and bulky because secondary winding is doubled. GD Topping exactly centre is not all feasible. Note: Overall bridge rectifier is better than centre tapped type rectifier. SEMICONDUCTOR DIO!Assignment on Diodes Cirenits - While analyzing circuits with a diode, the graphical method is often used because (@) graphs give mote accurate answer than solutions of equations (b) nodal or mesh analysis can not be used for the non-linear diode circuits (©) solution of circuits equations leads to multiple answer, which is unphysical (@ the non-linear diode equation makes the solution ofthe circuit equations very difficult, Vis given by 4 The input Vis given to the cireuit shown below: oH C= Ine R3100K2 VY, The V, is +17 suv [| "1 @ ssy| ! ® sy © @NoT Q Calculate I, and ID, in the circuit shown below. Assume the diodes are ideal. SEMICONDUCTOR: DIODESCalculate the current I, in the circuit shown below av 2K, (ideal diode) @ 1mA & -1mA @o (@2mA ‘The width of the depletion layers proportion to 7 1 1 9) (Doping © Doping ©Dovng Doping Which of the following option is correct for P'N diode shown below: bd N @ W,=W, () W,>W, ©W,2Vm @&) 2Vm — (©). <2Vm @ 2Vm PIV of a full wave bridge type rectifier. should be at least. Vr Wr @ Vm ©.2Vm oF om The circuit shown uses three identical diode having n=, = 10"'*A. Find the value of the current 1 to produce V, = 2 volt. (@ 3.8104 (b) 3nA “(280A @6na ‘The leakage current of a transistor are Top = 3A and Teg, = 0.3mA, I, = 30pA. The value of Bis (a) 79 (b) 81 a © 99 @ NOT SEMICONDUCTOR DIODESANSWER KEY @ 2 @ 3 4 @ 5 © © 1 @ & @) 9. @) 10. (a) @ 2 @ B. @) 4. © 15, (b) @ 17. &) 18. (@) 1». 20. (©) © 2. (a) 2B. @) 4. (@) SEMICONDUCTOR DIODESCHAPTER - 3: BIPOLAR JUNCTION TRANSISTORS ‘+ The bipolar junction transistor has three separately doped regions and contains two pn junctions. ‘© Assingle p-n junction has two modes of operation forward bias and reverse bias, + > Thebipolar transistor, with two P-n junction, therefore has four possible modes of operation, depenting on the bias condition of each p-n junction, which is one region for the vergatility of device. + With three separately doped regions, the bipolar transistor isa three terminal device. +The basic transistor principle is that the voltage between the two terminals controls he current through the third terminal. . ‘Current in the transistor is due to the flow of both electrons and holes, hence the name bipolar. «The n-p-n bipolar transistor contains a thin p-region between two t-regions. In contrast the p-m-p bipolar transistor contains a thin n-region sandwiched between two p-regions. «The three regions and their terminal connections are called the emitter, base and collector. . ‘The operation of the device depends, on the two p-n junction being in close proximity, so the with of the base must be very narrow, normally in the range of tenths of a micrometer (10° m). feyerec Fe . 0 Bs pio} p Cc Lao jo (einen (Collet Emitter-base Collector-base Junction (EBD) unction (CBI) B Base) «Of the tree regions, emitter is heavily doped, The next level of doping is collector and base is less than that of collector. IN, >No > + The doping of the sandwiched layer is considerably less than that of the outer layers (typically, 10:1 or less) +” Biitter is provided with medium area. «Base is provided with smallest area to reduee the transi trie, © ‘Collector is provided with the largest area to withstand heat dissipation. Symbol: ey Ee Cc B B (o-p-n transistor symbol) (p-r>p transistor symbol) Modes of Operation: ‘Made of Operations J,(C-B) ‘Applications ‘Active region RB ‘Asanamplifier Saturation region FB ‘Asanelectronicswitch Cut-off region RB Indigital circuit Reverseactivemodeor | 5, pp Asanamplifier with voltageand inverted mode current gain tobelow = BIPOLAR JUNCTION TRANSISTORSIna transistor ‘Emitter current - drift current Base current - recombination current Collector current - diffusion current The flow of charge carriers in a transistor between base and collector is due to the diffusion of ‘minority carriers and this action is called “transistor action”. Hence, transistor action takes place in the base region, ‘The total current flowing into the transistor must be equal to the total current flowing out of if applying Kirchhoff’s current law to the transistor as ifit were a single nade), Hence, the emitter current is equal to the sum of the collector are and base currents. The collector current comprise two components the majority and the minority carriers. The minority cartiet current is called the leakage current and is given the symbol {oq I, current will with emitter terminal open). : He = Renae + Toe] Ie It is also known as collector reverse-saturation current or thermally generated currert ithe transstor. Ig for Ge transistor is A range, Si transistor is nA range. Igo is very sensitive to temperature. Ig doubles for every 10°C rise in temperature For 1°C, ig approximately increases by 7%. Ti ae cour = Acorn Ico is independent of collector supply voltage. ‘The collector current is tess than the emitter current, There ate two reasons for this, Firstly, a of the emitter current consists of holes that do.A0t contribute to the collector current secondly, not all the electrons injected into the base are suiccessful in reaching the collector. Equation for Emitter Current: + Inatransistor under active region, emitter current is the forward current of emitter diode. Teale Leeteoe™ "| + Theemitter current exponentially increases with base to emiter voltage of transistor. . Ina transistor under active region V,, < LV. Typical value 0.2 V, For Si transistor [V, Typical value 0.7V © Voge teduced by 2.5 mV for 1°C rise in temperature, ie. ae - 2.5 mV PC| rT BIPOLAR JUNCTION TRANSISTORS‘Common Base Configuration: To fully describe the behaviour of a three terminal devices such as the common base amplifier, sequires two set of characteristics one for the ‘driving point” or input parameters and the other for the output side. - (o-p-n tuansistor C-B configuration) Input Characteristics: «The input set for the common-base amplifier as shown in figure relates an input current (f) to an imput voltage (Vig,) for various levels of output voltage Voy. Vee O02 04 06 08 1 (Gnput or driving painting characteristic for CB silican transistor amplifier) Ouitput Characteristic: © Itrelates I, to Vog for Various levels of input current I, as shown, L(A) T0310 1520 (@utput or collector characteristics for a CB transistor amplifier) + CB transistor is basically a current controlled current source (CCS). © The curves clearly indicate that a first approximation to the relationship between I, and I, inthe active region is given by BIPOLAR JUNCTION TRANSISTORS.ties of CB Highest ou ha (a): Configuration: Lowest input resistance (R, < 1000) tput resistance (Ry > 1M) Lowest current gain ( <1) Highest voltage gain Medium power gain (typical value 68) Output and input voltages are in phase ie. phase shift is 0. Lo CB amplifier current gain is loss and therefore bandwidth is large and hence CB amplifier is widely used as high frequency. In the de mode the levels of I, and I,, due to the majority carriers are related by a quantity called alpha and defined by the following equation. defined by. Me. Ve DP tansistoe -Note: The transist Common-Emitter transfer + resistance —> tran: fae White [ogo 18 collector to base current when emitter terminal is open. For ac situations where the point of aperation moves’on the characteristic curve, an ac alpha is The alpha is formally called common base amplification factor on current gain of common base tor’s amplifying action i's basically due to its capability of transfer its signal curreit from a low resistance circuit to high resistarice circuit, contracting the two terms transfer and resistor results in the name transistor; i.¢. ‘Configuration: BIPOLAR JUNCTION TRANSISTORSInput Characteristics: + The input characteristics area plot of the input current ([,) versus the input voltage (Vj) for a range of values of output voltage Ve_. Aiwa) 70 60 50 40} 30} 20 10} a 02 04 06 08 ™™ Output Characteristics: ‘©The output characteristics are a plot ofthe output current ({.) versus output voltage (V,,) for a range ‘of values of input current ([,). T(mA) Saturation Region Properties: + Moderate input resistance (around 1k.) © Moderate'output resistance (500 to 500 kQ) * Moderate current gain (typical value 49) * Moderate voltage gain * Highest power gain (typical value 4226) © Output and inpot voltages are out of phase shift = 180°, © [tis most common and frequency used amplifier. Beta (B): «Inde model (B>1) Forac Venue Range of B is 30 to 300. B in terms of « is |B La one BIPOLAR JUNCTION TRANSISTORSB is called the current gain of transistor in CE mode. {t is the most important specification of the transistor. B is also denoted by f, and always. 61, | Ba >B,.] or [Are > ha ekbth=Bltl, [e=O+Dl, E Common Collector Configuration (C-C): [ wove iN + _ + Vea! veda, % v {n-p-n transistor €-C configuration) ‘+ Itis popularly known as “Emitter follower”. + In common collector, collector resistance must be zero and output voltage is taken aoréss the emitter resistance. Properties: ¢ Highest input resistance (50k to 500k) +” Lowest output resistance (<1000) + Highest current gain +. Lowest voltage gain (close to unity and ideally one) + Output and input voltages are in phase ie. phase shif is 0°. + Emitter follower is basically a current controlled voltage source (CVS), Applications: + Asanaudio frequency power amplifier + Asa buffer (impedance matching device between high resistance to low resistance) + Indesigning of voltage sweep circuits + Asan high input resistance devices. + Asa“Boot strap emitter follower”. Gamma (7): Te Hel = 1+ rr B a Saturation region, => Active region, = Cut-off region BIPOLAR. JUNCTION TRANSISTORSNote: Tego? Saturation Region: Minimum I, required to keep the transistor under saturation region. Ie ede] in Vin re Ba} LP ie 8 Voc ier, =0 |/ alee! HO Tog =H, FR, =O [Foam com “RR Re Cut-off Region: Condition for cut-off region is Active Regian: Conditions for transistor under active region [0.2V Ico = (1 + B) Ign, Yoco =(+B)lco} or Toa In transistor if various leakage current are arranged in the sequence in ascending order then co I= BL, =100*0.747 = 7.47 Apply KVL in CE loop Veo =IRe + Vex + Op + IRE BIPOLAR JUNCTION TRANSISTORS ‘EeSoln, ‘V;, means potential of collector point w.r.to ground V,=V-+Voe if Rp =0) V,=Voc-IcRe if R, #0 Voc = TR + Veg + Ug + HyiRy (V, oF Vo) = Vo = Voo~ foe = (0-3 x 747 mA = 10 - 22.41 =-12.41 volt Negative sign indicates that transistor is not in active mode. Calculate value of Vy if Vig =2 volt. Vep = 2V Applying KVL in BB loop 2-Vyy - 50 Iy~ (I, + 1.) 0.5 = 0 V, = 5 +03x5=-54+15 Kh => 50.5 I, + 0.5, = 12 (I) Apply KVL in CE loop 5 = [eRe ~ Veg - 05 (Ip + i.) = 0 = 5.51, +051, = 48 2) Solving equation (1) and (2), we get I, = 0.015 mA; I, = 0.87 mA We have I, =I, = 0.015mA Je _ 087 ASO, Igy = 5 = gg, 7000874 = [In1> Fon ‘Therefore transfer isin saturation mode: Now, Vp + 5=1,Ro => Vj= 087 x5 ~5= 435-5 =-0.65 volt ‘The BIT amplifier of figure below has hi, = 100 Vie = 0.7V, Iny = 0. Calculate the values of Ry and R, such that its [, = ImA and Vgg = 2.5 V. Vcc 5V Re R, 10K; BIPOLAR JUNCTION TRANSISTORS‘Thevenin equivalent of base ground terminal —t E 2 ®) Rye ra) Si 7 WOR, RR Fem OM Rae Tos ORR 5 =——x10: Vouse = R410 Let us consider BIT is in active region by applying KVL around the base-emitter loop, then we get, Va — la Ry ~ Vor~ (lp +1003 = 0. 30 10R, Uae = 1px] |-0.7=1,00x03 f= =—— (v I=, R+10 (Re) oo 4 B Too “fe =Bla) 56 (Reta) 1 1 a x07 = +101) x03 R +10 (e4) 100 in 2500-2, = o7er( Boa awe +10) 2. 500 ~R, = 10R, + 100 IIR, = 400 Applying KVL in collector emitter loop 5=1gRe ~ Veg ~ (I+ 1,)03 = 0 _ 5=25-0,303 1 [Re = 2.194kQ] Q Find out Q-point where, B = 100 HV." 5V R= 2k ke Soln, Step-I: Assuming BIT is in active mode Vip = 0.7V, for Si. ‘Step-Il: Applying KVL in base emitter loop 5 —I,* 100 x 10°~ V,, =0, I, = 4.3 x 10° Step-III: I. I, ="43 * 10° 100 = 4.3ma Ic (active) “BIPGEAR JUNCTION TRANSISTORS| | Soin, Step-IV: Applying KVL in collector emitter loop fot lotion) Vog- 2 * 10 I~ Veg = 0 ce 5-02=2x 101, He eatuation) = 24 mA >I, Step-V= 1 (aie) > Ne (station BIT isin saturation region Q-point [ogrraony = 24 MA, Vog guy =0-2V) Find out Q-point? +Vcc= SV R= 1k y p99 yh Step-I: Assume BYT is in active mode Vj. = 0.7 volt Step-II: Apply KVL in base-emitter loop 35-330 x 10° 1,-0.7 -1 x 10°], 4.3 = 330 x 10° 1, +1 x 10° (I, + 1) 0 4.3 = I, (330 = 10° + 100 x 10°) Ty = 10HA. Step-ITE: Iain 7: Bly * 99 * 10 x 10% = 0.99mA Step-IV: Apply KVL in collector emitter loop for I x10? = ic * 10° Vox ay ~ 1p * 10" = 0 2 = 1.x 10 + (ly + I.) X10? 48 =1, (2 * 10) Togeay = 24 mA Step-V + Teraciv) < Kesaration) BIT is inactive mode StepAVI: Vee = Voom Ip Re + Ry) = 50.99 x 10° (2 x 103) ~ 1.98 = 3.02 Qpoint = erie) = 0.99MA, V, ‘CE (active) ~ 3.02) 2, this is the typically value in saturation mode for Si (fc = Bl, Uc = 9915) saturation) Find the collector voltage V, if B = 100. BIPOLAR JUNCTION TRANSISTORSing the transistor in active mode, KVL for the base circuit gives = 0.02mA, Ip = Bly = 2mA Yo=MO Vey 2 2° ° IL at the collector node yields pining the last two equations, and solving for V, yields [V- =3V| i sumed negligible (in active region). Find the current I,. assume both transition to be in the active mode. Writing KVL for the base circuit of Q, yields. 9, Ley = Taye 51 + Vigea + (10)Igy - 10= 0 7+ 0.7 + (10) I, ~ 10=0 ImA = 1 =], t Veg, = 9 ~ 0.7 = 8.3V Vcxz is positive, Q, is in the active region. Therefore I, is ImA. 'V. Use B = 50 for the transistor. BIPOLAR JUNCTION TRANSISTORSSolnt. Soln, Writing a KVL in the collector base loop yields 5 +Ro(Iy +1) +R, ly +07 =0 1, = Blg (the transistor is in active mode because Vgg = V = 2V) 43 43 43 I~ SIR+R, SIR,+S1 SIR. +1) Now, Vo = 5 Rolle + I) = 5 - (RQ)5I ly Wo= 27 [Re =2.3kQ) Find stability factor * of the given circuit: Where Apply KVL in (C-B) lop: 5+ Rolly + Ip) +R, ly + 0.7 =0 |B (assuming active mode) Rde (Ru}ratenaa 4, 438 4.38 438 Jo” ROepER 3(1+P)+51 53.3+2.38 With B = 50, we obtained s* = 0.008 rp BIPOLAR JUNCTION TRANSISTORSSoln. ) (@ The circuit is called a differential amplifier. Let us assume Q, to be off and Q, in the active mode, based on the voltage given Tay = IMA, Tey = Bley /(1+B) = 0.990 and Voy, = 12 - (5k) (0.99nA) ~ 5 = 2.05V Since Vg, is positive, Q, is in active mode. Assuming Vie, = which means that Vpp, = 2.5 — 4. sv Since Vig, is negative, our assumption of Q, being offs confirmed. As no current flows through Q, WV, V,=5-0.7=43 ¥, Let us assume Q, to be off and Q, in active mode Igy = INA; Ty = 0.990 Vop2 = 12 ~ (Sk) (0.99nA) — 2.5 = 4.55 V which confirmed that Q, is in active mode. V_5 25 - 0.7=1.8V Voge, = 0 - 1.8 =-1.8V Hence Q, is off and finally V, = 12 - (Sk) (0.99 nA) V7, =7.057| BIPOLAR JUNCTION TRANSISTORSAssignment on BJT The common emitter forward current gain of the transistor shown is B, = 100. +10V 1K TKD: 1kQ tov + ¥ ‘The transistor is operated in (@) Saturation region (6) Cutoffregion (©) Reverse active region (@ Forward active region Consider the circuit shown in figure. Ifthe fof the transistor is 30 and I.gq is 20nA and the input voltage is +SY, the transistor would be operated in @) Saturation region (b) Cut off region (©) Active region (@) Break down region ‘The common emitter amplifier shown in the figure is biased using a InA ideal current source. The approximate base current value. Veo= 5V Re = 1k |-§.v,. —— p=100 & dam ¥ @ WA ©) 10.A (©) 100pA (@ 1000mA BIPOLAR JUNCTION. TRANSISTORSTransistor circuit shown uses a silicon transistor with Vig, = 0.7V, Ic = I, and a de current gain of 100. The value of V, is 10K j50k2. i L__ f " - 100kQ| ¥ @ 4.65V & 5Vv (0) 63V @ 72V 5. Calculate the stablization factor for the below circuit, Vex 500KQ en B=100 @ 48 (b) 84 (24 @ NOt. 6. Ifthe transistar shown below is operating at saturation region, then the base current will be +10V Sk Ke. B=100 ¥ (@ 1p=20nA (1, >20HA (Iy=20mA —@) 1, > 20mA. 7. Calculate Vi, inthe circuit shown below @ ov ® IV ()-08V @02V BIPOLAR JUNCTION’ TRANSISTORS10. i. 13. Calculate the current gain (B) in the circuit given below a Vue 1V). rh mA @) 20 (b) 145 ~©@49 @ 30 Input and output resistance respectively are low for which of the following amplifier (a) Common base and common collector (b) Common collector and common base (c). Common base and common emitter (d)Common emitter and common collector Find base voltage V, with respect to ground given ([, = 1.8mA, Vig =-I0V, Veg = 1OV) +Vee — 470 Ver @ 107V (®) 82V ©93V @ NOT. The DC current gain () ofa BIT is 50, assuming that the emitter injection efficiency is 0.995, the base transport factor is (@ 0.980 (®) 0.985 (©) 0.990. 0.995 For the BIT circuit shown, assume that the | of the transistor is very large and Vig, of operation of the BIT is oxo tov w® (@) Cut-off () Saturation (© Nowmalactive _(@) Reverse active The circuit using a BIT with B = 50 and V,,, = 0.7V is shown in the figure. The base current I, and collector voltage V., are respectively. 430k03 a “bE {) Amd 4 (&)40qA and 16 volts (© 45pAand 11V (@)50A and 10V BIPOLAR JUNCTION TRANSISTORSFor an n-p-n transistor connected as shown in figure, Vp, = 0.7V. Given that reverse saturation current of the junction at room temperature 300°K is 10° A, the emitter current is, i RY @ 30mA ) 39 mA + ©49mA @ 20 mA Generally, the gain of a transistor amplifier falls at high ftequencies due to the (a) Internal capacitance of the device ~ (©) Coupling capacitor at the input (©) Skin effect @ Coupling capacitor at the output In the circuit of the figure, assume that the transistor is in the active region. It has a large Band its base emitter voltage is 0.7V. The value of I is 15 10k je * SkQ 4300 ¥ (@) Indeterminate since R,.is not given (1 nA (© 5nd @ 10 nA 17, Assuring Vey.) =0.2 V and B = 50, the mininmura base current (J) required to drive the transistor in the figure to saturation is ke 3V 1k. ¥ (@) SORA ©) 140nA (©) 60HA (@ 3KA 18. If the transistor in the figure is in the saturation region then C He By, denotes the z de current gain E (2) Ig is always equal to By. Ip (©) I, is always equal to -B 4, Ty (©) Sgis greater than or equal to Bg, Ip @ [gis less than or equal to By. BIPOLAR JUNCTION TRANSISTORS19. 20. 7. 2. 23. 25, 26. The early effect in a bipolar junction transistor is caused by (@) fast tum-on (©) fast tum off (©) large collector base reverse bias @) large emitter base forward bias ‘Thermal runway in junction transistor will take place if the quiescent point is such that 1 ® Vee? 3 Vee OVer < Voc 1 © Vee 2 Mee Ver < 5 Vee Early effect in BJT refers to (a) a valince breakdown’ (®) thermal runway (©) base narrowing (@)Zener breakdown Which one of the following statements is correct? in a transistor @) Togo is greater than Tog, and does not depend upon temperature. ©) [cao is greater than Ig, and doubles for every ten degfees rise in temperature © [ego is equal to Tog and double for every ten degrees rise in temperature (@ {cep is equal to Igg and doubles for every ten degrees rise in temperature ‘What is the reverse recovery time for a diode when switched from forward bias V,, to reverse bias Vp? o ‘Time taken to remove the stored minority carriers (b) Time taken by the diode voltage to attain zero value (©) Time to rémove stored minority carriers plus the time to bring the diode voltage to reverse bias @ Time taken by the diode current to reverse ‘The operation of BIT is based upon the flow of current due to which one of the following? (@) Donor and acceptor ions (b) Electrons only (© Holes only @Both electrons and holes Consider the following statements: specific features of BIT are 1. Very small on-state resistance 2. Presence of second breakdown 3. Infinite input resistance 4: Good performance in parallel operation Which of these statements are correct? @ 1,2, 3nd 4 ( 1,3 and 3 (3 and 4 (@) 1 and 2 ‘The breakdown voltage of a transistor with its base open is BV..g and that with emitter open is BV gga then @ BVce9 = BYcuo BV eu0 > BV cao © BVcr9 < BY ego. @BV cpg 18 not related to BVcgq ANSWER KEY L @ 2 © 2 © 4 @ 5.) & 1 @ & O . % @ 10. (@) il.) 12. (b) 13. () 4. © 15. (@), 16. (a) 1. @ 1B. @) 1%. © 20. @) 1. © 2. ©) 2B. @ 4. @ 8. @) 26. ©) BIPOLAR JUNCTION TRANSISTORSCHAPTER - 4: FIELD EFFECT TRANSISTORS (FET) ‘+ Itis voltage controlled device, + Itisa unipolar device. «_Itis a majority carrier device, + Leakage current almost ~ 0 since no minority carrier. + Excellent thermal stability since no minority carrier. © Lessnoise, © FET canbe designed without salt bias circuit. « Itis fabricated with Si only. «> Offset voltages afe zero, High input resistance device (2 MQ) © Large BAW, Device + GAIN B.W. product almost constant © Smaller in size than BUT. Disadvantages of FET: (1) Smaller gain (2) Smaller gain band width product. Construction: Three terminals are present and one channe! is also present. GATE, DRAIN and SOURCE are three terminals channel! may be n-channel or p-channel. Drain (0) brain (D) v P Gate) : 0 Tsource Tsource (S) wechanael JFET P-channel FET i Classification of FET: : FET JET MOSFET (3 Terminal device) (3 Terminal device) $,D,6 $)D,G+ Lsubstate I R10 10'9) R, (10° 10°9) MOSFET ID G. is ’ (echannel JEET symbol) Depletion Enhancement orDEMOSFET or E only MOSFET ‘N-channel P-Channel DEMOSFET —DEMOSFET ‘Wechannel EMOSFET —_E-MOSFET FIELD EFFECT TRANSISTORS (FET)Problems of FET: 1. Inthe given circuit of figure if V.,, ~ 0.4V, the transistor M, is operating in Vv M, (@) Linear region _ (b) Saturation region © M, sor (@ Cannot be determined Soln. For P-channel MOSFET Vepisay = Vga + Vay = (1 - 0) - 0.4 = 0.6 Vgp = Vg~ Vp = (1 = 0:3) = 0.7, Here Vey > Vp gay So, M, is in saturation region, Correct option is (b) 2, Inthe following circuit of figure, the region of operation of M, 1 ad | (@) Linear (b) Saturation © M, is Of (@) Cannot be determined Soln. ° In the circuit, Vos = Vg~ Vg 15-05 = 1V, Vos = Vy~ Ve = 0.5 - 0.5 = OV ‘DS (sat) Vos ~ Nan = 1-04 Vv here, Vos < Vosisat) and Vos a Van So, M, is in linear (triode) region. Correct option is (a). N-Channel JPET: It is unbiased JFET, channel ctoss sectional area is maximum and channel current density is rininromn, JEET Baising: re DI r P FIELD. EFFECT TRANSISTORS (FET)In an-channel JFET depletion layer is more penetrated into the channel near drain for n-channel IFET. Gate voitage is (-) ve. ‘Transfer Characteristic: Tove, oan Toes los Ves Vos anchannel JFET + Minimuoa gate to source voltage Ve, required to cut off the chanael is called as V,, eff Drain Characteristic: Pinch off Voltage: Parameters of JFET: 1. Gate to source voltage, I, afi 2; ‘Transconductance {g.,}, 1 tl 2 AV, 3. Amplification factor (11), = yp | os Toco’ [= Bim ™Pa range of pt = 2.5 to 150 AY, 4, Drain resistance (ra) = Sl Vescont’ typical value = 500 kQ. . c FIELD EFFECT- TRANSISTORS (FET)Q Soin, 5 It In the circuit of shown below the transistor parameter are as follow: Vip = -2V, Kp = Ima/V? rey aa 0.5K 22KQ 2k Tov @ The value of Veg is () ~3.77V () 3.77V ()-71V R, = 8KQ, R, = 22kQ, Ry = 0.5kQ, Ry = 2kQ. / at Ry | 29-1y= 525 500-10 =461V 2 RAR, (8+22) Assume transistor in saturation 10-V, I= Kp(Voo + Vin) Vo= Vg + Vso, 10 ~ (4.67 + Veg) = (0.5) (1) (Vg) = Vgg = 3:77V, “LTV, ‘Vg positive voltage. Correct option is (b) The value of is (@) 3.12 mA (&) 18.2 mA (7.12 mA 10-V, _10-(VG+V¥ os) (4.6743.77) _ DR Reo gg tama Correet option is (a) The value of Vz, is (@) 155V () 2.2V (© 122v 10=I,(R, + Ry) + Vey 10 Vep = 20 ~ Ip(Ry + R,) = 20 - 2:12 (2 + 0.5) = 12.2 V Correct option is (e) ‘The following reading were obtained experimentally fiom a JFET: vGS ov ov vGs N sv D mA 10.25mA oun @142ma * @535V 0.2V sv 9.65mA, __ Determine (i) a.c. drain resistance (ii) transconductance and (ii) amplification factor. FIELD EFFECT TRANSISTORS (FET)Soin. () With Vq, constantly at OV, the increase in V,,, from 7V to 1SV increases the drain current from 10mA to 10.25 mA i. Change in drain-source voltage, A Vp, = 15 ~ 7 = 8V. Change in drain current, AI, = 10.25 — 10 = 0.25mA, Al ay . ¢, drain resistance r= 27" 9 5ma 32K G@_ With V,,. constant at 15V, drain current changes from 10.25mA to 9.65mA as V.,. is changed from 0V to -0.2V. AV, = 0.2 - 0 = 0.2V, AL, = 10.25 - 9,65 = 0.6mA, ©. Transconductance, g,, = = 3mA/V = 3000 umho (i) Amplification factor: w= g,, xr = (32 x 10°) x (3000 x 10:5) = 96 JET Biasing: For the proper operation of n-channel JFET, gate must be negative w.ct. source. This can be achieved either by inserting a battery in the gate circuit or by a circuit known as biasing circuit. The latter method is preferred because batteries are cost by and required frequent replacement. (® Self bias: Fig. (A) shows the selfbias method. The resistor Rg is the bias resister. The d.e. component of drain current flowing through R, produces the desired bias voltage. The capacitor C, by passes the a.c. component of the drain current. V9 R,, fT, Signal Re Ve Ven Voltage across R,, [V; =1, Rs ‘Since gate current is negligibly small, the gate terminals is at d.c. ground ie. V, = 0 Vas =Vg~ Vs = 0 Ip Rg Ves =~p Rs Operating Point: The operating point (1e. zero signal [,, and V,,.) can be easily determined. Since the parameters of the JFET are usually known, zero signal I, can be calculated from the following relation, « Also Vg = Vp — Iy(Rp + Rs) ‘Thus d.c. conditions of JFET amplifier are fully specified. (ii) Voltage Divider Method; Fig. (b) shows potential divider method of biasing a JFET. This circuit is identical to that used of a transistor. The transistor R, and R, for ma voltage divider across dain supply Vig. The voltage V, across R, provides the necessary bias. Vp * Ry Ye eR, a ost oR Vos =V,— 1 Ry FIELD EFFECT TRANSISTORS: (FET)‘The citeuit is so designed that I, R, is larger than V, so that Vi. is negative. This provides correct ‘bias voltage, We can flit the operating point as under: f= 7B aiid Vpg = Vp In(Ry +R) . ‘Modes of Operation: ‘ 2. 3. Common source connection ‘Common drain connection ‘Common gate connection ‘Common Source Connection: The common source connection is most widely used arrangement. It is Soin, because this connection provides high input impedance, good volage gain and a moderate output impedance. However, the cit produces a phase reversal ie. ouput sigal is 180° out of phase wih Ina self bias n-channel JEET, the operation point is to be set at 1 = L.SmA and Vy, = 10V. The JEET parameters ate fnsg = SmA and V, =~2V. Find the values of R, and R,,. Given that Vig = 20v. Figure shown above, jy y re? (2 auses(iotg ] tee VI373 =0.55 or Vz, = -0.9V Now, V, ~Vs 8-09) =9V 2 R= 7 “Td FIELD EFFECT TRANSISTORS (FET)Applying Kirchoff’s voltage law to the drain citcuit, we have", Von = Ip Ry + Vo + Ip Ry 20 = 1.SmA x R, + 10 £09 (20-10-09) - = ——=6 7 Re 1.SmA aot) ‘Voltage Gain of SFET Amplifier: Fig. (c) shows a typical circuit of'¢ JFET amplifier. The JFET is a self Soln. biased by using the biasing network R, C,. The d.c. component of the drain current flowing through the source biasing resistance R, produces the derived bias voltage, the capacitor C, by pass the a.c. ‘component of drain current. It may be noted that biasing circuit is similar to the cathode bias for a ‘vacuum tube. The value of R, can be determined from the following relation. ¥, ‘as I. FR, an Signal | V5 ‘Where Vs = Voltage drop across R, and I, = current through R, like-a vacutim tube, a JFET is a voltage driven device, Therefore, the volage gain ofa JFET amplifier canbe determined inthe sane manner as for a vacuunt tube. BR, mt, Voltage gain of IFET amplifier is Ay = / TB h | 1) %8q o-\Ay = Since H=%* Bq, “a Pe Ifr,> R, then the latter can be neglected as compared to the farmer. re 0R, : Voltage gain, Ay= “or [4 = g, ‘The transconductance of a JFET used in a voltage arnplifier circuit is 3000 jxmho and load resistance is 10k, Calculate the voltage amplification of the circuit assuming that.7, >> R, 8q, = 3000 jmho, R, = 10kQ, AS 7,>>R, +. Ay = 8 Ry = 3000 10° x 10,000 = 30. Inthe JFET ‘circuit shown in figure, Find (i) Vp, and Vc.Soin.) Vag Vpn ~ Ip(Ry + R,) = 30 = 2.5mA (5 + 0.2) = 30 ~ 13 = 17V HIp Ry =~(2.5 « 10°) * 200 = 0.5 volt. @ V, SEFET Application: ‘The high input impedance and low output impedance and low noise level make JFET @ @, Gi) for superior to the BJT. Some of the circuit applications of JFET are. . As a Buffer Amplifier: & buffer amplifier i a stage of amplification that isolates the preceding stage from the following stage. Because of the high input impedance and low output impedance a JFET can act as an excellent buffer amplifier. Buffer |. [ Second lst Stage} aris ‘Sage P— High Z, Low 2. Phase Shift Oscillators: The high input impedance of JFET is especially valuable in phase shift oscillators to minimize the loading effect. Shows the phase shift oscillators using n-channel JFET. Rg Cy As RF Amplifier: In communication electronics; we have to use JFET RF amplifier in a R, instead of BIT amplifier far the following reasons. (@) The noise level of JFET is very low. (b) The antenna of thé Receiver receives a very weak signal that has an extremely tow amount of current. Since JFET is voltage controlled device. It will well respond to low current signally provides by the antenna, MOSFET: It is an integrated circuit Si chip. itis fabricated by VLSI by using planner technology. Pa fat Diffosed N channel SiO, Layer Potype substrate The entire area of MOSFET is less than $% of total area Of BIT. MOSFET are less noisy as compared to JFET. INMOSFET minority carrier storage time is zero, MOSFET are suitable for high free application. In depletion MOSFET. There is a pre-existing channel and the channel is diffused channel. FIELD EFFECT TRANSISTORS (FET) ETTInversion of charge To operate N-MOS under depletion mode gate is negatively biased with reference to source. For N-MOS Vp, is positive. ' When Vig..g? No charges available on aluminium plate. So, inversion charge will be zero. Maximum drain the diffused n-channel and due to recombination less €~ will be reaching the drain I,, decreasing. current is present is Ty... When Vicg applied: The gate provided with negative volage and therefore positive charges are created over Drain Characteristics: ‘Transfer Characteristi Tp (mA) Ves const Ip VIS. Vg / Vps constant Vos Veq Cutoff Homojunction: A homojunction is a semiconductor interface that occurs between layers of similar semiconductor ‘material, there materials have equal band gaps but typically have different doping. In most practical case.a homojunction occurs at the interface between on n-type (do nor doped) and p-type (acceptor doped) semiconductor such as Si this is called pn junction. This does not have to be the are through, the only requirement is that the same semiconductor (same band gap) is found on both sides of the junction, in contrast to be a heterojunction. Heterojunction: A heterojunction is the interface that occurs between two layers or regions of dissimilar crystalline semiconductors. There semiconductors materials have unequal band gaps as opposed to a homojunction. It is often advantageous to engineer the electronic energy bands in many solid state device applications including semiconductor lasers, solar cells and transistors to name a few. The FIELD EFFECT : TRANSISTORS (FET)| | combination of multiple heterojunctions together in a device is calle a heterostructure although the ‘wo terms are commonly used interchangeably. The requirement that each material be a semiconductor with unequal gaps is some what loose especially on smal length scales where electronic properties depends on spatial properties. A more modern definition may be to say that a heterojunction is the interface between any two solid state materials including crystalline and amorphous structure of «metalic, insulating, fast ion conductor and semiconductor material. Linked Questions Q In the circuit of shown below the transistor parameter are as follows. + Vip = 2, K, ploy 842: 0.5K 22k 240. ov Q The value of V,,, is (@ -3.77V () 3.71V (@-L71V @ 17 Sol, R,= 8k, R, = 22k, R, = 0.5kN, Ry = 2kQ. i -(% - 4) ~10)= Vo= (geo = (3 (20-10) = 4.67V 10-V, RK Moo Ml, Ve # Vo + Veg b j 10 - (4.67 V¥g.)= ©) (Y) Weg) = Vgq = 3.77V, -1.77V, Vag is positive voltage Correct option is (b) \ Q The value of fy is (@) 3.12 mA () 182 mA (O7I2mA — @ M2 mA h 10~V, 10-7 +Vgs) _10-(4.6743.7) 1, =1O=M 10 We *Yes) «10-4.6743.77) _ 5 19, i Son, lo Ry 05 mA Correct option is (a) Q The value of Vg, is | @ 1s.sv () 22V _ © 122 @55v Soin. 101, (Ry + Ry) + Vey - 10 Vop* 20 ~ 1,(R + Ry) = 20 - 2.122 + 0.5) = 12.2V Correct option is (¢) FIELD SGEFECT (TRANSISTORS (FET)CHAPTER — ZENER DIODE AND OPTO’ELECTRONICS ner Diode: Diodes which are designed with adequate power dissipation to operate in breakdown tegion may be employed voltage reference ot constant voltage devices. Such diodes aré known as avalanche, breakdown or zener diode. Symbol e——>f-o VAI characteristic V, —> Zener voltage of break down voltage, V, -> Cut in voltage, I, -» Zener current Zener diode is reversed biased heavily doped Si or Ge P-N junction diode which is operated in breakdown region Si is preferred to Ge due to it’s high temperature and current carrying capability. Forward bias V-I characteristic of zener diode is same as ordinary diode. When reverse biased voltage applied to zener diode, on increasing the reverse voltage, z2ner current is increased greatly from it’s normal cut off value. This voltage is V, or break down voltage. There are two mechanism of zener break down. (@ Zener break down / tunneling ({i) Avalanche multiplication, @ Zener break down / tunneling: When reverse bias is applied a very strong electric field is set up across the depletion layer and is enough to break or rupture the covalent bonds, Due to rupture of covalent bond Jarge number of electron bole pairs are produced which constituted the reverse saturation current! It occurs in heavily doped p-n junction diode, (i) Avalanche break down: It occurs in case of lightly doped p-n junction diode. Here minority carriers accelerated by field applied, they collide with semiconductor atoms in the depletion region. ‘Due to collision with valance electrons covalent bonds are broken and electron hole pairs are generated: These new carriers so produced acquire energy from applied potential and tun produce additional carriers. This forms cumulative process called as avalanche muttiptication. ‘Temperature Characteristic of Zener Diode: If reference voltage is above 6 volt (where physical mechanism involved is avalanche multiplication) temperature coefficient is positive. But below 6 volt where zaner breakdown isinvotved and temperature coeflicient is negative, Explanation of Above Mechanism: UR de 4 vo A) RY OL t F ‘The source V and resistor R are selected in such a manner that diode is operating in breakdown tegion. Voltage across R, is V,, and diode current is 1,. It have two type of regulation. i I ‘ ZENER DIODE\ANDYOPTO: ELECTRONICS@ Line Regulation: = Vary, R, = constant, V, = constant ¥ TITY, T (lightly) 1, T (highly) Vi= Venue Tas? Ts mae almost constant Vy= IR, = constant Load Regulation: R, Vary, V,= constant, V, = constant : V; = constant, I = constant RTH TY, T (lightly) 7, (highly) 1, 4 Re Renae Ie = ema A he win ». Vp =1, R, = almost constant. ‘We have to take care of I, other wise zener diode will burst. Q. —_ Forthe givextcircuit what is the value of R, so that voltage across R, is maintained at 12 volt. Ifload current variation |, is from 0 —200 mA, In this case also determine the value of P, max. wove, 1 1 Ry. ¥ ¥ Soln, Tp = Leis + par» I= 0 + 200 = 200mA, 16-12 16-V,= 102. eBs => Rs Zoos |, Varies ftom 0 to 200mA. S0, (I pas, = 4g ~ Ein = 200 ~ 0 = 200mA, ac = Ve pan = 127% 200 mA, = 2.4 watt A zener-diode exhibits a constant voltage of 5.6 Volt for currents greater than 5 times the knee current. L,, is specified to be ImA. The zener is to be used in design of a sheet regulator fed from a 15 volt supply. The load current varies over the range of (0 ~ 15) mA. Find a suitable value of resistor R. What is the maximum power dissipation of zenet diode. Soln. Given, V, = 5.6 volt, V; = 15 volt, Ty = (0~ 15)mA, I, = SmA @ Ty = OD max * Gopin = 15 + 5 = 20mA Isv 5.6 BR i) maximum power dissipation 1, = 20mA, P= V, I, = 5.6 x 20mA = 112m watt ZENER DIODE AND-OPTO ELECTRONICSQ Design a voltage regulator that will maintain an output voltage of 20V across a 1k@ load with an input that will vary between 30V and S0v, Determine value of Ry and maximum current I, 20 Sola, I, = Fj =20mA ydaax = Dane + 20MA, Cydia = Uy aig) + 20mA = 20mA Won = Grain, Bs * Ye 10 20x10 30 = 20 x Ry + 20; Ry = 50+20 Cayax = pg 7 0m = le # Le, $0, Joy = 60 ~ 20 = 40 mA. Q. For zener diode shown in figure the (V,) at knee is 7 volt, the knee current is negligible and zener diode dynamic resistance is 10Q.. Ifthe input voltage V, range is from (10 to 16 volt) then what is the range of output Voltage? R ? Soln, vf ve Af zener dynamic resistance is considered 2000 10-7_ 3 1x3. s=s Amp, = 74 =7.14v0lt nia “279 319 AMP Wo)nin 210 7 16=7 9x10 Sax = “9 2 Woman 7* pq > Vodaiax = 7-43 volt Use of Zener diode as a Shunt Regulator: Zener diode is used in designed of shunt regulator so named because the regulator circuit appears in parallel circuit with load, ZENER’ DIODE AND ‘OPTOELECTRONICSSteps for Solving Problems: (Check the states of zener diode (ON or OFF) by removing in from the network and calculating the voltage across the resulting open citcuit yee 0= RR,’ ON -> V, V,> Vy (i Substitute the appropriate equivalent circuit and solved for the derived unknown. ‘Tunneling: In case of tunneling number of electron in valance band in p-type will be (increases) and due to that value of current will (increase). So, breakdown is achieved at smaller value of V,. Type I: Far fixed V, and R, > - Lok Q FR, = 1.2k For the given circuit calculate @ Vo () Vay OL @P, Soln. Check the status of zener diode (ON or OFF) Cc ‘ Step-I: “7 rR vy, Let there is no diode in the circuit poe os “1241 22 16 = —2x12=8.23V Mo" 23 VR Yo" RR, diode will be OFF. =8.3 ie Vy %4|=> Zener diode can not inter into breakdown region, Thus circuit across diode will be open. Step-II: The equivalent, circuit will be same as above drawn =>|[P=0| 73V and V, = 16 ~ 8.73 = 7.27 volt. a I 3.0K ve aw veiw @% OE oP, OV, ZENER DI@DE“AND °OPTO. ELECTRONICS[ ¢ 3.0k. 6x3 4 Zener diode will go in breakdown region and output will remain LOV not 12V. 107] Step-II: Draw equivalent circuit =12Volt, But V, = 10V < 12V tk bP wv Applying KCL at point P h=hth 110. 1 4627, 8 8 7710=26.7mWV, V, = 16 ~ 10 = 6V Type-I: Calculating of range of V{Vijgayy atid Vigil a8Suming R, and R ate fixed, LR Theory: v, Given diode’is on; 1(0 > p,q) because it is not fixed. Since diode is ON. So, V, will be fixed. Given R,, is fixed. So 1, will be fixed. . V,=Vq+Vz, here Vz —> fixed, L, -> fixed only variables are V, and so I, also & (Vp )max = Gena = (dae GR * (Vda = Vp Ltt, = [Wes “Tew FTIR +V | (Pan =( Dn ERY, ZENER: DIODE‘AND*@PTO. ELECTRONICS:Soln. Calculate range of V, for which zener diode is in ON state. 200 oe vy eet 50 _ 230 tO eS _ _. 50-50 adain = Fenin * L= O+ = FF MA». VPage = [gdnne * RI *Y, : 22 .0220420=3687V 50 nin = (Cdnin * RI + V, = 5 *0-224+20=23.67 volts If diode current varies from SmA to 40mA and load current is 25mA. What are the limits between. for which V, may vary without loss of regulation in circuit. Since diode is ON; V, = V, oF (Ip)max = Canax + hy = 40 + 25 = 65 mA Again = Cain +1, = 5 + 25 = 30 mA & Wdnax = Veda * Vz = UpdmaeR + Vz = (65 * 3.75) + 50 = 293.75V &. Dein = Vedmin + Vz = Upmin * R + Vz = 30 * 3.75 + 50 = 162.50V o. Range of V, = 162.50V < V, < 293.75V. ‘Type-III: Calculation of range of R, assuming V, and R, ate fixed ‘Theory: ZENER DIODE ‘AND. OPTO ELECTRONICShere V, and R,, are fixed, V, = V, is fixed. 1, ~ [0 t0 Dyas] 1 Vj=IRR+V, Cmax = Oydnax * 4, Cain = Cain + I, iy wv sy SK a Soln, Given, V, = 5V, V; = 20V, I,,, = 9mA, feel jeeeuloue Bad Te U9 1SKQ Range of R: 15KQ tag 7 aka) Q Calculate regulated output voltage for given circuit. Veaov, 7 x $8200 12KO wit 8.2KQ ¥ Soln. 24.6 Volt. Q. Calculate output voltage and zener diode current in regulator circuit. V, (SV) Vv, (Regulated (espinado ed ae ZENER DIODE AND-OPTO ELECTRONICS@ Soln. V,, = 7.6V, I, = 3.66.mA IC Voltage Regulators: Positive Voltage Regulators in 7800 series. (Output Voltage) 17805 +5V 2. 7806 46 3. 7808 +8V 4, 7810 lov 5. 7812 Rv 6 7815 Isv 7," 7818 18v 8 1724 mv Negative Voltage Regulation in 7900 Series: 1. 7905 SY 2, 7906 ~v 3.7908 Vv 4. 7909 Nv 5. - 7912 -12v- 6 7915 -1sv 7 78 ~18V ZENER :DIODE_AND:OPTO ELECTRONICSCHAPTER - 6: OPERATIONAL AMPLIFIER symbol: (""! FP S—ouput E Input2—s. (#) Non-inverting terminal, (-) Inverting terminal Input impedance : Few mega Q (Very high), Output impedance : Less than 1000 (Very low) Differential and Common Mode OperationtOne of the more important features ofa differential circuit + ov, dt fe where the scale factor is -RC. v, Integrator: (= «Input bias current : #——* 2 @ Input offset current: I), = [I,"|- hy] @) Input offiet voltage : V,, = V; -V, a Note: Due to mismatching between V, and V, output voltage may be positive or negative so we apply offset voltage (V,.) Slew Rate: Another parameter reflecting the op-amp's ability to handling varying signal is slew rate, defined as slew rate = maximum rate at which amplifier output can change in volts per micro second. ah ISR. / 1s} with tin ps. Q — Caleulate the slew rate of given circuit. 240KQ yyy [| > (0.02V, « = 300 * 10") OPERATIONAL AMPLIFIER,Soln, Fora gain of magnitude 4,, =| @ @) @ @ _|R,|_ 240K R| 10KQ K = Ag, V,= 240.2V) => 0.48V < SR _0.5v/us K 048 =24. The output voltage provides. 1.1x10Srad/sec Voltage Buffer: A voltage buffer circuit provides a means of isolation on input signal from a load by using a stage having unity gain with no phase or polarity inversion. toy, eT, Vv; 5 Controlled Sources: Op-amp can be used to form various types of controlled sources. An input voltage can be used to control on output voltage or current of an input current can be used to control on ‘output voltage or current—There type of connections ate suitable far use in various instrument system. (Cirouit) It has four types: Voltage Controlled Voltage Source 2) Voltage Controlled Current Source Current Controlled Current Source (4) Current Controlled Voltage Source Voltage Controlled Voltage Source: An ideal form ofa voltage source whose output V, is controlled by on input voltage V, is shown in figure. The output voltage is seen to be independent on the inpt voltage, Ths ype of circuit can be bul using an op-amp as shown in figure. Inverting op-amp: Now KCL at point A Nov-inverting op-amp: + By virtual ground condition V, Now KCL at point A O-¥, Vi, OPERATIONAL AMPLIFIER@ Voltage Controlled Current Source: An idea! form of circuit providing an output current controlled by an input voltage is that of figure. The output current is dependent on the input voltage. Practica Circuit: ves =i Loy, @) Current Controlled Voltage Source: An ideat form of a voltage source controlled by a input current is shown in figure. The output voltage is dependent on the input current Practical Circuit T in ? te aR) {Current Controlled Current Source: An ideal form of a circuit providitig on output curent dependent on an input current is shown in figuee. In this type of circuit on output current is provided dependent on tlie input current. Practical Circuit: gatsB-[ieB) aa, resistor and capacitor asin figure shown has a practical slope of ~ Bp toed wns re Gaeta eal sara pe) Ths ge in below the cutoff frequency is constant at at a cut off frequency ofa RoC. Mope od. 2nkG| —20 98 R vv (a erasing hE ~S Re + wa a 5 fn Ni FO) voltage i toeaaeaa tamer Second Order Filter: Connecting two sections of fier as in given figure result ina second order low pass filter with cut off at 40 48 decade closer to the ideal characteristic. fon * Srey OPERATIONAL AMPLIFIER.R R VW Ay <20 dBidecade | \\40 aBidecade vo mv ! te, oF aA High-Pass Active Filter: First and second order high-pass active filter can be built as shown in figure. I The amplifier cut of equcicy's [= 5-9] witha sécond order fiterR, =R, and C,™=C result isthe same cut off frequency asin figure. R, R ¥ R eo G oto La, ac [aap Veo fopa R, re ¥ ¥ Band Pass Filter: Figure shows a band pas filter using two stages. The 1* a high pass fiter and the second a low pass filter, The combined operation being the desired band pass response. OPERATIONAL AMPLIFIERInstrument Amplifier: Soin: R R ~ >, ki R BR, Calculation of output voltage: Roy K=2U-h) - z 4 () Vi-K=IR ~Q ¥,-Vy= ik! ~Q) V-V, WieVy= UR sV-V, Tse oe 2R" ai nr GEER) foo (2E YB). ‘An Active filter shown in figure. The DC gain and 34B out off Sequency are nearly rt R, = 15.9KQ, R, = 159KQ, C = InF (@) 40d, 3.14KHz () 40dB, IKHz (©) 20dB, 628KHz (d) 20dB, IKHz R/O+RG 8) ~ Ry x RI+R,CS) Lov, =2 =10 = 2010g,,10 = 204B {log,,10=1} Fos] 1. 1 at | TR Goy V2 On putting the value of R,, C, and comparing LHS. end RLS. @ = 1KHz, At 34B frequency QPERATIONAL AMPLIFIER120) Q. _ Inthe given op-amp find, the value of output voltage. Given V, Boy = 2 * 105, Veg = SV. Inverting terminal Ve 5 vy 7 ab ‘Non-inverting terminal Soln: Let Ag, is open loop voltage gain. In this care V, = (V,—V,)Ag, => Vo = (4.2), x 2 * 10x 10% => 4 x 10 =0.4V [V,q, > output will vary between + V,., and -V,2] IfV, = -2HV, V, = 448V Vo = (4 #2) % 2 105 106 = 12 x 104 = 12 For Ideal Op-amp (Open Loop): Input and output voltage characteristic of open loop Op-amp. It is clear that open loop op-amp is able to amplify signals of very small amplitude. So, practically, open loop Op-amp is not used. For Ideal Op-Amp (Open loop): ( R,= &, (ii) Agy = ©, (ii) Ry = 0, (iv) Slew rate = 0 (¥) CMRR = &. (vi) Band width = 0 ve Ideal Op-amp Ay, = 00 psy > My= Ag, Vidi Vy Va Concept of Virtual Ground: © hf. Lov, 5 Me ‘A, > idealcase) vied In ideal case, I, = 1, =0 OPERATIONAL AMPLIFIER. casiSoln. Inthe given op-amp circuit, Find the output voltage. 400K 40K. V.=01V Lev, Cunent FeotK isze0 The given op-amp is inverting amplifier. By the inverting amplifier gain formula As A777 R Given, R,= 400K, R= 40K, Vj = O.1V. =V, 400 012-7 40 % a alt For the given op-amp circuit. Find voltage gain { 7, ) 450K “Brox. 100K ¥,-0_0-V ~100 a te Oy 4y, 10 450 450 ~ ‘ 9 ‘Now KCL at point B. v . 4507100" 700” (Now by equation ()'V = -45 V) th, 4.50, -457,-V, 450° 100 100 Ky ASV, ASV, 45V, Me ag wclon ole On solving = 759 “aso “100 * 100% 20 9 In the given figure of OP-amp. Find the value of resistance R. RVs 100K QPERATIONAL AMPLIFIER-> ESER T E S TE eTT REINTIO Ga) Soln. By virtual ground condition V,=V,=0 KCLat point A V-0_0-¥, ¥, 100K R 100K R -RY, y,22hK oe 00K ~@ Now KCL at point B hah, oi) 100K "100K % . ye (Given) w (A) By equation (i), (ii) and (A), R= 450KQ Q Inthe given circuit of op-amp, Find I, and I, 10K. Vin1V Weenie Soln, This is inverting amplifier 77° = | |=—| V,=-l0v = For current 1, 0-(-10)=1,x25KQ 10 ahaa 0.4mA — For current I, = 0-(-10)=100K x1 = I= 0.1mA = = 1+1,= 0440.1 = 05 mA Q Based on Non-inverting amplifier. 20K. . From the above given op-amp. Find I, and 1, Sola, By VGP, V, = V, = IV. KCL at point A, = 2h=vV 5 0° OPERATIONAL ‘AMPLIFIER1-5 I,= Ima = 5 = Ima, I= 55 =0.2mA, l)=1 (1 + 0.2) =+(1.2)mA So, the current direction of | and J, will be reverse. Q __ Inthe given figure of op-amp. Find the value of I, and 1, ? Soln, This is non-inverting amplifier. V, = V, = SV by VGP. ‘Now, KCL at point A, 25. 025 _5-Vo 5 y, = 257, 1,=22=5md, T= iK 4K 5K [y= 1-1, =-5-5=—0mA Voltage Follower: Means a unity gain non-inverting op-amp. Open circuit >Loy,-v, e (b) R,=0,R20 —~ ©-R,=0, any value of R, For which value of Rand R, it makes voltage follower. Re ‘ores Voltage Follower: { R= Verylow ‘This resistance range is used for impedance matching or used as buffer Difference Amplifier: In the above given op-amp figure. Find the value of output voltage ia term of V, and V,. _ OPERATIONAL AMPLIFIERFE [Som By the VGP condition V, = V, = V. f V-V_V-%, i For the upper loop, = = z a) ' t Wo-v_ Vv F For the lower loop, . ze i) on (A) +R) By Ry Sha ReRy OR” Now, when V, be at ground, then, ne V,sV, = Voy +¥on Total |" Re | Q Inthe given op-amp circuit. Find the output voltage V,? 33K os RK YY, R= 66K. Soln. V, = 3(4 ~ 2), V, = 6 volt Hence, So, thon RG) a8 aR Me) R, A OPERATIONAL AMPLIFIER.Q. __ Inthe given op-amp circuit, Find the value of V,. R= Sohn. Ft conierng fst iverting op, Vo == FEV => we 2220 4x90 _, 360 Now, considering non-inverting loop V, = s0r10 7 100 wT 100 = Ve (ps 3396 2. ¥,=(39.6+(-207)) = 19.6 Volt Adder: 3B vo— SOW. Vs &, \v=0} Vv, vs & Vv. Soln: By VGP = V,=V,=0 Vv KW _0-% at A424 0h TV 3V, KCL at point A ROR'Ro GR WV, +¥, +4) So, the above op-amp is working as a inverting adders. For the given op-amp circuit, Find the value of output voltage. 2R R R V, a a v——} vs Soin. KCL at point B i=” ,%-¥ Ks or |P=L0,4¥, +m) R R 3 2R ~ (128) aheDLG heh) aCe] So, this is non-inverting adder. OPERATIONAL AMPLIFIERpeo Q Inthe given op-amp figure. Find the output voltage. Loy, Soln. By VGP condition (Virtual Ground Position) (V, = V,) Let V,= V, = V. 4-V Now, KCL at point B, 2-V _3-V 2,3 V0 aw 242 Now, KCL at point A, 5 50? 40°25 74025 43-8 ,B, 13% Now putting the value of Vs 45 a 25 120° 75" 150 50 100K pomt Q tsvo KV tsvo—40k In the above given op-amp circuit, find output voltage. Soln. Vv, = V, = V (By VGP) 18-V KCL at posit = at positive terminal, 20 v7 Otay, KCL at positive terminal, —, 3 = “100K 50 50 ao taet ek oh, =9.V ik Loy, =11v, OPERATIONAL AMPLIFIER. calSoin, For the op-amp (1), this is non-inverting amplifier. 10 v, (ue), =1V, = Op-amp (2) is working like buffer, V,, = MV, -R = Op-amp (3) is working lke inverting amplifier, Y = WWW, = 11K, Because I, =1, = V,-V, = 0 24mA *« a 2A was 4 In the given op-anp circuit find V, and I. By VGP -> V,=V,=2V Now, KCL at point A 01 = 22M gy, =-2gvor, 1, =28 =14md, |) = 14 +04 = LSmA 8 R, ; OPERATIONAL AMPLIFIERQ Inthe given op-amp figure. Find the output voltage 190K 2.5 = 0, Now, KCL at point A, = +—2= Soln. By VGP,-V, = V, o's 10-(-30) _¥,-10 40 _Y%,-10 30 200 "50° 200 Now, KCL at second OP-amplifier sh =1T, Volt Q inthe given Op-amp circuit. Find V,? 300K. voy 10K @) 10K V, ' Vay P ie 10x1 Vi = =05V i =V.= Solu. ¥, =75 797050, By VGP condition, V, = V, = 0.5V 2-05. 05-% fat A, =>: at 5 y, =-2.5¥olt Now, KCL at point A, >To =—S tah In the given Op-amp circuit. Find output voltage, S10KQ_ 680KQ. 22KQ. Vr 7 ¥ cee y,, 20x10-0 _ ¥,-20x10 Soin, We will 1st caluate V,, Tg 510 1Ly 528 : aise HTg <20K10%, V, =5.86x10“Volt => 20x10) 510) 510 80 5 x5,86%10°V , ¥, =~0.081Volt, V, = 0.409 Volt Similarly on solving, V, = OPERATIONAL AMPLIFIERSoln, Soin. Calculate the output voltage for the circuit with input V, * 40m, V, = 20m. 40K. SESS |. V,= Va = 0, Now applying KCL in inverting loop 40, 20_ VO, _~(40x124-20%47)x470 12~ 470° ° 47x12 =eh, = -1183.93mV => V, =-1.183Volt Calculate the output current I, in the given circuit. V.= 10mVo 2062 Me Vi F, Vi TOOK $160 Potential at A and B points are equal by VOP. ie. V, = V_ = 0 Now applying KCL in inverting loop Y=0 0K _y _10x100x107 x10") gy 200 100K 200 $s. 5 Now, fy = 4.5 4.0.00005 = 0.54 10 “100k In the given Op-amp circuit. Find I, and V,? 0415 I Imp, 3K 75M, Lyall, = 7.5mA ‘OPERATIONAL AMPLIFIER.%, Q Inthe given cirouit find voltage gain 5. 2KQ. Soln, ¥, = 61420447 =125; ¥,— Q Inthe given circuit find V,? OPERATIONAL AMPLIFIER.6-0 _0-Y, Soin, V,, = V, = O{VGP}, Now, KCL at point A, rhea 0-%, Verh Now, KCL at point B, a8 Q. _ Inthe circuit calculate the output voltage V,? @ IV, =3V, then V,? Gi IfV, = Sola, (i) When V, = 3V, diode D, will 6n, Now KCL in D, loop a cl Sate 22 ¥,=-9¥olt (i) When V, = -3V, diode D, will o9, Now, KCL in D, loop V-0_0-%_ 3 = Yay, =45V0lt 2 3 23 Q Inthe given circuit calculate 4 Is 10K, Now, KCL at point A. hy hat =0=5(V-V,)+10V—K) + 2V =0 15%, = SV ~5%, +107 -10¥, +2 =0 21 =15h, = V = Now, KCL at point A w-V 15h +(-I;)=0=%,-V-21,=0 = V,-—2= 27, a tha2,» pe OPERATIONAL AMPLIFIER.Q Inthe given circuit find value of I, Soln. By VGP, V, = V, =V. Firstly, KCL in non-inverting terminal Hove, oh Rot ~@ Similarly, KCL in inverting terminal 0-V _V-h, % area = h=W=aV=2 + (ii) Now, putting value of (ji) in equation () DC Characteristic of Op-amp: @ Input bias current (For DC analysis) ii) Input offset vottage Vo ¥ Jy l+1 2 @ Input bias current = Let Ig" Aly |, OY Al LR, de LR, To compensate effect of input bias current R.,,,,i8 used. -- [Rony =, II Ry @ Input offset currents Lag =|p" |-[1y" |, Yo = Ros > output if V; =0, due to input offset current. @) Calculate I,, Given Vo. = 10m, |f,-| = 30004, Ip, ~ 100pA. Find (a) Calculate maximum output voltage due to Vig and I,”. (b) Calculate R comperate. (©) Calculate output voltage if Ris connected. OPERATIONAL AMPLIFIER,Soln. (i) If we are considering input bias current then J,, = 0, as we have already assumed | /,* |=| ,”|- (i IER 8 connected, then input bias curent will not considered, only I, willbe considered. TER sap 8 vis connects then for zero input = zero output. = (1-42) 10 +10.300n4 = 110+3m¥ =113m¥ ©) Rey Bla = OKO R, oh (Erm +Rylos = (1442) stom 0K 0094 |_oy, Rg Soln, toa[ Vat Rta {2 AmV +500K x150nA = 101 x 4+ 75 = 404 + 75 = 479mvolt, Calculation of CMRR Va AVe Q Inthe given circuit. Find the value of CMRR? ve—h- > Fe R Soln, WaQn- VY), Vy=U-Vy) 2 V,=Vi-V= A, =1 Lov, For 4,, V,=V;.=> de=0 -.CMRR OPERATIONAL AMPLIFIER,| Sola. In the op-amp circuit, CMRR = 40dB and A, = 50uB. Find A. ‘Here, CMRR = Common Mode Rejection Ratio ‘A, Difference Mode gain, A, = Common Mode gain CMRR and A, are given in dB. First off all we will change it in normal value. 40dB = 20 log,, CMRR => CMRR = doar =100 = S0dB = 20log,, A, Ay__, 316.27. oer CMRR ~~ 100 2.5. Ay . = A= 10 = 31622 => CMRR = 7° = Ag= Ag = 3.16 ‘What is the maximum value of input voltage given to an voltage follower so, that there is no distortion (Glew rate is given). ¥,=V,,sinot, Slew Rate = Vmocosat , S.R. = Vimo -. For the circuit shown below the value of V, is, 10KQ_ a _19Ka ~ KAY ast 6Ve 4 + . af fees ¥ 4 2 2 4 @aV ® -3V O3V @-4Vv 6x6 2 R ( 40\2 24 e =27, =| |r, =[ 14 |S = @xte4 Vo e163" "* ( Reo} 3 = O43 For the circuit shown below the input resistance is vy Aa r) Pigs no 10K ¥ @ 38KQ ®) 17kKQ © 25KQ @ 47KQ. OPERATIONAL AMPLIFIER.Soin. Soln. Soln, ki, =i, = 24, V, =2ki, +10ki, Since op-amp is ideal, V, =V,,2ki, vy, ar, =2k1s104{; +4)» +10K(, +4) The voltage transfer characteristic of an operation amplifier is shown in figure. What are the values of gain and offset voltage for this op-amp. (@) 10, 1mVv (b) 7500, ~1m\v" ©) 20, 2mV (@) 7500,-2mV V,=A,(V,, + V5), Vos > Offset Voltage, Ay > VoltageGain = 75K a, (2-Om¥ ‘Osiset voltage is Vag =-V,, /V = ‘An inverting operational amplifier shown in figure has an open gain of 1000 and closed loop gain of 4, gain error is > Ley, (@) 04% @& 05% 25% @ 2% Gain ertor is given as ae-4{u4) ‘A, = 1000 (Open-toop gain) Rag 1, = in), Ag =——(1+4) = 0.5% R (Closed loop gain), Ag tooo" t) In the following non-inverting amplifies. The op-amp has an open loop gain of 86dB, gain error is 150KQ i Ll, (@) 0.0125% (&) 0.13% (E)0930% (@) 0.0675% OPERATIONAL AMPLIFIER:Soln, Gain error for non-inverting amplifier is given by set {n8) where 4, +> open loop gain 20log,_ 4, =86(given) 4, =20,000, R, = 1S0KQ, R, = 12KA 1 150 " in error is AB ==——| 1+ |= 6.75x10 =0.0675% So, gain error is 48 pea 2 ) or Ag =0.0675% Q —_Op-Amp of a given figure has open loop gain of 45. What is closed loop gain of an op-amp. 20K=RE Soln. For non-inverting Acy = Differentiator: dW, dt Q. Inthe given differentiator, if V,= sin(2x x 10%). Draw wave form of Vp. Réel SK, OA Loy, OPERATIONAL AMPLIFIERsom. 7 =-cR, Hi a? 0.1x 10° x1.5x10?.cos(2x10"4),20x 107 V, =~3ux 107 cos(2xx 1074) = 0.09 cos(2x 10°) 035) Practical Differentiator: maim |_oy, 5 foe RG UF SAVIFSE.R) a SRG, Q Inthe given practical differentiator circuit. Find output voltage. 1£V, = sin ¢ —-— cane ve Ge es) ye IMO. 7 Ly, + Vo Soin, Ya. ~SRC, 09. S=Joo,S? =~ Vin UFSREY Mas To 1 1 “CES 425) ay , . 1 aa sin(¢—90") => %, =~ 5.0080 2 OPERATIONAL AMPLIFIERVeo Me ad é 20 othee- By KCL at node, N, R +, dt 0 dt RC, Integrating both sides, we get, [a= ae =| i a Practical Integrator Circuit: (Lossy Integration) RE 4 R = vem |v, —t h R comp Ry || R= RR, >> R,) For which we have, 7, ‘4 Fics) OF 1 1) SRC, FRIR, If Ris lage, the lossy integrator application the ideal integrator. A 1 ___ RR i ORC+R IR YiH(oRC,y ‘The break frequency (/'= f,) at which the gain is 0.707 (R, /R,) (of ~ 34B below its value of RR). IIHR GY =A 145} Solving for f = f,, we get OPERATIONAL ‘AMPIAFIER,: Soln, 2 Soln, In the integrator circuit, find the value of output voltage? R= SOKO (C= O15uF Reskal oN V=0rsin 1006 Low, RyIR, -10 -10 Vas T4SR,C, 1+ jx100%50x0.15x10% 140.757 Ves) Vos) = 0-8sin(100r +4), where § = 143.14, V,, = 0.8 For the circuit shown below the output voltage V, is 2.5 V, in response with to input voltage V, = SV. the finite open loop differential gain of the op-amp. Ee @ 5x 10* ) 250.5 (2x 10* @ 501 Vist y _ Aub, 2500417 © S01 If open loop gain is A,, = 999, then closed loop gain is (@ 0.999 & 0.999 (©) 1:001 @ -1.001 Ko Aw 999 19,999 ¥, 144, 14999 ‘The op-amp shown below has a very poor open-loop voltage gain of 45 but is otherwise ideal. The closed-loop gain of amplifier is =9(2.5)(801) = Avge => Ay = 250.5 AV, Vo) = Vor Aya = 999, 100KQ_ 2KQ ¥ ve— @ 20 @ 45 @s ; My he ‘Aclosed | alo Aw closed lop gain Aa =i —%__-45 1+(45)(02) OPERATIONAL AMPLIFIERCHAPTER - 7: DIGITAL ELECTRONICS a Boolean Algebra: LA+A=4, 2At1=1, 3.44024, 4.44 4=1, 5.4.4=6,6.415 4 94= 40.44 AB= A, LLAA4B)= A +B) = AB, 13.4+AB= A+B, 14.44 4B = A+B, 15.A(A+B)= A+B Nate: 4+BC =(A+B)(4+C) Boolean Law: () Commutative Law: 4+B= B+ A,4B= B.A Associative Law: 44(B+C)=(4+B)+C, A(B.C)=(A.B)C @) Distributive Law: 4+B.C=(4+B)(4+C), A(B+C) = AB+ AC (4) Demorgan’s Law: 4B = 4+B,A+B=AB YY ‘The Boolean expression (X +¥)(X +Y)(X +¥) is equivalent to (a) XY AF ee Xr @ Sola: (X47 X +¥)= 47 + HF =o(X + YX + PX +¥)=(X+ YAY + FY) = XV+ XY = XY Q. Given that 4B + 4C+BC = AB+AC, then (4+C\(B+C)(4+B) is equivalent to (@ (4+ BY 4+0) (4+B)A+0) (© (A+B\4+0) (@(A+ BY A440) Soln. Using devality (4+B)(4+C)(B+C)=(4+ BY A+C) 2 Expression 4+ 4B+ ABC+ ABCD+ ABCDE would be similar to @ A+4B+CD+E (&) A+B+CDE (© A+BC+CD+DE VO) A+ B4C+D4E Son, F = 4+4B+ABC+ ABC(D+ DE) = A+AB+ AB(C+C(D+E)) = A+ A(B+B(C+D+E)) = A+B+C+D+E ‘Complement and Dual of Expression:(For calculating dual of a expression multiply is replaced by plus sign, while plus sign is replaced by multiply. After calculating dual primed variable are replaced by aired. Variable while unprimed by primed variables Q Calculate dual complement of given expression ¥(4, B,C) = ABC + ABC Q ¥,(A,B,C)=(4+B+C)(4+B+C), ¥(4,B,C)=(A+B+C(A+B+O0) Minterms: For 7 variables we have 2" minterms. Here each minterm js obtained by from AND operation, of n variables of n variables with each variable being primed if corresponding bit of binding number is zero, unprimed if corresponding bit is 1. Sum of all minterms is always equal to 1. DIGITAL. ELECTRONICSMaxterms: It is nothing but simply complement of minterm and each minterm is complement of maxterm. ‘Maximum term for O11 is Maxternt for number 110 is 4+B+C. SOP + SUM OF PRODUCT, POS — PRODUCT OF St Examples: AA, B,C) = Z, 3, 5, 6, 7) SOP, (A, B, C) = 1(0, 3,75, 6, 7) -e.sce--. POS Q AAB,O= 25,6) Soln. m+, +m, = ABC + ABC + ABC Q RAB, C= 200, 2,4, 7)... SOP = MMMM, = (A+B+C\(A+B+C(A+B+C A+B +0) Deriving sum of product (SOP) expression ftom the truth table Derive a minterm expression for the following table Input Output c B A Y 0 0 0 0 % a 1 1 0 1 0 0 0 1 1 1 V- 0 0 1 I 0 i 0 gobe4 1 1 0 i . q 1 1 0 Y = ABC+ ABC+ABC + ABC Deriving product of sum (POS) expression from a truth table Detive a Maxterm expression for the following truth table Input Oitpat c B A Y pos = 0 0 0 0 0 0 % 1 1 0 1 0 0 0 1 1 1 4 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Y=(A+B+C\A+B+C(A+B+CYA+B+C) KARNAUGH MAP Combination Logic Circuit: It is a method of simplication of boolean alzebra. It can minimize number of gates and number of terms. At the same time it minimizes number of litercals. But at the same time Tesull of K-Map is not unique. Simplification of K-map can be give different results. Maurice kamaugh deviséd a graphical technique to simplify Boolean expression for a two variable realization, This technique can be used for any number of variables. DIGITAL ELECTRONICSParing in K-Map: In case of n-variables K-Map if number ofterms in a pair are 2° then number of terms in simplified expression are (n—m). From the fore going we see that a pair (group of two) reduces 10 one Variable a quad eliminates 2 variables, an octet eliminates 3 variables in case of 4 variables K-map. Methods of Solving Problems by K-Map: ‘Write a winterm Boolean expression from the truth table, 2. Place the 1’s on the appropriate squares of the K-map. 3. Circle the isolated I’s which do not form adjacencies 4, Loop pairs of adjancencies 5. Loop any octet, 6. Loop any quad that contains one or more 1's which have not already been looped. 7. Simplify by dropping terms that contain a variable and its complement within the loop. 8, Orthe remaining terms (one term per loop) and write the simplified minterm Boolean expression. 3-Variable K-Map: A 3 variables expression will be 2° = 8 squares, In this 2 variables will be on one side of the fail and oné below. It can be drawn horizontally or vertically. cQ 1 . ABLCC _4BABABABAB ABOoo}O]1 00 01 11 10 ABo1/2[3 é (of2fel4 aBuif6l7] 1 ¢Ui715 AB 10[4]5 4-Variable K-Map: A four variable Boolean function is (A, B, C, D). Its K-map will be with 16 squares. adQoo o_o wLoyy3]2 HBO? ~ U Vabatoh. oil 4s [7] nah [spa ah 2418 spades 1o[ 8 [9 [arfio /ariable Map 1." Badjacent squares yield a single variable. 2 3. Id a three variab! 4+ Individual ce ell four vale tem. Q I(X,Xq.XyyX,) =2(0,2,3,5,7,8,9,10, 11) + Zde(4,15). A fnetion with don’t care condition is as follows. The minimized expression for this function is, (@) absbd+cd+abe Wabtbdtcd+abd © absbd+bc+abd (@ Above all Soln, ‘The K-map is as shown below: _ 2WDIGUDAL. ELECTRONICSUse of don’t care Conditic Soln. f = AB+CD+ABD+BD If we take Zd instead cd, with @b then, f = AB+CD+BD+ ABC ADC oo of 10 ohio 1) spe] a 4]0stp| 6] ua] 13] 15[ 14] 10 [Gf [ar fab +bd+be+abd Minimize the 4-variable expression using D a Map, 'f(4,B,C, D) = n(4,6,10,12, 13,15). ap 0 or fe ud 18. 10 2 iL 13 3| 7 [os (ory 14 9 11 Bio] (A+B +D)(B+C +D)(A+B +D)(A+B+C+D) ole £(A,B,C,D) =! When the output for input is immaterial whether a 1 or 0, we put on X or in the K-map and call it don’t care condition. Such functions are incompletely Specified functions. ‘Output may be specified for only a combination of input leaving the rest undecided. For instance in four variable input, output may be specified for some say upto m, leaving the rest unspecified either 0 or I such an expression is expressed as Ina certain application four input A, B, C, D are Feb to logic circuit, producing an output which operates a relay, The relay turns on when /(4,B,C,D) = | for the following states of the inputs (ABC D): 0000, 0010, 0101, 0110, 1101 and 1110 states 1000 and 1001 do not occur and far the remaining states the relay is off. The minimized Boolean expression F is @ AcD+BCD+ BCD. () BCD+ BCD+ AcD © 48D+BcD+BCD @ 4BD+ BCD + BCD ‘The K-Map is as follows: ABR 0.01 11 10 oo Fi] 1] 3 [0] olf 4 [fist 7 [fis ui 2] UB [is bs 10 |*8 [x9 |'11] 10 ABD + BCD + BCD S(A,B,C,D) = a(4,5,6,7,8,12) +4(1,2,3,9,11,14) ABK 000111 10 ooo [xt [x3 feo 0 Fast aT| 11 f)-13] 15 fas 10 fo [x9 i [10 DIGITAL ELECTRONICS‘A,B,C,D) =(A+BYC+D+ A) jes: Positive Logic: logic 0 = OV, logic 1 = SV. legative Logic: logic 1 = OV, logic 0 = SV. Logic Logic-Gates: There are the most basic and most important building blocks of any digital system including computers. Three logic gates are AND, OR and NOT gates. These three gates together can be used to construct the logic circuit for any given logic or boolean expression. (Symbot) OR Gates: [Y= 4+] * It isa logic circuit with 2 or more than two inputs and one output. It isa logic chrouit with 2 or more than two in Switching Circuit of OR Gate: Y=A+B (ho light, Voltage sae ‘Truth Table for OR gate: Y=A+B 2 =lel—lela | Q) Negative Logic or Gate: 2) Positive Logic or Gate: eo AND Gate: [F= 4B) 4S——{}—v-A3 {Symbol of AND Gate} Itis a logic circuit having two or more than two input and one output. Switching Cireuit of AND Gate: tL “30 Ameena} Voltage Source suitan-it pada = QR yk Duitehed cigebled = AND yok = AB DIGITAL ELECTRONICS‘Truth Table: =[-yeyofa =le|—lele (1) Positive logic AND gate: s—kk —_q ok it i, Pte Moye OR pe Note: Negative logic OR gate is same as positive logic AND. gate and vice-versa while positive logic OR gate is same as negative logic AND gate and vice-versa, (Symbol NOT Gate) It.is one input and one output logic gate whose output is always the complement of the Input. AlY=A Truth Table: O/T ‘Y=A.B =~ Vt \egic ok ee @) Negative logic AND gate: - Switch Circuit of NOT Gate: ‘ NAND Gate: NAND stands for NOT-AND. An AND gate followed by a NOT circuit makes it a NAND gate. The truth table of a NAND gate is obtained from truth table of an AND gate by complementing the output entries. a oon Ae vA Input Output A B NAND 0 0 1 0 1 1 1 0 1 1 L 0 NAND = Tif out of vipat B Oy un ould A. DIGITAL ELECTRONICSE ‘When both inputs are high ina NAND gate the output is tow. NAND.gate gives zero output only in high input condition. Switching Circuit of Nanp Gate: ‘ ws The NAND gate is called an universal gates as all functions OR, AND; NOT can_be realized from. it “Not: ey AND: s—D=p A a ue Ar D- $e ‘NOR Gate: NOR stands for NOT-OR. Thus the NOR Gate output is obtained by complementitig the output of OR gate. Thus output of NOR gate lic | when alts input are logic 0 For all other cases the output is logic 0, NOR gate also called as universal gate because all designed by this gate. po) ABA Input Output : . a B Pe outpt O= Ary vipot 4 ipurd 0 0 1 0 odpat 4a. ah m4 1 0 0 . 1 1 0 OpsPut of NOR will gate be high when all ofits input are low. NOR gates as universal Gate: OR, NOT, AND can be derived using only NOR gate. Nor MV oR = BNKND, a NoR » AND: 8 AD = Bend EXOR Gate: The output of 2 input EX-OR gate is logic 1 when the two inputs are unequal and output is logic 0 when two inputs are equal. — Ay -a08 DIGITAL: ELECTRONICSQ Design Y =(B+C)(DE+F) by vse of minimum number of 2 input NAND gates. c rp X= G +O) DE+F) rp Put bubble at input of OR gate and at the output of AND gate. D [> a —> Y=(B+CDE+F) 2 F Invert OR is NAND gate AND-invert is NAND gate B— [.- Y=(B+C\DEH) ‘Design ofa boolean expression by minimum number of NOR gate: 1* Step: Write boolean expression in form of OR and AND gate, 24 Step: Place a bubble at the output of gates, place a bubble at each of the inputs of AND gate. 3° Step: NOT followed by NOT means original literal. Q _ Inthe network shown below f can be written as @) Moms tN (0) omy tte wr RTs @ xx Soln, Ousput of gate 1 is «5% +X 4h Yip FENG Ly By Mya Xp Output of gate 2 is yx, +x, Output of gate 3 is (xx, +34), = Hy +4, Output of gate 4 is xxx, 435%, +4, Output of gate 5 is xxx, 35 +5)%%5 45% So, output of gate n would be BER Ha Correct answer is (c) hg AXGH GL, ne Ny + Ky Fae DIGITAL ELECTRONICSSoln. Soln. °F the input to the digital circuit shown below consisting of a cascade of 20 XOR gates is X, then the output Y is equal to. Pee @ x ®) ¥ @o @l Correct answer is (d) Output of I XOR = Z1¢ x] = ¥, Output of 2 XOI So after 4, 6, 8, .... 20XOR output will be IfA= 0 in logic expression Z=[A+EF +BC + Di{4+ DE +BC + DE}, then @ z=0 @) Z=1 © Z=BC @ z=BC 5 ae Be E+ DIA + BC El Z=[A+BC+ D+ EFI A+ BC+ DE +F)) = (AXBC+ ER Plas Be + Oe Er = (x+ y)\(r+5) = X=A+BC for A =0,Z= BC Correct answer is (4) The simplified form of a logic function ¥ = A(B+C(4B+ AC) = AB+ AC(AB+ A (B+ AC(AB.AC) = AB+ AC((A+B).(A+C)) = AB+AC(A+AC4B. @ 4B. (&) 4B (© 4B @ 4B Correct answer is (b) ) = AB If x¥+%y =Z, then XZ +XZ is equal to @yY oY @o @l XZ + XZ = X(X¥ + XV) + X(XF + Fv) = X(AY + XV)+ Xv =xV+ IV =¥ In the following circuit the outpot zis, ty UO @ A+B+C (&) ABC (© AB+BC+AC (d) Above all DIGITAL ELECTRONICSDigital output are required to be generated in accordance with sequence in which input signals are received, whichis not possible with the combinational circuit generated should depend on present ani past history of input. Such circuit is called as sequential circuit Sequential Circuit Le Q SR-Lateh: ‘ a CIKTR[S | On tlofol 2 h 7 oli[ 4 7 . ‘ruth Table: |] X : Input ether 0 or 1 1 [1 [1 | tavaita [ro [x[x[@. S-R Flip Flop with NAND TDS 0, it R D-Flip Flop (Delay): When S = D, R = D, Now SR becomes D type Flip Flop. ‘Truth Table DQ, [Qa D ap fololo y 7 ofijo | Qu 1foft 1fifa DIGITAL ELECTRONICSG32) J-K Flip Flop: S=J@Q,); R=KQ,) > Toggle State =)-lele]< —lel—lolam Notes Problem in IK flip lop is race around condition. ‘T-type (Toggle) Flip Flop: J = K = T then T = Flip Flop. 7 Q Input | Ques fos 0 |e IK Q 1 y Positive Pulse Negative Pulse 1 0. Positive — Negative Negative Positive edge edge edge edge ety g2) Acclock pulse may be either positive or negative. A positive clock source‘remains at 0 during the interval between pulses and goes 0 to 1 during the occurrence ofa pulse. The pulse goes through two signal transitions; from 0 to 1 and return from 1 to 0.9n figure 1 and 2, positive transition is defined as the positive edge and the negative transition as the negative edge. Time Diagram Representation: eproaiecie F LE LATL Input = —9y + oweinae—] LU LSt Positive " Q cLK— e DIGITAL ELECTRONICSIf we take positive edge: Q. For negative edge draw the time diagram of D Flip-Flop? D Qq Son, Td For negative edge draw time diagram of D type flip flop. cL Sy IfD is high then output is high. IfD is low output is low. Q __ Forthe positive clock pulse find the timing diagram of JK flip flop. Initially Q=0- Q. Consider a latch circuit shown in figure below, which of the following let of input is invalid for circuit. R nl ,H=0 ()R=0H=1 @©R=1,H=1 @R=1,H=0 DIGITAL ELECTRONICSoO Soln, -|-|-]-le]elelel = HlHlolo}-j-lolol= =lel—|e]-fel-lelo 0 0 0 1 x x 1 1 Counters Asynchronous or ripple or serial Synchronous or parallel or fast (Ring counter (ii) Twisted tail or thomson or mobious (Type of shift registers) Asynchronous Counter: No, common clock-clock is output of previous flip-flop. In synchronous counter common clock is used. . What is meaning of MOD-12 counter =, number of states are 12. 10-1112 states 2, 213-12 states 3, 31412 states 4, 1-12-12 states MOD 12 means divide by 12. £ MoD12 hf 1; Counter wT, Qrrene Asynchronous Counter: J Ql kK Q JandK ‘are connected to Vee 25= Kal | Note: 1. Total number of flip-flop required for Mod-N counter N= 2". 2. 3 bit means MOD-8 counter => MOD 8 = 25 means 3 Flip-Flop required. 3. 4 bit-+16 MOD -»2 -> 4 Flip Flop required DIGITAL ELECTRONICS: Gss) MOD-8 Asychronous Counter: m Q| BQ] fl + K, 3 Tc, 3, hk, 3 ‘Truth Table [ey CLK | Q, | 9, |.Q) — UW uU | I 1 fofofo Twill { — 2 [ololi way op ay rye ty sotto el ! t poy | 4 fofifi om 3 [1[olo 6 filofi 7 [1]1]o 8 fififi Bdge —> Positive, —> (8) up counter (i) Down counter Edge -> Negative — (i) up counter (i) Down counter Vv, l of 5} -—er = K @ KO tk, & J, Q ab | me = Q,, Q, Qy are standard output Case (i): Ifthe output is of first fip-flop is given as circuit to next flip-flop it will act as up counter. Case (i): If O of Ist fip Hop is given.as circuit to next flip-flop it will act as down counter. 1ORV,. i, Q Ky Q Design MOD-6 UP Counter: [, DIGITAL_ELECTRONICSDesign gate in such a manner that 101 goes to 000 or if we replace NAND gate by OR gate then if also does the same function. ‘Synchronous Counter: @ Common clock is there (ii) There are fast ‘Widely used If MOD is in form of 2N then design is simple, If MOD is not in form of 2N then design by use of K-map. Example: MOD-10 UP counter. Ls kK, CIR [2 Thr remove Q. Find MOD of the counter: I—K, , @ K, 4 & ox——_t+= @1 @) 2 @3 @4 Sola. Module of counter 3, J, =G,, J,=Q,, Ky=1, K,=1 DIGITAL: ELECTRONICS,After one clock pulse Q =), Q,=0, Jy =1, 5,=1, Ky=t, Kab After two clock pulse Q,=90, Q=1, Jy=0, J,=0, Ky= So reading JMOD-3 Counter Q. °. The circuit shown in figure below is (@ a MOD-2 counter (©) Generate sequence.00, 10, 01,01 ... Soln. The truth table is shown below: Present State Flip Flop Input Qh Qs ™ Th 00 1 0 04 1 10 1 1d 1 Q .~ Consider a sequential circuit sho 5 clock pulse is K,=1,,Q)=0,0,=1 (®)A MOD-3 counter (@ Generate sequence 00, 10, 00, 00 .... Next State Qi" Q5° oo. se) 0 0 0 0 in figuie. Initially all the flip-flop are reset output Q, Q, Q, after @ 100 © 101 © 110 @m Soln. This is a 3 bit counter, so the output sequence is eK oO Tnitially 0 0 0 o o 1 2 0 1 0 3 0 1 4. 4 Loa 0 5 1 0 1 6 1 1 0 Le DIGITAL ELECTRONICS- Q. The counter shown in figure below is @ (@) MOD-8 up counter (®)MOD-8 down counter (©) MOD-6 up counter (@MOD-6 down counter Soin, FFC | FFB | FFA JKC | JKB | JKA | C'B*AT wi fia fa | ay 000 | 000 | 110 | 140 00 | 110 | ut | 101 900.) 001 | 110} 100, ui | iii |i | ont 01 | 000 | 110 | o10 01 ] 110} 111} 008 00 [001 | 110 | 000 SHIFT REGISTER Register’s are used to stare group of flip-flop. To store’n-bits r-bits n-flip-flop are required in register. ‘Depending upon input and output registers can be classified as (2) SIPO [Serial input parallel out] (4) PIPO [Parallel input parallel output] (1) SISO [Serial input serial output] ) PISO [Parallel in serial output] 4-Bit SISO al To provide n-bit data out (n-1) click pulse required. To store n-bit data n-click pulse required: SIPO (4-Bit) D, D, i Inpu—fb, r wt [LIL fl DIGITAL ELECTRONICSPISO Soin, Soln, applied, what are contents of shift register. To provide n-bit data in n-clk pulse required, to provide parallel out no circuit pulse required. | np —B, Bp, aH wle Control Control 0» Parallel input, Control | -> Serial output Lew! La-et Lim ra Initial contents of 4-bit SIPO, ring shift register, shown in figure is 0110. After 3 clock pulses are afo]ifife ’ 1010. So content are 1010. The frequency of the pulse at Zin the N/W. Show in figure below is SUL ont ait MOD-25 4B TaARTE"|_Ring Counter | para Coster| [ripe Counter} + ohason Counted (@ 10H 160K (© 40Hz (@ Sz 10-bit ring counter is a MOD-10, so it divides the 160 KHz input by 10. Therefore, w= 16KHz. The four bit parallel counter is a MOD-16, Thus, the frequency atx = 1 KHz, the MOD - 25 ripple coutitér produces a frequency at y = 40Hz. (IKhz / 25 = 40Hz). The four bit Johnson counter is a MOD-8. This the frequency at z= 5 Hz. Consider a sequential circuit using three J-K flip-flop and one AND gate shown in figure output of the circuit becomes ‘1’ after every N-clock cycle. The value of N is, @4 ®7 ©8 ~@6 DIGITAL’ ELECTRONICSGm) Soln, Let initially output is 1, then ‘Ring Counter: Design MOD-S'ring counter. After éach 10 steps is reads again 0000. Tock, Ring counter is shift register with feedback applied last flip-flop output Q to input of first flip flop. Ring counter is one bit is logic one and it will rotate with clock. In r-bit ring counter number of use state is n. ‘Number of unused states in n-bit ring counter is 2"~ nm. ciK Q&S OG rr rr Iteea seco OeelOhe oe 2 6 1 0 a 0 3 0 0 1, 0. 0 ]}5State 4° 0 0 o'1 9 s 0 0 o 0 IL 6 1 0 0 0 0 7 0 1 o 0 0 8 06 0° 1 0. oO. [)SState 9 0 0 0 L oO loo 0 oO ot Johnson Counter or (Twitled Ring Countet) or Switch Tail Counter or Creeping Counter or Mobies Counter or Walking Counter. oH a a Equivalent Cireui CLK DIGITAL ELECTRONICS‘Truth Table : CLK . To O_o oH 1 Co o 0 2 1 Go 0 3 1 1 CO 40 17 © s @op tt Ga Oe une) ean 7 0 0 @=D 8 O@ 0 0 @ In Johnson counter with n-fip-flop maximum possible states are 2n states or maximum uses states. Unused states are 2" - 2n 50% duty cycle. ‘When a Johnson counter is working in uses state the operation frequency ff2n, 1 HaltAdd & 7 ‘Sum B— ‘Carry 2. ~ Truth Table: ‘AB | _suM | CARRY a 0 oft 0 0; |e 0 erie L Logical expression SUM = AB+ AB = AB, Carry = AB 3. Logic Diagram: B ‘SUM / [-- Full Adder: — SUM “A@BOC= Dm(l,2, 4,7) pr c CARRY =AB+BC+CA=Em(3,5,6,7) ‘Truth Table ABC sum] carry] t—0-0F 0] 0 oo. 1 o o 1 of 1] o eter 0 L io el 1] o 1 01 o t 11 .ofo] 4 1oiia 1 L DIGITAL ELECTRONICS.Logie Diagram: Apc H—> ) >—senecsns D7 D— SD — as nc + caccaRR Note: In full adder, if all logic gates have same delay then to provide sum of carry output it require minimum 2 tpd delay. Now Full Adder Using Half Adder: =D « eres Full Adder Using NAND Gate: . pH ?<- D- Ds c L_ Carry Half Subtractor: re BS }—Borrow AB Truth Table: ee es Ae Toi Tis rman ertry re o 0 Logie Diagram: >it. [—Borow DIGITAL ELECTRONICS.HS Using NAND Gate: . A@B (Diff) AB (Borrow) Full Subtractor: a—f— Li 7 ye [DI A@BOCEM(,2,4.7) COLES | poo Emn(t,2, 3:7) ‘Truth Table: ABC Boron] [o-oo 0 mt 1 o10 1 ane L 100 ° 10] ° 110 0 bit 1 Logic Circuit: ) > renee {Difference} Borrow Full Subtracter Using Half Adder: | D4 5 ) >——-aezec Borrow DIGITAL ELECTRONICSCHAPTER — 8: MICROPROCESSOR Itis an electronic chip that have computing and decision making ability. It is an integrated electronic chip that fetch instruction fom memory execute then and provide result Bus: _Itis group of parallel combination of metal wires that is used interface two different devices. Main memory is also called as RAM Program is always stored in RAM. ROM system software is stored. Micro Controller: It is the example of ASIC design (Application specific integrated chip). Machine Language: Commands written in the form.of binary patter such language is called as machine language. Assembly Language: It commands writen in the form of English language than, itis called as “Mnemonics” such type of language is called as Assembly language. LANGUAGE: Low Level Language: Assembly language and machine language are low level languages. High Level Language: Ex. C, C*, JAM etc. Compiler: Read whole program at once and produce its object code that is executed by microprocessor. Itis only a software, Interpreter: Read one instruction at one time and produce it to be the object that is executed by microprocessor ty “Microprocessor | Bit of Microprocessor | Technology sed 4008 7 PMOs 8008 8 NMOS 8080 8 NMOS 8085 8 NMOS 8086 16 HMOs 8085 is improved version of 8080. Numbers of bits executed by microprocessor at a time is also called 1 machine cycle. Size of ALU is known as size of accumulator called is bits of processor. 1 Speed of Processor: |S ©—————-« f Execution Time 8085 Architecture: © Ttis a 40p ia T,, Pin number 20 is ground pid Number chip enable is available. Clockout XX Gy Vee yo ( +4 n sD—| Serial Transfer ase sop<— — _ " is ae " RSTIS—> RST65—>| jae RST5.s—} " INTR->| os ne (= NTA eo) state HOLD—+| Control and Signal pins HLDAS| | + write ‘Status Pins READY—+| nee RESETIN—>| Le ate RESETOUT«—| MICROPROCESSORInterrupts: (1) Trap 2) RST 7.5 (3) RST6.5° (4) RSTS.S (5) INTR Internal Architecture: ie ALU (Arithmetic Logic Unit) (@) accunmlator (©) Resistors (© Register array 2. Timing and control 3. Interrupt contol circuit Registers: 1. General purpose registers: B, C, D, E, H, L all are 8 bits. 2. Special purpose registers (@) USER accurilde (©) Accumulator register {8 bit} (c) States register (fag resister’s) (8 bit) (@ Stack pointer (16 bit) (e) Program counter (PC) (16 bit) User not Accessible: (@) Temporary register (8 bits) (b) Interrupt register (8 bit) (© Latches (16 bits) Status Register / Flag Register: DD BRD D DD DB S| Z| xfac] x] P| xjcy sh L_synag ty Plas Ausiliary Flag L_—+z6r0 Flag Accumulator Register: 8-bit special type of registers. It performs arithmetic and logic operations Addressing Mode’s: : (a) Register Addressing Mode: Address of data given in form of register in the instruction. EOX: MOV, C. (b) Direct Addressing Mode: If address of data directly given in the instruction = direct addressing mode Ex: IN 25H. (© Immediate Addressing Mode: Ex. MVI B, 2FH @ Indirect Réglster Addressing Mode: Ex. MOV B, M (©) ‘Implicit ‘Implied Addressing Mode: If address of data not required in the instruction then it is called as implicit addressing mode, Ex. NOD, CMA, HHLT. Few Instruction Sets: @) ADD: Bx. ADD R->any register A, B, C, D, E, HL, M [A] < [A] + [8] []> Content of register. @)- ADI, 8 bit data: [A] < [A] + 8 bit data @)SUBR: (A] < [Al (RI (4) SUIR: [A] < [A] -8 bits data INK, R: [R] < [8] + Iys5) ©, DER, R: [RK] © (RY - lose) A Logical Instructions: 1. AND R: (A]<-[A} AND (RY 2. ORA, R: [A] <[A] OR [D] 3. XRA, R: [A] < [A] @[R] CMA: Complement of Accumulator Register: [A] <—[A} HET: Haltor stop execution. MICROPROCESSOR4 if. ?, aon qa) SS) exe CSIR-UGC-NETHRF-CHEMISTRY Assignment : ELECTROCHEMISTRY Activity coefficients calculated using Debye-Huckel law are always {a)Lessthanzero. —_(b) Greater thanone (©) Equal te one (@)Lessthanone ‘The standard cell potential for the reaction, Zn(s)+ Cu?* (aq) —> Zn?* +Cu(s),at25°C is 0.5. The standard free energy (in k3) is: (241 (b)-48.25 ©3965 (@)-193.0 ‘The total charge supplied in am electrobtic process for depositing copper from copper sulfate solution is one Faraday. This will result in a cathodic deposition of (a) 63.55 g of Cu (1 MofCu) (b)31.78 gof Cii(1/2M of Cx) (©) 10 gofCu(2MofCu) {127.1 gofCa (1/4 Mola} “Thenumber of electrons lost during electrolysis of 0.355.g of Cris: : - {0.001 N, (Wy OLN, (0.02, Moon, . Which ofthe following batteries is NOT rechargeable? {a)Nickel-cadmium (b)Lead-storage (©) Lithium-ion (@)Zinc:carbon ‘The solubility of silver halides in water vaties as, ()Agl AgBr> AgCl> Agl () AgCl=AgF 0,AG® <0;Q 0;AG" <0;Q>K {©) Bly >0,AG" > 0,Q>K @ EX, > 0,46" <0;0 {e)Mgeanreduce both Zn? and Fe? (@)Mgcan reduce Zn But not Fe®* ‘Which one of the following equationsis used for the calculation of equilibrium constant (K) of an electro- chemical cell reaction (n= number of electrons transferred, F = Faraday constant and E = standard redox potential)? (@) nk (oFE° /RT) (b) InK =~(nFE°/RT) (©) Ink =(RT/nFB*) (@ mK =-(RT IEE?) Givenstandard electrode potentials Fe** + 2¢ > Fe, E° (~)0.440V; Fe” +3e—> Fe, B® =(~)0.360 V. Thestandard electrode potential (E°) for Fe +e» Fe" is: (@)-0.476V (b)-0.404-V (c) +0404. V (@+0771V ‘The mean ionic molality of2~1 electrolyte is: @ 44m ©) 93 (27% m @108m ‘The diffusion current ina polarogram is proportional to (@) Theresidual current (@) The migration current. (©) The wave height (@) The concentration of the supporting electrolyte. Which one of the following conductormetric titrations will show a linear increase of the conductance with vohume of the titrant added up to the break point and an almost constant conductance afterwards. (a) Astrong acid with astrong base (b) Astrong acid witha weak base (c)Aweak acid with a strong base (a) A weak acid with a weak base. (in Sarat 26:0, 3 Sarak Near HT New DONEIG, Ph. 011-26851008, 2681009 wocareerendeavoatcom BESS Gru Nagac: 48, First Floor Mall Road, GTB. Nagar (Metro Gate No.3), Deh 09, Pb: 011-65467244, 272418452B. 4. 25. 26. 21, 29, . G3 Forthe EMF of ahydrogen electro¥etobezeo, the pressure of hydrogen required inneutral pis (@) 1x107 atm (8) 1410" dim ©) atm (a) 0.0atm ‘The reduction potential values of Cu’4 |Cu and Cu?* |Cu* are0.34 and 0.15 V, respectively The equilib- rium constant forthe reaction, Ciu+ Cu” —==2Cu* is: . - (a) 3:60%107 (b) 4.95.10" (9) 83210 (a) 3.0110 ‘The reduction potentials of Cr,OF |Cr* and Cr* | Cr are +).33 and—0.74Y, respectively. The reduction potential of Cr,03- / Cris: (9 10295V (b)+0.590V. (9 +0.195V (a) +1.770V Which ofthe following electrolytes is used inhighiy developed hyttrogen~air fuelcells? = (a)Phosphoric acid (b) 1 MKOH (HO, (a) fNa,CO,|,, Forthecelt Ag(s)|AgC1(satd), NaCl(aq,m,)|NaCI(aq,m, ), AgCl(satd)/A.g(s) wherem, and m, are m,), the standard cell potentials: (@-RT in(m, /mz) (b)Zero (© -RTin(a, fa,) (a) -FRTIn(a,) ‘The mean ionic activity coefficient of 0.0005 mol kg"! CaCl, in water at 25°C is: (a) 0.98 (b) 0.67 {c)0.81 (4) 0.91 Forthe cell: Ca (Hg)| CaSO, (8/3)H,0(s)| CaSO, (ag,satd.)| Hg,SO, (s)| He ‘The temperature dependence of emfinvolsis given by E =1.0185~4.05x 10° (T-293) -9.5 x10"? (T-293)° ‘Thechange inentropy at 25° C for thecellreaction is: (@) -253 K™ snot (©) 9.653K" mot (0) 8.3x104 3 K7' mot" (Zero: ‘Anexample for.an ion-selective electrodes: (@)quinhytroncelectrode |< - (hydrogen electrode (@glasselectrode (@ dropping mercury electrode. Forthe reaction, Hg,Cl, (s) +H, (g) > 2Hg(£)*+ 21Ci{aq), the correct representation of thecell and the thermodynamic properties AG, AH and AS at298 K respectively, are (given : Eg, ~0.2684 V and tem- Pefature coeficient = —3%10"* VK) (2) PtH (g.1 atm) HC1(aq) 11g, C2, (9) H4e(2) AG =~51.8kimol"!, AH =-69}3 mol, AS (b) PtH, (g,1 atm)] H1C1(aq)fF1g,Cl, (s)fHe (2) AG =-25.9 kJmo}, AH = -34.5k) mol, AS = -29 IK“'mol” (©) Hg (£)}He2Cl, (s)] HCI(aq)]H, (2,3 atm)fPn AG = 51.8 kJmol™, AH = ~69 kJ mol"', AS = 58 JK (© 4ia(2)\He2Clz(s)] HCI (aq) |B, (1 atm)|Pt AG =51.8kimol”, AH = 69% mol, AS = 58 IK-'mol 58 K“*mot ort ‘Via Sarai: 28-A/11, Sia Sarah Neat MIT, New Del 16, Ph=011-26851008, 26861008 wwcarserendeavonrcom, GTB Nagar 48, First Floor, MallRoad, GTB. Nagar (Metro Gate No. 3), Delhi-09, Ph: 011-65462244, 2746184530. 31 32, 34, 35. 36. 31. From the\lata of two half-cellreactions: 7 5 AgCI(s) +e —> Sg(s}+CF (aa) B=402V Ag" (aq) > Ag(s) 9 = 40.80 . the sohubility productofAgCla1 298 K,, is calculated to be ae (a) 1.5%107° (b) 2.1107 (6) 3.0«10% (@ 12x10 ‘Statement: The potential for the cell, Pt|H, (g,1 atm)|HCI(é)|AgCI(s)]Ag(s)decreases as the concentra tion of HClis increased, Reason: The méan ionic activity coefficient decreases with increase in HC] concentration. ‘Assertion: In a plotofE vs {HCY the intercept at the potential axis is equal to the standard reduction potential ofthe hydrogen electrode. (a)Both Reason and Assertion are correct. _(b) Both Reason and Assertionare wrong (©) Reason is correcttbut Assertion is wrong. _(d) Reasonis wrong but Assertion is correct. ‘The half-wave potential fora reversible reduction ofa metal ion in potarographyis independent of (a) Concentration ofthe supporting electrolyte (b) Concentration of the electroactive species. ae (©) Concentration of the completing agent. Ce (@) Temperature of the solution. The solubility product of silver sulphate at 298 K is ) 03 \0">- Ifthe standard reduction potential ofthe half: cell Ag” +¢ > Ag is 0.80 V, thestandard reduction potential of the half-cell Ag,SO, +2¢—> 2Ag +SO}-is: (a)0.15V (b)0.2V (c) 0.65 V. (a)0.95V Match the following: P.Coulomeny L Dropping mereuryelectrode Q lonselective electrode UW. Current efficiency R Polarography MIL Dead stop end point ‘S.Amperometry TV. Membrane potential : V.Conductometer ” VI Actinometer. (@) PAL, QUY, R-l, SIT (b) P-1, QI, RN, S-V (PV QV, Rulll, S-1V (a) PAD, QUY, RA, S-VI A substance undergoes a two electron reversible reduction at dropping mercuryelestrade, and gives a diffusion consent of 7.5 . When the potential at the dropping mecury electiode is-0.615 V, the current is 1.5 pA. The By (invol willbe (@)-0.683 (b)-0.674 (©)-0.652 (4)-0.633 In the reversible chemical reaction taking place under standard condition at 298K and } atm in a Daniel cell, Zn|2n** (aq)[Cu (aq)}cu the beat change is: (a) equal to AH” (b) equal to TAS” (c) equal to zero {@equal to AU Ifstandard emfofthe cell, Cu}Cu** (aq) \{Cu(NH,), |” 2g. NH, |Ca is 0.35, then stability constant of the formation cupric amine complex is: (2) 10x10? ®) 84x10° (© 7.010" (@ 43x10 ja Sarai : 28-A/11, Sa Sarai, Near IIT; New DeInE16, Ph: O11-26851008, 26861009 wnncareerendeavour.com GTB Nagar 48, First Floor, Mall Road, GTB. Nagar (Metro Gate No.3), DelhFO9, Ph: DI-65462244, 2724184538.- _ Giventhe standard potential for the fo lowing half-cel eactionat 298K. 39. 40. 4 a 43, 44. 45: 46. Cu'(aq)+e° > Cu(s) By ==0.52" Cut (ag) 2" > Cu (aq) - Ey =0.16V Calculate the AG® (KJ) for the reaction, 2Cu* (aq) ~> Cu(s)+Ca™* {a)-34.740 (b)-65.720 (0) 69.480 (@)-131.440 Given that HF", Fe) =-0.04 V and By (Fe Fe) =-0.44V, the valu of By (Fe Fe") is (@)0.76V ~ ()-0.40V ()-0.76V @o40v According o the Debye-Huckel limiting law, the mean activity coeflicientof'5.<}0~ mol kg"? aqueous. ~~ solution of CaCl, at25°C is (the Debye-Huckel constant ‘A’ canbe taken to be 0.509) ° (2) 0.63 0.72 (-)0.80 (09 According tothe Debye Hucke! limiting Jaw, if the concentration ofa difute aqueous solution of KClis increased 4-fold, the value of n'y. (7. is the molal mean ionic activity coefficient) will (a) decrease bya factor of 2 (b)increase bya factor of 2 (0) decrease by a factor C4 (d) increase bya factor of 4, Given the siandard cell potentials as below: AgCl+e=Ag+CI”, E° = 0.2223 V; Ag? +e= Ag, Bo =0.799V. ‘The solubility product for thereaction, AgCl = Ag* +CIP is: (@) 280x107" ——(b) 0.801071” (©) 28.910" {@) 1.80107 ‘The velocity of 1; ionin water is 2x10 cm/sec when 100V is applied between two electrodes separated by2cm. The mobility of 1 j* ion in water's, (@) 4x10%em?stV" (b) x10 stv (@) 4Vem?s (8) 2.5410 Vsem? “The specific conductivity ofa saturated solution of AgClat 25°Cis 3,41310°S.cm”! and that of wateris 1.6010. Sem“. The molar conductivity at infinite dilution is 138.3 S.cm?. What is the solubility of AgClin water in moles/I at 25°C: (i3xter (b) L1sx10% (2) 1.15%10° (@)1.31«10° When NaOH (aq,) solutions titrated with HCl (aq), the variation of conductance as a function of volume of JACI (increasing volume towards the right on the’ x-axis) will take the shape of the curve as in g gl 9 g qf HANA ANS 3 a wanna aL ofria ia orncl a ornel (aa (yb we (ad. ‘The ionic strength ofa solution containing 0.1 molal each of copper sulphate and alumniniuss sulphateis: (02m (6)0.7m (1.9m (@10m - (Cin Sava 25-00, a Sora, Near INT, New DeNF16, Ph: 011-26851008 26961009 wroccarcerendeavour.com GTB Nagar 48, First Floor, Mall Road, GT.B, Nagar bctca Gate No.3) DeiP09, Py: O11-65462244, 27241845,