Elonics E4000 Low Power CMOS Multi Band Tunner Datasheet PDF

E4000
MULTISTANDARDCMOSTERRESTRIALRFTUNER

KEYFEATURES DESCRIPTION
SupportforMultipleBroadcastStandards The E4000 is a highly integrated multiband RF
o NorDig2.0 tuner IC implemented in CMOS, ideal for digital
o MBRAI2.0 TV and radio broadcast receiver solutions. The
ScalablePowerConsumption digitally programmable multiband tuner
o 118mWTypicalOperation architecture allows the user to reconfigure the
o 15mWinDVBHMode RFfrontendfordifferentbroadcaststandards.
o <60uWPowerDown DVBT(174240MHz,470858MHz)
1.5VAnalogueandDigitalSupplyOperation
VariableGainLowNoiseAmplifier(LNA) CMMBTerrestrial(470858MHz)
o AutonomousAutomaticGainControl DTMB(174240MHz,14521492MHz)
withRSSI
o <4dBReceiverNoiseFigure ISDBT(470862MHz)
o 64MHzto1700MHzInputFrequency DVBH(470858MHz,16721678MHz)
Range
FlexibleIFAmplifierandChannelFilter TDMB(174240MHz,14521492MHz)
o ProgrammableChannelBandwidth DAB/DAB+(174240MHz,14521492MHz)
o DigitalIFGainControl
FlexibleClockingModes GPSL1band(1575MHz)(withadditional
o MasterorSlaveModeDevice LNA)
o 16MHz32MHzInputFrequency FMradio(64108MHz)
Range
o ProgrammableOutputClock It is designed to interface directly to a digital
FrequencyRange demodulator,andcontainsafullyintegratedLNA,
o CMOSorcustomlowpowerLVDS programmable RF filter, and RF mixers providing
OutputLevels superiorrealworldperformance.
FractionalNSynthesiserwithFullyIntegrated At the heart of the E4000 is Elonics innovative
VCOandLoopFilter DigitalTune architecture, which allows the user
I2CCompatibleControlBus to adjust the performance of the tuner for
o 3.3VTolerantInterface optimumlinearityornoisefigureaccordingtothe
o 4Addresses signal conditions. It enables manufacturers to
32PinQFNPackage significantly improve reception quality, whilst
o 5x5x0.9mmBodySize supportingmultiplebroadcaststandards.
o PbFree The E4000 contains a single input LNA with RF
o RoHSCompliant filter, whose centre frequency can be
programmedoverthecompletefrequencyrange
APPLICATIONS from 64MHz to 1700MHz. This greatly simplifies
TVEnabledCellPhones antenna management especially for applications
thatrequiresupportformorethanonebroadcast
PortableMultimediaPlayers standard.
PCandPCPeripherals
IPTV
SetTopBoxes
NIMandhalfNIMmodules
E4000Datasheet4v0Copyright2010ElonicsLtd
DocumentNumber:SE4000DS001
www.elonics.com
E4000

TABLEOFCONTENTS
KEYFEATURES1
APPLICATIONS1
DESCRIPTION1
TABLEOFCONTENTS2
ORDERINGINFORMATION5
PACKAGEMARKINGDIAGRAM5
PINFUNCTIONS 7
ABSOLUTEMAXIMUMRATINGS 8
MOISTURESENSITIVITY 8
RECOMMENDEDOPERATINGCONDITIONS 8
DCELECTRICALCHARACTERISTICS9
ACELECTRICALCHARACTERISTICS 11
POWERCONSUMPTION 13
TIMINGCHARACTERISTICS 14
TYPICALCHARACTERISTICS 15
REGISTERMAP 17
DEVICEDESCRIPTION 23
1.1 TwoWire,I2CInterface 23
1.2 SerialInterfaceProtocol 23
1.3 FrequencySynthesiser 25
1.4 PLLFeedbackdivider(/Z) 26
1.5 X,Sigmadeltasetup 26
1.6 RVCOoutputdivider 26
1.7 Threephasemixing 26
1.8 ExampleFrequencysynthesizerconfiguration 27
1.9 VCOCalibration 27
1.10 E4000SignalPath 28
1.11 FrequencyBandSelection 29
1.12 GainControl 30
1.13 LNAGainControl 30
1.13.1 LNASerialInterfaceGainContro 31
1.13.2 LNAdigitalPWMgaincontrol32
1.13.3 LNAAutonomousGainControl33
1.13.4 LNASupervisorGainControl33
1.14 ReceivedSignalStrengthIndicator(RSSI)34
1.15 MixerGainControl 34
1 15.1 MixerGainSerialInterfaceControl34
1.15.2 MixerGainAutonomousControl35
1.16 LNAGainenhancement35
1.17 IFGainControl35
1.17.1 IFgainLinearity/SensitivityMode35
1.17.2 IFGainSerialInterfaceControl36
1.17.3 IFGainDigitalPWMControl40
1.17.4 IFGainDigitalControl41
1.18 OutputCommonModeVoltage42
1.19 RFFilter43
1.20 IFFilter44
1.21 MixerFilter44
1.22 IFRCFilter45
1.23 IFChannelFilter46
1.24 CombinedFilterResponse48
E4000Datasheet4v0 UNCONTROLLEDWHENPRINTEDUNLESSSTAMPEDOTHERWISE
SE4000DS001 Copyright2010ElonicsLtd
August2010 Page2
E4000

1.25 DCOffsetCorrection48
1.26 DCOffsetControl49
1.27 DynamicDCOffsetCorrection49
1.27.1 LookUptable49
1.27.2 TimeVaryingDCOffsetCompensation50
1.28 ClockOutput51
1.29 ClockInput53
1.30 Reset53
1.31 PowerSaveModes54
1.31.1 PowerDownMode 54
1.31.2 StandbyMode 54
1.32 Initialisation 55
APPLICATIONINFORMATION 56
PACKAGEDESCRIPTION 57
REVISIONHISTORY 58
LEGALNOTICES 59

August2010 Page3
E4000

BLOCKDIAGRAM
August2010 Page4
E4000

ORDERINGINFORMATION
OrderCode Ambient Package Moisture PeakSoldering
TemperatureRange SensitivityLevel Temperature
E4000EQG 40to+85C QFN325x5mm MSL1 260C
body(Pbfree)
E4000EQGD 40to+85C QFN325x5mm MSL1 260C
body(Pbfree,
drypackedand
vacuumsealed)
E4000EQGR 40to+85C QFN325x5mm MSL1 260C
body(Pbfree,
tapeandreel)
Notes
1) Tubequantity=95
2) Reelquantity=3500
PACKAGEMARKINGDIAGRAM
E4000EQG
YYWWZMMC

Line1 ElonicsLogoFixed
Line2 E4000Fixed(DeviceName)
EQGFixed
Line3 YYWWVariable(DateCode)
Z Variable (Trace code e.g. A, B, C X, Y, Z lots molded in the
sameworkweek
MMCVariable(Manufacturingcode)
August2010 Page5
E4000

PININFORMATION
TUN_DGND1
TUN_DGND0
TUN_DVDD
PLL_GND
PLL_VDD
CLOCKIN
Top view
AVDD
XTAL
AGND 1 CKOUTP
VBG CKOUTN
REXT GAIN1
RFSHIELD Elonics GAIN0
RFIN E4000 IVOUTP
LNAGND IVOUTN
LNAGND2 QVOUTP
LNAVDD QVOUTN
IFVDD
IFGND
A0
A1
STBYB
PDNB
SDAT
SCLK
QFN32
5x5mm

August2010 Page6
E4000

PINFUNCTIONS
Pin Name Type Description
1 AGND Ground 0V.ConnecttoTuneranalogueground
Band gap voltage. A 10nF decoupling capacitor should be
2 VBG AnalogueOutput placed between this pin and 0V. The capacitor should be
placedclosetothispin.
Reference current generation. A 10k, 1%, resistor should be
3 REXT AnalogueOutput
placedbetweenthispinand0V.
4 RFSHIELD Ground RFShield,connecttoLNAGND
5 RFIN AnalogueInput RFinput.50Rimpedance.
6 LNAGND Ground 0V
7 LNAGND2 Ground 0V,connecttoLNAGND
8 LNAVDD Supply 1.5V
9 IFVDD Supply 1.5V
10 IFGND Ground 0V
11 A0 DigitalInput TunerI2Cdeviceaddresscontrol(bit0).(3 3Vtolerant).
12 A1 DigitalInput TunerI2Cdeviceaddresscontrol(bit1).(3.3Vtolerant).
Normal operation = 1.5V (3.3V tolerant). Standby = 0V. If
13 STBYB DigitalInput
unused,connectAVDD
Normaloperation=1.5V 3.3Vtolerant).Powerdown=0V.If
14 PDNB DigitalInput
unused,connectAVDD
15 SDAT DigitalI/O I2Cdata.Pullupto1 5V(3.3Vtolerant).Pullupresistor>4.5k
16 SCLK DigitalInput I2Cclockinput.(3V3tolerant).
17 QVOUTN AnalogueOutput QChanne Outputve
18 QVOUTP AnalogueOutput QChanne Output+ve
19 IVOUTN AnalogueOutput IChannelOutputve
20 IVOUTP AnalogueOutput IChannelOutput+ve
Gain control input. Either digital IF or IF PWM input (3V3
21 GAIN0 Digital/PWM
tolerant).
Gain control input. Either digital IF or RF PWM input (3V3
22 GAIN1 Digital/PWM
tolerant).
LVDSorCMOS
23 CKOUTN ClockOutputve.Ifunused,shouldbeleftasnoconnect.
output
LVDSorCMOS
24 CKOUTP ClockOutput+ve.Ifunused,shouldbeleftasnoconnect.
output
25 TUN_DVDD Supply 1.5V
26 TUN_DGND0 Ground 0V
27 TUN_DGND1 Ground 0V
ConnecttocrystalORClockinputfromexternalsource(1.5V
28 CLOCKIN Oscillator
logiclevels).
29 XTAL Oscillator Connecttocrystal.Ifunused,shouldbeleftasnoconnect.
30 PLL_GND Ground 0V.DonotconnectdirectlytoLNAGND
31 PLL_VDD Supply 1.5V
32 AVDD Supply 1.5V

August2010 Page7
E4000

ABSOLUTEMAXIMUMRATINGS
Condition Min Max Units

StorageTemperature 65 +150 C
SupplyVoltage(LNAVDD,PLL_VDD,IFVDD, GND0.3 GND+1.65 V
TUN_DVDD,AVDD)
AnalogueInputs/Outputs GND0.3 AVDD+0.3 V
DigitalInputs GND0.3 +3.6 V
I2CInterfaceInputs GND0.3 +3.6 V
RFInputPower +10 dBm
LeadTemperature(10ssoldering) +260 C
Stressesbeyondthoselistedmaycausepermanentdamagetothedeviceormayimpairdevicereliability.
Thedeviceshouldbeoperatedwithinrecommendedoperatingconditions.
ThisisanESDSensitiveDevicemanufacturedinaCMOSprocess.Itisthereforesusceptibletodamagefrom
excessive voltage such as is caused by static discharge. Proper ESD precautions must be taken during
handling,storageandoperationofthisdevice
MOISTURESENSITIVITY
Devices are qualified to IPC/JEDEC JSTD020B, determining moisture sensitivity and acceptable storage
conditions. The rating of this product is as indicated within the Ordering Information section of this
datasheet.
RECOMMENDEDOPERATINGCONDITIONS
Condition Min Typ Max Units

OperatingTemperature 40 +25 +85 C
SupplyVoltage(TUN_DVDD,LNAVDD,PLL_VDD, +1.4 +1.5 +1.6 V
IFVDD,AVDD)
GroundVoltage 0 V
AnalogueInputs 0 +1.6 V
DigitalInputs(ExceptCLOCKIN,pin28) 0 +3.6 V
CLOCKIN 0.7 +1.6 V
DeviceFunctionandElectricalCharacteristicscanonlybemaintainedifoperatingconditionsareadhered
to.
August2010 Page8
E4000

DCELECTRICALCHARACTERISTICS
Operating parameters specified with all supplies = 1.5V, GND = 0V, Tambient=25 degrees unless otherwise
stated.
Parameter Description Min Typ Max Units

SupplyVoltages
AVDD, Supplyvoltage 1.4 1.5 1.6 V
PLL_VDD,
LNAVDD,
IFVDD,
TUN_DVDD
IDDcont Supplycurrent(Continuousoperating 79 mA
mode)
(Variesdependingontunerconfiguration)
IDDStby Supplycurrent(standbymode) 4 mA
IDDPD Supplycurrent(powerdown) 60 uA
ClockOutputs(CMOS)
VohCMOS Outputsignalhigh 0.8x V
TUN_DV
DD
VolCMOS Outputsignallow 0.25x V
TUN_DV
DD
ICMOS Outputcurrent 5 mA
Jitter ClockoutputRMSjitter 5 ps
ClockOutputs(Custom,lowpowerLVDS)
VohLVDS Outputsignalhigh TUN_DV V
DD
VolLVDS Outputsignallow TUN_DV V
DD0.4
ILVDS Outputcurrent(Note1) 4 mA
RLVDS Differentialoutputimpedance(LVDS) 500 Ohm
Jitter ClockoutputRMSjitter 5 ps
ZSOURCE Sourceimpedance(CMOS)(Note2) 1000 Ohm
DigitalInputs(PDNB.ADDR,GAIN,CLOCKIN)
VilCMOS Voltageinputlow 0.3x V
TUN_DV
DD
VihCMOS Voltageinputhigh 0.7x V
TUN_DV
DD
I2CInterface
VilI2C Inputlogiclowlevel 0.3x V
TUN_DV
DD
August2010 Page9
E4000

VihI2C Inputlogichighlevel 0.7x V
TUN_DV
DD
VolI2C Outputlogiclevellow(Note3) 0.4 V
NOTES
1. LVDSoutputcurrentisprogrammable.
2. Ifloadimpedanceisdifferentmayrequireaterminationresistor.
3. PullupresistoronI2Cdatalineshouldbe>4k7Ohms.
August2010 Page10
E4000

ACELECTRICALCHARACTERISTICS
RF
FIN InputFrequencyRange 64 1700 MHz
NFFM Noisefigure(FM) 4.5 dB
NFVHF Noisefigure(VHF) 4.5 dB
NFUHF NoiseFigure(UHF) 3.8 dB
NFLBAND Noisefigure(LBand) 4.3 dB
IIP3 InputreferredIP3point(minimumgain) 5 dBm
S1150R InputReturnloss(50Rsystem) 15 dB
S1175R Inputreturnloss(75Rsystem) 20 dB
ProgrammableRFtrackingFilter(Note4)
FC RFFilterCentreFrequency(programmable 350 1700 MHz
between)
F3BW RFFilter3dBBandwidth 200 MHz
FREJ RFoutofbandrejection(>150%FC) 10 dB
TypicalGain(Note5)
Gt TotalGainrange 2 99 dB
G1 LNAGainRange 5 30 dB
G2 MixerGainRange 4 12 dB
G3 IFGainRange 4 57 dB
G3 StepSize 1 dB
G f Gainflatness(IFfrequencyband)(Note6) 1dB dB
Referenceoscillator
Fosc Frequency 16 26 32 MHz
Cosc Load(presentedbyE4000) 10 pF
Posc Crystalpowercapability 100 W
NOTES
4. RFfilterstrackwithLNA onfiguration.Whenoperatingatf<240MHzfilterislowpasstype.Forf>350MHzfilterisbandpasstype
5. Gainisprogrammab e.Valuesquoteddetailthetypicalrangetowhichgainscanbeset.
6. Filtersminimised.DC4MHz
FrequencySynthesiser(Note7)
FVCO VCOfrequencyrange 2600 3900 MHz
/R R(VCOoutput)dividerratio 2 48
FLO LocalOscillatorFrequencyRange 64 1700 MHz
FLO LocalOscillatorFrequencyStepSize(Note8) 10 20000 Hz
Integratedphasenoise(1kHz8MHz) -29 dBc
dBc
PhaseNoise@10kHz -80
/Hz
dBc
PhaseNoise@2MHz -125
/Hz
/Z Z(phasedetector)divideratio 64 255

August2010 Page11
E4000

IFChannelFiltering
Fc ChannelFiltercornerfrequency(Note9) 2.15 5.50 MHz
A20M Attenuationat10MHz(fc=4MHz,) 70 dB
IQBasebandOutputs
Vpp DifferentialPeaktoPeakOutputVoltage 1000 mV

Vcm CommonModeVoltage(Note10) 0.58 V
Rout SingleEndedOutputImpedance 250 Ohm
Load Outputload 15k Ohm
Outputloadcapacitance 10 pF
AIMB DifferentialItoQAmplitudeImbalance 0.2 dB
PIMB DifferentialItoQPhaseImbalance 5 degree
NOTES
7.Section1.3documentsFrequencySynthesizerconfigurationforvariousstates.
8.LOfrequencystepsizevariesdependingon/Rratioset.
9.Programmablewith0.2MHzstepsize.
10.Commonmodeoutputvoltageisprogrammable
August2010 Page12
E4000

POWERCONSUMPTION
Thepowerconsumptionofthisdeviceisdependentontheoperatingmode.
Parameter Min Typ Max Units

PON(1) 108 mW
PON(2) 118 mW
PSTBY(3) 6 mW
PGATED(4) 15 mW
PGATED(5) 17 mW
PPWDN(6) 60 uW
NOTES

1. Continuousoperatingmode.CKOUToff.Normalreceptionenvironment
2. Continuousoperatingmode.CKOUTon.Severereceptionenvironment(Inthepresenceofastrongadjacentchannelinterferer)
3. Standbymode
4. Gated.AssumedeviceisinOperatingmodefor1cycleandStandbyfor9cycles.CKOUToff Normalreceptionenvironment
5. Gated.AssumedeviceisinOperatingmodefor1cycleandStandbyfor9cycles.CKOUTon. everereceptionenvironment
6. Powerdownmode
August2010 Page13
E4000

TIMINGCHARACTERISTICS
InitialisationTiming
Tinit Signalpathinitialisation(frompoweron) 2 20 ms
Tinit_stby Signalpathinitialisation(fromstandby) 1 2 ms
Tinit_osc Oscillatorturnontime 100 s
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF
SDAT
SCLK
tLOW tHIGH

Figure1:I2CinterfaceTimingRequirements

Parameter Symbol Min Max Units

SetuptimeforStartcondition tSU:S A 600 ns
HoldtimeforStartcondition tHD:STA 600 ns
Clocklowtime tLOW 1300 ns
Clockhightime tHIGH 600 ns
tSU:DAT 100 ns
tHD DAT 900 ns
tSU:STO 600 ns
Bus free time between Stop tBUF 500 ns
andStart
I2Cclockfrequency CLKI2C 1 MHz
August2010 Page14
E4000

TYPICALCHARACTERISTICS
Operatingparametersarespecifiedforallsupplies=1.5V,GND=0V,Tambient=25degreesunlessotherwise
stated.
84 80
Supply current (mA)
79
82
Supply current (mA)

78
80 77
78 76
76 75
74 Baseband channel filter can be 74
72 disabled at low input power, 73
reducingsupplycurrent 72
70
71
-100 -80 -60 -40 -20 0
0 500 1000 1500 2000
RF input pow er (dBm ) Fre que ncy (M Hz)

Supplycurrentvs.RFinputpowertotuner Supplycurren vs.ope atingfrequency
(maintaining1Vppdifferentialoutputamplitude)

Su p p ly cu rren t (m A )
77 10
76
5
Gain (dB)
75
74 0
73 0 400 800 1200 1600
-5
72
1.4 1.45 1.5 1.55 1.6 -10
Supply voltage (V) Frequency (MHz)

Supplycurrentvs.operatingvoltage E4000gainvs.frequency(normalised)

20
IIP3 (dBm)
0
-100 -80 -60 -20 20 0
40
60
-80
RF input pow er (dBm)

IIP3vs.RFinputpower(E4000gainssettomaintain
1Vppdiffoutputswing)
August2010 Page15
E4000

0 0
0 500 1000 1500 2000
0 500 1000 1500 2000
-10 -5
-20 LNA gain

S11 (dB)
- 10
S11 (dB)
-30 =25dB
- 15
-40
- 20
-50
- 25
LNA gain
-60 =0dB
- 30
Freque ncy (MHz)
Frequency (MHz)
Return loss vs. frequency vs. LNA gain setting (75R Returnlossvs.frequencyvs.LNAgainsetting(50R
environment). environment)
0
0.00
-1400 500 600 700 800 900
Attenuation (dB)
0 5 10 15 20 -2
-20.00 Attenuation (dB)
-3
-4
-40.00 -5
-6
-60.00 -7
-8
-80.00 -9
-10
Frequency (MHz)
Frequency (MHz)
Programmable,basebandchannelfilterfrequency Programmable, RF filter frequency response,

response,(4.1MHzfiltercornerfrequencysettingis (666MHzsettingisshown).
shown)

-60
-701000 10000 100000 1000000
Phase noise (dBc/Hz)
-80
-90
-100
-110
-120
-130
Frequency offset from carrier (Hz)
Localoscillatorphasenoisevs.frequencyoffsetfrom
carrier
August2010 Page16
E4000

REGISTERMAP
Colour Explanation
Green Reserved register
Yellow User control register R/W
Purple User control register R

Blue User should not over-write default values
Bitnumber Address 6 5 4 3 2 1 0(LSB)

7(MSB)
0x00h Reserved PORdetect Standb RESET
Master2 Default=00000 =1aftera 1=normal 1=reset
reset. operation 0=normal
Write1to 0=standby operation
clear mode
register

0x01h Reserved
Master2 Default=00000000
0x02h Elonicsidentifier
0x05h Reserved E4000Clockselect
Inputclock Default=0000000 00=Crystalclocksource
(default)
01=DividedPLL
Donotwritetothisregister
0x06h Reserved Outputclockfrequency Clockoutput CMOSconfiguration
Reference Default=000 00=Cry talfreq1 logic Or
clock (default) 0=LVDS LVDSdrivestrength
01=Crystalfreq2 1=CMOS
10=Crystalfreq4 (default) See1.28
0x07h Reserved Inputclockfreqrange Frequencyband PLLlocked
Synth1 Default=000 00=1632MHz(default) 00=VHFII 1=locked
Alwayswrite00 01=VHFIII
10=UHF(default)
11=Lband
0x08h Reserved
Synth2 Default=00000000
0x09h Feedbackdivider/Z
Synth3 Seesection1.4
0x0ah SigmadeltaX(LSB)
Synth Seesection1.5
0x0bh SigmadeltaX(MSB)
Synth5 Seesection1.5
0x0dh Reserved Enable3 VCOoutputdivider/R
Synth7 Default=00000 phase Default=001
mixing Seesection1.6
0=disable
(default)
See1.7

August2010 Page17

E4000

Bitnumber Address 6 5 4 3 2 1 0
7
0x0eh Reserved VCOcal VCOrange VCOrange VCOcal VCOcalmode
Synth8 Default=00 warningflag lowflag. highflag update 00=autocaloff
Usershould Usershould Write1to 01=autocalon(default)
updateloop updateloop update 10=supervisormode
whena whena whenin 11=autocaloff
value1is value1is supervisor
read(bit2) read mode
(bit2)
0x0fh Reserved VCOrange
Synth9 Default=0000 Default=1000
0x10h Reserved RFfilterDefault=0000
filt1 Default=0000 Seesection1 19
0x11h Mixerfilter IF Cfilt r
filt2 Default=0000 Defaul =0000
Seesection1.21 Seesection1.22
0x12h Reserved Filter IFchannelfilter
filt3 Default=00 disable Default=00000
1=disable Seesection0
0=enable
(default)
See0
0x14h Reserved LNAgain
Gain1 Default=0000 00X0=5dB(default)
00X1=2.5dB
0100=0dB
0101=2.5dB
0110=5dB
0111=7.5dB
1000=10dB
1001=12.5dB
1010=15dB
1011=17.5dB
1100=20dB
1101=25dB
111X=30dB
Seesection1.13.1
0x15h Reserved Mixergain
Gain2 Default=0000000 0=4dB
(default)
1=12dBSee
1.15
0x16h Reserved IFstage4gain IFstage3gain IFstage2gain IFstage1
Gain3 Default=0 00=0dB01=1dB 00=0dB01=3dB(default) 00=0dB01=3dB gain
10=2dB(default) 10=6dB 10=6dB 0=3dB
11=3dB 11=9dB 11=9dB(default) 1=6dB(defa
Seesection0 Seesection0 Seesection0 ult)
See0
0x17h Reserved IFstage6gain IFstage5gain
Gain4 Default=00 000=3dB(default) 000=3dB(default)
001=6dB 001=6dB
010=9dB 010=9dB
011=12dB 011=12dB
100=15dB 100=15dB
Seesection0 Seesection0

August2010 Page18

E4000

7
0x1Ah LNAgain LNAgain LNAupdate Linearity Gaincontrolmode
AGC1 highflag lowflag Write1to mode Seesection1.12
Usershould Usershould updatein Seesection Default=0000
updateloop updateloop supervise 1.17.1
whena whena mode Default=1
value1is value1is
read(bit5) read(bit5)
0x1Bh LNAautonomouscontrolcalibrationvalue
AGC2
0x1Ch Receivedsignalstrengthindicator
AGC3 Seesection0
0x1Dh LNAautonomouscontrolHighthreshold
AGC4 WritethresholdvaluewhenE4000isinitialised
0x1Eh LNAautonomouscontrolLowthreshold
AGC5 WritethresholdvaluewhenE4000isinitialised
0x1Fh Reserved Reserved LNA LNAautonomouscontrolAveragingtime
AGC6 Default=0 Alwayswrite=00 calibration Default=0000
request See1.13.3
0x20h Reserved RFgain Mixerthreshold Mixergain
AGC7 Default=00 control See1.15.2 control
gainstep mode
size0= 1=auto
2.5dB
(default)
1=5dB
0x21h Sensitivity/Linearitymodeswitchpoint Sensitivity/
AGC8 Default=0101101(45dB) linearity
Seesection1.17 1 mode
control
1=auto
control
0=user
control
(default)
0x24h Reserved LNAgainenhancementlevel LNAgain
AGC11 Default=00000 Default=00 enhance
enable

0x25h Reserved Linearity Linearity
AGC11 Default=000000 monitor monitorflag
resetflag Donotwrite
Donotwrite tothis
tothis register
register
0x29h Reserved DCoffsetcal
DC1 Default=0000000 request
Write1See
section0
0x2Ah Reserved IchannelDCoffset
DC2 Default=00 Seesection0
0x2Bh Reserved QchannelDCoffset
DC3 Default=00 Seesection0
0x2Ch Reserved Qchanneloffsetrange Reserved Ichanneloffsetrange
DC4 Default=00 Seesection0 Default=00 Seesection0

August2010 Page19

E4000

7
0x2Dh Reserved Timevarying DCrange DCrange DCoffsetQ DCoffsetI
DC5 Default=000 DCoffset enable detector LUTenable LUTenable
range disables enable Default=1 Default=1
increment autorange 1=enable See1.27.1 See1.27.1
enable calibration (default)
Disable=0 (onlyduring Seesection
(default) initialcal) 0
Seesection
1.27.2

0x2Eh DCoffsetthreshold
DC6 Seesection1.27.2
0x2Fh Reserved IFcommonmodevoltageadjust
DC7 Default=00000 Seesection1.18

0x30h Reserved ZeroLNA. ZeroLNA
DC8 Default=000000 Donotwrite Donotwrite
tothis tothis
register register
0x50h Qrange00 DCoffsetQ00
QLUT0 Lookuptabledata Look uptabledata
Seesection1.27.1 Seesection1.27.1
0x51h Qrange01 DCoffset Q01
QLUT1 Lookuptabledata Lookuptabledata
Seesection1.27.1 Seesecti n1.27.1
0x52h Qrange10 DCo fsetQ10
QLUT2 Lookuptabledata Look uptabledata
0x53h Qrange11 DCoffsetQ11
QLUT3 Lookuptabledata Lookuptabledata
0x60h Irange00 DCoffsetI00
ILUT0 Lookuptabledata Lookuptabledata
ILUT1 Lookuptabledata Lookuptabledata
Seesection1 27.1 Seesection1.27.1
ILUT2 Lookup abledata Lookuptabledata
ILUT3 Lo kuptabledata Lookuptabledata
Seesection1 27.1 Seesection1.27.1
0x70h Reserved Timevarying Timevarying Timevarying TimevaryingDCoffsetI
Dctime1 Default=000 DCoffsetI DCoffsetI DCoffsetI channelmode
lowflag. highflag. channel 00=TimevaryingDCoffset
Usershould Usershould update. off
updateloop updateloop Write1to 01=TimevaryingDCoffset
whena whena updateloop on
value1is value1is supervisor 10=Supervisormode
read read mode 11=TimevaryingDCoffset
off

Seesection1.27.2

August2010 Page20

E4000

7
0x71h Reserved Timevarying Timevarying Timevarying TimevaryingDCoffsetQ
Dctime2 Default=000 DCoffset DCoffset DCoffset channelmode
Qlowflag. Qhighflag. Qchannel 00=TimevaryingDCoffset
Usershould Usershould update. off
updateloop updateloop Write1to 01=TimevaryingDCoffset
whena whena updateloop on
value1is value1is supervisor 10=Supervisormode
read read mode 11=TimevaryingDCoffset
off
Seesection1.27.2
0x72h TimevaryingDCoffsetthreshold
Dctime3 Seesection1.27.2
0x73h Reserved TimevaryingDCoffsettimercontrol
Dctime4 Default=00000 Seesection1.27.2
0x74h PWMupperthresholdGain0
PWM1 Default=00000011
Seesection1.17.3
0x75h PWMlowerthresholdGa n0
Seesection1.17.3
0x76h PWMupperthresholdGain1
Se section1.13.2
0x77h PWMlowerthresholdGain1
Seesection1 13.2
0x78h Reserved Quadgendriverbias
Bias Default=000000 Default=11
Referencecurrentcontrol
Seesection1.11
0x79h Rese ved Quadgenbias Dividerbias
Default=0000 Default=00 Default=00
Referencecurrentcontrol Referencecurrentcontrol
Donotwritetothisregister Donotwritetothisregister
0x7ah Clockoutputpowerdownkey
Writing10010110willpowerdownE4000clockoutput
Seesection0
0x7bh Cont olbit Channelfiltercalibrationvalue Channel
Alwayswrite Seesection0 filtercal.
0 Write1to
instructa
calibration
0x7dh Reserved I2Cregister
Default=0000000 address
address
increment
See1.3

August2010 Page21

E4000

7
0x7eh Writevalue=0x01htopermitaccesstosubsequentregisters
Key0

0x7fh Writevalue=0xfehtopermitaccesstosubsequentregisters
Key1

0x86h Configuresdigitalup/downgaincontrolmode
Ctrl1 0x50h(default)=PolarityA
0x51h=polarityB
0x87h ConfiguresMixer
Ctrl2 Write0x20hwhentunerisinitialised

0x88h ConfiguresMixer
Ctrl3 Write0x01hwhentunerisinitialised

0x9fh ConfiguresLNA
Ctrl4 Write=0x7fhwhentunerisinitialised

0xa0h ConfiguresLNA
Ctrl5 Write0x07hwhentunerisinit alised

0xa3h ConfiguresIFgain
Ctrl6 Default=0x21h.Ifrequired,write=0x10htoreduceIFgainby6dB(tooptimizesignallevelintoademodulator)
Ctrl8 Default=0x1ah.Ifrequired,write=0x06htoreduceIFgainby6dB(tooptimizesignallevelintoademodulator)
Ctrl10 Default=0xa6h.Ifrequired,write=0x64htoredu eIFgainby6dB(tooptimizesignallevelintoademodulator)

Note: Registers addresses above 0x80h should not be written to with the exception of those highlighted
above
August2010 Page22

E4000

DEVICEDESCRIPTION
1.1 TwoWire,I2CInterface
TheE4000usesatwowire,I2Ccompatibleserialinterface.Pins15(SDAT)and16(SCLK)areboth3.3V
tolerant,permittinginterfacingwith3.3VI2Cmasterdevices.
TheE4000isaslaveonlydevice,supportingsevenbitaddressing.Thedeviceaddresscanbeconfigured
usingtheA0&A1inputpins.Theaddressisconfiguredpertable1(Note:7and8bitaddressesarequoted.
The8bitaddressincludesthereadwritebit).
TheI2CdatalinerequiresapullupresistortoVDD(3.3Vtolerant).Thisresistorvalueshouldbe>4k7Ohms.
A1(Pin12) A0(Pin11) Deviceaddress(7 Deviceaddress(8 Deviceaddress(8

bit) bit)(write) bit)(read)
0 0 0x64h 0xc8h 0xc9h
0 1 0x65h 0xcah 0xcbh
1 0 0x66h 0xcch 0xcdh
1 1 0x67h 0xceh 0xcfh
Table1:Serialinterfacedeviceaddress
1.2 SerialInterfaceProtocol
Theserialprotocolsupportsserialwritesandreads,bothtoindividualandsequentialaddressestofacilitate
programmingspeed.Readorwriteoperationsareimplementedasshownbelow.

Figure2:SingleBytewrite

Figure3:Pagewrite
August2010 Page23
E4000

Figure4:Singlebyteread

Figure5:Sequen ialread

A dummy read or write command should be sent to the E4000 after the tuner is first powered on or is
reset.Thiswillnot beacknowledged butwill configure the E4000I2Cinterface.After thispointI2Cread
andwritecommandsbehavenormally.
Register0x7Dh[0]maybeusedtocontrolwhetherasequentialreadorwriteincrementsregisteraddress
betweeneachread.Toconfiguretocontinuousreadfromthesameregister setthisbit= 0.Thisfeature
maybeusefultoauserwhowishestocontinuouslyreadthesameregisterduringoperationofthetuner.
August2010 Page24
E4000

1.3 FrequencySynthesiser

Figure6:FrequencySynthesizerarchitecture

ThearchitectureoftheE4000Frequencysynthesizerisshowninfigure6.Thisgeneratesthelocaloscillator
whichisusedinthemixertodownconvertRFtobaseband.TheVCOoutputisdividedbyRtogenerate
thelocaloscillatorforthedownconversionmixer.
TheVCOoutputisalsopassedtothefeedbackdivider,whereitsfrequencyisdividedbeforebeingsentto
thephase/frequencydetector.ThesigmadeltadynamicallydithersthedivisionbetweenZand
alternativedividersettings.Thispermitsset ingofanonintegerdividervaluegivinghighaccuracyinthe
frequenciestowhichthelocaloscillatorcanbelocked.Thearchitectureofthisdividerensuresthatthe
localoscillatormaintainslowphasenoiseacrosstherangeofsettings.
ThephasedetectorcomparesthedividedVCOfrequencywiththereferenceoscillatorfrequencyand
generatesatuningvoltagetopulltheVCOtothecorrectfrequency.
Thedividerandsigmadeltavaluesneedtobesetaspertheformulae
fVCO=fOscillator*(Z+X/Y) (equation1)

And

fLO=fVCO/R (equation2)
WhereY=65536andfOscillatoristhecrystalfrequency(e.g.26MHz).ValuesR,X,YandZareconfigurable
usingthetunerserialinterface.
Togeneratea0HzIFfrequency,thelocaloscillatorfrequencyshouldbesetsothatitisthesameastheRF
frequency.TheVCOshouldbeoperatedwithintherangeof2600to3900MHz.
August2010 Page25
E4000

1.4 PLLFeedbackdivider(/Z)
The/Ndivideriscontrolledbyregister0x09h.
ForexampletosetN=99
Set0x09h=99(decimal)
1.5 X,Sigmadeltasetup
ThevalueofXisdefinedbyregisters0x0Ah[7:0](LSB)&0x0Bh[7:0](MSB).Thiscanbesetbetween0and
65535.
Forexample,tosetX=5041
(5041decimal=13b1hex)
Register0x0ah=b1h=177(decimal)
Register0x0bh=13h=19(decimal)
1.6 /RVCOoutputdivider
Theoutputdivider,R,issetaspertable2.Notethedifferenceinsettingswhenusingthreephasemixing
(describedinsection1.7).
Output divider /R Division (3 phase Division (3 phase

[2:0] mixingdisabled) mixingenabled)
0x0dh[2:0]
000 2 4
001 4 8
010 6 12
011 8 16
100 12 24
101 16 32
110 20 40
111 24 48

Table2:Outputdivider
1.7 Threephasemixing
Threephasemixingcombineshighspeedclockstocreatealocaloscillatorclockwithsloweredgespeeds.
Thisisusedtoreducethehighfrequencyharmonics,whichwhenoperatingatlowfrequencieswouldbe
withinthetunerbandwidth.Thisfeaturepreventsinterferersignalsmixingwithharmonicsofthelocal
oscillatorfrequency,increasingthedynamicrangeofthetuner..
ItisrecommendedthatthreephasemixingshouldbeusedforVHFoperationandnotforUHForLband
operation.Thisisenabledordisabledusingregister0x0Dh[3].Notetheeffectenablingthisfeaturehason
the/Rdivisionasshownintable2.
August2010 Page26
E4000

1.8 ExampleFrequencysynthesizerconfiguration
TotunetoanRFsignalof666MHz,andforazeroIFoutputfrequency,theLOfrequency=666MHz
ThepermittedVCOfrequencyrangeisbetween2600and3900MHz.
666MHziswithintheUHFfrequencyband.ForUHFband,3phasemixingshouldbeturnedoff.
Usingsection1.3,equation2andchoosingR=4fromtable11givesaVCOfrequencyof2664MHz,(choose
anacceptableVCOfrequencyrangewhileusingavalueofRthatispossibletoset).
0x0Dh=1

Usingsection1.3equation1andfora26MHzcrystalfrequency.
N+X/Y=fvco/foscillator=2664/26=102.4615385
N=102 (theintegerpartofthis)
0x09h=102(decimal)

X/Y=0.4615385 (theremainder)
SinceY=65536
X=30247=7627
0x0Ah=0x27h=39(decimal)
0x0Bh = 0x76h = 118 (decimal)

1.9 VCOCalibration
TheE4000VCOshouldbecalib atedafterafrequencychangeinordertooptimiseperformance.A
calibrationisinstructedbywriting1to0x0Eh[2].Afterbeinginstructedtocalibrate,theE4000willself
calibratewithouttheneedforuserintervention.0x0Eh[1:0]shouldbeset=01,turningonautocalibration.
TheE4000periodicallymonitorswhethertheVCOisoperatinginitsoptimumcondition.Ifeverrequired,
theE4000willrecalibratetomaintainoptimalVCOperformance.However,arecalibrationwillbearare
event.
August2010 Page27
E4000

1.10 E4000SignalPath

Figure7:BlockdiagramoftheE4000signalpath
TheE4000signalpathcontainsawidebandLNA(64MHzto1 7GHz).TheRFsignalisfiltered,reducingthe
effectoffaroutblockingsignals.Thesignalisthendownconvertedtobasebandbythemixer,withIandQ
phase channels generated. The IF signal is filtered to attenuate adjacent channel interferers. Signals are
thenamplifiedsuchthatlevelsareoptimalforsamplingbythebasebandsADCs.Tunergaincanbevaried
from2to99dBprovidingalargedynamicrangeofsignalreception.
TheLNAfrequencyresponseisoptimisedfordifferentfrequencybandsasdescribedinsection1.11.
Gains can be controlled by various methods, as described in section 1.12. These include on chip
autonomous control or baseband control using a PWM interface, digital up / down interface or using
registerwritesviathe 2Cserialinterface.
Filterscanbeconfiguredasdescribedinsection1.19to0.
UnwantedDCoffsetsintheIFgainpathareeliminatedasdescribedinsection1.25.
August2010 Page28
E4000

1.11 FrequencyBandSelection
Thefrequencybandshouldbeinitialisedaspertable3.ThisregisterconfigurestheLNAtohaveoptimum
gainatthefrequencyofoperation.
Band Register0x07h[2:1]
VHFII(64108MHz) 00
VHFIII(170240MHz) 01
UHF(default)(470858MHz) 10
L(14521680MHz) 11
Table3:Frequencybandselection
Whenselectingfrequencybandstheusershouldalsoconfigureregister0x78h[1:0].Thissetsbiascurrents
usedasreferences,suchthatthetunerisoptimizedforoperationinthedifferentfrequencybands.
Band Register0x78h[1:0]
VHFII(64108M) 11
VHFIII(170240M) 11
UHF(default)(470858MHz) 11
L(14521680MHz) 00
Table4:Frequencybandbiascurrentreferenceoptimisation
August2010 Page29
E4000

1.12 GainControl
Theoptimumgainsettingsrequiredforthedifferentelementsofthesignalpathwillvary,dependingon
theenvironmentinwhichthetunerisbeingused.Forexample,thereceivedsignalmaybeatalowpower
level.Ifso,highgainsarerequiredtoachievethetunernoisefigurethatgivesoptimumsensitivity.Or
theremaybeahighpowersignalreceived,inwhichcaseoptimumgainsmaybelowerasamplifier
linearity,ratherthannoise,maybethetunerlimitation.
TheE4000canbeconfiguredsuchthatgainsmaybecontrolledusingavarietyofmechanisms.TheLNA
gaincanbecontrolledautonomouslybythetunerbasedonthepowerlevelmeasuredusinganonchip
widebandpowerdetector.Alternatively,LNAgainsmaybecontrolledbasedonpowersmeasuredbya
basebandspowerdetector.TheE4000supportsPWMorI2Cserialinterfacecontrolinterfacesthrough
whichthebasebandcaninstructagainchangeasrequired.
IFgainupdatesmayalsobeinstructedusingaPWMorI2Cserialinterface.Inaddition,theIFgaincontrol
alsosupportsa2pindigitalstepup/downcontrolinterface.
ThemodeinwhichTunergainsarecontrolledcanbeconfiguredpertable5.Themodeofoperationshould
beselectedusingregister0x1Ah[3:0].
AGC_mode[3:0] AGCmode
0x1A[3:0]
0000 Serialinterfacecontrol
0001 IFPWMcontro LNAserialinterfacecontrol.
0010 IFPWMcontrol LNAautonomouscontrol
0011 IFPWMcontrol.LNAsupervisorcontrol
0100 IFserialinterfacecontrol.LNAPWMcontrol.
0101 IFPWMcontrol.LNAPWMcontrol.
0110 IFdigitalcontrol.LNAserialinterfacecontrol.
0111 IFdigitalcontrol.LNAautonomouscontrol.
1000 IFdigitalcontrol.LNAsupervisorcontrol.
1001 IFserialinterfacecontrol.LNAautonomouscontrol.
1010 IFserialinterfacecontrol.LNAsupervisorcontrol
Table5:Gaincontrol

1.13 LNAGainControl
It is recommended that the LNA gains are configured for different received power levels per figure 8.
Operation with the suggested settings maintains the optimum balance of noise figure and linearity for a
givenoperatingenvironment.
Two ranges are suggested the first is for the case where received power is seen to be increasing. The
second is for the case where received power is seen to be decreasing. This provides approximately 5dB
hysteresisandpreventsthegainfromchatteringduetominorfluctuationsinreceivedpower.Thepower
quotedisthewidebandpowerreceivedbythetuner.
August2010 Page30
E4000

LNA Gain thresholds
35
30
25
20
LNA Gain (dB)
15 Increasing power
10 Decreasing power
0
-50 -40 -30 -20 -10
5-
10-
Input Power (dBm)

Figure8:LNAgaincontrol
Whenusingautonomousorsupervisormodes,theRFgaincontrolwillautomaticallyfollowthisprofile.LNA
gainstepsizeisapproximately2.5dB.Ifdesired,theusercaninstructalargerstepsizetobeused(5dB).
Thisiscontrolledbyregister0x20[5].
1.13.1 LNASerialInterfaceGainControl
The LNA gain can be controlled using register writes via the serial interface. Gains are configured as per
table6.
LNAgain LNAgain(dB)
0x14h[3:0] (typical)
00X0 5

00X1 2.5

0100 0
0101 2.5
0110 5
0111 7.5
1000 10
1001 12.5
1010 15
1011 17.5
1100 20
1101 25
111X 30

Table6:LNAserialinterfacecontrol
August2010 Page31
E4000

1.13.2 LNAdigitalPWMgaincontrol
WhenoperatinginPWMgaincontrolmode,thetunerchangesLNAgainbasedonadigitalPWMsignal
generated by the user and received by the tuner at pin 22 Gain1. The user should generate this PWM
signalaspertable7,toindicatewhetherthetunerneedstoincrementordecrementLNAgainorleavethe
gainunchanged.
PWMdutycycle Tuneraction
50% Nochangeingain
>75% Incrementgain
<25% Decrementgain
Table7:PWMIFgaincontrolDutycycle
ThePWM dutycycleforwhich the tunerwilltreatthereceivedsignalasanincrementcanbemodified

using register 0x76h. Similarly, the duty cycle for a decrement case can be modified by register 0x77h.
Values to which these registers should be programmed vary depending on the period of the PWM input
signal.
ThetunerusesadigitalinputtosamplethePWMsignalreceived Thesignalisoversampled.Timingofthe
detectorissuchthattheE4000inputiscompatiblewithaPWMcontrolsignalwithperiodbetween2and
157us. When calculating the duty cycle, the E4000 will treat every 2 falling edges received as a signal
period.Timingisillustratedinfigure9.
Period
Switch Switch Switch point Switch
point point point
50% = No >75% = Increment
change
Figure9:LNAPWMgaincontroltimingdiagram
Aflowdiagramdetailingoperationofthiscontrolschemeisshowninfigure10.
Thismethodisnotcompatiblewithpulsedensitymodulationcontrolsignals.
August2010 Page32
E4000

Figure10:LNAPWMgaincontrolflowdiagram
1.13.3 LNAAutonomousGainControl
ThetuneriscapableofdeterminingwhentheLNAgainneedstobechangedandmodifyingthisgainsuch
thatoptimaloperationismaintained.Anonchipwidebandpowerdetectormeasuresthesignalamplitude
receivedbythetuner(inthebandwidth641700MHz).Thedetectorwillmeasureaveragereceivedsignal
poweroveraperiodoftimepertable8.Ifthevalueisaboveorbelowthethresholdlevelssetinregisters
0x1Dh and 0x1Eh, then the gain will be updated When changing gains, the control loop will step
sequentiallythroughthepossiblesettingsuntilthedesiredsignallevelisreached.
Register0x1F[3:0] AGCcontrolloopupdaterate(us)
0000 60
0001 120
0010 240
0011 480
0100 960
0101 1920
0110 3840
0111 7680
1000 15360
1001 30720
1010 61440
Table8:AGCcontrolloopupdaterate
1.13.4 LNASupervisorGainControl
Insupervisormode,theLNAcontrolloopoperatesasper1.13.3LNAautonomouscontrol.However,the
controlloopwillnotupdategainsuntilinstructedtobytheuser.
TheE4000willindicatewhetheraLNAgainchangeisrequiredbysettingregister0x1Ah[7or6]=1.Ifa
gainchangeisrequired,theusershouldwrite0x1Ah[5]=1whichwillinstructthelooptoupdategain.

August2010 Page33
E4000

1.14 ReceivedSignalStrengthIndicator(RSSI)
Thereceivedsignalstrengthmeasuredbythetunercanbeobservedbytheuserthroughregister0x1Ch.
TheRSSIwillfunctionacrossarangeofinputpowers(50to10dBm).Thisistherangeofinputpowers
overwhichtheLNAgainshouldbemodifiedtomaintainlinearity.Forreceivedpowerslowerthanthisthe
LNAshouldbesettomaximumgain.
TheRSSIindicatorcanbeaccessedwhenoperatinginautonomousorsupervisorgaincontrolmodebutnot
whenusingPWMorserialinterfacecontrol.
TheRSSIregisterisscaledvs.receivedpowerasperfigure11.
Figure11:RSSIdetectorregistervaluevs.detectorinputpower
Note:Thepowershowninfigu e11istheRMSinputpowertotheRSSIdetector.ThisrelatestotheE4000
inputpowerpertheformula
E4000inputpower=RSSIdetectorpowerLNAgain
1.15 MixerGainControl
1.15.1 MixerGainSerialInterfaceControl
TheMixermaybecontrolledusingregisterwritesviatheserialinterface.Gainsaresetaspertable9.The
mixer gain should be set high when a low signal level is received (<~ 35dBm) and set low when a high
signallevelisreceivedattheinputtothetuner(>~35dBm).TheE4000receivedpowercanbemonitored
usingtheRSSIindicator
Mixergain Mixergain(dB)
0x15h[0] (typical)
0 4
1 12
Table9:Mixergaincontrol
August2010 Page34
E4000

1.15.2 MixerGainAutonomousControl
TheMixermaybeconfiguredsuchthatagainchangeoccursautomaticallyastheLNAgainischanged.This
featureisenabledbysetting0x20h[0]=1.Register0x20h[4:1]shouldbeprogrammedwiththedesired
thresholdvalueforwhichtheuserwishesmixergaintochange.ThisthresholdcorrespondstoaLNAgain
valueasshownintable6.Itisrecommendedthattheuserconfigures0x20h=0x15h.Thiswouldmeanthat
themixergainswitchesstatewhenLNAgainissetto7.5dB.ForhigherLNAgains,Mixergain=12dB.For
7.5dBorlowergains,Mixergain=4dB.
SincetheLNAgaincontrolincludesHysteresis,themixergainwillnottogglearoundapointduetosmall
fluctuationsininputpower.

1.16 LNAGainenhancement
Itisrecommendedthatregister0x24hiswritten=5oninitializationofthetuner.ThiswillenabletheLNA
gain enhancement mode. This is an automated control feature that will ncrease the NA gain by an
additional 5dB when LNA and mixer are set to maximum gain levels. This mode s intended to optimize
tunernoisefigureincaseswheregainishigh,(smallsignalsarerece ved).TheLNAgainnumbersquoted
throughoutthisdocumentassumethatthisregisterisprogrammedtotherecommendedvalue.

1.17 IFGainControl
IFgainscanbecontrolledusingthemethodsdescribed nsections1.17.1to1.17.4.
1.17.1 IFgainLinearity/SensitivityMode
InsomecircumstancesitmaybepreferabletooptimisetheIFgainsfornoise(foroptimumsensitivity)or
linearity(largesignalhandling,suchasinthepresenceofanadjacentchannelinterferer).Theusercanset
whetherthetuneroptimisesgainsforoptimumsensitivityorlinearityusing0x1Ah[4].Themodemaybe
switchedbytheuserbasedonthetunersreceivedsignalpower(sensitivitymode<~60dBm)orbasedon
theuserdetectingthepresenceonanadjacentchannelinterferer.
AGCramp IFgainmode
0x1A 4]
0 Linearity
1 Sensitivity
Table10:IFgaincontrolmode
Alternatively,thetunercanbeconfiguredtoautomaticallyswitchbetweensensitivityandlinearitymodes.
Thisfeatureiscontrolledusingregister0x21h.Bits6to1canbeprogrammedtothetunergainatwhich
theuserwishesthedevicetoswitchbetweenlinearity&sensitivitymodes.Forexample,defaultsetting=
45dB.WhenLNA+mixer+IFgainis<45dB,thetunerwilloperateinlinearitymode.SomeHysteresisis
includedtopreventmodesswitchingaroundduetosmallfluctuationsinpower.
Automatedcontrolofthisgainoptimisationmodeisenabledbysetting0x21h[0]=1.
August2010 Page35
E4000

1.17.2 IFGainSerialInterfaceControl
IFstage1gain IFstage1gain(dB)
0x16h[0] (typical)
0 3
1 6

Table11:IFstage1gaincontrol
00 0
01 3
10 6
11 9
00 0
01 3
10 6
11 9

00 0
01 1
1x 2

000 3
001 6
010 9
011 12
1xx 15
August2010 Page36
E4000

000 3
001 6
010 9
011 12
1xx 15

August2010 Page37
E4000

Linearity Mode
Register0x16h Register0x17h IFStage1 IFStage2 IFStage3 IFStage4 IFStage5 IFStage6 TotalGain(dB)
0x7f 0x24 9 9 9 3 15 15 60
0x5f 0x24 9 9 9 2 15 15 59
0x3f 0x24 9 9 9 1 15 15 58
0x1f 0x24 9 9 9 0 15 15 57
0x5d 0x24 9 6 9 2 15 15 56
0x3d 0x24 9 6 9 1 15 15 55
0x1d 0x24 9 6 9 0 15 15 54
0x5b 0x24 9 3 9 2 15 15 53
0x3b 0x24 9 3 9 1 15 15 52
0x1b 0x24 9 3 9 0 15 15 51
0x59 0x24 9 0 9 2 15 15 50
0x39 0x24 9 0 9 1 15 15 49
0x19 0x24 9 0 9 0 15 15 48
0x5c 0x24 0 6 9 2 15 15 47
0x3c 0x24 0 6 9 1 15 15 46
0x1c 0x24 0 6 9 0 15 15 45
0x5a 0x24 0 3 9 2 15 15 44
0x3a 0x24 0 3 9 1 15 15 43
0x1a 0x24 0 3 9 0 15 15 42
0x58 0x24 0 0 9 2 15 15 41
0x38 0x24 0 0 9 1 15 15 40
0x18 0x24 0 0 9 0 15 15 39
0x50 0x24 0 0 6 2 15 15 38
0x30 0x24 0 0 6 1 15 15 37
0x10 0x24 0 0 6 0 15 15 36
0x48 0x24 0 0 3 2 15 15 35
0x28 0x24 0 0 3 1 15 15 34
0x08 0x24 0 0 3 0 15 15 33
0x40 0x24 0 0 0 2 15 15 32
0x20 0x24 0 0 0 1 15 15 31
0x00 0x24 0 0 0 0 15 15 30
0x40 0x23 0 0 0 2 12 15 29
0x20 0x23 0 0 0 1 12 15 28
0x00 0x23 0 0 0 0 12 15 27
0x40 0x22 0 0 0 2 9 15 26
0x20 0x22 0 0 0 1 9 15 25
0x00 0x22 0 0 0 0 9 15 24
0x40 0x21 0 0 0 2 6 15 23
0x20 0x21 0 0 0 1 6 15 22
0x00 0x21 0 0 0 0 6 15 21
0x40 0x20 0 0 0 2 3 15 20
0x20 0x20 0 0 0 1 3 15 19
0x00 0x20 0 0 0 0 3 15 18
0x40 0x18 0 0 0 2 3 12 17
0x20 0x18 0 0 0 1 3 12 16
0x00 0x18 0 0 0 0 3 12 15
0x40 0x10 0 0 0 2 3 9 14
0x20 0x10 0 0 0 1 3 9 13
0x00 0x10 0 0 0 0 3 9 12
0x40 0x08 0 0 0 2 3 6 11
0x20 0x08 0 0 0 1 3 6 10
0x00 0x08 0 0 0 0 3 6 9
0x40 0x00 0 0 0 2 3 3 8
0x20 0x00 0 0 0 1 3 3 7
0x00 0x00 0 0 0 0 3 3 6
August2010 Page38
E4000

Sensitivity mode
Register0x16h Register0x17h IFStage1 IFStage2 IFStage3 IFStage4 IFStage5 IFStage6 TotalGain(dB)
0x7f 0x24 9 9 9 3 15 15 60
0x5f 0x24 9 9 9 2 15 15 59
0x3f 0x24 9 9 9 1 15 15 58
0x1f 0x24 9 9 9 0 15 15 57
0x5f 0x1c 9 9 9 2 15 12 56
0x3f 0x1c 9 9 9 1 15 12 55
0x1f 0x1c 9 9 9 0 15 12 54
0x5f 0x14 9 9 9 2 15 9 53
0x3f 0x14 9 9 9 1 15 9 52
0x1f 0x14 9 9 9 0 15 9 51
0x5f 0x0c 9 9 9 2 15 6 50
0x3f 0x0c 9 9 9 1 15 6 49
0x1f 0x0c 9 9 9 0 15 6 48
0x5f 0x04 9 9 9 2 15 3 47
0x3f 0x04 9 9 9 1 15 3 46
0x1f 0x04 9 9 9 0 15 3 45
0x5f 0x03 9 9 9 2 12 3 44
0x3f 0x03 9 9 9 1 12 3 43
0x1f 0x03 9 9 9 0 12 3 42
0x5f 0x02 9 9 9 2 9 3 41
0x3f 0x02 9 9 9 1 9 3 40
0x1f 0x02 9 9 9 0 9 3 39
0x5f 0x01 9 9 9 2 6 3 38
0x3f 0x01 9 9 9 6 3 37
0x1f 0x01 9 9 9 0 6 3 36
0x5f 0x00 9 9 9 2 3 3 35
0x3f 0x00 9 9 9 1 3 3 34
0x1f 0x00 9 9 9 0 3 3 33
0x57 0x00 9 9 6 2 3 3 32
0x37 0x00 9 9 6 1 3 3 31
0x17 0x00 9 9 6 0 3 3 30
0x4f 0x00 9 9 3 2 3 3 29
0x2f 0x00 9 9 3 1 3 3 28
0x0f 0x00 9 9 3 0 3 3 27
0x47 0x00 9 9 0 2 3 3 26
0x27 0x00 9 9 0 1 3 3 25
0x07 0x00 9 9 0 0 3 3 24
0x45 0x00 9 6 0 2 3 3 23
0x25 0x00 9 6 0 1 3 3 22
0x05 0x00 9 6 0 0 3 3 21
0x43 0x00 9 3 0 2 3 3 20
0x23 0x00 9 3 0 1 3 3 19
0x03 0x00 9 3 0 0 3 3 18
0x41 0x00 9 0 0 2 3 3 17
0x21 0x00 9 0 0 1 3 3 16
0x01 0x00 9 0 0 0 3 3 15
0x44 0x00 0 6 0 2 3 3 14
0x24 0x00 0 6 0 1 3 3 13
0x04 0x00 0 6 0 0 3 3 12
0x42 0x00 0 3 0 2 3 3 11
0x22 0x00 0 3 0 1 3 3 10
0x02 0x00 0 3 0 0 3 3 9
0x40 0x00 0 0 0 2 3 3 8
0x20 0x00 0 0 0 1 3 3 7
0x00 0x00 0 0 0 0 3 3 6
August2010 Page39
E4000

1.17.3 IFGainDigitalPWMControl
WhenoperatinginPWMgaincontrolmode,thetunerchangesIFgainbasedonaPWMsignalgeneratedby
thebasebandandreceivedbythetuneratpin21Gain0.TheusershouldgeneratethisPWMsignalasper
table17,toindicatewhetherthetunerneedstoincrement/decrementIFgainorleavethisunchanged.
PWMdutycycle Tuneraction
50% Nochangeingain
>75% Incrementgain
<25% Decrementgain
Table17:PWMIFgaincontrolDutycycle
The duty cycle for which the tuner will treat the received signal as an increment can be modified using
register0x74h.Similarly,thedutycycleforadecrementcasecanbemodifiedbyregister0x75h.Values
towhichtheseregistersshouldbeprogrammedvarydependingontheperiodofthePWM nputsignal.
ThetunerusesadigitalinputtosamplethePWMsignalreceived Thesignalisoversampled.Timingofthe
detectorissuchthattheE4000inputiscompatiblewithaPWMcontrolsigna withperiodbetween2and
157us. When calculating the duty cycle, the E4000 will treat every 2 falling edges received as a signal
period.Timingisillustratedinfigure12.
Period
Switch Switch Switch point Switch
point point
point
50% = No >75% = Increment

change
Figure12:IFPWMgaincontroltimingdiagram
Aflowdiagramdetailingoperationofthiscontrolschemeisshowninfigure13.
Thismethodisnotcompatiblewithpulsedensitymodulationcontrolsignals.

August2010 Page40
E4000

Figure13:IFPWMgaincontrolflowdiagram
1.17.4 IFGainDigitalControl
ItispossibletocontrolIFgainusinga2pindigitalcontrolinterface.Thegainischangeddependingonthe
stateofPins21Gain0and22gain1.Gainsareincrementedordecrementedinstepsof1dB.Thedefault
truthtableisshowninTable18.
Digitalcontrol Tuneraction
Gain1/Gain0
00 Decreasegain
01 Holdgain
10 Holdgain
11 Increasegain
Table18:IFgaindigitalinterfacecontrol
Analternativelogicschemeisprovided.Thislogiccanbecanbeselectedbysetting0x86h=0x51h.Atruth
tableisshownintable19.
Digitalcontrol Tuneraction
Gain1/Gain0
00 Holdgain
01 Increasegain
10 Decreasegain
11 Holdgain
Table19:IFgaindigitalinterfacecontrol

Figure14detailstheflowdiagramthatshouldbefollowedwhenusingthisgaincontrolinterface.

Figure14:Digitalup/downgaincontrolinterfaceflowdiagram
August2010 Page41
E4000

Note: A no change condition must be sent between sequential increment or sequential decrement
commands.
Each state should be maintained for > 130ns in order for the E4000 to sample levels and instruct a gain
change.
1.18 OutputCommonModeVoltage
Thecommonmodeoutputvoltageofthetunerdefaultsto0.58V.ItispossibletoincreasethisDCvoltage
levelaspertable20.
Register0x2Fh[2:0] Common mode voltage

(mV)
000 580
001 650
010 650
011 700
100 850
101 900
110 900
111 950

Table20:Outputcommonmodevoltage
It may be possible to programme the tuner output common mode voltage level to match the Baseband
ADCcommonmodevoltagelevel,eliminatingtherequirementforDCblockingcapacitors.Ifthisfeatureis
useditshouldbenotedthattunerlinear tymaydegradeascommonmodevoltageisincreased.Itshould
alsobenotedthatinsomecircumstances,voltagesmayvarybyupto+/160mVvs.nominalvalue,(dueto
a combination of process / temperature variation and tuner DC offsets). If DC blocking capacitors are
removed,thebasebandADCwouldberequiredtotoleratethisvariation.
August2010 Page42
E4000

1.19 RFFilter
TheE4000willfilterthesignalattheLNA.Thisfilteringisconfiguredusingregister0x10haspertable21.
NotetheeffectoftheFreqband[1:0]settinginregister0x07h.Boththetypeoffilter(lowpassorband
pass)anditsbandwidtharechangeddependingonthefrequencybandused.
LNAfilter[3:0] 1dB Bandwidth of 1dB Bandwidth of Centre frequency Centre frequency

Register 0x10h lowpassfilter. lowpassfilter. ofbandpassfilter. ofbandpassfilter.
[3:0] (MHz) (MHz) (MHz) (MHz)

Freq band [1:0] = Freq band [1:0] = Freq band [1:0] = Freq band [1:0] =
00(VHFII) 01(VHFIII) 10(UHF) 11(L)

0000(default) 268 509 360 1300
0001 268 509 380 1320
0010 268 509 405 1360
0011 268 509 425 1410
0100 268 509 450 1445
0101 268 509 475 1460
0110 268 509 505 1490
0111 268 509 540 1530
1000 299 656 575 1560
1001 299 656 615 1590
1010 299 656 670 1640
1011 299 656 720 1660
1100 299 656 760 1680
1101 299 656 840 1700
1110 299 656 890 1720
1111 299 656 970 1750

Table21:RFFilterbandwidth
Figure15:RFfilterfrequencyresponseexamples
August2010 Page43
E4000

1.20 IFFilter
TheIFpathcontains3filteringsectionsthatareusedtoattenuateadjacentchannelinterferersandprovide
antialiasfilteringsuchthathighfrequenciesareeliminated.Optimumfiltersettingswillvarydependingon
thechannelbandwidth,adjacentchannelinterferersize,ADCsamplingspeedandADCantialiasfilter
response.
1.21 MixerFilter
Thisfiltersectionislocatedbetweenthemixerand1stIFgainstage.Filterattenuationisconfiguredasper
table22andfigure16.

Reg0x11h[7:4] 0.2dBBandwidth
0xxx 27
1000 4.6
1001 4.2
1010 3.8
1011 3.4
1100 3

1101 2.7

1110 2 3
1111 1.9

Table22:Mixerfiltersettings

Figure16:Mixerfiltersettings
August2010 Page44
E4000

1.22 IFRCFilter
ThisfilterislocatedbetweenearlyIFgainstages.Filterattenuationisconfiguredaspertable23andfigure
17.
Reg0x11h[3:0] 3dB bandwidth

(MHz)
0000 21.4
0001 21
0010 17.6
0011 14.7
0100 12.4
0101 10.6
0110 9
0111 7.7
1000 6.4
1001 5.3
1010 4.4
1011 3.4
1100 2.6
1101 1 8
1110 1 2
1111 1
Table23:IFRCfilterattenuation

Filtersetting0000
Filtersetting1111
Figure17:IFRCfilterresponse
August2010 Page45
E4000

1.23 IFChannelFilter
Thechannelfilterisasharprollofffilter,attenuatingadjacentchannelinterferers.Responseisaspertable
24andfigure18.
IFchannelfiltersetting Filtercornerfrequency IFchannelfiltersetting Filtercornerfrequency

Register0x12h[4:0] (MHz) Register0x12h[4:0] (MHz)
00000 5.5 10000 3
00001 5.3 10001 2.95
00010 5 10010 2.9
00011 4.8 10011 2.8
00100 4.6 10100 2 75
00101 4.4 10101 2.7
00110 4.3 10110 2.6
00111 4.1 10111 2.55
01000 3.9 11000 2.5
01001 3.8 11001 2.45
01010 3.7 11010 2 4
01011 3.6 11011 2.3
01100 3.4 11100 2.28
01101 3.3 11101 2.24
01110 3.2 11110 2.2
01111 3.1 11111 2.15
Table24:IFchannelfilter
Setting00000 Filter responses for

settings 11111, 10111,
01111, 01011, 00111,
00000areillustrated
Setting11111
Figure18:IFchannelfilterresponse
Thechannelfilterscornerfrequencymayvaryslightlyfromchiptochip.TheE4000containsacalibration
featurebywhichtheusercanoptimisethechannelfiltersetting.Toinstructafiltercalibrationtheuser
shouldwriteregister0x7Bh[0]=1.Thecalibrationwillcalculateavaluebasedonfrequencyerrorvs.
nominalcornerfrequency.Thisisstoredinregister0x7Bh[6:1].Scalingisasperfigure19.
Forexample,whenusinga26MHzreferenceclockavalueof45isobserved.Thisindicatesthatfilter
cornerfrequencyis10%lowerthannominalvalueintable24.Theusercanselecttheoptimumfilter
August2010 Page46
E4000

settingbasedonthisvalue.Ifacornerfrequencyof3.9MHzisdesired,theoptimumsettingwouldbethe
4.3MHz(nominal)filtersetting(4.3MHznominal10%=3.87MHzactual).
Calibrationvaluevs.filterscalingrequiredisshowninfigure19.Alternativelytheformulabelowcanbe
usedtocalculatethefilterscalingrequired.
Percentageerror=100(64xRCfiltercalvalue/Referenceclockfrequency(MHz))
Filter calibration
150
100
clock =
50
Filter % error
16MHz
0 clock =
-50 0 20 40 60 80 26MHz
clock =
-100
32MHz
-150
-200
RC filter value

Figure19:Filtercalibration
Ifdesireditispossiblefortheusernottousethefiltercalibration.Ifso,itisrecommendedthatthefilter
cornerfrequencyisset350kHzabovethewantedbandedge.
August2010 Page47
E4000

1.24 CombinedFilterResponse
Figure20illustrateshowthedifferentfiltersmaybecascadedtogether,producingthedesiredoverall
frequencyresponse.Theoptimumcombinationoffiltersettingswilldependontheusagescenario,(e.g.
receivedsignalchannelbandwidth,presenceofadjacentchannelinterferer,levelofbasebanddigital
filtering,basebandADCsamplingrateetc).

Figure20:CascadedFrequencyResponse
Theremaybescenarioswherethechannelfiltercanbedisabled.Forexample,whenthebasebanddetects
thatthereisnotalargeadjacentchannel nterfererpresent.Thisgivesapowersavingofapproximately
15mW.Thefiltermaybeenabledordisabledusingreg ster0x12h[5].Whenthechannelfilterisdisabled,
theusershouldensurethatotherfiltersaresetsuchthatrejectionissufficienttoprovideantialiasfiltering
forthesubsequentbasebandADCs.
1.25 DCOffsetCorrection
DCoffsetsareshiftsintheDCoperatingpointsofcircuits.Thesecanbecausedbyvariouseffectssuchas
localoscillatorinjectionorcircuitmismatches.Unlessmanaged,DCoffsetscanbeaprobleminZeroIF
receiversystemsastheycanreducetheavailableheadroomforsignalswingpotentiallydegradinglinearity.

Figure21:EffectofDCoffset
Tomanageoffsets,theE4000containsDCoffsetadjustmentfeatures.TheseoperateindependentlyonI
andQchannels.

August2010 Page48
E4000

1.26 DCOffsetControl
TherearethreemechanismsforDCoffsetcontrol;aninitialcalibration,alookuptableandatimevarying
trackingofDCoffset.Thesemechanismsaredescribedinsections0to1.27.2.TheDCoffsetisdependent
onthedeviceandonthefrequencyofoperation.TheE4000willperformacalibrationroutineinorderto
reduceoffsetstoalowlevel.Thisroutineisperformedafteraresetorcanbeinstructedtorunbytheuser.
Register0x29h[0]shouldbeset=1torequestaDCoffsetcalibration.
Note1:TheDCrangedetectorshouldbeleftenabledwhenperformingthiscalibration(defaultsetting).
(Register0x2Dh[2]).
ItisalsopossibletosetDCoffsetmanually.TheresolutionofIandQchanneloffsetcontrolsaresetusing
register0x2Ch.Highresolutiongivesveryfinevoltagestepsvs.lowresolution(formaximumtunergain
~40mVvs.300mVstepsize)butdoesnotcoveraslargeavoltagerange.Thehighestresolutionsetting
thatworksforagivendeviceisrecommendedasthiswillgivemostaccuratecontrol.Theoffsetitselfmay
beprogrammedusingregisters0x2Ahand0x2Bh.
1.27 DynamicDCOffsetCorrection
TheE4000gainwillbechangedasreceivedinputpowersvary ThiscanresultinDCoffsetschanging.The
E4000hastwomethodsofdynamictrackingtocompensateforthischange.
ForfastesttrackingofDCoffsetsitisrecommendedthatboththelookuptable(1.27.1)andtimevarying
DCoffsetcompensation(1.27.2)areused.ThelookuptablemovesDCoffsettoapproximatelythecorrect
levelwhilethetimevaryingcompensationsubsequentlyfinetunestoreachtheoptimumlevel.
1.27.1 LookUptable
Thefirstmethodofdynamictrackingistoprogramandusethelookuptablesinregisters0x50hto0x53h
and0x60hto0x63h.TheDCoffsetwillbechangedtothevaluesstoredintheseregistersasmixerandIF
stage0gainsarevaried.ThiscompensatesforanyvariationseeninDCoffsetasgainsarechanged.
Lookuptablesareenabledasdefault(register0x2Dh[1:0]).Ifthismethodisnotused,thisfeatureshould
bedisabled.Thenamingconventionfortheregistersissuchthatthefirstnumberreferstothemixergain
setinregister0x15h[0] ThenextnumberreferstoIFstage1gainwhichissetbyregister0x16h[0].I.e.DC
offsetQ00storesthevaluethatwillcompensateforQchannelDCoffsetandwillbeautomaticallyentered
intoregister0x2Bh[5:0]whengainsarechangedsuchthat0x15h[0]=0and0x16h[0]=0.Similarly
Qrange00referstotheQrangesettingsetinregister0x2C[5:4].
Ifthelookuptablefeatureisenabled,theusershouldpopulatethetableaspartofthetunerinitialisation.
TheusermustcyclethrougheachcombinedgainsettingofthemixerandIFgainstage1.Themixergainis
setinregister0x15h[0]andIFstage1gainissetbyregister0x16h[2:0].ADCoffsetcalibrationshouldbe
instructedateachgainsettingandtheresultingvaluesread.Thevaluesshouldthenbeprogrammedinto
thelookuptable.ItisrecommendedthatthisinitializationisperformedwithotherIFgainssetto
maximumvalues.
August2010 Page49
E4000

1.27.2 TimeVaryingDCOffsetCompensation
AfurthermethodoftrackingtimevaryingDCoffsetchangesistousetheE4000sDCoffsetmonitor.Thisis
enabledaspertable25.
Dynamic tracking Dynamic DC offset I Dynamic DC offset Q

mode channelmode[1:0] channelmode[1:0]
0x70h[1:0] 0x71h[1:0]
Off 00 00
Auto(recommended) 01 01
Supervisor 10 10
Off 11 11

Table25:TimevaryingDCoffsetcontrol
ThismonitordetectswhethertheDCoffsetgoesaboveorbelowathresholdsetby0x72h[7:0].Ifso,a
controlloopwillincrementordecrementtheDCoffsetvalueuntilanacceptablelevelisreached.The
controllooptimingissetbyregister0x73h[2:0].Bothregistersshouldremainsetatdefaultvalues.
Ifregister0x2Dh[3]isset=1,thisconfiguresthetimevaryingDCoffsettoallowthecontrollerto
incrementDCoffsetrange.IfaminimumormaximumlevelofDCoffseti reached,theDCoffsetrange
willbeincreased,allowingalargerrangeofoffsettrackingifrequired.
Asupervisorymodeofoperationisalsoprovidedinwhichthecontrollooprunsasdescribedabove.
However,thetunerwillnotchangeDCoffsetuntilinstructedtobytheuser.If0x70h[4or3]=1,anI
channelDCoffsetincrementordecrementisrequired.Writingavalueof1to0x70h[2]willinstructthe
E4000toperformthisupdate.Similarly Qchannelupdatescanbecontrolledusingregister0x71h.
ItisrecommendedthattimevaryingDCoffsetisusedtoensureaccuratecorrectionofDCoffsets.
August2010 Page50
E4000

1.28 ClockOutput
There are a number of clocking options for the E4000 set according to system and performance
requirements.

Figure22:E4000Masterclocksource,singleendedCMOSo differentialLVDSoutputs

Figure23:E4000slavemode,singleendedCMOSclockinputfrombasebandorotherclocksource

Figure24:E4000andbasebandprocessorhaveseparateclocks
August2010 Page51
E4000

TheE4000providesadifferentialoutputclockwhichcanbeusedtodriveotherdevicesinthesystem.The
clock is configured using register 0x06h. The logic levels of the clock output can be configured to 1.5V
CMOSorcustomlowpowerLVDSlevelsaspertable26.
Register0x06h[2] Clock output logic
level
0 LVDS

1 CMOS(default)

Table26:Clockoutputlogiclevels
Note1:InCMOSmode,bothnormalandinvertedoutputsareprovided.
Note 2: CMOS voltage levels are such that these can clock a baseband using the low power LVDS clock mode The baseband can subsequently
switchtoLVDSlogiclevelsorsingleendedCMOSclocklevels.
When operating in CMOS clock mode, the source impedance is approximately 1000R. If the load is high
impedancethenaterminationresistormayberequiredtopreventreflectionsduetomismatch.
Theoutputclockratecanbesetaspertable27.
Register0x06h[4:3] Clockoutput(MHz)
00 Crystalfreq1(default)
01 Crystalfreq2
10 Crystalfreq4
Table27:Clockoutputspeed
WhenoperatinginthelowpowerLVDSmode,theclockdrivercurrentcanbeselectedaspertable28.This
permits a reduction in power dissipation, depending on the differential termination presented to the
device,theinputthresholdsofthereceiverandonthelossesbetweenE4000clockoutputandinput.
Register0x06h[1 0] LVDSdrivestrength(mA)
00 1
01 2
10 3
11 4

Table28:ClockoutputLVDSdrivestrength

WhenoperatinginCMOSclockmode,theoutputcanbeconfiguredforsingleendedoperationaspertable
29
Register0x06h[1:0] CMOSclockconfiguration
00 Differential
01 Singleended
10 Singleended
11 Singleended

Table29:ClockoutputCMOSconfiguration
Ifitisnotrequiredbyotherdevices,theE4000clockoutputcanbedisabledusing0x7Ah.Awriteofvalue
10010110(96h)willdisabletheoutputclock.Anyothervaluewillleavetheclockenabled.Todisablethe
clock,itisalsorequiredtosettolowpowerLVDSclockmode.
August2010 Page52
E4000

Typically,theoutputclockwillinitialise100safterthetunerispoweredon.
1.29 ClockInput
It is possible to generate the E4000 clock using an external device and to input the clock into pin 28
CLOCKIN.Thisisanalternativeclockconfigurationmodetotheonchiposcillatordescribedinsection0.
IfaclocksignalispresentthiswillbedetectedbytheE4000andtheonchiposcillatorwillbeturnedoff.
aTheinputclocksourcemusthaveaminimumDCvoltagelevelof0.7V.Thispinwillnottolerate3.3Vlogic
inputs. If it is desired to use a 3.3V logic signal to clock the tuner then a pot ntia divider should be
connected externally to the tuner to reduce voltage swing. Clock input frequency should be within the
range16to30MHz.Clockinputjittershouldbe<5psRMStoavoidreductionintunerperformance.
1.30 Reset
Inresetmodeallregistersareresettotheirdefaultconditionsandalldigitalstatemachinesinitialised.The
chipcanbeinstructedtoperformaresetusingtheI2Cregister0x00h[0].Thisregisterisselfclearing.Also,
theE4000willmonitorthesupplyvoltage.Ifthisdropsbe ow0.8Vforlongerthan100ns,aresetwillbe
appliedautomatically.
Register0x00h[2]containsapoweronresetdetector.TheE4000willsetthisto1afterpoweruporaftera
resetoccurs.Writing1tothisbitcausestheregistertoclear.Thiscansubsequentlybereadtodetermine
whetherthetunerhasundergoneareset.
August2010 Page53
E4000

1.31 PowerSaveModes
1.31.1 PowerDownMode
ThedeviceenterspowerdownmodeunderthecontrolofthePDNBinput(pin14).Inpowerdownmode
alltheanaloguecircuitsaredisabledandclocksstopped.TheclockoutputsandCrystaloscillatorpinsdo
notfunction.TheE4000willbeoperational20msafterthepowerdowninputgoeshigh,Tinit_pd.
PDNB
IVOUTP/N,
QVOUTP/N
t
Tinit_pd

Figure25:PDNBStartUpTiming
1.31.2 StandbyMode
ThedeviceentersstandbymodeunderthecontroloftheSTBYBinput(pin13).Alternatively,thiscanbe
controlledusingtheI2Cregister0x00h[1].
Instandbymodemuchoftheanaloguecircuitryisdisabled.However,theclockoutputandserialinterface
are left running. After exiting s andby mode, the tuner will configure as it was set before the standby
occurred.ThestandbymodeisintendedfortimeslicinguseinDVBHapplications
TheE4000datapathwillbeoperationa 2msaftertheSTBYBinputgoeshigh,Tinit_stby.
STBYB
IVOUTP/N,
QVOUTP/N
t
Tinit_stby(2ms)

Figure26:STBYBStartUpTiming
August2010 Page54
E4000

1.32 Initialisation
Crystal oscillator enabled

Tuner output clock
synthesizer and data

I2C communications
path operational
avalailable
Frequency
Power applied
enabled

Figure27:Typicalinitialisationtimeline
The tuner will typically take around 2ms from powe being applied to being fully operational. A clock
outputwilltypicallybeavailableafter100us.I2Ccommunicationsarepossibleafter110us.
Frequency synthesizer and data path operational is defined as he point where the E4000 initialisation is
completebutdoesnotincludetheuserconfigurationofthetuner,(e.g.gaincontrol).
Whensupplydomainsareconnectedtogethernopowersupplysequencingisrequired.However,ifauser
decides to separate the tuners different supply domains, care should be taken with supply sequencing.
AVDDshouldbepresentwhenPLL_VDDisturnedon.IFVDDshouldberampedafterothersupplies.
August2010 Page55
E4000

APPLICATIONINFORMATION
TUNER DVDD (+1 5V) TUNER AVDD (+1.5V)
L6 L1 L2
100nH 100nH 100nH
32
AVDD
25 31
TUN_DVDD PLL_VDD
C10 9
IFVDD
100pF 27 8
TUN_DGND1 LNAVDD
26
TUN_DGND0
L3
100nH C3 C2 C5 C11 C12
100pF 100nF 100pF 100pF 100pF
Tuner
Ground 1
AGND0
7
LNAGND2
4 L4 L5
RFSHIELD
100nH 100nH
FIT OPTION 6
LNAGND
28 10
CLOCK N CLOCK N FGND
30
PLL_GND
29 Tuner
XTAL Ground
C9
20
IVOUTP IVOUTP
00nF
C8
CONNECT 19
IVOUTN IVOUTN
TO LNAGND
100nF
C4 IF
RF 5
RFIN_1 RFIN_1 OUTPUTS
NPUT
100pF
C7
18
QVOUTP QVOUTP
100nF
21 C6
GAIN0 GA N0 17
AGC QVOUTN QVOUTN
CONTROL 100nF
INPUTS 22
GAIN1 GA N1
1 24
I2C A0 A0 CKOUTP CKOUTP
ADDRESS
ELECT 12 A1 23
A1 CKOUTN CKOUTN
15
MICRO SDAT SDAT
3
CONTROL REXT
I/F 16 2
SCLK SCLK VBG
14 C1 R1
PDNB PDNB 10nF 10k
HARDWARE
CONTROL
I/F 13
STBYB STBYB Tuner
Ground
IMPORTANT NOTES
1. E4000 metal paddle (bottom of package) should be connected to TUNER GROUND
2. Pins 4, 6, 7 should be connected to a common LNAGND plane, separate from the tuner ground plane
3. C6,7,8,9 Optional dependent on ability to match output common mode voltage to input common mode
voltage of baseband demodulator input

August2010 Page56
E4000

PACKAGEDESCRIPTION

CommonDimensions
Symbol Minimum Nominal Maximum
A 0 85 0 90 1.0
A1 0 0.0 0.05
A3 0.20ref
D 4.90 5.0 5.1
D1 3.5
D2 3.2 3.3 3.4
E 4.90 5.0 5.1
E1 3.5
E2 3.20 3.30 3.40
L 0.35 0.40 0.45
L1 0.1
b 0.18 0.23 0.30
N 32
Tolerances for
e 0.50 Form & Position
Symbol Notes
k 0.20 aaa 0.15
R bmin/2 bbb 0.10
T 0.15 ccc 0.10

August2010 Page57
E4000

REVISIONHISTORY
Changed
Date Release DescriptionofChanges
Pages
10Dec08 1v0 Preliminarytechnicalrelease
26Mar09 2v0 Updatedparametricdata
21Jan10 2v1 Updatedexternalpackageandcomponentdiagram
27Jan10 2v2 Partnumberupdatedwithdrypackoption 5
Updated to preproduction status, updated component
27April10 3v0
diagram
26May10 3v1 Updatedpinnames
19August
4v0 UpdatedtoProductionreleasestatus
10

August2010 Page58
E4000

LEGALNOTICES
Productinformationiscurrentasofpublicationdate.ElonicsLtd(Elonics)productsandservicesaresold
subject to Elonics terms and conditions of sale, delivery and payment supplied at the time of order
acknowledgement.
Elonicswarrantsperformanceofitsproductstothespecificationsineffectatthedateofshipment.Elonics
reserves the right to make changes to its products and specifications or to discontinue any product or
servicewithoutnotice.Customersshouldthereforeobtainthelatestversionofrelevantinformationfrom
Elonicstoverifythattheinformationiscurrent.
TestingandotherqualitycontroltechniquesareutilisedtotheextentElonicsdeemsnecessarytosupport
itswarranty.Specifictestingofallparametersofeachdeviceisnotnecessarilyperformedunlessrequired
bylaworregulation.Inordertominimiserisksassociatedwithcustomerapplications,thecustomermust
useadequatedesignandoperatingsafeguardstominimiseinherentorproceduralhazards.Elonicsisnot
liable for applications assistance or customer product design. The customer is solely responsible for its
selection and use of Elonics products. Elonics is not liable for such selection or use nor for use of any
circuitryotherthancircuitryentirelyembodiedinaElonicsproduct.Elonicsprodu tsarenotintendedfor
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Elonicsdoesnotgrantanylicence(expressorimplied)underanypatentright,copyright,maskworkrightor
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Any representations made, warranties given, and/or liabilities accepted by any person that differ from
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August2010 Page59

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E4000

Parameter Description Min Typ Max Units

Parameter Min Typ Max Units

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF

Parameter Symbol Min Max Units

Supply current (mA)

Supply voltage (V) Frequency (MHz)

RF input pow er (dBm)

-20 LNA gain

Programmable,basebandchannelfilterfrequency Programmable, RF filter frequency response,

Bitnumber Address 6 5 4 3 2 1 0(LSB)

A1(Pin12) A0(Pin11) Deviceaddress(7 Deviceaddress(8 Deviceaddress(8

Output divider /R Division (3 phase Division (3 phase

ThePWM dutycycleforwhich the tunerwilltreatthereceivedsignalasanincrementcanbemodified

50% = No >75% = Increment

Register0x2Fh[2:0] Common mode voltage

LNAfilter[3:0] 1dB Bandwidth of 1dB Bandwidth of Centre frequency Centre frequency

Reg0x11h[3:0] 3dB bandwidth

IFchannelfiltersetting Filtercornerfrequency IFchannelfiltersetting Filtercornerfrequency

Setting00000 Filter responses for

Dynamic tracking Dynamic DC offset I Dynamic DC offset Q

Crystal oscillator enabled

synthesizer and data

TUNER DVDD (+1 5V) TUNER AVDD (+1.5V)

Reproduction of information from Elonics datasheets is permissible only if reproduction is without

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