RAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM1 is
port ( clk : in std_logic;
enr : in std_logic; --enable read,should be '0' when not in use.
enw : in std_logic; --enable write,should be '0' when not in use.
addr_in : in std_logic_vector( 15 downto 0);
addr_out : in std_logic_vector( 15 downto 0);
dataout : out std_logic_vector(3 downto 0); --output data
datain : in std_logic_vector (3 downto 0) --input data

);
end RAM1;
architecture ram of RAM1 is
type memory_type is array (0 to 15) of std_logic_vector(3 downto 0);
signal mem : memory_type ;
begin
process (clk)
begin
if clk'event and clk = '1' then
if (enw = '1') then
mem( conv_integer( addr_in)) <= datain ;
elsif(enr ='1') then
dataout <= mem( conv_integer( addr_out)) ;
end if ;
end if;
end process;
end ram;

Results:
 ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity simple_alu is
port( Clk : in std_logic; --clock signal
A,B : in signed(7 downto 0); --input operands
Op : in unsigned(2 downto 0); --Operation to be performed
R : out signed(7 downto 0) --output of ALU
);
end simple_alu;

architecture alu of simple_alu is

--temporary signal declaration.

signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0');

begin

Reg1 <= A;
Reg2 <= B;
R <= Reg3;

process(Clk,Op)
begin

if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle.
case Op is
when "000" =>
Reg3 <= Reg1 + Reg2; --addition
when "001" =>
Reg3 <= Reg1 - Reg2; --subtraction
when "010" =>
Reg3 <= not Reg1; --NOT gate
when "011" =>
Reg3 <= Reg1 nand Reg2; --NAND gate
when "100" =>
Reg3 <= Reg1 nor Reg2; --NOR gate
when "101" =>
Reg3 <= Reg1 and Reg2; --AND gate
when "110" =>
Reg3 <= Reg1 or Reg2; --OR gate
when "111" =>
Reg3 <= Reg1 xor Reg2; --XOR gate
when others => NULL;
 end case;
end if;

end process;

end alu;

output:
 Stack
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity stack is
port( Clk : in std_logic; --Clock for the stack.
Enable : in std_logic; --Enable the stack. Otherwise neither push nor pop will happen.
Data_In : in std_logic_vector(15 downto 0); --Data to be pushed to stack
Data_Out : out std_logic_vector(15 downto 0); --Data popped from the stack.
PUSH_barPOP : in std_logic; --active low for POP and active high for PUSH.
Stack_Full : out std_logic; --Goes high when the stack is full.
Stack_Empty : out std_logic --Goes high when the stack is empty.
);
end stack;
architecture Behavioral of stack is
type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0);
signal stack_mem : mem_type := (others => (others => '0'));
signal stack_ptr : integer := 255;
signal full,empty : std_logic := '0';
begin
Stack_Full <= full;
Stack_Empty <= empty;

--PUSH and POP process for the stack.

PUSH : process(Clk,PUSH_barPOP,Enable)
begin
if(rising_edge(Clk)) then

--PUSH section.
if (Enable = '1' and PUSH_barPOP = '1' and full = '0') then
--Data pushed to the current address.
stack_mem(stack_ptr) <= Data_In;
if(stack_ptr /= 0) then
stack_ptr <= stack_ptr - 1;
end if;
--setting full and empty flags
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = 255) then
full <= '0';
empty <= '1';
 else
full <= '0';
empty <= '0';
end if;
end if;

--POP section.
if (Enable = '1' and PUSH_barPOP = '0' and empty = '0') then
--Data has to be taken from the next highest address(empty descending type stack).
if(stack_ptr /= 255) then
Data_Out <= stack_mem(stack_ptr+1);
stack_ptr <= stack_ptr + 1;
end if;
--setting full and empty flags
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = 255) then
full <= '0';
empty <= '1';
else
full <= '0';
empty <= '0';
end if;
end if;
end if;
end process;
end Behavioral;

output:
 Queue
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo is
port ( clk : in std_logic;
enr : in std_logic; --enable read,should be '0' when not in use.
enw : in std_logic; --enable write,should be '0' when not in use.
dataout : out std_logic_vector(7 downto 0); --output data
datain : in std_logic_vector (7 downto 0); --input data
empty : out std_logic; --set as '1' when the queue is empty
full : out std_logic --set as '1' when the queue is full
);
end fifo;

architecture Behavioral of fifo is

type memory_type is array (0 to 255) of std_logic_vector(7 downto 0);
signal memory : memory_type :=(others => (others => '0')); --memory for queue.
signal readptr,writeptr : std_logic_vector(7 downto 0) :="00000000"; --read/write pointers.
signal error:std_logic;
begin
process(clk)
begin
if(clk'event and clk='1' and enr ='1') then
dataout <= memory(conv_integer(readptr));
error <= '0';
readptr <= readptr + '1'; --points to next address.
end if;
if(clk'event and clk='1' and enw ='1') then
memory(conv_integer(writeptr)) <= datain;
writeptr <= writeptr + '1'; --points to next address.
end if;
if(readptr = "11111111") then --resetting read pointer.
readptr <= "00000000";
end if;
if(writeptr = "11111111") then --checking whether queue is full or not
full <='1';
writeptr <= "00000000";
else
full <='0';
end if;
if(writeptr = "00000000") then --checking whether queue is empty or not
empty <='1';
else
 empty <='0';
end if;
end process;
end Behavioral;

OUTPUT: