PH 411 Physics Laboratory I (Electronics)

Instruction Manual

Index
Page No

Experiment 1 Transistor characteristics-BJT & FET 4

Experiment 2 Common Emitter (CE) Amplifier 7

Experiment 3 Rectification of AC signal 8

Experiment 4 Operational Amplifier Circuits I 10

Experiment 5 Operational Amplifier Circuits II 12

Experiment 6 Oscillator Circuits 14

Experiment 7 Logic Gates 16

Experiment 8 Digital Circuits I 19

Experiment 9 Digital Circuits II 22

Experiment 10 Microprocessor 8085 24

DEPARTMENT OF PHYSICS
INDIAN INSTITUTE OF TECHNOLOGY, GUWAHATI
July-November 2010
General Instructions to Students

1. On the very first day of the lab familiarize yourself with the power supply, function
generator, oscilloscope, bread board, and digital multimeter (DMM). You may request for
the copies of respective manual. You may also request the Teaching Assistant or the
instructor to guide you in learning these basic operations.

2. With the help of DMM learn to check the diode and transistors and to measure the value of
resistance.

3. The instruction manual provides the necessary information to perform the experiments.
However alternate circuits exist for most cases and students are encouraged to try out circuits
other than given in this manual (with prior permission from the instructor). The procedure
given is brief. Instructions given in italics are for self-study. Do try them if you want
proficiency in electronic circuitry.

4. Before attending the lab read the instruction manual THOROUGHLY and
CAREFULLY for analyzing the circuits to be used. You should consult any of the good
text or reference books on the subject in advance. This will help you to have tentative
estimates of the voltages and currents you are going to handle and enable you to set the
measuring instrument without trouble.

5. Derive the relevant formula or workout the relevant waveforms expected from the
experiment.

6. You should bring with you sufficient number of A4 size white papers, graph sheets, tracing
paper, for compiling the report and other stationery items required for data recording and
analyses.

7. The format of the report should be:

(a) Name Roll No. Date of Experiment

(b) Experiment title:
(c) Objective/Aim:
(d) Formulas, if any, with brief description
(e) Equivalent Circuit(s) if necessary
(f) Expected waveform as a function of input if applicable
(g) Observation Table(s)
(h) Input/Output waveform traces wherever necessary
(i) Graph(s) with proper labeling
(j) Calculations, if any
(k) Summary of results
(l) Brief discussion of results
(m) Suggestion(s) / New circuit idea pertaining to the experiment / Specific precautions

8. You are expected to come prepared with points (a) to (f) of above and get it signed by the
instructor before starting the experiment. Five marks are reserved for the same.

9. You have to complete the report and submit in your FOLDER FILE on the scheduled date of
experiment

10. Observations should be signed by either TA or the instructor available

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11. The performance in this course will be evaluated on the basis of DAY-to-DAY lab
activities, a theory exam / Quiz, and the final end-semester exam.

Lab reports (Daily) – 40 Marks

Theory / Quiz – 20 Marks
End Sem Exam – 40 Marks

12. Any kind of feedback on the improvement of this course is always welcome.

With best wishes,

Dr. Dipak Kr Gowsami

Dr Agam Prakash Vajpeyi

(Instructors – PH 411)

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 1. Transistor characteristics – BJT & FET

Aim: 1. To study the input and output characteristics of a PNP/ NPN transistors in common
base OR common emitter configurations.
2. To obtain the drain characteristics of a JFET.

Equipment: Power Supply (0-15V), DMM’s (0 to 15V) and components.

Circuit Diagrams:

Fig: 1.1 Common Base Configuration of PNP transistor

Fig: 1.2 Common Emitter Configuration of PNP transistor

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 Fig: 1.3 JFET – circuit for drain characteristics

Observation:

1. Using the given PNP/NPN transistor make the CB/CE circuit as shown in Fig. 3.1/3.2. Before
starting the experiment, adjust the power supply such that IE is in the measurable mA range with
VEE=1V. Set both the voltage sources VCC and VEE to 0 V. Make sure that both IE and IC are
zero. If IE is not zero, short the emitter-to-base terminal. Under this condition, vary the
collector terminal voltage VCC step by step from 0 to 10V. For each VCC setting, measure the
collector current IC and collector-to-emitter voltage VCB. Tabulate the readings. Repeat
measurement for different values of emitter current say IE =5, 10, 15, 20 mA etc. The emitter
current IE can be set by varying the emitter bias VEE to a maximum extent of 2V. Plot IC VS VCB
for different IE.

2. To study the input characteristics of the CB configuration given in Fig. 3.1, set both the
voltage sources VCC and VEE to zero. By varying IE from 0 to 30 mA in steps, record the
emitter-to-base voltage VEB. Tabulate IE versus VEB data. Variation of IE is possible by varying
the emitter source voltage VEE. Repeat the above measurements for different values of collector-
to-base voltage VCB (say, 0 to 10V) by varying VCC in steps. Plot the input characteristics (VEB
versus IE) for different values of VCB . From the plots determine the current gain α.

3. Make the common emitter (CE) circuit as shown in Fig. 3.2. Measure the output
characteristics i.e. IC versus VCE for different values of base currents IB = 0, 0.05, 0.1, 0.15, 0.2
mA. Do not exceed VCE beyond 10V. Similarly measure the input characteristic IB versus VBE
for VCE =0, 0.3, 0.4, 0.6, 0.8 and 1V. Plot the input and output characteristic curves for CE
configurations. From the plots determine the current gain β. Draw the static load line and
determine the Q point. Obtain transfer characteristics ie., IB vs. IC and determine current gain β.

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4. To study the I-V characterization of the JFET, make the circuit as shown in Fig.3.4. Initially
set VGS to zero, by shorting the gate-to-source terminals or by setting VGG=0. By varying the
bias voltage VDD from 0 to 15V in steps, measure the drain current ID as a function of the
voltage drop across drain to source, VDS. Repeat the above ID versus VDS measurements for
different values of VGS namely VGS = + 0.5, -0.5, -1, -1.5, -2.0 (negative sign implies the reverse
biasing of gate terminal). Plot ID versus VDS for different values of VGS. Determine the pinch-
off voltage from the plots and the safe limit of VDS.
Compile your results and discuss the properties of the CB OR CE configurations from data
obtained from your experiments.

Try out:
1. Repeat the transistor characteristic measurements using an NPN transistor. Remember to
appropriately bias the E-B and C-B terminals.
2. Single stage CE amplifier.

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 2. Common Emitter (CE) Amplifier

Aim: To (i) calculate Gain of the amplifier (ii) find out the clipping voltages for positive and
negative polarity peaks of the output signal, (iii) study the frequency response to calculate
bandwidth for sinusoidal, square and triangular waves, (iv) compare the input and output
frequency spectrum.
Vcc
15V

R1 RC
470k 4.7k C2
22uF
+
C1
C
V1
22uF
+ B Q1
2N2222 RL
-20m/20mV
4.7k
E
R2 RE
1kHz 33k 220

Fig. 2.1. CE Amplifier

Procedure:

1. Connect the input sinusoidal signal at point B as shown in Fig. 2.1 using DC blocking
capacitor. Connect load resistance at C with another DC blocking capacitor as shown in
the circuit to take output across the load.
2. Connect input and output signal to the oscilloscope. Calculate the gain of this amplifier
by taking the ratio of the output and the input amplitude. Make sure that both the input
and output sine waves are not clipped or distorted in any way. If they are reduce the
amplitude of the input sine wave until nice clean looking sine waves are present at both
input and output terminals. Also note the polarity of output sine wave relative to the
applied input signal.
3. Slowly increase the amplitude of the input sine wave until the output sinusoidal wave
begins to clip. Note the voltage at which clipping is on the positive or negative polarity
peaks.
4. Keep increasing the input voltage until the other polarity peak of the sine wave output
begins to clip and not down the voltage at which it occurs.
5. Tabulate the variation of voltage gain with frequency of the input sinusoidal, square and
triangular waves and plot frequency vs gain curve. Calculate the bandwidth and lower
and upper cut off frequency.

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C
 3. Rectification of AC signal

Aim: To construct Half wave, Full wave and Bridge Rectifier circuits using diodes.

Equipment & components required: Step down transformer with centre tap (12-0-12V) or
(9-0-9V), C.R.O., diodes, capacitor and resistors, regulator chips (IC 7809 and IC 7909).

Circuit diagrams:

Fig: 3.1 Full Wave Rectifier Circuit

Fig: 3.2 Full Wave Rectifier with Capacitive filter

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 Fig: 3.3 Regulated Dual Power Supply using bridge rectifier circuit

IC 7809 3-pin voltage regulators IC 7909

Pin 1: in 78xx – positive regulators Pin 1: grd
Pin 2: grd 79xx – negative regulators Pin 2: in
Pin 3: out Pin 3: out
1 2 3 12 3

Procedure:

1. Make the full wave rectifier circuit as shown in the fig.3.1. Measure the input peak to
peak voltages using the oscilloscope. Trace the output signal across the resistor using
the oscilloscope. Measure the peak voltage of output signal.

2. To study the effect of capacitive filter, make the circuit as shown in fig.3.2. Trace the
output both with the capacitor disconnected and connected. Measure the dc voltage
across the output using a voltmeter. Discharge the capacitor before every use.

3. Connect the dual power supply circuit as shown in fig. 3.3. 78xx and 79xx series IC’s
are positive and negative voltage 3-pin regulators respectively. Measure the wave forms
at the input and output (both the positive and negative voltages).

Try Out:
1. Try to modify the circuit in fig. 3.3 to produce on output that gives variable + Ve or –Ve
regulated outputs. Read the manufacturer’s manual on 3-pin regulator chips.

2. Construct and study a voltage doubler circuit

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 4. Operational Amplifier Circuits I
Aim: To construct (a) inverting OR non inverting amplifier and perform (b) addition, (c)
subtraction of analog signals using an operational amplifier.

(Note: Draw all the equivalent circuits and work out the expressions for the output
voltages and the voltage gain of the amplifier, final values of gain can be worked out
after measuring the actual resistances used).

Circuit diagram:

Fig: 4.1 Non inverting Amplifier

Fig: 4.2 Inverting Amplifier

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 Fig: 4.3 Adder circuit Fig: 4.4 Subtractor Circuit

Observations:
Before attempting to fabricate the circuits given above, measure the op amp. parameters
such as the off-set voltages, CMRR etc. Compensate for the off-sets and then proceed. The
relevant circuits are given in Millman & Halkias or Gayakwad’s book.

1. Make the non-inverting amplifier circuit as shown in fig.4.1. Give a d.c. input of say 2 V
and measure V0. Repeat the above step for different R2/R1 ratio and verify the function of
the non-inverting amplifier as a scale changer. Now give a sinusoidal input signal ‘Vi’
with frequency 1 kHz and peak to peak voltage 5 V. Trace the input and output signals.
Measure the peak to peak voltage of output signal V0. Repeat for various input
frequencies.

2. Make the inverting amplifier circuit as shown in fig. 4.2. Give a d.c. input of say 2 V
and measure V0. Repeat the above step for different R2 and R1 values and verify the
function of the inverting amplifier as a scale changer. Now give a sinusoidal input signal
‘Vi’ with frequency 1 kHz and peak to peak voltage 5 V. Trace the input and output
signals. Measure the peak to peak voltage of output signal V0. Repeat for various input
frequencies.

3. Make the adder circuit as shown in fig. 4.3. Set V1= +1V and V2=0. Measure the output
voltage. Repeat the measurement for V2 = 1, 2, 3 and 4V. Check the output voltage and
compare it with V0 = -(V1+V2), the theoretical value. Tabulate the experimental output
voltage and the excepted (theoretical) values. Can you construct appropriate inverter
circuit such that the output is V0=V1+V2

4. Make the subtractor circuit as shown in Fig. 4.4. Set V1=0, and measure the output
voltage V0 for V2= 0, ±1, ±2, ±3, and ±4V. Tabulate the input and output voltages.
Compare the measured output voltage with the expected (theoretical) voltage.

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 5. Operational Amplifier Circuits II

Aim: To construct an integrator and differentiator of analog signals using an operational

amplifier.

Circuit Diagram

Fig: 5.1 Integrator Circuit

Fig: 5.2 Differentiator circuit

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 1. Connect the integrator circuit as shown in Fig. 5.1. Apply a sinusoidal input signal ‘Vi’
with frequency 1 kHz and peak to peak voltage 5V. Trace the input and output signals.
Measure the peak to peak voltage of output signal V0. Tabulate the readings. Repeat the
experiment for square and triangular waves. Repeat for C= 0.047µF and 0.1µF.
Calculate the output voltage theoretically and compare with the experimental data.

2. Connect the differentiator circuit as shown in Fig. 5.2. For sine wave, square wave and
triangular wave inputs Vi (1 kHz and Vpp = 5V), measure the peak to peak output
voltage. Trace the input and output signals. Calculate the theoretical output data.

Try out:
1. Solve the differential equation d2V/dt2+K1dV/dt+K2V-V1=0, construct an analog
computer circuit using operational amplifiers. Using an input signal with frequency 1
kHz and peak to peak voltage 7V, measure the output voltage and compare with input
signal d2V/dt2.

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 6. Oscillator Circuits

Aim: a) To construct audio frequency oscillators of the type LC (Colpitt oscillator)

Circuit Diagram:

Fig: 6.1 Colpitt Oscillator

Observation:

Assemble the Colpitt oscillator circuit shown in Fig. 6.1. The frequency of oscillation is
given by the expression, f=1/(2π√LCT), where CT is the total capacitance. Trace the
oscillator output. Repeat for different values of CT. Measure the frequency of the oscillator
using a CRO. Compare the experimental frequencies with the theoretical values.
Compile the results and enclose the traced waveform.
Precaution: List out the precautions and any steps followed by you.

Aim: b) To construct an astable multivibrator using IC 555.

Circuit Diagram:

Fig: 6.2 Free-running M.V.

(RA=1k, RB=3k3,10k, 18k)

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 Observation: Assemble the astable circuit shown in Fig. 6.2. Trace the output waveform.
Try to use the control voltage terminal and vary the output pulse width and observe the
output waveform. The square wave output will have frequency f= 1.4/[C (RA+2RB)].
Repeat for different RA, RB and C values.
Compile the results and enclose the traced waveform.

Precaution: List out the precaution and any special steps followed by you.

Pin-out diagram for each IC555 chip is given in Appendix I.

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 7. Logic Gates

Aim: To construct logic gates using discrete components, obtain their truth table and prove
the universality of NAND / NOR gates.

Equipments: Power supplies (-15 to 15V), Voltmeter.

Circuit diagram:

Fig: 7.1 OR gate

R=1k
Truth Table
INPUT OUTPUT(Y)
A B
Volts Logic level Volts Logic level Volts Logic level
0 0
1 0
0 1
1 1

1k, 330E
Fig: 7.2 AND gate circuit using diodes

Truth Table
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 INPUT OUTPUT(Y)
A B
Volts Logic level Volts Logic level Volts Logic level
0 0
0 1
1 0
1 1

Fig: 7.3 NOT or Inverter gate using transistor

15k, 100k, 2k, 1k
INPUT OUTPUT
Volts Logic level Volts Logic level
0
1

Aim: b) To prove the universality of the NOR gate.

Circuit diagrams: [Make your own truth tables to verify the function of each logic gate]

Fig: 7.4 OR gate using NOR gates (IC 7427)

Fig: 7.5 AND gate using NOR gates(IC 7427)

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 Fig: 7.6 Exclusive OR gate using NOR gates

Observation:

1. The discrete and IC circuits corresponding to the various logic gates are given above
along with their truth table tabulation. The voltages 0 V and +5V are respectively taken
as logic level “0” and “1” respectively. Obtain the truth table for various values of
binary inputs A and B by obtaining the corresponding output Y in each case. Measure
the output voltage V0 and observe status of the LED at the output. A glowing LED
indicates a logic level 1.
2. While wiring up the logic gate IC s give care to the pin out diagram corresponding to
each IC. Give 5V as supply voltage.
3. To prove the universality of NOR gates, make the connection as shown in corresponding
figures. Determine the truth table experimentally and compare with the truth table of the
corresponding gate.

Pin-out diagrams for each IC chip are given in Appendix I.

Precaution: list out precautions taken by you. Write down the special techniques or simpler
circuits followed by you if any.

Note: prove the universality of the NAND gate as exercise.

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 8. Digital Circuits-I

Aim: a) Verification of De Morgan’s theorems.

Circuits:

Fig.8.1 Fig. 8.2

Input Output
A B A+B(RHS) A.B(LHS)
Volt Logic Level Volt Logic Volt Logic Volt Logic
Level level level
0 0
0 1
1 0
1 1

Fig. 8.3 Fig. 8.4

Input Output
A B A.B(RHS) A+B(LHS)
Volt Logic Level Volt Logic Level Volt Logic Volt Logic
level level
0 0
0 1
1 0
1 1

b) To construct an Exclusive OR gate and an half adder circuit using IC-7400

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 Fig. 8.5 Exclusive OR gate

Truth Table

Input Output
A B Y
Volt Logic Level Volt Logic Level Volt Logic Level
0 0
0 1
1 0
1 1

Fig: 8.5. Half adder using NAND gates

Truth Table

A B SUM CARRY
Volt Logic Level Volt Logic Level Volt Logic Level Volt Logic Level
0 0
0 1
1 0
1 1

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 Observation:

1. To verify the De Morgan’s theorem experimentally, make the IC circuits as shown in

figure 8.1 to figure 8.4. Obtain the truth table for various binary inputs A and B and
corresponding output Y. In each case measure the output voltage V0 and prove that LHS =
RHS for both the laws..
2. Construct exclusive OR logic gate using IC 7400. Verify the truth table for various binary
input A and B. Measure the output voltage V0
3. Make the half adder circuit using IC7400. Obtain the corresponding truth table.

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 9. Digital Circuits-II

Aim:
a) Design a JK Flip-Flop and a binary ripple counter using IC 7476.

Fig: 9.1 J-K Flip-flop

J K CLK Q Q
Volt Logic Volt Logic Volt Logic level Volt Logic level
level level
0 0
0 1
1 0
1 1

Connect the J-K flip flop circuit as shown in figure 9.1 using IC 7476. In IC 7476 connect
the pin no. 5 to +5V and pin no. 13 to ground. Set J and K inputs to low (0 state) by
connecting the switches S1 and S3 to ground. Connect a square wave input signal with peak
voltage 5V and frequency 1 kHz to Ck input.

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 Fig: 9.2. Binary Ripple Counter (count down)

Connect the binary counter circuit as shown in figure 9.2. Connect the square wave from
function generator as clock input (Ck) of 5V peak and 20 Hz frequency. Connect the switch
S1 to ground to set ‘0’ state for J and K. Reset the counter by connecting the switch S2 to
ground. Record the state of counter (Q output). Connect the switch S2 to +5V and see
whether there is any change in counter state. Now, connect the switch S1 to 5V, thereby
setting J=K=1 state. Record the counting sequence. Find out whether the counting is up or
down [How will you reverse the counting from down to up or vice versa?].

Pin-out diagrams for each IC chip are given in Appendix I.

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 10. Programming exercises using a 8085A µP trainer kit

Aim: Elementary programming exercises on a µP trainer kit.

Background: A µP trainer kit consists of basic units required for a simple computer,
namely, a microprocessor chip(CPU), memory(EPROM, and RAM), input device(Hex key-
pad and cassette tape) and output device(seven segment display unit- four address fields
followed by two data fields). Programmable peripheral chips such as 8155 and 8255 provide
the necessary interface between the µP and the external circuitry. These physical units
constitute the basic hardware of the system. Software in the form of a set of instructions
written using the 8085 instruction set makes the µP perform a set of desired operations. It
has to borne in mind that the instructions should be converted into the hexadecimal form
while keying in (most trainer kits come with a C language compiler to facilitate
programming, but in this exercise this provision is not used). A system program ( commonly
called the operating system) resides in the EPROM and gets loaded whenever the kit is
switched on.l The MICROFRIEND DYNA-85 kit given to you is based on the INTEL 8085
A . The CPU operates at 3 MHz (system clock). The RAM locations (C000)16 to (FFFF)16
are available for the user to enter any desired program. Single key system commands are
provided in the trainer kit for facilitating easy operation of the kits. These commands
available in the form of soft keys are described below:
<RES> →Does hardware reset. The word “FriEnd” appears in the display when pressed
<DCR>→Decrements memory address presently displayed
<INR>→ Increments memory address presently displayed
<EXEC>→ Starts execution of <GO> command
<SET>→ Used for modifying contents of RAM locations reserved for the user
<GO> → Used for loading the memory address of the beginning of the program
<STEP>→ For executing program in single step or break-point mode
<REG>→ Keys let you examine or modify the CPU registers [To use this command
press <REG> and press one A, B, C, D, E, F, 8 or 9 for choosing the registers A, B, C, D,
E, Flag H or L respectively. The flag register bits are
S Z X AC X P X C
where S is the sign flag, Z is the zero flag, AC is the auxiliary carry flag, P is
the plus flag and C is the carry flag (X means don’s care).
To enter a program, follow the following sequence:
<RES>
<SET> C000
XX ! first hex instruction is entered in the place of XX
<INR> ! this command increments address to C001
.
! enter the entire program by keying one 8 bit no. in hex
. in each location and moving to next by pressing <INR>
<INR> 76 ! last instruction in the program

To execute the entered program, use the following command:

<RES>
<GO> C000 ! load program which starts at address C000
<EXEC> ! execute the loaded program

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It is usually desired that the result of a computation is readily available after the execution of the
program. The subroutine called MODIDT which resides in the EPROM at the address (036E)16
can be used to display the contents of register A (accumulator) to the data fields of the display
units. In order to use this to display the result of any computation use following sequence
instructions:

<move result to register A>

<move zero into register B>
CALL MODIDT ! Key in the address 03 6E in the place of MODIDT

You should know that the CALL MODIDT commands changes the state of all CPU registers
and all flags and hence be careful to use this only towards the end of the program.

Exercises:
1. Add two 8 bit numbers with (a) one number in register A and the other in register B (b)
one number is in the register C and other in register H, (c) the two number in locations
C050 and C060.
2. Add two 16 bit numbers.
3. Subtract two 8 bit numbers in locations D030 and D0D0
4. Subtract two 16 bit numbers.
5. Find the largest and the smallest of the given three numbers in locations C150, C151 and
C152. Store the largest number in C156 and the smallest number in C157.
6. Multiply the given 8 bit numbers and displays the results.
7. Divide the given numbers. Display quotient in display fields.
8. Divide the indivisible numbers and display the quotient in display field and reminder in
location D135.

Load ten 8-bit numbers in ten memory locations and sort then according to ascending order.

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 Appendix I:

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 Pin diagram of IC 7402

Pin diagram of IC 7476

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