Benha University Mid Term Exam

Faculty of Engineering- Shoubra Date: 28/4/2014

Electrical Engineering Department Computer Architecture
Third Year Computer Engineering Duration : 75 min

Answer all the following questions No. of questions: 3

Illustrate your answers with sketches when necessary. Total Mark: 40 points
The exam is 2 paged

Question 1: 10 points
For each of the following statements, indicate whether it is True or False
a- For forwarding you need only look at the data available in the WB stage.
b- A dynamic branch predictor is always better than a static one.
c- A perfect branch predictor combined with data forwarding would allow a processor to
always keep its pipeline full.
d- Register renaming eliminates stalls due to anti (WAR) dependences on registers

e- With single-issue, in-order execution, and the classical five-stage pipeline with no bypassing,
WAW hazards never cause any bubbles (stalls) in the pipeline.

f- A convoy in vector architecture is the set of vector instructions that could execute together

g- Vector architecture cannot handle matrices that are sparsely located in memory

h- Scoreboarding is a technique that allows out of order execution by handling antidependences

and output dependences.

i- Pipelining increases instruction throughput but does not reduce the instruction execution
time.

j- Forwarding in pipeline processor means that data can be passed directly to another stage
ONLY after WB stage.

Question 2 10 points
1- A non-pipeline system takes 500ns to process a task; the same task can be processed in a six-
stage pipeline with the time delay of each stage as follows 80ns, 120ns, 100ns, 180ns, 70ns, and
120ns.
a. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup
that can be achieved?
b. If the largest stage is split into 2 equal stages. Determine the speedup ratio of the pipeline
for the 100 tasks. What is the maximum speedup that can be achieved?
2- Draw the pipelined timing diagram for the following :
Load A M
Load B M
Add C A + B
Store M C
Branch X
Question 3 20 points
A processor using Tomasulos algorithm in its floating-point unit has one CDB. It can issue two
instructions per cycle. The figure shows the current state of the processor, at the very end of a clock
cycle. The adder is not doing anything, but the multiplier has just finished an operation. A new cycle
begins now.
Instruction status
Instruction Issue Execution Write
result
MUL F0, F1, F2 Yes Yes
ADD F1, F0, F3 Yes
ADD F2, F3, F2 Yes
ADD F3, F1, F4
ADD F0, F1, F2

Register status
Vi Qj
F0 Mul1
F1 Add1
F2 Add2
F3 20
F4 43
F5 12
F6 3.75
F7 0.01

Reservation Stations
Name Busy Op V V Q Q
j k j k
Add1 Yes Add 20 Mul1
Add2 Yes Add 20 75
Add3 No
Mul1 Yes Mul 125 75
Mul2 No

A) What will happen in this new cycle when the processor tries to issue the next two instructions?
Update the figure to reflect the resulting state of the processor. If one or both of the two instructions
cannot issue in this cycle, briefly explain why it/they cannot issue. [8 points]
B) The multiplier and the adder are both free to begin a new computation in this cycle. Which
instructions can begin to execute in the adder and which in the multiplier? Update the figure to reflect the
resulting state after beginning execution for these instructions. [5 points]
C) What is going to be broadcast on the CDB in this cycle? Update the figure to reflect the state after the
broadcast and the resulting actions are complete. [7 points]