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PRC/PRS is not broken.
For reliability reasons, it is
unrealistic to expect all global
telecommunication networks to
be synchronized to a single PRC/
PRS. Real networks use a flatter
timing distribution structure with
a number of PRC/PRS running
independently. Each telecom pro-
vider usually has its own PRC/PRS,
which means that the worldwide
telecommunication network con- Figure 2: Synchronization does exist in Ethernet on each hop between two adjacent nodes, but it is not passed from
hop to hop.
sists of synchronized islands con-
nected with plesiochronous links.
While PRC/PRS and SSU/BITS
are usually implemented as
standalone products with tim-
ing-only functionality (no data
transmission), SEC/SMC are almost
exclusively implemented as a part
of networking product such as an
add-drop multiplexer.
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which can be accomplished with
general purpose PLLs. However,
the PLL used in SyncE must pro-
vide additional functions beyond
jitter cleaning.
For example, if the receiving
PHY device (Node 2, PHY 1 in
Figure 3) gets disconnected from
the line, the recovered clock fre-
quency will either stop or start to
drift depending on the implemen-
tation of the clock recovery circuit.
The general purpose PLL will pass
this big frequency change to the
transmitting PHY device (Node 2,
PHY 2 in Figure 3). As a result, not
only is the transmission of syn-
chronization signal going to fail,
but the data transmission could
fail as well.
The PLL used in SyncE must
be able to detect failure of the
recovered clock and switch the Figure 4: Timing in a carrier-grade SyncE system is composed of two timing cards that feed clocks to multiple line
PLL to either another good refer- cards via a common backplane.
ence in the system or into hold-
over mode. Requirements for
SyncE are outlined in the timing
characteristics of synchronous
Ethernet equipment clock (ITU
G.8262/Y1362) specifications.
These specifications are based
on ITU-T G.813 specification for
SDH clocks. The major require-
ments of ITU-T G.8262/Y1362 are
the following:
Free-run accuracyThe ac-
curacy of PLL output when
it is not driven by a reference
should be equal or better
than 4.6ppm over a time
period of one year. This is a
very accurate clock relative
to the clock accuracy for tra-
ditional Ethernet (100ppm).
HoldoverThe PLL con-
stantly calculates the aver- Figure 5: A next-generation DLC requires Ethernet and telecom clock frequencies.
age frequency of the locked
reference. If the reference monitor the quality of its as a jitter and wander filter. is that a SyncE DPLL needs to be
fails and no other references input references. If the refer- The narrower the loop band- able to lock and generate clock
are available, the PLL goes ence deteriorates (disappears width, the better the jitter frequencies used in Ethernet
into holdover mode and or drifts in frequency), the and wander attenuation. (25MHz, 125MHz and 156.25MHz),
generates an output clock PLL raises an alarm (interrupt) Jitter and wander tolerance as opposed to telecom clocks
based on a calculated aver- and switches to another valid The PLL should tolerate large (19.44MHz, 155.52MHz) used in
age value. Holdover stability reference. jitter and wander at its input, SONET/SDH.
depends on the resolution of Hitless reference switchingIf and still maintain synchro- Carrier-grade SyncE systems
the PLL averaging algorithm the PLL's reference fails, it nization without raising any must provide highly reliable op-
and the frequency stability of will lock to another available alarms. eration under all network condi-
the oscillator used as the PLL reference without phase dis- These stringent requirements tions. To do this, the most critical
master clock. turbances at its output. can be met only with a DPLL components within the system
Reference monitoringThe Jitter and wander filter- similar to DPLLs used for SONET/ are made redundant, including
PLL needs to constantly ingThe PLL can be viewed SDH clocks. The major difference timing.
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Timing in a carrier-grade SyncE backplane. The DPLL is the most tects active reference failure and intrinsic jitter. Depending on the
system is composed of two timing important part of the timing card. switches the line card DPLL to lock application, this DPLL might also
cards that feed clocks to multiple Timing card DPLL references can to the redundant reference. Like need to generate telecom fre-
line cards via a common backplane come externally from a SSU/BITS, any DPLL, a line card DPLL requires quencies such as 8KHz, 2.048MHz,
(Figure 4). All line cards synchro- internally from line cards, or from a crystal oscillator. 1.544MHz, 34.368MHz, 44.736MHz
nize to the clock coming from an the other timing card in the sys- However, this can be a low- and many others.
active timing card. If the active tim- tem. Timing card DPLLs should cost oscillator as the line card Figure 5 illustrates a next-gen-
ing card clock fails (i.e. the card is meet all ITU-T G.8262/Y1362 re- DPLL is not required to go into eration Digital Loop Carrier (DLC)
unplugged), line cards will synchro- quirements. holdover (except for short time requiring Ethernet and telecom
nize to the clock coming from the As seen in Figure 4, the line periods when switching between clock frequencies. DLCs are in-
redundant timing card. Switching cards each have a DPLL that is active and redundant clocks). For stalled in the neighborhood to ag-
from one timing card to the other used for jitter reduction and fre- long-term holdover, the system gregate traffic from multiple POTS,
should not cause any interruption quency translation. For example, relies on a timing card DPLL. xDSL and T1/E1 to minimize the
or failure in the system. frequency translation is required Therefore, a timing card DPLL number of the lines going to the
Having two timing cards pro- to convert from the 25MHz back- requires higher quality crystal Central Office (CO) and increase
tects against an internal failure if plane clock to one or more clocks oscillators (TCXO, OCXO). xDSL data rates by shortening the
one of the cards fails. As seen in required by the Ethernet PHY, such Smaller SyncE systems that do length of the copper lines.
Figure 4, to protect from external as 125MHz, 156.25MHz, 155.52MHz not need timing redundancy will Aggregated traffic is carried to
clock reference failures, the tim- or any other. generally have only one DPLL. the CO via a fiber cable or several
ing cards are designed to be able The line card DPLL must also This DPLL should meet all require- copper lines. Traditionally, DLCs
to synchronize to more than one provide hitless switching between ment of the timing card DPLL and have used SONET/SDH or T3/E3
reference. A timing card accepts the active and redundant clocks the line card DPLL combined. to transmit data between the
references from multiple sources, and provide clock continuity for This DPLL should have narrow DLC and CO. However, these links
selects one, cleans it from phase a short period, such as when loop bandwidth, good holdover are being replaced by Ethernet
noise with a DPLL, and distrib- the active clock unexpectedly (TCXO or OCXO required), hitless because of its lower capital and
utes it to the line cards via the disappears before the system de- reference switching and very low operational costs.
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