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Contents
Chapter Page
Introduction............................................................................ 310
Function block ............................................................................ 317
Input and output signals ............................................................. 317
Setting parameters ..................................................................... 320
Technical data ............................................................................ 324
Thermal overload protection, two time constants (PTTR, 49) ......... 326
Introduction ................................................................................. 326
Principle of operation .................................................................. 326
Function block ............................................................................ 330
Input and output signals ............................................................. 330
Setting parameters ..................................................................... 331
Technical data ............................................................................ 332
Breaker failure protection (RBRF, 50BF)......................................... 333
Introduction ................................................................................. 333
Principle of operation .................................................................. 333
Function block ............................................................................ 336
Input and output signals ............................................................. 337
Setting parameters ..................................................................... 337
Technical data ............................................................................ 338
Pole discordance protection (RPLD, 52PD) .................................... 339
Introduction ................................................................................. 339
Principle of operation .................................................................. 339
Pole discordance signalling from circuit breaker ................... 342
Unsymmetrical current detection ........................................... 342
Function block ............................................................................ 342
Input and output signals ............................................................. 343
Setting parameters ..................................................................... 343
Technical data ............................................................................ 344
Directional underpower protection (PDUP, 32)................................ 345
Introduction ................................................................................. 345
Principle of operation .................................................................. 346
Low pass filtering................................................................... 348
Calibration of analog inputs ................................................... 348
Function block ............................................................................ 350
Input and output signals ............................................................. 350
Setting parameters ..................................................................... 351
Technical data ............................................................................ 352
Directional overpower protection (PDOP, 32).................................. 353
Introduction ................................................................................. 353
Principle of operation .................................................................. 354
Low pass filtering................................................................... 356
Calibration of analog inputs ................................................... 356
Function block ............................................................................ 358
Input and output signals ............................................................. 358
Setting parameters ..................................................................... 359
Technical data ............................................................................ 360
Broken conductor check (PTOC, 46)............................................... 361
Introduction ................................................................................. 361
Principle of operation .................................................................. 361
Function block ............................................................................ 362
Input and output signals ............................................................. 362
Setting parameters ..................................................................... 363
Technical data ............................................................................ 363
Contents
Introduction............................................................................ 807
Principle of operation............................................................. 807
Function block ....................................................................... 807
Input and output signals ........................................................ 808
Setting parameters ................................................................ 809
Generic double point function block (DPGGIO).......................... 809
Introduction............................................................................ 809
Principle of operation............................................................. 809
Function block ....................................................................... 810
Input and output signals ........................................................ 810
Setting parameters ................................................................ 810
Generic measured values function block (MVGGIO).................. 810
Introduction............................................................................ 810
Principle of operation............................................................. 810
Function block ....................................................................... 810
Input and output signals ........................................................ 811
Setting parameters ................................................................ 811
Setting parameters ..................................................................... 812
Technical data ............................................................................ 812
LON communication protocol .......................................................... 813
Introduction ................................................................................. 813
Principle of operation .................................................................. 813
Setting parameters ..................................................................... 830
Technical data ............................................................................ 830
SPA communication protocol........................................................... 831
Introduction ................................................................................. 831
Principle of operation .................................................................. 831
Communication ports............................................................. 839
Design ........................................................................................ 840
Setting parameters ..................................................................... 840
Technical data ............................................................................ 841
IEC 60870-5-103 communication protocol ...................................... 842
Introduction ................................................................................. 842
Principle of operation .................................................................. 842
General.................................................................................. 842
Communication ports............................................................. 852
Function block ............................................................................ 852
Input and output signals ............................................................. 855
Setting parameters ..................................................................... 860
Technical data ............................................................................ 863
Automation bits (AUBI) .................................................................... 864
Introduction ................................................................................. 864
Principle of operation .................................................................. 864
Function block ............................................................................ 865
Input and output signals ............................................................. 865
Setting parameters ..................................................................... 867
Single command, 16 signals (CD) ................................................... 879
Introduction ................................................................................. 879
Principle of operation .................................................................. 879
Function block ............................................................................ 879
Input and output signals ............................................................. 880
Setting parameters ..................................................................... 880
Multiple command (CM) and Multiple transmit (MT)........................ 881
Contents
Introduction............................................................................ 916
Design ................................................................................... 916
Technical data ....................................................................... 920
Binary output modules (BOM) .................................................... 920
Introduction............................................................................ 920
Design ................................................................................... 921
Technical data ....................................................................... 923
Static binary output module (SOM)............................................. 923
Introduction............................................................................ 923
Design ................................................................................... 923
Technical data ....................................................................... 925
Binary input/output module (IOM)............................................... 926
Introduction............................................................................ 926
Design ................................................................................... 926
Technical data ....................................................................... 929
Line data communication module (LDCM) ................................. 931
Introduction............................................................................ 931
Design ................................................................................... 931
Technical data ....................................................................... 932
Serial SPA/IEC 60870-5-103 and LON
communication module (SLM) ................................................ 933
Introduction............................................................................ 933
Design ................................................................................... 933
Technical data ....................................................................... 935
Galvanic RS485 communication module.................................... 936
Introduction............................................................................ 936
Design ................................................................................... 936
Technical data ....................................................................... 938
Optical ethernet module (OEM) .................................................. 938
Introduction............................................................................ 938
Functionality .......................................................................... 938
Design ................................................................................... 938
Technical data ....................................................................... 939
mA input module (MIM) .............................................................. 939
Introduction............................................................................ 939
Design ................................................................................... 939
Technical data ....................................................................... 941
GPS time synchronization module (GSM) .................................. 941
Introduction............................................................................ 941
Design ................................................................................... 941
Technical data ....................................................................... 944
GPS antenna .............................................................................. 944
Introduction............................................................................ 944
Design ................................................................................... 944
Technical data ....................................................................... 946
IRIG-B time synchronization module IRIG-B .............................. 947
Introduction............................................................................ 947
Design ................................................................................... 947
Technical data ....................................................................... 948
Dimensions ...................................................................................... 949
Case without rear cover.............................................................. 949
Case with rear cover................................................................... 950
Flush mounting dimensions ........................................................ 951
Contents
Glossary......................................................................................... 1014
About this chapter Chapter 1
Introduction
Chapter 1 Introduction
1
Introduction to the technical reference manual Chapter 1
Introduction
en06000097.vsd
The Application Manual (AM) contains application descriptions, setting guidelines and setting
parameters sorted per function. The application manual should be used to find out when and for
what purpose a typical protection function could be used. The manual should also be used when
calculating settings.
The Technical Reference Manual (TRM) contains application and functionality descriptions
and it lists function blocks, logic diagrams, input and output signals, setting parameters and tech-
nical data sorted per function. The technical reference manual should be used as a technical ref-
erence during the engineering phase, installation and commissioning phase, and during normal
service.
The Installation and Commissioning Manual (ICM) contains instructions on how to install
and commission the protection IED. The manual can also be used as a reference during periodic
testing. The manual covers procedures for mechanical and electrical installation, energizing and
checking of external circuitry, setting and configuration as well as verifying settings and per-
forming directional tests. The chapters are organized in the chronological order (indicated by
chapter/section numbers) in which the protection IED should be installed and commissioned.
The Operators Manual (OM) contains instructions on how to operate the protection IED dur-
ing normal service once it has been commissioned. The operators manual can be used to find
out how to handle disturbances or how to view calculated and measured network data in order
to determine the cause of a fault.
The IED 670 Engineering guide (EG) contains instructions on how to engineer the IED 670
products. The manual guides to use the different tool components for IED 670 engineering. It
also guides how to handle the tool component available to read disturbance files from the IEDs
on the basis of the IEC 61850 definitions. The third part is an introduction about the diagnostic
tool components available for IED 670 products and the PCM 600 tool.
The IEC 61850 Station Engineering guide contains descriptions of IEC 61850 station engi-
neering and process signal routing. The manual presents the PCM 600 and CCT tool used for
station engineering. It describes the IEC 61850 attribute editor and how to set up projects and
communication.
2
Introduction to the technical reference manual Chapter 1
Introduction
The chapter Local human-machine interface describes the control panel on the
IED. Display characteristics, control keys and various local human-machine in-
terface features are explained.
The chapter Basic IED functions presents functions that are included in all
IEDs regardless of the type of protection they are designed for. These are func-
tions like Time synchronization, Self supervision with event list, Test mode and
other functions of a general nature.
The chapter Distance protection describes the functions for distance zones
with their quadrilateral characteristics, phase selection with load encroachment,
power swing detection and similar.
The chapter Current protection describes functions such as overcurrent pro-
tection, breaker failure protection and pole discordance.
The chapter Voltage protection describes functions like undervoltage and ov-
ervoltage protection as well as residual overvoltage protection.
The chapter Frequency protection describes functions for overfrequency, un-
derfrequency and rate of change of frequency.
The chapter Multipurpose protection describes the general protection function
for current and voltage.
The chapter Secondary system supervision includes descriptions of functions
like current based Current circuit supervision and Fuse failure supervision.
The chapter Control describes the control functions. These are functions like
the Synchronization and energizing check as well as several others which are
product specific.
The chapter Scheme communication describes among others functions related
to current reversal and weak end infeed logic.
The chapter Logic describes trip logic and related functions.
The chapter Monitoring describes measurement related functions used to pro-
vide data regarding relevant quantities, events, faults and the like.
The chapter Metering describes primarily Pulse counter logic.
The chapter Station communication describes Ethernet based communication
in general including the use of IEC61850, and horizontal communication via
GOOSE.
The chapter Remote communication describes binary and analog signal trans-
fer, and the associated hardware.
The chapter Hardware provides descriptions of the IED and its components.
The chapter Connection diagrams provides terminal wiring diagrams and in-
formation regarding connections to and from the IED.
The chapter Time inverse characteristics describes and explains inverse time
delay, inverse time curves and their effects.
The chapter Glossary is a list of terms, acronyms and abbreviations used in
ABB technical documentation.
3
Introduction to the technical reference manual Chapter 1
Introduction
1.3.1 Introduction
Outlines the implementation of a particular protection function.
Logic diagrams
Logic diagrams describe the signal logic inside the function block and are bordered by dashed
lines.
Signal names
Input and output logic signals consist of two groups of letters separated by two dashes. The first
group consists of up to four letters and presents the abbreviated name for the corresponding
function. The second group presents the functionality of the particular signal. According to this
explanation, the meaning of the signal BLKTR in figure 4 is as follows:
BLKTR informs the user that the signal will BLOCK the TRIP command from
the under-voltage function, when its value is a logical one (1).
Input signals are always on the left hand side, and output signals on the right hand side. Settings
are not displayed.
Input and output signals can be configured using the CAP531 tool. They can be connected to the
inputs and outputs of other functions and to binary inputs and outputs. Examples of input signals
are BLKTR, BLOCK and VTSU. Examples output signals are TRIP, START, STL1, STL2,
STL3.
Setting parameters
Signals in frames with a shaded area on their right hand side represent setting parameter signals.
These parameters can only be set via the PST or LHMI. Their values are high (1) only when the
corresponding setting parameter is set to the symbolic value specified within the frame. Example
is the signal Block TUV=Yes. Their logical values correspond automatically to the selected set-
ting value.
Internal signals
Internal signals are illustrated graphically and end approximately. 2 mm from the frame edge. If
an internal signal path cannot be drawn with a continuous line, the suffix -int is added to the sig-
nal name to indicate where the signal starts and continues, see figure 3.
4
Introduction to the technical reference manual Chapter 1
Introduction
BLKTR
TEST
TEST
&
Block TUV=Yes BLOCK-int.
>1
BLOCK
VTSU
BLOCK-int.
&
STUL1N
BLOCK-int.
& >1 & TRIP
t
STUL2N
BLOCK-int.
START
&
STUL3N
STL1
STL2
STL3
xx04000375.vsd
Figure 1: Logic diagram example with -int signals
External signals
Signal paths that extend beyond the logic diagram and continue in another diagram have the suf-
fix -cont., see figure 2 and figure 3.
5
Introduction to the technical reference manual Chapter 1
Introduction
STZMPP-cont.
>1
STCND
& STNDL1L2-cont.
1L1L2
STNDL2L3-cont.
&
1L2L3
& STNDL3L1-cont.
1L3L1
& STNDL1N-cont.
1L1N
& STNDL2N-cont.
1L2N
STNDL3N-cont.
&
1L3N
>1 STNDPE-cont.
>1
1--VTSZ 1--STND
>1 &
1--BLOCK
BLK-cont.
xx04000376.vsd
Figure 2: Logic diagram example with an outgoing -cont signal
6
Introduction to the technical reference manual Chapter 1
Introduction
STNDL1N-cont.
>1
STNDL2N-cont. 15 ms
& t STL1
STNDL3N-cont.
STNDL1L2-cont. >1 15 ms
& t STL2
STNDL2L3-cont.
15 ms
STNDL3L1-cont. & t STL3
>1
15 ms
& t START
>1
BLK-cont.
xx04000377.vsd
Figure 3: Logic diagram example with an incoming -cont signal
Input signals are always on the left hand side, and output signals on the right hand side. Settings
are not displayed. Special kinds of settings are sometimes available. These are supposed to be
connected to constants in the configuration scheme, and are therefore depicted as inputs. Such
signals will be found in the signal list but described in the settings table.
7
Introduction to the technical reference manual Chapter 1
Introduction
IEC 61850 - 8 -1
CAP531 Name Logical Node
Inputs TUV1-
PH2PUVM
U3P TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
Outputs
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2 Diagram
ST2L1 Number
ST2L2
ST2L3
en05000330.vsd
1.4.2 Requirements
The system engineer must have a thorough knowledge of protection systems, protection equip-
ment, protection functions and the configured functional logics in the protective devices. The
installation and commissioning personnel must have a basic knowledge in the handling electron-
ic equipment.
8
Introduction to the technical reference manual Chapter 1
Introduction
9
Introduction to the technical reference manual Chapter 1
Introduction
Revision Description
- First release
10
About this chapter Chapter 2
Local human-machine interface
Chapter 2 Local
human-machine
interface
11
Human machine interface Chapter 2
Local human-machine interface
The local human machine interface is equipped with an LCD that can display the single line di-
agram with up to 15 objects.
The local human-machine interface is simple and easy to understand the whole front plate is
divided into zones, each of them with a well-defined functionality:
12
Human machine interface Chapter 2
Local human-machine interface
13
Small size graphic HMI Chapter 2
Local human-machine interface
2.1 Introduction
The small sized HMI is available for 1/2, 3/4 and 1/1 x 19 case. The LCD on the small HMI
measures 32 x 90 mm and displays 7 lines with up to 40 characters per line. The first line dis-
plays the product name and the last line displays date and time. The remaining 5 lines are dy-
namic. This LCD has no graphic display potential.
2.2 Design
The LHMI is identical for both the 1/2, 3/4 and 1/1 cases. The different parts of the small LHMI
is shown in figure 8
14
Small size graphic HMI Chapter 2
Local human-machine interface
1 2 3
en05000055.eps
8 7
15
Medium size graphic HMI Chapter 2
Local human-machine interface
3.1 Introduction
The 1/2, 3/4 and 1/1 x 19 cases can be equipped with the medium size LCD. This is a fully
graphical monochrome LCD which measures 120 x 90 mm. It has 28 lines with up to 40 char-
acters per line. To display the single line diagram, this LCD is required.
3.2 Design
The different parts of the medium size LHMI is shown in figure 9The LHMI, exists in an IEC
version and in an ANSI version. The difference is on the keypad operation buttons and the yel-
low LED designation.
16
Medium size graphic HMI Chapter 2
Local human-machine interface
1 2 3
en05000056.eps
8 7
17
Keypad Chapter 2
Local human-machine interface
4 Keypad
The keypad is used to monitor and operate the IED. The keypad has the same look and feel in
all IEDs in the IED 670 series. LCD screens and other details may differ but the way the keys
function is identical. The keypad is illustrated in figure 10.
The keys used to operate the IED are described below in table 1.
The help key brings up two submenus. Key operation and IED information.
Opens the main menu, and used to move to the default screen.
18
Keypad Chapter 2
Local human-machine interface
Key Function
The Local/Remote key is used to set the IED in local or remote control mode.
The E key starts editing mode and confirms setting changes when in editing mode.
The right arrow key navigates forward between screens and moves right in editing mode.
The left arrow key navigates backwards between screens and moves left in editing mode.
The up arrow key is used to move up in the single line diagram and in menu tree.
The down arrow key is used to move down in the single line diagram and in menu tree.
19
LED Chapter 2
Local human-machine interface
5 LED
5.1 Introduction
The LED module is a unidirectional means of communicating. This means that events may occur
that activate a LED in order to draw the operators attention to something that has occurred and
needs some sort of action.
There are alarm indication LEDs and hardware associated LEDs on the right hand side of the
front panel. The alarm LEDs are found to the right of the LCD screen. They can show steady or
flashing light. Flashing would normally indicate an alarm. The alarm LEDs are configurable us-
ing the PCM 600 tool. This is because they are dependent on the binary input logic and can there-
fore not be configured locally on the HMI. Some typical alarm examples follow:
20
LED Chapter 2
Local human-machine interface
Bucholtz trip
The RJ45 port has a yellow LED indicating that communication has been established between
the IED and a computer.
The Local/Remote key on the front panel has two LEDs indicating whether local or remote con-
trol of the IED is active.
21
LHMI related functions Chapter 2
Local human-machine interface
6.1 Introduction
The adaptation of the LHMI to the application and user preferences is made with:
The function block can be used if any of the signals are required in a configuration logic.
22
LHMI related functions Chapter 2
Local human-machine interface
LHMI-
LocalHMI
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD
en05000773.vsd
Each indication LED on the LHMI can be set individually to operate in six different sequences;
two as follow type and four as latch type. Two of the latching sequence types are intended to be
used as a protection indication system, either in collecting or restarting mode, with reset func-
tionality. The other two are intended to be used as signalling system in collecting (coll) mode
with an acknowledgment functionality. The light from the LEDs can be steady (-S) or flickering
(-F). For details, refer to Technical reference manual.
23
LHMI related functions Chapter 2
Local human-machine interface
6.4.2 Design
The information on the LEDs is stored at loss of the auxiliary power to the IED in some of the
modes of the HLED. The latest LED picture appears immediately after the IED is successfully
restarted.
Operating modes
Collecting mode
- LEDs which are used in collecting mode of operation are accumulated con-
tinuously until the unit is acknowledged manually. This mode is suitable
when the LEDs are used as a simplified alarm system.
Re-starting mode
- In the re-starting mode of operation each new start resets all previous active
LEDs and activates only those which appear during one disturbance. Only
LEDs defined for re-starting mode with the latched sequence type 6 (Latche-
dReset-S) will initiate a reset and a restart at a new disturbance. A distur-
bance is defined to end a settable time after the reset of the activated input
signals or when the maximum time limit has elapsed.
Acknowledgment/reset
From local HMI
- The active indications can be acknowledged/reset manually. Manual ac-
knowledgment and manual reset have the same meaning and is a common
signal for all the operating sequences and LEDs. The function is positive
edge triggered, not level triggered. The acknowledgment/reset is performed
via the Reset-button and menus on the LHMI. For details, refer to the Op-
erators manual.
Automatic reset
- The automatic reset can only be performed for indications defined for
re-starting mode with the latched sequence type 6 (LatchedReset-S). When
the automatic reset of the LEDs has been performed, still persisting indica-
tions will be indicated with a steady light.
Operating sequences
The sequences can be of type Follow or Latched. For the Follow type the LED follow the input
signal completely. For the Latched type each LED latches to the corresponding input signal until
it is reset.
24
LHMI related functions Chapter 2
Local human-machine interface
The figures below show the function of available sequences selectable for each LED separately.
For sequence 1 and 2 (Follow type), the acknowledgment/reset function is not applicable. Se-
quence 3 and 4 (Latched type with acknowledgement) are only working in collecting mode. Se-
quence 5 is working according to Latched type and collecting mode while sequence 6 is working
according to Latched type and re-starting mode. The letters S and F in the sequence names have
the meaning S = Steady and F = Flash.
At the activation of the input signal, the indication operates according to the selected sequence
diagrams below.
In the sequence diagrams the LEDs have the characteristics shown in figure 12.
en05000506.vsd
Sequence 1 (Follow-S)
This sequence follows all the time, with a steady light, the corresponding input signals. It does
not react on acknowledgment or reset. Every LED is independent of the other LEDs in its oper-
ation.
Activating
signal
LED
en01000228.vsd
Sequence 2 (Follow-F)
This sequence is the same as sequence 1, Follow-S, but the LEDs are flashing instead of showing
steady light.
Sequence 3 (LatchedAck-F-S)
This sequence has a latched function and works in collecting mode. Every LED is independent
of the other LEDs in its operation. At the activation of the input signal, the indication starts flash-
ing. After acknowledgment the indication disappears if the signal is not present any more. If the
signal is still present after acknowledgment it gets a steady light.
25
LHMI related functions Chapter 2
Local human-machine interface
Activating
signal
LED
Acknow.
en01000231.vsd
Sequence 4 (LatchedAck-S-F)
This sequence has the same functionality as sequence 3, but steady and flashing light have been
alternated.
Sequence 5 (LatchedColl-S)
This sequence has a latched function and works in collecting mode. At the activation of the input
signal, the indication will light up with a steady light. The difference to sequence 3 and 4 is that
indications that are still activated will not be affected by the reset i.e. immediately after the pos-
itive edge of the reset has been executed a new reading and storing of active signals is performed.
Every LED is independent of the other LEDs in its operation.
Activating
signal
LED
Reset
en01000235.vsd
Sequence 6 (LatchedReset-S)
In this mode all activated LEDs, which are set to sequence 6 (LatchedReset-S), are automatically
reset at a new disturbance when activating any input signal for other LEDs set to sequence 6
(LatchedReset-S). Also in this case indications that are still activated will not be affected by
manual reset, i.e. immediately after the positive edge of that the manual reset has been executed
a new reading and storing of active signals is performed. LEDs set for sequence 6 are completely
independent in its operation of LEDs set for other sequences.
26
LHMI related functions Chapter 2
Local human-machine interface
Definition of a disturbance
A disturbance is defined to last from the first LED set as LatchedReset-S is activated until a set-
table time, tRestart, has elapsed after that all activating signals for the LEDs set as Latche-
dReset-S have reset. However if all activating signals have reset and some signal again becomes
active before tRestart has elapsed, the tRestart timer does not restart the timing sequence. A new
disturbance start will be issued first when all signals have reset after tRestart has elapsed. A di-
agram of this functionality is shown in figure 16.
From
disturbance
length control 1 New
per LED 1 disturbance
set to
sequence 6
tRestart
& t
&
1
1
&
en01000237.vsd
In order not to have a lock-up of the indications in the case of a persisting signal each LED is
provided with a timer, tMax, after which time the influence on the definition of a disturbance of
that specific LED is inhibited. This functionality is shown i diagram in figure 17.
Activating signal
To LED
To disturbance
AND
tMax length control
t
en05000507.vsd
27
LHMI related functions Chapter 2
Local human-machine interface
Disturbance
t Restart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
en01000239.vsd
Figure 18: Operating sequence 6 (LatchedReset-S), two indications within same disturbance
Figure 19 shows the timing diagram for a new indication after tRestart time has elapsed.
28
LHMI related functions Chapter 2
Local human-machine interface
Disturbance Disturbance
t Restart t Restart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
en01000240.vsd
Figure 20 shows the timing diagram when a new indication appears after the first one has reset
but before tRestart has elapsed.
29
LHMI related functions Chapter 2
Local human-machine interface
Disturbance
t Restart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
en01000241.vsd
Figure 20: Operating sequence 6 (LatchedReset-S), two indications within same disturbance
but with reset of activating signal between
30
LHMI related functions Chapter 2
Local human-machine interface
Disturbance
t Restart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
en01000242.vsd
HLED-
LEDMonitor
BLOCK NEWIND
RESET ACK
LEDTEST
en05000508.vsd
31
LHMI related functions Chapter 2
Local human-machine interface
32
LHMI related functions Chapter 2
Local human-machine interface
33
LHMI related functions Chapter 2
Local human-machine interface
34
About this chapter Chapter 3
Basic IED functions
35
Analog inputs Chapter 3
Basic IED functions
1 Analog inputs
1.1 Introduction
In order to get correct measurement results as well as correct protection operations the analog
input channels must be configured and properly set. For power measuring and all directional and
differential functions the directions of the input currents must be properly defined. The measur-
ing and protection algorithms in IED 670 are using primary system quantities and the set values
are done in primary quantities as well. Therefore it is extremely important to properly set the
data about the connected current and voltage transformers.
In order to make Service Values reading easier it is possible to define a reference PhaseAn-
gleRef. Then this analog channels phase angle will be always fixed to zero degree and all other
angle information will be shown in relation to this analog input. During testing and commission-
ing of the IED the reference channel can be freely change in order to facilitate testing and service
values reading.
Note!
VT inputs are sometimes not available depending on ordered type of Transformer Input Module
(TRM).
36
Analog inputs Chapter 3
Basic IED functions
en05000456.vsd
With correct setting of the primary CT direction, CTStarPoint set to FromObject or ToObject, a
positive quantities always flowing towards the object and a direction defined as Forward always
is looking towards the object. To be able to use primary system quantities for settings and cal-
culation in the IED the ratios of the main CTs and VTs must be known. This information is given
to the IED by setting of the rated secondary and primary currents and voltages of the CTs and
VTs.
The CT and VT ratio and the name on respective channel is done under General settings/Analog
module in the parameter settings tool PST.
37
Analog inputs Chapter 3
Basic IED functions
TA40-
ANALOGIN12I
ERROR
CH1
NAMECH1
CH2
NAMECH2
CH3
NAMECH3
CH4
NAMECH4
CH5
NAMECH5
CH6
NAMECH6
CH7
NAMECH7
CH8
NAMECH8
CH9
NAMECH9
CH10
NAMECH10
CH11
NAMECH11
CH12
NAMECH12
en05000711.vsd
TB40-
ANALOGIN6I
ERROR
CH1
NAMECH1
CH2
NAMECH2
CH3
NAMECH3
CH4
NAMECH4
CH5
NAMECH5
CH6
NAMECH6
en05000712.vsd
38
Analog inputs Chapter 3
Basic IED functions
TC40-
ANALOGIN9I3U
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
NAMECH7
CH7
CH8
NAMECH8
NAMECH9
CH9
CH10
NAMECH10
NAMECH11
CH11
CH12
NAMECH12
en05000713.vsd
TD40-
ANALOGIN6I6U
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
NAMECH7
CH7
CH8
NAMECH8
NAMECH9
CH9
CH10
NAMECH10
NAMECH11
CH11
CH12
NAMECH12
en05000714.vsd
39
Analog inputs Chapter 3
Basic IED functions
40
Analog inputs Chapter 3
Basic IED functions
Table 10: Output signals for the ANALOGIN6I6U (TD40-) function block
Signal Description
ERROR Analogue input module status
CH1 Analogue input 1
CH2 Analogue input 2
CH3 Analogue input 3
CH4 Analogue input 4
CH5 Analogue input 5
CH6 Analogue input 6
CH7 Analogue input 7
CH8 Analogue input 8
CH9 Analogue input 9
CH10 Analogue input 10
CH11 Analogue input 11
CH12 Analogue input 12
Table 12: Basic general settings for the ANALOGIN12I (TA40-) function
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
41
Analog inputs Chapter 3
Basic IED functions
42
Analog inputs Chapter 3
Basic IED functions
Table 13: Basic general settings for the ANALOGIN9I3U (TC40-) function
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
43
Analog inputs Chapter 3
Basic IED functions
44
Analog inputs Chapter 3
Basic IED functions
Table 14: Basic general settings for the ANALOGIN6I6U (TD40-) function
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim5 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint6 FromObject - ToObject - ToObject= towards pro-
ToObject tected object, FromOb-
ject= the opposite
CTsec6 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim6 1 - 99999 1 3000 A Rated CT primary current
VTsec7 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim7 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec8 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim8 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec9 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
45
Analog inputs Chapter 3
Basic IED functions
46
Authorization Chapter 3
Basic IED functions
2 Authorization
To safeguard the interests of our customers, both the IED 670 and the tools that are accessing
the IED 670 are protected, subject of authorization handling. The concept of authorization, as it
is implemented in the IED 670 and the associated tools is based on the following facts:
The IED users can be created, deleted and edited only with the User Management Tool (UMT)
within PCM 600. The user can only LogOn or LogOff on the LHMI of the IED, there are no
users, groups or functions that can be defined on the IED LHMI.
47
Authorization Chapter 3
Basic IED functions
Figure 24: Right-clicking to get the User Management Tool IED Users.
By left-clicking on the IED Users submenu, the tool will open in the right-side panel:
48
Authorization Chapter 3
Basic IED functions
By default, the IEDs are delivered so that users are not required to log on to operate the IED.
The default user is the SuperUser. Before doing any changes to the User Management in the IED
it is recommendable that the administrator uploads the Users and Groups existent in the IED.
If situation requires so, one can restore the factory settings, overwriting all existing settings in
the User Management Tool database.
Note!
Even if the administrator empties the tool database, the users previously defined are still in the
IED. They cannot be erased by downloading the empty list into the IED (the tool wont down-
load an empty list), so it is strongly recommended that before you create any user you create
one that belongs to the SuperUser group.
If the administrator marks the check box User must logon to this IED, then the fields under
the User Management tab are becoming accessible and one can add, delete and edit users.
To add a new user, the administrator will press the button that is marked with a black arrow, see
figure 26 on the User subtab:
49
Authorization Chapter 3
Basic IED functions
Upon pressing this button, a window will appear, enabling the administrator to enter details
about the user, assign an access password and (after pressing Next and advancing to the next
window) assign the user to a group:
50
Authorization Chapter 3
Basic IED functions
Once the new user is created, it will appear in the list of users. Once in the list, there are several
operations that can be performed on the users, shown in figure 29
No. Description
1 Delete selected user
2 Change password
3 Add another group to the user permissions
51
Authorization Chapter 3
Basic IED functions
The Group subtab is displaying all the pre-defined groups and gives short details of the per-
missions allowed to the members of a particular group:
It also allows the administrator to add another (already created) user to a group, in the same way
it could assign one more group to an user, on the Users subtab.
The Functions subtab is a descriptional area, showing in detail what Read/Write permissions
has each user group, in respect to various tools and components.
Finally, after the desired users are created and permissions assigned to them by means of user
groups, the whole list must be downloaded in the IED, in the same way as from the other tools:
52
Authorization Chapter 3
Basic IED functions
No. Description
1 Upload from IED
2 Download to IED
Once a user is created and downloaded into the IED, that user can perform a LogOn, introducing
the password assigned in the tool.
If there is no user created, an attempt to log on will cause the display to show a message box
saying: No user defined!
If one user leaves the IED without logging off, then after the timeout (set in Settings\General
Settings\HMI\Screen\ Display Timeout ) elapses, the IED will return to a Guest state, when only
reading is possible. The display time out is set to 60 minutes at delivery.
If there are one or more users created with the UMT and downloaded into the IED, then, when
a user intentionally attempts a LogOn or when the user attempts to perform an operation that is
password protected, the LogOn window will appear
The cursor is focused on the User identity field, so upon pressing the E key, one can change
the user name, by browsing the list of users, with the up and down arrows. After choosing
the right user name, the user must press the E key again. When it comes to password, upon
pressing the E key, the following character will show up: $. The user must scroll for every
letter in the pasword. After all the letters are introduced (passwords are case sensitive!) choose
OK and press E key again.
If everything is O.K. at a voluntary LogOn the LHMI returns to the Authorization screen. If the
LogOn is OK, when required to change for example a password protected setting, the LHMI re-
turns to the actual setting folder. If the LogOn has failed, then the LogOn window will pop-up
again, until either the user makes it right or presses Cancel.
53
Self supervision with internal event list Chapter 3
Basic IED functions
3.1 Introduction
The self-supervision function listens and reacts to internal system events, generated by the dif-
ferent built-in self-supervision elements. The internal events are saved in an internal event list.
The self-supervision status can be monitored from the local HMI or a SMS/SCS system.
Under the Diagnostics menu in the local HMI the present information from the self-supervision
function can be reviewed. The information can be found under Diagnostics\Internal Events or
Diagnostics\IED Status\General. Refer to the Installation and Commissioning manual for a
detailed list of supervision signals that can be generated and displayed in the local HMI.
A self-supervision summary can be obtained by means of the potential free alarm contact (IN-
TERNAL FAIL) located on the power supply module. The function of this output relay is an
OR-function between the INT-FAIL signal see figure 32 and a couple of more severe faults that
can occur in the IED, see figure 31
54
Self supervision with internal event list Chapter 3
Basic IED functions
Some signals are available from the IES (IntErrorSign) function block. The signals from this
function block are sent as events to the station level of the control system. The signals from the
IES function block can also be connected to binary outputs for signalization via output relays or
they can be used as conditions for other functions if required/desired.
Individual error signals from I/O modules can be obtained from respective module in the Signal
Matrix Tool. Error signals from time synchronization can be obtained from the time synchroni-
zation block TIME.
55
Self supervision with internal event list Chapter 3
Basic IED functions
56
Self supervision with internal event list Chapter 3
Basic IED functions
57
Self supervision with internal event list Chapter 3
Basic IED functions
Figure 33: Simplified drawing of A/D converter for the 600 platform.
The technique to split the analog input signal into two A/D converters with different amplifica-
tion makes it possible to supervise the incoming signals under normal conditions where the sig-
nals from the two converters should be identical. An alarm is given if the signals are out of the
boundaries. Another benefit is that it improves the dynamic performance of the A/D conversion.
The self-supervision of the A/D conversion is controlled by the ADx_Controller function. One
of the tasks for the controller is to perform a validation of the input signals. This is done in a
validation filter which has mainly two objects: First is the validation part, i.e. checks that the
A/D conversion seems to work as expected. Secondly, the filter chooses which of the two signals
that shall be sent to the CPU, i.e. the signal that has the most suitable level, the ADx_LO or the
16 times higherADx_HI.
When the signal is within measurable limits on both channels, a direct comparison of the two
channels can be performed. If the validation fails, the CPU will be informed and an alarm will
be given.
58
Self supervision with internal event list Chapter 3
Basic IED functions
IS---
InternalSignal
FAIL
WARNING
CPUFAIL
CPUWARN
TSYNCERR
RTCERR
en04000392.vsd
59
Time synchronization Chapter 3
Basic IED functions
4 Time synchronization
4.1 Introduction
Use the time synchronization source selector to select a common source of absolute time for the
IED when it is a part of a protection system. This makes comparison of events and disturbance
data between all IEDs in a SA system possible.
Time definitions
The error of a clock is the difference between the actual time of the clock, and the time the clock
is intended to have. The rate accuracy of a clock is normally called the clock accuracy and means
how much the error increases, i.e. how much the clock gains or loses time. A disciplined clock
is a clock that knows its own faults and tries to compensate for them, i.e. a trained clock.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical structure. A module
is synchronized from a higher level and provides synchronization to lower levels.
Syncronization from
a higher level
Module
Optional syncronization of
modules at a lower level
en05000206.vsd
60
Time synchronization Chapter 3
Basic IED functions
RTC at startup
At IED startup, the internal time is free running. If the RTC is still alive since the last up time,
the time in the IED will be quite accurate (may drift 35 ppm), but if the RTC power has been
lost during power off (will happen after 5 days), the IED time will start at 1970-01-01. For more
information, please refer to section "Time synchronization startup procedure" and section "Ex-
ample, binary synchronization".
If the synchronization message, that is similar to the other messages from its or-
igin has an offset compared to the internal time in the IED, the message is used
directly for synchronization, that is for adjusting the internal clock to obtain zero
offset at the next coming time message.
If the synchronization message has an offset that is large compared to the other
messages, a spike-filter in the IED will remove this time-message.
If the synchronization message has an offset that is large, and the following mes-
sage also has a large offset, the spike filter will not act and the offset in the syn-
chronization message will be compared to a threshold that defaults to 100
milliseconds. If the offset is more than the threshold, the IED is brought into a
safe state and the clock is thereafter set to the correct time. If the offset is lower
than the threshold, the clock will be adjusted with 1000 ppm until the offset is
removed. With an adjustment of 1000 ppm, it will take 100 seconds or 1.7 min-
utes to remove an offset of 100 milliseconds.
Synchronization messages configured as coarse will only be used for initial setting of the time.
After this has been done, the messages are checked against the internal time and only an offset
of more than 10 seconds will reset the time.
Rate accuracy
In the REx670 IED, the rate accuracy at cold start is about 100 ppm, but if the IED is synchro-
nized for a while, the rate accuracy will be approximately 1 ppm if the surrounding temperature
is constant. Normally it will take 20 minutes to reach full accuracy.
61
Time synchronization Chapter 3
Basic IED functions
Coarse message is sent every minute and comprises complete date and time, i.e.
year, month, day, hours, minutes, seconds and milliseconds.
Fine message is sent every second and comprises only seconds and milliseconds.
IEC60870-5-103 is not used to synchronize the relay, but instead the offset between the local
time in the relay and the time received from 103 is added to all times (in events and so on) sent
via 103. In this way the relay acts as it is synchronized from various 103 sessions at the same
time. Actually, there is a local time for each 103 session.
The minute pulse is connected to any channel on any Binary Input Module in the IED. The elec-
trical characteristic is thereby the same as for any other binary input.
If the objective of synchronization is to achieve a relative time within the substation and if no
station master clock with minute pulse output is available, a simple minute pulse generator can
be designed and used for synchronization of the IEDs. The minute pulse generator can be created
using the logical elements and timers available in the IED.
62
Time synchronization Chapter 3
Basic IED functions
The definition of a minute pulse is that it occurs one minute after the last pulse. As only the
flanks are detected, the flank of the minute pulse shall occur one minute after the last flank.
Pulse data:
en05000251.vsd
The default time-out-time for a minute pulse is two minutes, and if no valid minute pulse is re-
ceived within two minutes a SYNCERR will be given.
If contact bounces occurs, only the first pulse will be detected as a minute pulse. The next minute
pulse will be registered first 60 s - 50 ms after the last contact bounce.
If the minute pulses are perfect, e.g. it is exactly 60 seconds between the pulses, contact bounces
might occur 49 ms after the actual minute pulse without effecting the system. If contact bounces
occurs more than 50 ms, e.g. it is less than 59950 ms between the two most adjacent positive (or
negative) flanks, the minute pulse will not be accepted.
63
Time synchronization Chapter 3
Basic IED functions
or the RTC backup still keeps the time since last up-time. If the minute pulse is removed for in-
stance for an hour, the internal time will drift by maximum the error rate in the internal clock. If
the minute pulse is returned, the first pulse automatically is rejected. The second pulse will pos-
sibly be rejected due to the spike filter. The third pulse will either synchronize the time, if the
time offset is more than 100 ms, or adjust the time, if the time offset is small enough. If the time
is set, the application will be brought to a safe state before the time is set. If the time is adjusted,
the time will reach its destination within 1.7 minutes.
The DNP3.0 communication can be ? to be the source of the Course time synchronisation. The
fine synch source must be another when high accuracy time working is required.
The IRIG interface to the IED supplies two possible synchronization methods, IRIG-B and PPS.
IRIG-B
IRIG-B is a protocol used only for time synchronization. A clock can provide local time of the
year in this format. The B in IRIG-B states that 100 bits per second are transmitted, and the
message is sent every second. After IRIG-B there is a number of figures stating if and how the
signal is modulated and the information transmitted.
To receive IRIG-B there are two connectors in the IRIG module, one galvanic BNC connector
and one optical ST connector. IRIG-B 12x messages can be supplied via the galvanic interface,
and IRIG-B 00x messages can be supplied via either the galvanic interface or the optical inter-
face, where x (in 00x or 12x) means a figure in the range 1-7.
00 means that a base band is used, and the information can be fed into the IRIG-B module via
the BNC contact or an optical fiber. 12 means that a 1 kHz modulation is used. In this case the
information must go into the module via the BNC connector.
If the x in 00x or 12x is 4, 5, 6 or 7, the time message from IRIG-B contains information of the
year. If x is 0, 1, 2 or 3, the information only contains the time within the year, and year infor-
mation has to come from the tool or HMI.
The IRIG Module also takes care of IEEE1344 messages that are sent by many IRIG-B clocks,
as IRIG-B previously did not have any year information. IEE1344 is compatible with IRIG-B
and contains year information and information of time-zone.
It is recommended to use IEEE 1344 for supplying time information to the IRIG module. In this
case, also send the local time in the messages, as this local time plus the TZ Offset supplied in
the message equals UTC at all times.
PPS
An optical PPS signal can be supplied to the optical interface of the IRIG module.
The PPS signal is a transition from dark to light, that occurs 1 second +- 2 us after another PPS
signal. The allowed jitter of 2 us is settable.
64
Time synchronization Chapter 3
Basic IED functions
TIME-
TIME
TSYNCERR
RTCERR
en05000425.vsd
Table 21: Basic general settings for the TimeSynch (TSYN-) function
Parameter Range Step Default Unit Description
CoarseSyncSrc Off - Off - Coarse time synchroniza-
SPA tion source
LON
SNTP
DNP
FineSyncSource Off - Off - Fine time synchronization
SPA source
LON
BIN
GPS
GPS+SPA
GPS+LON
GPS+BIN
SNTP
GPS+SNTP
IRIG-B
GPS+IRIG-B
PPS
SyncMaster Off - Off - Activate IEDas synchro-
SNTP-Server nization master
65
Time synchronization Chapter 3
Basic IED functions
66
Time synchronization Chapter 3
Basic IED functions
67
Time synchronization Chapter 3
Basic IED functions
Table 27: Basic general settings for the TimeSynchIRIGB (TIRI-) function
Parameter Range Step Default Unit Description
SynchType BNC - Opto - Type of synchronization
Opto
TimeDomain LocalTime - LocalTime - Time domain
UTC
Encoding IRIG-B - IRIG-B - Type of encoding
1344
1344TZ
TimeZoneAs1344 MinusTZ - PlusTZ - Time zone as in 1344
PlusTZ standard
68
Parameter setting groups Chapter 3
Basic IED functions
5.1 Introduction
Use the six sets of settings to optimize IED operation for different system conditions. By creat-
ing and switching between fine tuned setting sets, either from the human-machine interface or
configurable binary inputs, results in a highly adaptable IED that can cope with a variety of sys-
tem scenarios.
A setting group is selected by using the local HMI, from a front connected personal computer,
remotely from the station control or station monitoring system or by activating the correspond-
ing input to the ACGR function block.
Each input of the function block can be configured to connect to any of the binary inputs in the
IED. To do this the PCM 600 configuration tool must be used.
The external control signals are used for activating a suitable setting group when adaptive func-
tionality is necessary. Input signals that should activate setting groups must be either permanent
or a pulse exceeding 400 ms.
More than one input may be activated at the same time. In such cases the lower order setting
group has priority. This means that if for example both group four and group two are set to ac-
tivate, group two will be the one activated.
Every time the active group is changed, the output signal SETCHGD is sending a pulse.
The parameter MAXSETGR defines the maximum number of setting groups in use to switch be-
tween.
69
Parameter setting groups Chapter 3
Basic IED functions
The above example also includes seven output signals, for confirmation of which group that is
active.
The SGC function block has an input where the number of setting groups used is defined.
Switching can only be done within that number of groups. The number of setting groups selected
to be used will be filtered so only the setting groups used will be shown on the PST setting tool.
ACGR-
ActiveGroup
ACTGRP1 GRP1
ACTGRP2 GRP2
ACTGRP3 GRP3
ACTGRP4 GRP4
ACTGRP5 GRP5
ACTGRP6 GRP6
SETCHGD
en05000433.vsd
70
Parameter setting groups Chapter 3
Basic IED functions
SGC--
NoOfSetGrp
MAXSETGR
en05000716.vsd
Table 30: Output signals for the ActiveGroup (ACGR-) function block
Signal Description
GRP1 Setting group 1 is active
GRP2 Setting group 2 is active
GRP3 Setting group 3 is active
GRP4 Setting group 4 is active
GRP5 Setting group 5 is active
GRP6 Setting group 6 is active
SETCHGD Pulse when setting changed
71
Parameter setting groups Chapter 3
Basic IED functions
72
Test mode functionality Chapter 3
Basic IED functions
6.1 Introduction
Most of the functions in the IED can individually be blocked by means of settings from the local
HMI or PST. To enable these blockings the IED must be set in test mode. When leaving the test
mode, i.e. entering normal mode, these blockings are disabled and everything is set to normal
operation. All testing will be done with actually set and configured values within the IED. No
settings will be changed, thus mistakes are avoided.
While the IED is in test mode, the ACTIVE output of the function block TEST is activated. The
other two outputs of the function block TEST are showing which is the generator of the Test
mode: On state input from configuration (OUTPUT output activated) or setting from LHMI
(SETTING output activated).
While the IED is in test mode, the yellow START LED will flash and all functions are blocked.
Any function can be de-blocked individually regarding functionality and event signalling.
Most of the functions in the IED can individually be blocked by means of settings from the local
HMI. To enable these blockings the IED must be set in test mode (the output ACTIVE in func-
tion block TEST is set to true), see example in figure 40. When leaving the test mode, i.e. enter-
ing normal mode, these blockings are disabled and everything is set to normal operation. All
testing will be done with actually set and configured values within the IED. No settings will be
changed, thus no mistakes are possible.
The blocked functions will still be blocked next time entering the test mode, if the blockings
were not reset.
The blocking of a function concerns all output signals from the actual function, so no outputs
will be activated.
The TEST function block might be used to automatically block functions when a test handle is
inserted in a test switch. A contact in the test switch (RTXP24 contact 29-30) can supply a bi-
nary input which in turn is configured to the TEST function block.
Each of the protection functions includes the blocking from TEST function block. A typical ex-
ample from the undervoltage function is shown in figure 40.
The functions can also be blocked from sending events over IEC 61850 station bus to prevent
filling station and SCADA databases with test events e.g. during a maintenance test.
73
Test mode functionality Chapter 3
Basic IED functions
U Disconnection
Normal voltage
U1<
U2<
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466.vsd
Figure 40: Example of blocking the time delayed undervoltage protection function.
TEST-
Test
INPUT ACTIVE
OUTPUT
SETTING
en05000443.vsd
74
Test mode functionality Chapter 3
Basic IED functions
Table 34: Output signals for the Test (TEST-) function block
Signal Description
ACTIVE Terminal in test mode when active
OUTPUT Test input is active
SETTING Test mode setting is (On) or not (Off)
NOEVENT Event disabled during testmode
75
IED identifiers Chapter 3
Basic IED functions
7 IED identifiers
7.1 Introduction
There are two functions that allow you to identify each IED individually: ProductInformation
function has seven pre-set, settings that are unchangeable but nevertheless very important:
IED Type
ProductDef
FirmwareVer
IEDMainFunType
SerialNo.
Ordering No.
ProductionDate.
Diagnostics/IED Status/ProductIdentifiers
They are very helpful in case of support process (such as repair or maintenance). TerminalID
function is allowing you to identify the individual IED in your system, not only in the substation,
but in a whole region or a country.
76
Signal matrix for binary inputs (SMBI) Chapter 3
Basic IED functions
8.1 Introduction
The SMBI function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way binary inputs are brought in for one
IED 670 configuration.
SI01-
SMBI
INSTNAME BI1
BI1NAME BI2
BI2NAME BI3
BI3NAME BI4
BI4NAME BI5
BI5NAME BI6
BI6NAME BI7
BI7NAME BI8
BI8NAME BI9
BI9NAME BI10
BI10NAME
en05000434.vsd
77
Signal matrix for binary inputs (SMBI) Chapter 3
Basic IED functions
Signal Description
BI6 Binary input 6
BI7 Binary input 7
BI8 Binary input 8
BI9 Binary input 9
BI10 Binary input 10
78
Signal matrix for binary outputs (SMBO) Chapter 3
Basic IED functions
9.1 Introduction
The SMBO function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way binary outputs are sent from one
IED 670 configuration.
SO01-
SMBO
BO1 INSTNAME
BO2 BO1NAME
BO3 BO2NAME
BO4 BO3NAME
BO5 BO4NAME
BO6 BO5NAME
BO7 BO6NAME
BO8 BO7NAME
BO9 BO8NAME
BO10 BO9NAME
BO10NAME
en05000439.vsd
79
Signal matrix for binary outputs (SMBO) Chapter 3
Basic IED functions
Signal Description
BO6 Signal name for BO6 in Signal Matrix Tool
BO7 Signal name for BO7 in Signal Matrix Tool
BO8 Signal name for BO8 in Signal Matrix Tool
BO9 Signal name for BO9 in Signal Matrix Tool
BO10 Signal name for BO10 in Signal Matrix Tool
80
Signal matrix for mA inputs (SMMI) Chapter 3
Basic IED functions
10.1 Introduction
The SMMI function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way milliamp (mA) inputs are brought in
for one IED670 configuration.
The outputs on the SMMI are normally connected to the MVGGIO function block for further
use of the mA signals.
SMI1-
SMMI
INSTNAME AI1
AI1NAME AI2
AI2NAME AI3
AI3NAME AI4
AI4NAME AI5
AI5NAME AI6
AI6NAME
en05000440.vsd
81
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
11.1 Introduction
The SMAI function block (or the pre-processing function block, as it is also known) is used
within the PCM 600 in direct relation with the Signal Matrix Tool SMT (please see the overview
of the engineering process in the Application manual, chapter Engineering of the IED). It
represents the way analog inputs are brought in for one IED 670 configuration.
The output singal AI1 to AI4 are direct output of the in SMT connected input to AI1 to AI4. AIN
is always the neutral current, calculated residual sum or the signal connected to AI4. Note that
function block will always calculate the residual sum of current/voltage if the input is not con-
nected in SMT. Applications with a few exceptions (HEDIF, BBDIF) shall always be connected
to AI3P.
PR01-
SMAI
BLOCK SYNCOUT
DFTSPFC SPFCOUT
GRPNAME AI3P
AI1NAME AI1
AI2NAME AI2
AI3NAME AI3
AI4NAME AI4
TYPE AIN
NOSMPLCY
en05000705.vsd
PR02-
SMAI
BLOCK AI3P
GRPNAME AI1
AI1NAME AI2
AI2NAME AI3
AI3NAME AI4
AI4NAME AIN
TYPE
en07000130.vsd
82
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
Table 41: Output signals for the SMAI (PR01-) function block
Signal Description
SYNCOUT Synchronisation signal from internal DFT reference function
SPFCOUT Number of samples per fundamental cycle from internal DFT ref-
erence function
AI3P Group 1 analog input 3-phase group
AI1 Group 1 analog input 1
AI2 Group 1 analog input 2
AI3 Group 1 analog input 3
AI4 Group 1 analog input 4
AIN Group 1 analog input residual for disturbance recorder
Table 42: Input signals for the SMAI (PR02-) function block
Signal Description
BLOCK Block group 2
Table 43: Output signals for the SMAI (PR02-) function block
Signal Description
AI3P Group 2 analog input 3-phase group
AI1 Group 2 analog input 1
AI2 Group 2 analog input 2
AI3 Group 2 analog input 3
AI4 Group 2 analog input 4
AIN Group 2 analog input residual for disturbance recorder
83
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
Note!
Settings DFTRefExtOut and DFTReference shall be set to default value InternalDFTRef if no
VT inputs are available. Internal nominal frequency DFT reference is then the reference.
Table 44: Basic general settings for the SMAI (PR01-) function
Parameter Range Step Default Unit Description
DFTRefExtOut InternalDFTRef - InternalDFTRef - DFT reference for exter-
AdDFTRefCh1 nal output
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
DFTReference InternalDFTRef - InternalDFTRef - DFT reference
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - Ph-N - Input connection type
Ph-Ph
TYPE 1-2 1 1 Ch 1=Voltage,2=Current
84
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
Table 45: Advanced general settings for the SMAI (PR01-) function
Parameter Range Step Default Unit Description
Negation Off - Off - Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 1 10 % Limit for frequency calcu-
lation in % of UBase
UBase 0.05 - 2000.00 0.05 400.00 kV Base Voltage
Table 46: Basic general settings for the SMAI (PR02-) function
Parameter Range Step Default Unit Description
DFTReference InternalDFTRef - InternalDFTRef - DFT reference
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - Ph-N - Input connection type
Ph-Ph
TYPE 1-2 1 1 Ch 1=Voltage,2=Current
Table 47: Advanced general settings for the SMAI (PR02-) function
Parameter Range Step Default Unit Description
Negation Off - Off - Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 1 10 % Limit for frequency calcu-
lation in % of UBase
UBase 0.05 - 2000.00 0.05 400.00 kV Base Voltage
85
Summation block 3 phase (SUM3Ph) Chapter 3
Basic IED functions
12.1 Introduction
The SUM3Ph function block is used in order to get the sum of two sets of 3 ph analog signals
(of the same type) for those IED functions that might need it.
SU01-
Sum3Ph
BLOCK AI3P
DFTSYNC AI1
DFTSPFC AI2
G1AI3P AI3
G2AI3P AI4
en05000441.vsd
Table 49: Output signals for the Sum3Ph (SU01-) function block
Signal Description
AI3P Group analog input 3-phase group
AI1 Group 1 analog input
AI2 Group 2 analog input
AI3 Group 3 analog input
AI4 Group 4 analog input
86
Summation block 3 phase (SUM3Ph) Chapter 3
Basic IED functions
Note!
Settings DFTRefExtOut and DFTReference shall be set to default value InternalDFTRef if no
VT inputs are available.
Table 50: Basic general settings for the Sum3Ph (SU01-) function
Parameter Range Step Default Unit Description
SummationType Group1+Group2 - Group1+Group2 - Summation type
Group1-Group2
Group2-Group1
-(Group1+Group2)
DFTReference InternalDFTRef - InternalDFTRef - DFT reference
AdDFTRefCh1
External DFT ref
Table 51: Advanced general settings for the Sum3Ph (SU01-) function
Parameter Range Step Default Unit Description
FreqMeasMinVal 5 - 200 1 10 % Amplitude limit for fre-
quency calculation in %
of Ubase
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
87
Authority status (AUTS) Chapter 3
Basic IED functions
13.1 Introduction
The AUTS function block (or the authority status function block) is an indication function block,
which informs about two events related to the IED and the user authorization:
the fact that at least one user has tried to log on wrongly into the IED and it was
blocked (the output USRBLKED)
the fact that at least one user is logged on (the output LOGGEDON)
AUTS-
AuthStatus
USRBLKED
LOGGEDON
en06000503.vsd
88
Goose binary receive Chapter 3
Basic IED functions
GB01-
GooseBinRcv
BLOCK OUT1
INSTNAME OUT1VAL
OUT2
OUT2VAL
OUT3
OUT3VAL
OUT4
OUT4VAL
OUT5
OUT5VAL
OUT6
OUT6VAL
OUT7
OUT7VAL
OUT8
OUT8VAL
OUT9
OUT9VAL
OUT10
OUT10VAL
OUT11
OUT11VAL
OUT12
OUT12VAL
OUT13
OUT13VAL
OUT14
OUT14VAL
OUT15
OUT15VAL
OUT16
OUT16VAL
OUT1NAM
OUT2NAM
OUT3NAM
OUT4NAM
OUT5NAM
OUT6NAM
OUT7NAM
OUT8NAM
OUT9NAM
OUT10NAM
OUT11NAM
OUT12NAM
OUT13NAM
OUT14NAM
OUT15NAM
OUT16NAM
en07000047.vsd
89
Goose binary receive Chapter 3
Basic IED functions
Table 54: Output signals for the GooseBinRcv (GB01-) function block
Signal Description
OUT1 Binary output 1
OUT1VAL Valid data on binary output 1
OUT2 Binary output 2
OUT2VAL Valid data on binary output 2
OUT3 Binary output 3
OUT3VAL Valid data on binary output 3
OUT4 Binary output 4
OUT4VAL Valid data on binary output 4
OUT5 Binary output 5
OUT5VAL Valid data on binary output 5
OUT6 Binary output 6
OUT6VAL Valid data on binary output 6
OUT7 Binary output 7
OUT7VAL Valid data on binary output 7
OUT8 Binary output 8
OUT8VAL Valid data on binary output 8
OUT9 Binary output 9
OUT9VAL Valid data on binary output 9
OUT10 Binary output 10
OUT10VAL Valid data on binary output 10
OUT11 Binary output 11
OUT11VAL Valid data on binary output 11
OUT12 Binary output 12
OUT12VAL Valid data on binary output 12
OUT13 Binary output 13
OUT13VAL Valid data on binary output 13
OUT14 Binary output 14
OUT14VAL Valid data on binary output 14
OUT15 Binary output 15
OUT15VAL Valid data on binary output 15
OUT16 Binary output 16
90
Goose binary receive Chapter 3
Basic IED functions
Signal Description
OUT16VAL Valid data on binary output 16
OUT1NAM Signal name for reservation request in Signal Matrix Tool
OUT2NAM Signal name for reservation request in Signal Matrix Tool
OUT3NAM Signal name for reservation request in Signal Matrix Tool
OUT4NAM Signal name for reservation request in Signal Matrix Tool
OUT5NAM Signal name for reservation request in Signal Matrix Tool
OUT6NAM Signal name for reservation request in Signal Matrix Tool
OUT7NAM Signal name for reservation request in Signal Matrix Tool
OUT8NAM Signal name for reservation request in Signal Matrix Tool
OUT9NAM Signal name for reservation request in Signal Matrix Tool
OUT10NAM Signal name for reservation request in Signal Matrix Tool
OUT11NAM Signal name for reservation request in Signal Matrix Tool
OUT12NAM Signal name for reservation request in Signal Matrix Tool
OUT13NAM Signal name for reservation request in Signal Matrix Tool
OUT14NAM Signal name for reservation request in Signal Matrix Tool
OUT15NAM Signal name for reservation request in Signal Matrix Tool
OUT16NAM Signal name for reservation request in Signal Matrix Tool
91
Goose binary receive Chapter 3
Basic IED functions
92
About this chapter Chapter 4
Differential protection
Chapter 4 Differential
protection
93
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1.1 Introduction
The REx 670 differential function for two winding and three winding transformers is provided
with internal CT ratio matching and vector group compensation, when required zero sequence
current elimination is made internally in the software.
The function can be provided with up to six three phase sets of current inputs. All current inputs
are provided with percentage bias restraint features, making the REx 670 suitable for two- or
three winding transformers in multi-breaker station arrangements.
94
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
2-winding applications
2-winding power
transformer
xx05000048.vsd
2-winding power
transformer with
unconnected delta ter-
xx05000049.vsd tiary winding
2-winding power
transformer with 2 cir-
cuit breakers on one
xx05000050.vsd side
2-winding power
transformer with 2 cir-
cuit breakers and 2
CT-sets on both sides
xx05000051.vsd
3-winding applications
3-winding power
transformer with all
three windings con-
nected
xx05000052.vsd
3-winding power
transformer with 2 cir-
cuit breakers and 2
CT-sets on one side
xx05000053.vsd
Autotransformer with 2
circuit breakers and 2
CT-sets on 2 out of 3
sides
xx05000057.vsd
95
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The setting facilities cover for applications of the differential protection to all types of power
transformers and autotransformers with or without on-load tap-changer as well as for shunt re-
actor or and local feeder within the station. An adaptive stabilizing feature is included for heavy
through-faults. By introducing the tap changer position, the differential protection pick-up can
be set to optimum sensitivity covering internal faults with low fault level.
Stabilization is included for inrush currents respectively for overexcitation condition. Adaptive
stabilization is also included for system recovery inrush and CT saturation for external faults. A
fast high set unrestrained differential current protection is included for very high speed tripping
at high internal fault currents.
Innovative sensitive differential protection feature, based on the theory of symmetrical compo-
nents, offers best possible coverage for power transformer windings turn-to-turn faults.
The main CTs are normally supposed to be starWYE connected. The main CTs can be stared in
any way (i.e. either "ToObject" or "FromObject"). However internally the differential function
will always use reference directions towards the protected transformer as shown in figure 51.
Thus the IED will always internally measure the currents on all sides of the power transformer
with the same reference direction towards the power transformer windings.
IW1 IW2
Z1S1 Z1S2
E1S1 E1S2
IW1 IW2
IED
en05000186.vsd
Even in a healthy power transformer, the currents are generally not equal when they flow
through the power transformer, due to the turn"s ratio and the connection group of the protected
transformer. Therefore the differential protection must first correlate all currents to each other
before any calculation can be performed.
96
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Numerical IEDs have brought a large number of well-known advantages and new functionality
to the protective relaying. One of the benefits is the simplicity and accuracy of calculating sym-
metrical components from individual phase quantities. Within the firmware of a numerical IED,
it is no more difficult to calculate negative-sequence components than it is to calculate zero-se-
quence components. Diversity of operation principles integrated in the same protection function
enhances the overall performance without a significant increase in cost.
Before any differential current can be calculated, the power transformer phase shift, and its
transformation ratio, must be allowed for. Conversion of all currents to a common reference is
performed in two steps:
all current phasors are phase-shifted to (i.e. referred to) the phase-reference side,
(whenever possible a first winding with starWYE connection)
all currents magnitudes are always referred to the first winding of the power
transformer (typically transformer high-voltage side)
97
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The two steps of conversion are made simultaneously on-line by the pre-programmed coeffi-
cient matrices, as shown in equation 1 for a two-winding power transformer, and in equation 2
for a three-winding power transformer.
Note!
These are internal compensation within the differential function. The protected power trans-
former data are always entered as they are given on the nameplate. Differential function will by
it self correlate nameplate data and select proper reference windings.
1 2 3
(Equation 1)
where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side
1 2 3 4
(Equation 2)
where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side
4. is Differential current contribution from W3 side
98
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1. Power transformer winding connection type, such as starWYE (i.e. Y/y) or delta
(i.e. D/d)
2. Transformer vector group such as Yd1, Dy11, YNautod5, Yy0d5 etc., which in-
troduce phase displacement between individual windings currents in multiples of
30.
3. Settings for elimination of zero sequence currents for individual windings.
When the end user enters all these parameters, transformer differential function automatically
calculates off-line the matrix coefficients. During this calculations the following rules are used:
For the phase reference, the first winding with set starWYE (i.e. Y) connection is always used.
For example, if the power transformer is a Yd1 power transformer, the HV winding (Y) is taken
as the phase reference winding. If the power transformer is a Dy1, then the LV winding (y) is
taken for the phase reference. If there is no starWYE connected winding, such as in Dd0 type
of power transformers, then the HV delta winding (D) is automatically chosen as the phase ref-
erence winding.
The fundamental frequency differential currents are in general composed of currents of all se-
quences, i.e. the positive-, the negative-, and the zero-sequence currents. If the zero-sequence
currents are eliminated (see section "Optional Elimination of Zero-sequence Currents"), then
99
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
the differential currents can consist only of the positive-, and the negative-sequence currents.
When the zero-sequence current is subtracted on one power transformer side, then it is subtract-
ed from each individual phase current.
As it can be seen from equation 1 and equation 2 the first entered winding (i.e. W1) is always
taken for ampere level reference (i.e. current magnitudes from all other sides are always trans-
ferred to W1 side). In other words, within the differential protection function, all differential cur-
rents and bias current are always expressed in HV side primary Amperes.
It can be shown that the values of the matrix A, B & C coefficients (see equation 1 and
equation 2) can be in advanced pre-calculated depending on the relative phase shift between the
reference winding and other power transformer windings.
Table 58 summarizes the values of the matrices for all standard phase shifts between windings.
Matrix for winding with 30 lagging Not applicable. Matrix on the left
1 -1 0 used.
1
0 1 1
3
1 0 1
Matrix for winding with 90 lagging Not applicable. Matrix on the left
0 -1 1 used.
1
1 0 1
3
1 1 0
100
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Matrix for winding with 90 leading Not applicable. Matrix on the left
0 1 -1 used.
1
-1 0 1
3
1 1 0
Matrix for winding with 30 leading Not applicable. Matrix on the left
1 0 -1 used.
1
-1 1 0
3
0 1 1
By using this table complete equation for calculation of fundamental frequency differential cur-
rents for two winding power transformer with YNd5 vector group and enabled zero sequence
current reduction on HV side will be derived. From the given power transformer vector group
the following is possible to be concluded:
101
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1. HV winding will be used as reference winding and zero sequence currents shall
be subtracted on that side
2. LV winding is lagging for 150
With help of table 58, the following matrix equation can be written for this power transformer:
where:
IDL1 is the fundamental frequency differential current in phase L1
(in W1 side primary amperes)
IDL2 is the fundamental frequency differential current in phase L2
(in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3
(in W1 side primary amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
IL2_W1 is the fundamental frequency phase current in phase L2 on W1 side
IL3_W1 is the fundamental frequency phase current in phase L3 on W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on W2 side
IL2_W2 is the fundamental frequency phase current in phase L2 on W2 side
IL3_W2 is the fundamental frequency phase current in phase L3 on W2 side
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)
As marked in equation 1 and equation 2, the first term on the right hand side of the equation,
represents the total contribution from the individual phase currents from W1 side to the funda-
mental frequency differential currents compensated for eventual power transformer phase shift.
The second term on the right hand side of the equation, represents the total contribution from the
individual phase currents from W2 side to the fundamental frequency differential currents com-
pensated for eventual power transformer phase shift and transferred to the power transformer
W1 side. The third term on the right hand side of the equation, represents the total contribution
from the individual phase currents from W3 side to the fundamental frequency differential cur-
rents compensated for eventual power transformer phase shift and transferred to the power trans-
former W1 side. These current contributions are important, because they are used for calculation
of common bias current.
The fundamental frequency differential currents are the "usual" differential currents, the magni-
tudes of which are applied in a phase-wise manner to the operate - restrain characteristic of the
differential protection. The magnitudes of the differential currents can be read as service values
102
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
from the function and they are available as outputs IDL1MAG, IDL2MAG, IDL3MAG from the
differential protection function block. Thus they can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.
Differential currents are calculated as shown in equation 1and equation 2. If by setting parame-
ters is defined on which winding OLTC is located and what is the no-load voltage change for
each step the differential function will make no load voltage on that power transformer side de-
pendent on actual OLTC position. Thus, if for example the OLTC is located within winding 1
the no-load voltage Vn_W1 will be treated as function of actual OLTC position in equation 1and
equation 2. Thus for every OLTC position corresponding value for Ur_W1 will be calculated
and used in above-mentioned equations. By doing this complete on-line compensation for
OLTC movement is achieved. Differential protection will be ideally balanced for every OLTC
position and no false differential current will appear irrespective on actual OLTC position.
Typically the minimum differential protection pickup for power transformer with OLTC is set
between 30% to 40%. However with this OLTC compensation feature it is possible to set differ-
ential protection in IED 670 to more sensitive pickup value of 15% to 20%.
OLTC position is measured within IEC 670 by function block YLTC. Within this function block
the OLTC position value is continuously monitored to insure its integrity. When any error with
OLTC position is detected the alarm is given which shall be connected to the OLTCxAL input
into the differential function block. While OLTCxAL input has logical value one the differential
protection minimum pickup, originally defined by setting parameter IdMin, will be increased by
the set range of the OLTC. Alternatively the differential current alarm feature can be used to
alarm for any problems in the whole OLTC compensation chain.
two-winding differential protection in IED 670 can on-line compensate for one
OLTC within protected power transformer
three-winding differential protection in IED 670 can on-line compensate for up
to two OLTCs within protected power transformer
103
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Bias current
The bias current is calculated as the highest current amongst individual winding current contri-
butions to the total fundamental frequency differential currents, as shown in equation 1 and
equation 2. All individual winding current contributions are already referred to the power trans-
former winding one side Amperes (typically power transformer HV winding) and therefore they
can be compared regarding their magnitudes. There are six (or nine in case of three winding
transformer) contributions to the total fundamental differential currents, which are the candi-
dates for the common bias current. The highest individual current contribution is taken as a com-
mon bias (restrain) current for all three phases. This "maximum principle" makes the differential
protection more secure, with less risk to operate for external faults and in the same time brings
more meaning to the breakpoint settings of the operate - restrain characteristic.
It shall be noted that if the zero-sequence currents are subtracted from the separate contributions
to the total differential current, then the zero-sequence component is automatically eliminated
from the bias current as well. This ensures that for secondary injection from just one power
transformer side the bias current is always equal to the highest differential current regardless of
the fault type. During normal through-load operation of the power transformer, the bias current
is equal to the maximum load current from two (three) power transformer windings.
The magnitudes of the common bias (restrain) current expressed in the HV side Amperes can be
read as service values from the function. In the same time it is available as outputs IBIAS from
the differential protection function block. Thus, it can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.
For application with so called "T" configuration, i.e. two restraint CT inputs from one side of the
protected power transformer, such as in the case of breaker-and-a-half scheme the primary CT
ratings can be much higher then the rating of the protected power transformer. In order to deter-
mine the bias current for such T configuration, the two separate currents flowing on the T-side
can be scaled by additional setting. This is done in order to prevent unwanted de-sensitizing of
the overall differential protection. In addition to that, the resultant currents into the protected
power transformer winding, which is not directly measured is calculated, and included as well
in the common bias calculation. The rest of the bias calculation procedure is the same as in pro-
tection schemes without breaker-and-a-half scheme.
In most cases, power transformers do not properly transform the zero sequence current to the
other side. A typical example is a power transformer of the starWYE-delta type, e.g. YNd1.
Transformers of this type do not transform the zero-sequence quantities, but zero-sequence cur-
rents can flow in the earthed star connected winding. In such cases, an external earth fault on the
104
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
starWYE-side causes the zero-sequence currents to flow on the starWYE-side of the power
transformer, but not on the other side. This results in false differential currents - consisting ex-
clusively of the zero-sequence currents. If high enough, these false differential currents can
cause an unwanted disconnection of the healthy power transformer. They must therefore be sub-
tracted from the fundamental frequency differential currents if an unwanted trip is to be avoided.
For delta windings this feature shall be enabled only if an earthing transformer exist within dif-
ferential zone on the delta side of the protected power transformer.
Removing the zero-sequence current from the differential currents decreases to some extent sen-
sitivity of the differential protection for the internal earth faults. In order to counteract this effect
to some degree, the zero-sequence currents are subtracted not only from the three fundamental
frequency differential currents, but automatically from the bias current as well.
The unrestrained (i.e. non-stabilized) part of the differential protection is used for very big dif-
ferential currents, where it should be beyond any doubt, that the fault is internal. This settable
limit is constant (i.e. not proportional the bias current). Neither harmonic, nor any other restrain
is applied to this limit, which is therefore allowed to trip power transformer instantaneously.
The restrained (i.e. stabilized) part of the differential protection compares the calculated funda-
mental differential (i.e. operating) currents, and the bias (i.e. restrain) current, by applying them
to the operate - restrain characteristic. Practically, the magnitudes of the individual fundamental
frequency differential currents are compared with an adaptive limit. This limit is adaptive be-
cause it is dependent on the bias (i.e. restrain) current magnitude. This limit is called the operate
- restrain characteristic. It is represented by a double-slope, double-breakpoint characteristic, as
shown in figure 52. The restrained characteristic is determined by the following 5 settings:
1. IdMin (Sensitivity in section 1, multiple of trans. HV side rated current set under
the parameter RatedCurrentW1)
2. EndSection1 (End of section 1, as multiple of transformer HV side rated current
set under the parameter RatedCurrentW1)
3. EndSection2 (End of section 2, as multiple of transformer HV side rated current
set under the parameter RatedCurrentW1)
4. SlopeSection2 (Slope in section 2, as multiple of transformer HV side rated cur-
rent set under the parameter RatedCurrentW1)
5. SlopeSection3 (Slope in section 2, as multiple of transformer HV side rated cur-
rent set under the parameter RatedCurrentW1)
1. IdMin
2. EndSection1
3. EndSection2
4. SlopeSection2
5. SlopeSection3
105
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
operate current
[ times I1r ]
Operate
5
unconditionally
UnrestrainedLimit
4
Operate
3
conditionally
2
Section 1 Section 2 Section 3
SlopeSection3
1
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5
EndSection1
restrain current
EndSection2 [ times I1r ]
en05000187.vsd
where:
Figure 52: Description of the restrained-, and the unrestrained operate characteristics
The operate - restrain characteristic is tailor-made and can be designed freely by the user after
his needs. A default characteristic is recommended to be used. It gives good results in a majority
of applications. The operate - restrain characteristic has in principle three sections with a sec-
tion-wise proportionality of the operate value to the bias (restrain) current. The reset ratio is in
all parts of the characteristic is equal to 0.95.
Section 1: This is the most sensitive part on the characteristic. In section 1, normal currents flow
through the protected circuit and its current transformers, and risk for higher false differential
currents is relatively low. Un-compensated on-load tap-changer is a typical reason for existence
of the false differential currents in this section. Slope in section 1 is always zero percent.
106
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Section 2: In section 2, a certain minor slope is introduced which is supposed to cope with false
differential currents proportional to higher than normal currents through the current transform-
ers.
Section 3: The more pronounced slope in section 3 is designed to result in a higher tolerance to
substantial current transformer saturation at high through-fault currents, which may be expected
in this section.
The operate - restrain characteristic should be designed so that it can be expected that:
for internal faults, the operate (differential) currents are always safely, i.e. with a
good margin, above the operate - restrain characteristic
for external faults, the false (spurious) operate currents are safely, i.e. with a good
margin, below the operate - restrain characteristic
For power transformer differential protection application, the negative-sequence based differen-
tial currents are calculated by using exactly the same matrix equations, which are used to calcu-
late the traditional phase-wise fundamental frequency differential currents. However, the same
equation shall be fed by the negative-sequence currents from the two power transformer sides
instead of individual phase currents, as shown in matrix equation 4 for a case of two-winding,
YNd5 power transformer.
1 2 3
(Equation 4)
where:
1. is Neg. Seq. Diff Currents
2. is Negative Sequence current contribution from W1 side
3. is Negative Sequence current contribution from W2 side
107
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
and where:
IDL1_NS is the negative sequence differential current in phase L1 (in W1 side primary amperes)
IDL2_NS is the negative sequence differential current in phase L2 (in W1 side primary amperes)
IDL3_NS is the negative sequence differential current in phase L3 (in W1 side primary amperes)
INS_W1 is negative sequence current on W1 side in primary amperes (phase L1 reference)
INS_W2 is negative sequence current on W1 side in primary amperes (phase L1 reference)
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)
j 120
o 1 3
a is the complex operator for sequence quantities, e.g. a=e = + j
2 2
Because the negative sequence currents always form the symmetrical three phase current system
on each transformer side (i.e. negative sequence currents in every phase will always have the
same magnitude and be phase displaced for 120 electrical degrees from each other), it is only
necessary to calculate the first negative sequence differential current i.e. IDL1_NS.
As marked in equation 4, the first term on the right hand side of the equation, represents the total
contribution of the negative sequence current from W1 side compensated for eventual power
transformer phase shift. The second term on the right hand side of the equation, represents the
total contribution of the negative sequence current from W2 side compensated for eventual pow-
er transformer phase shift and transferred to the power transformer W1 side. These negative se-
quence current contributions are phasors, which are further used in directional comparisons,
made in order to characterize a fault as internal or external. See section "Internal/external fault
discriminator" for more information.
The magnitudes of the negative sequence differential current expressed in the HV side Amperes
can be read as service values from the function. In the same time it is available as outputs IDNS-
MAG from the differential protection function block. Thus, it can be connected to the distur-
bance recorder and automatically recorded during any external or internal fault condition.
The algorithm of the internal/external fault discriminator is based on the theory of symmetrical
components. Already in 1933, Wagner and Evans in their famous book "Symmetrical Compo-
nents" have stated that:
108
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The internal/external fault discriminator responds to magnitudes and the relative phase angles
of the negative-sequence fault currents at different windings (i.e. sides) of the protected power
transformer. The negative sequence fault currents must of course first be referred to the same
phase reference side, and put to the same magnitude reference. This is done by the matrix ex-
pression (see equation 4).
Operation of the internal / external fault discriminator is based on the relative position of the two
phasors representing winding one (i.e. W1) and winding two (i.e. W2) negative-sequence cur-
rent contributions, defined by expression shown in equation 4. It practically performs directional
comparison between these two phasors. First, the LV side phasors is positioned along the zero
degree line. After that the relevant position of the HV side phasor in the complex plain is deter-
mined. In case of three-winding power transformers, a little more complex algorithm is applied,
with two directional tests. The overall directional characteristic of the internal/external fault dis-
criminator is shown in figure 53, where the directional characteristic is defined by two setting
parameters:
1. IMinNegSeq
2. NegSeqROA
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
90 deg
120 deg
If one or the Internal/external
other of fault boundary
currents is too
low, then no
measurement NegSeqROA
is done, and
(Relay
120 degrees
Operate
is mapped
Angle)
IMinNegSeq
External Internal
fault fault
region region
270 deg
en05000188.vsd
In order to perform directional comparison of the two phasors their magnitudes must be high
enough so that one can be sure that they are due to a fault. On the other hand, in order to guar-
antee a good sensitivity of the internal/external fault discriminator, the value of this minimum
limit must not be too high. Therefore this limit value, called IminNegSeq, is settable in the range
from 1% to 20% of the differential protection"s base current, which is the power transformer
winding one rated current. The default value is 4%. Only if magnitudes of both negative se-
quence current contributions are above the set limit, the relative position between these two pha-
sors is checked. If either of the negative sequence current contributions, which should be
compared, is too small (less than the set value for IminNegSeq), no directional comparison is
made in order to avoid the possibility to produce a wrong decision. This magnitude check, as
well guarantee stability of the algorithm, when power transformer is energized. The setting Neg-
SeqROA represents the so-called Relay Operate Angle, which determines the boundary between
the internal and external fault regions. It can be selected in the range from 30 degrees to 90
degrees, with a step of 1 degree. The default value is 60 degrees. The default setting somewhat
favours security in comparison to dependability.
If the above condition concerning magnitudes is fulfilled, the internal/external fault discrimina-
tor compares the relative phase angle between the negative sequence current contributions from
the W1 and W2 sides of the power transformer using the following two rules:
110
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
If the negative sequence currents contributions from W1 and W2 sides are 180
degrees out of phase, the fault is external (i.e. W1 phasors is outside internal fault
region)
For example, for any unsymmetrical external fault, the respective negative sequence current
contributions from the W1 and W2 power transformer sides will be exactly 180 degrees apart
and equal in magnitude, regardless the power transformer turns ratio and phase displacement.
One such example is shown in figure 54, which shows trajectories of the two separate phasors
representing the negative-sequence current contributions from HV and LV sides of an Yd5 pow-
er transformer (e.g. after the compensation of the transformer turns ratio and phase displacement
by using equation 4) for an unsymmetrical external fault. Observe that the relative phase angle
between these two phasors is 180 electrical degrees at any point in time. There is not any current
transformer saturation for this case.
"steady state"
for HV side 90
neg. seq. phasor
60
150 30
10
ms
180 0
0.1 kA
0.2 kA
0.3 kA
10 0.4 kA
ms
210 330
"steady state"
240 for LV side
270 neg. seq. phasor
en05000189.vsd
Figure 54: Trajectories of Negative Sequence Current Contributions from HV and LV sides
of Yd5 power transformer during external fault
Therefore, under all external fault condition, the relative angle is theoretically equal to 180 de-
grees. During internal fault, the angle shall ideally be 0 degrees, but due to possible different
negative sequence source impedance angles on W1 and W2 sides of the protected power trans-
111
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
former, it may differ somewhat from the ideal zero value. However, during heavy faults, CT sat-
uration might cause the measured phase angle to differ from 180 degrees for external, and from
about 0 degrees for internal fault. See figure 55 for an example of a heavy internal fault with
transient CT saturation.
180 0
trip command
in 12 ms
external
fault Internal fault
0.5 kA declared 7 ms
region
210 330 after internal
fault occured
1.0 kA
240 300
1.5 kA
270
HV side contribution to the total negative sequence differential current in kA
Directional limit (within the region delimited by 60 degrees is internal fault)
en05000190.vsd
Figure 55: Operation of the internal/external fault discriminator for internal fault with CT
saturation
However it shall be noted that additional security measures are implemented in the internal/ex-
ternal fault discriminator algorithm in order to guaranty proper operation with heavily saturated
current transformers. The trustworthy information on whether a fault is internal or external is
typically obtained in about ten milliseconds after the fault inception, depending on the setting
IminNegSeq, and the magnitudes of the fault currents. At heavy faults, approximately five mil-
liseconds time-to-saturation of the main CT is sufficient in order to produce a correct discrimi-
nation between internal and external faults.
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
If the same fault has been positively recognized as internal, then the unrestrained negative se-
quence differential protection places its own trip request. Any block signals by the harmonic and
/ or waveform criteria, which can block the traditional differential protection are overridden, and
the differential protection operates quickly without any further delay. This logic guarantees a
fast disconnection of a faulty power transformer for any heavier internal faults.
If the same fault has been classified as external, then generally, but not unconditionally, a trip
command is prevented. If a fault is classified as external, the further analysis of the fault condi-
tions is initiated. If all the instantaneous differential currents in phases where start signals have
been issued are free of harmonic pollution, then a (minor) internal fault, simultaneous with a pre-
dominant external fault can be suspected. This conclusion can be drawn because at external
faults, major false differential currents can only exist when one or more current transformers sat-
urate. In this case, the false instantaneous differential currents are polluted by higher harmonic
components, the 2nd, the 5th, etc.
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Harmonic restrain
The harmonic restrain is the classical restrain method traditionally used with power transformer
differential protections. The goal is to prevent an unwanted trip command due to magnetizing
inrush currents at switching operations, or due to magnetizing currents at over-voltages.
The magnetizing currents of a power transformer flow only on one side of the power transformer
(one or the other) and are therefore always the cause of false differential currents. The harmonic
analysis (the 2nd and the 5th harmonic) is applied to instantaneous differential currents. Typically
instantaneous differential currents during power transformer energizing are shown in figure 56.
The harmonic analysis is only applied in those phases, where start signals have been set. For ex-
ample, if the content of the 2nd harmonic in the instantaneous differential current of phase L1 is
above the setting I2/I1Ratio, then a block signal is set for that phase, which can be read as
BLK2HL1 output of the differential protection.
Waveform restrain
The waveform restrain criterion is a good complement to the harmonic analysis. The waveform
restrain is a pattern recognition algorithm, which looks for intervals within each fundamental
power system cycle with low instantaneous differential current. This interval is often called cur-
rent gap in protection literature. However, within differential function this criterion actually
searches for long-lasting intervals with low rate-of-change in instantaneous differential current,
which are typical for the power transformer inrush currents. Block signals BLKWAVLx are set
in those phases where such behavior is detected. The algorithm do not requires any end-user set-
tings. The waveform algorithm is automatically adapted dependent only on the power transform-
er rated data.
Figure 56: Inrush currents to a transformer as seen by a protective IED. Typical is a high
amount of the 2nd harmonic, and intervals of low current-, and low rate-of-change
of current within each period.
114
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
When parameter OpCrossBlock=On cross blocking between phases will be introduced. There is
not any time settings involved, but the phase with the operating point above the set bias charac-
teristic (i.e. in the operate region) will be able to cross-block other two phases if it is self-blocked
by any of the previously explained restrained criteria. As soon as the operating point for this
phase is below the set bias characteristic (i.e. in the restrain region) cross blocking from that
phase will be inhibited. In this way cross-blocking of the temporary nature is achieved. In should
be noted that this is the default (i.e. recommended) setting value for this parameter.
When parameter OpCrossBlock=Off, any cross blocking between phases will be disabled. It is
recommended to use the value Off with caution in order to avoid the unwanted tripping during
initial energizing of the power transformer.
The open CT circuit condition will create unexpected operations for line differential protection
function under the normal load conditions. It is also possible to damage secondary equipment
due to high voltage produced from open CT circuit outputs. Therefore, it is always a requirement
from security and reliability points of view to have open CT detection function to block the dif-
ferential protection function in case of open CT conditions and at the same time, produce the
alarm signal to the operational personal to make quick remedy actions to correct the open CT
condition.
The built-in open CT feature in RED 670 can be enabled or disabled by a setting parameter
OpenCTEnable(Off/On). When enabled, this feature will prevent mal-operation of the line dif-
ferential function when a loaded main CT connected to the differential protection is by mistake
open circuited on the secondary side. It shall be noted that this feature can only detect interrup-
tion of one CT phase current at the time. If two or even all three-phase currents of one set of CT
are accidentally interrupted at the same time this feature cannot operate and the differential func-
tion will give trip signal if the false differential current is sufficiently high. In order to ensure
115
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
blocking of the differential protection for open CT condition this algorithm must operate within
10 ms in order to be able to prevent unwanted operation of the differential protection under all
loading conditions.
The principle applied in order to detect an open CT is a simple pattern recognition method, sim-
ilar to the waveform check which has been with advantage used by the Power Transformer Dif-
ferential Protection in order to detect the magnetizing inrush condition. The open CT detection
principle is based on the fact, that for an open CT, the current in the phase with the open CT will
suddenly drop (at least theoretically) to zero (i.e. as seen by the protection!), while the currents
of the other two phases continue as before.
The open CT function is supposed to detect an open CT under normal conditions, that is, with
the protected multi-terminal circuit under normal load. If the load currents are very low or zero,
the open CT condition cannot be detected. The open CT algorithm will only detect an open CT
if the load on the power transformer is from 10% to 110% of the rated load. Outside this range
an open CT condition is not even looked for. The search for an open CT starts after 60 seconds
(50 seconds in 60 Hz systems) since the bias current enters the 10110% range. The Open CT
detection feature can also be explicitly deactivated by setting: OpenCTEnable = 0 (Off).
If an open CT is detected and the output OPENCT set to 1, then all the differential functions are
blocked, except of the unrestrained (instantaneous) differential. An alarm signal is also produced
after a settable delay (tOCTAlarmDelay) to report to operational personal for quick remedy ac-
tions once the open CT is detected. When the open CT condition is removed (i.e. the previously
open CT reconnected), the functions remain blocked for a specified interval of time, which is
also a setting (tOCTResetDelay). The task of this measure is to prevent an eventual mal-opera-
tion after the reconnection of the previously open CT secondary circuit.
The open CT feature will work only during normal loading condition. Thus, the open CT feature
will be automatically disabled for all external faults, big overloads and inrush conditions.
The open CT algorithm provides detailed information about the location of the defective CT sec-
ondary circuit. The algorithm will clearly indicate terminal side, CT input and phase in which
open CT condition has been detected. These indications are provided via the following outputs
from the differential function:
1. Boolean output OPENCT will provide instant information to indicate that open
CT circuit has been detected
2. Boolean output OPENCTAL will provide time delayed alarm that the open CT
circuit has been detected. Time delay is defined by setting parameter tOCTAlarm
3. Integer output OPENCTINPUT will provide information on which CT input
open CT circuit has been detected (1=CT input No 1; 2=CT input No 1)
4. 4. Integer output OPENCTPHASE will provide information in which phase open
CT circuit has been detected (1=Phase L1; 2= Phase L2; 3= Phase L3)
Once the open CT condition is declared the algorithm will stop to search for further open CT
circuits. It will wait until the first open CT circuit has been corrected. First of all it shall be noted
that once the open CT condition has been detected it can be only automatically reset within the
differential function itself. It is not possible to externally reset open CT condition. In order to
automatically reset the open CT circuit alarm the following conditions have to be fulfilled:
116
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Open CT condition in defective CT circuit has been rectified (e.g. current asym-
metry disappears)
Above two conditions are fulfilled for longer time than defined by the setting pa-
rameter tOCTReset
After the reset the open CT detection algorithm will start again to search for any other open CT
circuit within the protected zone.
RET670
ADM Differential function
Trafo
Data
A/D conversion scaling with CT
IDL2
Derive equation to calculate differential currents
individual windings
Open CT logic on W2 side
phase current
IDL1MAG
Fundamental frequency (phasor
based) Diff current, phase L1 &
ratio
IDL2MAG
Fundamental frequency (phasor
based) Diff current, phase L2 &
phase current contributions from
individual windings
IDL3MAG
Fundamental frequency (phasor
based) Diff current, phase L3 &
phase current contributions from
individual windings
MAX IBIAS
en06000544.vsd
Figure 57: Treatment of measured currents within IED for transformer differential function
Figure 57 shows how internal treatment of measured currents is done in case of two winding
transformer.
117
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The following currents are inputs to the power transformer differential protection function. They
must all be expressed in true power system (primary) Amperes, i.e. as measured.
1. Instantaneous values of currents (samples) from HV, and LV sides for two-wind-
ing power transformers, and from the HV, the first LV, and the second LV sides
for three-winding power transformers.
2. Currents from all power transformer sides expressed as fundamental frequency
phasors, with their real, and imaginary parts. These currents are calculated within
the protection terminal by the fundamental frequency Fourier filters.
3. Negative-sequence currents from all power transformer sides expressed as pha-
sors. These currents are calculated within the protection terminal by the symmet-
rical components module.
118
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
BLKUNRES
IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG
IBIAS STL1
AND
BLOCK
BLKRES
TRIPRESL1
AND
OR 1
Harmonic
Wave BLKWAVL1
block
5th BLK5HL1
Harmonic
Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
OR
AND
OpCrossBlock=On
en06000545.vsd
Figure 58: Transformer differential protection simplified logic diagram for Phase L1.
119
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 59: Transformer differential protection simplified logic diagram for external/internal
fault discriminator
TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3
TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3
TRIP
TRNSSENS OR
TRNSUNR
en05000278.vsd
120
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
121
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
5. If a start signal is issued in a phase, but the fault has been classified as external,
then the instantaneous differential current of that phase is analyzed for the 2nd
and the 5th harmonic contents. If there is less harmonic pollution, than allowed
by the settings I2/I1Ratio, and I5/I1Ratio, then it is assumed that a minor simul-
taneous internal fault must have occurred. Only under these conditions a trip
command is allowed. The cross-block logic scheme is automatically applied un-
der such circumstances.
6. All start and blocking conditions are available as phase segregated as well as
common (i.e. three-phase) signals.
IDL1 MAG
a
a>b
I Diff Alarm b
IDL3 MAG
a
a>b
I Diff Alarm b
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
T2D1-
T2WPDIF_87T
I3PW1CT1 TRIP
I3PW1CT2 TRIPRES
I3PW2CT1 TRIPUNRE
I3PW2CT2 TRNSUNR
TAPOLTC1 TRNSSENS
OLTC1AL START
BLOCK STL1
BLKRES STL2
BLKUNRES STL3
BLKNSUNR BLK2H
BLKNSSEN BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
T3D1-
T3WPDIF_87T
I3PW1CT1 TRIP
I3PW1CT2 TRIPRES
I3PW2CT1 TRIPUNRE
I3PW2CT2 TRNSUNR
I3PW3CT1 TRNSSENS
I3PW3CT2 START
TAPOLTC1 STL1
TAPOLTC2 STL2
OLTC1AL STL3
OLTC2AL BLK2H
BLOCK BLK2HL1
BLKRES BLK2HL2
BLKUNRES BLK2HL3
BLKNSUNR BLK5H
BLKNSSEN BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
en06000250.vsd
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 60: Output signals for the T2WPDIF_87T (T2D1-) function block
Signal Description
TRIP General, common trip signal
TRIPRES Trip signal from restrained differential protection
TRIPUNRE Trip signal from unrestrained differential protection
TRNSUNR Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS Trip signal from sensitive neg. seq. diff. protection
START Common start signal from any phase
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
BLK2H Common second harmonic block signal from any phase
BLK2HL1 Second harmonic block signal, phase L1
BLK2HL2 Second harmonic block signal, phase L2
BLK2HL3 Second harmonic block signal, phase L3
BLK5H Common fifth harmonic block signal from any phase
BLK5HL1 Fifth harmonic block signal, phase L1
BLK5HL2 Fifth harmonic block signal, phase L2
BLK5HL3 Fifth harmonic block signal, phase L3
BLKWAV Common block signal, waveform criterion, from any phase
BLKWAVL1 Block signal, waveform criterion, phase L1
BLKWAVL2 Block signal, waveform criterion, phase L2
BLKWAVL3 Block signal, waveform criterion, phase L3
IDALARM Alarm for sustained diff currents in all three phases
OPENCT An open CT was detected
OPENCTAL Open CT Alarm output signal. Issued after a delay ...
IDL1 Value of the instantaneous differential current, phase L1
IDL2 Value of the instantaneous differential current, phase L2
IDL3 Value of the instantaneous differential current, phase L3
IDL1MAG Magnitude of fundamental freq. diff. current, phase L1
IDL2MAG Magnitude of fundamental freq. diff. current, phase L2
IDL3MAG Magnitude of fundamental freq. diff. current, phase L3
IBIAS Magnitude of the bias current, which is common to all phases
IDNSMAG Magnitude of the negative sequence differential current
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 61: Input signals for the T3WPDIF_87T (T3D1-) function block
Signal Description
I3PW1CT1 Three phase winding primary CT1
I3PW1CT2 Three phase winding primary CT2
I3PW2CT1 Three phase winding secondary CT1
I3PW2CT2 Three phase winding secondary CT2
I3PW3CT1 Three phase winding tertiary CT1
I3PW3CT2 Three phase winding tertiary CT2
TAPOLTC1 Most recent tap position reading on OLTC 1
TAPOLTC2 Most recent tap position reading on OLTC 2
OLTC1AL OLTC1 alarm
OLTC2AL OLTC2 alarm
BLOCK Block of function
BLKRES Block of trip for restrained differential feature
BLKUNRES Block of trip for unrestrained differential feature
BLKNSUNR Block of trip for unrestr. neg. seq. differential feature
BLKNSSEN Block of trip for sensitive neg. seq. differential feature
Table 62: Output signals for the T3WPDIF_87T (T3D1-) function block
Signal Description
TRIP General, common trip signal
TRIPRES Trip signal from restrained differential protection
TRIPUNRE Trip signal from unrestrained differential protection
TRNSUNR Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS Trip signal from sensitive neg. seq. diff. protection
START Common start signal from any phase
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
BLK2H Common second harmonic block signal from any phase
BLK2HL1 Second harmonic block signal, phase L1
BLK2HL2 Second harmonic block signal, phase L2
BLK2HL3 Second harmonic block signal, phase L3
BLK5H Common fifth harmonic block signal from any phase
BLK5HL1 Fifth harmonic block signal, phase L1
BLK5HL2 Fifth harmonic block signal, phase L2
BLK5HL3 Fifth harmonic block signal, phase L3
BLKWAV Common block signal, waveform criterion, from any phase
BLKWAVL1 Block signal, waveform criterion, phase L1
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Signal Description
BLKWAVL2 Block signal, waveform criterion, phase L2
BLKWAVL3 Block signal, waveform criterion, phase L3
IDALARM Alarm for sustained diff currents in all three phases
OPENCT An open CT was detected
OPENCTAL Open CT Alarm output signal. Issued after a delay ...
IDL1 Value of the instantaneous differential current, phase L1
IDL2 Value of the instantaneous differential current, phase L2
IDL3 Value of the instantaneous differential current, phase L3
IDL1MAG Magnitude of fundamental freq. diff. current, phase L1
IDL2MAG Magnitude of fundamental freq. diff. current, phase L2
IDL3MAG Magnitude of fundamental freq. diff. current, phase L3
IBIAS Magnitude of the bias current, which is common to all phases
IDNSMAG Magnitude of the negative sequence differential current
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 64: Basic parameter group settings for the T2WPDIF_87T (T2D1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
ON
SOTFMode Off - ON - Operation mode for
ON switch onto fault
tAlarmDelay 0.000 - 60.000 0.001 10.000 s Time delay for diff cur-
rents alarm level
IDiffAlarm 5 - 100 1 20 %IB Diff. current alarm pickup
level set as % of W1
base current
IdMin 0.10 - 0.60 0.01 0.30 IB Sust. dif. cur. alarm; mul-
tiple of Winding 1 rated
current
EndSection1 0.20 - 1.50 0.01 1.25 IB End of section 1, multi-
ple of Winding 1 rated
current
EndSection2 1.00 - 10.00 0.01 3.00 IB End of section 2, multi-
ple of Winding 1 rated
current
128
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
129
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 65: Basic general settings for the T3WPDIF_87T (T3D1-) function
Parameter Range Step Default Unit Description
RatedVoltageW1 0.05 - 2000.00 0.05 400.00 kV Rated voltage of trans-
former winding 1 (HV
winding) in kV
RatedVoltageW2 0.05 - 2000.00 0.05 231.00 kV Rated voltage of trans-
former winding 2 in kV
RatedVoltageW3 0.05 - 2000.00 0.05 10.50 kV Rated voltage of trans-
former winding 3 in kV
RatedCurrentW1 1 - 99999 1 577 A Rated current of trans-
former winding 1 (HV
winding) in A
RatedCurrentW2 1 - 99999 1 1000 A Rated current of trans-
former winding 2 in A
RatedCurrentW3 1 - 99999 1 7173 A Rated current of trans-
former winding 3 in A
ConnectTypeW1 WYE (Y) - WYE (Y) - Connection type of wind-
DELTA (D) ing 1: Y-wye or D-delta
ConnectTypeW2 WYE (Y) - WYE (Y) - Connection type of wind-
DELTA (D) ing 2: Y-wye or D-delta
ConnectTypeW3 WYE (Y) - DELTA (D) - Connection type of wind-
DELTA (D) ing 3: Y-wye or D-delta
ClockNumberW2 0 [0 deg] - 0 [0 deg] - Phase displacement
1 [30 deg lag] between W2 & W1=HV
2 [60 deg lag] winding, hour notation
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ClockNumberW3 0 [0 deg] - 5 [150 deg lag] - Phase displacement
1 [30 deg lag] between W3 & W1=HV
2 [60 deg lag] winding, hour notation
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ZSCurrSubtrW1 Off - ON - Enable zer. seq. current
ON subtraction for W1 side,
On / Off
130
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
131
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 66: Basic parameter group settings for the T3WPDIF_87T (T3D1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
ON
SOTFMode Off - ON - Operation mode for
ON switch onto fault feature
tAlarmDelay 0.000 - 60.000 0.001 10.000 s Time delay for diff cur-
rents alarm level
IDiffAlarm 5 - 100 1 20 %IB Diff. current alarm pickup
level set as % of W1
base current
IdMin 0.10 - 0.60 0.01 0.30 IB Section1 sensitivity,
multi. of base curr, usu-
ally W1 curr.
IdUnre 1.00 - 50.00 0.01 10.00 IB Unrestr. prot. limit, multi.
of base curr. usually W1
curr.
CrossBlockEn Off - ON - Operation Off/On for
ON cross-block logic
between phases
NegSeqDiffEn Off - ON - Operation Off/On for neg.
ON seq. differential protec-
tions
IMinNegSeq 0.02 - 0.20 0.01 0.04 IB Neg. seq. curr. limit, mult.
of base curr, usually W1
curr.
NegSeqROA 30.0 - 120.0 0.1 60.0 Deg Operate Angle for int. /
ext. neg. seq. fault dis-
criminator
Table 67: Advanced parameter group settings for the T3WPDIF_87T (T3D1-) function
Parameter Range Step Default Unit Description
EndSection1 0.20 - 1.50 0.01 1.25 IB End of section 1, multi. of
base current, usually W1
curr.
EndSection2 1.00 - 10.00 0.01 3.00 IB End of section 2, multi. of
base current, usually W1
curr.
SlopeSection2 10.0 - 50.0 0.1 40.0 % Slope in section 2 of
operate-restrain charac-
teristic, in %
SlopeSection3 30.0 - 100.0 0.1 80.0 % Slope in section 3 of
operate-restrain charac-
teristic, in %
I2/I1Ratio 5.0 - 100.0 1.0 15.0 % Max. ratio of 2nd harm. to
fundamental harm dif.
curr. in %
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Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
133
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
2.1 Introduction
The function can be used on all directly or low impedance earthed windings. The restricted earth
fault function can provide higher sensitivity (down to 5%) and higher speed as it measures indi-
vidually on each winding and thus do not need harmonics stabilization.
The low impedance function is a percentage biased function with an additional zero sequence
current directional comparison criteria. This gives excellent sensitivity and stability for through
faults. The function allows use of different CT ratios and magnetizing characteristics on the
phase and neutral CT cores and mixing with other functions and protection IED's on the same
cores.
xx05000058.vsd
The REF protection is of low impedance type. At least three-phase power transformer termi-
nal currents, and the power transformer neutral point current, must be fed separately to RET670.
These input currents are then conditioned within RET670 by mathematical tools. Fundamental
134
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
frequency components of all currents are extracted from all input currents, while other eventual
zero sequence components (e.g. the 3rd harmonic currents) are fully suppressed. Then the resid-
ual current phasor is constructed from the three line current phasors. This zero sequence current
phasor is then vectorially added to the neutral current, in order to obtain differential current.
The following facts may be observed from the figure 66 and the figure 67 (where the three-phase
line CTs are lumped into a single 3Io current, for the sake of simplicity).
zone of protection
s I zs1 Ia = 0
o A (L1) a (L1)
u I zs1 Ib = 0
B (L2) b (L2)
r
c I zs1 Ic = 0
C (L3) c (L3)
e
U zs Current in the neutral (IN )
3Io=3I zs1 IN = -3Izs1 IN serves as a directional
reference because it has
the sam e direction for both
internal and external faults.
en05000724.vsd
135
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
power system
contribution to
fault current zone of protection
s Izs2 Izs1 Ia = 0
o A (L1) a (L1)
u Izs2 Izs1
B (L2) Ib = 0 b (L2)
r
c Izs2 Izs1 Ic = 0
e C (L3) c (L2)
MTA
IN
Reference is
ROA
neutral current
en05000725.vsd
Restrain for Operate for
external fault internal fault
1. For an external earth fault, (figure 66) the residual current 3Io and the neutral
conductor current IN have equal magnitude, but they are 180 degree out of phase
due to internal CT reference directions used in IED670. This is easy to under-
stand, as both CTs ideally measure exactly the same component of the earth fault
current.
2. For an internal fault, the total earth fault current is composed generally of two ze-
ro-sequence components. One zero-sequence component (i.e. 3IZS1) flows to-
wards the power transformer neutral point and into the earth, while the other
zero-sequence component (i.e. 3IZS2) flows out into the connected power system.
These two primary currents can be expected to be of approximately opposite di-
rections (about the same zero sequence impedance angle is assumed on both sides
of the earth fault). However on the secondary CT sides they will be approximate-
ly in phase due to internal CT reference directions used in IED670. The magni-
tudes of the two components may be different, dependent on the magnitudes of
zero sequence impedances of both sides. No current can flow towards the power
system, if the only point where the system is earthed, is at the protected power
transformer. Likewise, no current can flow into the power system, if the winding
is not connected to the power system (circuit breaker open and power transformer
energized from the other side).
3. For both internal and external earth faults, the current in the neutral connection
IN has always the same direction, that is, towards the earth.
4. The two measured zero sequence current are 3Io and IN. The vectorial sum be-
tween them is the REF differential current, which is equal to Idiff = IN +3Io.
136
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
Because REF is a differential protection where the line zero sequence (residual) current is con-
structed from 3 line (terminal) currents, a bias quantity must give stability against false opera-
tions due to high through fault currents. An operate - bias characteristic (only one) has been
devised to the purpose.
It is not only external earth faults that REF should be stable against, but also heavy
phase-to-phase faults, not including earth. These faults may also give rise to false zero sequence
currents due to saturated line CTs. Such faults, however, produce no neutral current, and can
thus be eliminated as a source of danger, at least during the fault.
The REF has only one operate-bias characteristic, which is described in the table 69, and shown
in the figure 68.
As a differential protection, the REF calculates a differential current and a bias current. In case
of internal earth faults, the differential current is theoretically equal to the total earth fault cur-
rent. The bias current is supposed to give stability to REF protection. The bias current is a mea-
sure of how high the currents are, or better, a measure of how difficult the conditions are under
which the CTs operate. The higher the bias, the more difficult conditions can be suspected, and
the more likely that the calculated differential current has a component of a false current, prima-
rily due to CT saturation. This law is formulated by the operate-bias characteristic. This char-
acteristic divides the Idif - Ibias plane into two parts. The part above the operate - bias
characteristic is the so called operate area, while that below is the block area, see the figure 68.
137
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
operate current in pu
5
4 operate
1
minimum base sensitivity 50 %
default base sensitivity 30 % first slope block
maximum base sensitivity 5 %
0 1 2 3 4 5 6
1.25 pu bias current in per unit
(98000017)
Figure 68: Operate - bias characteristic of the restricted earth fault protection REF.
Idiff = IN + 3 Io
(Equation 5)
where:
IN current in the power transformer neutral as a fundamental frequency phasor,
3Io residual current of the power transformer line (terminal) currents as a phasor.
If there are two three-phase CT inputs on the HV winding side for the REF protection (such as
in breaker-and-a-half configurations), then their respective residual currents are added within
REF function so that:
138
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
The bias current is a measure (expressed as a current in Amperes) of how difficult the conditions
are under which the instrument current transformers operate. Dependent on the magnitude of the
bias current, the corresponding zone (section) of the operate - bias characteristic ia applied, when
deciding whether to trip, or not to trip. In general, the higher the bias current, the higher the
differential current required to produce a trip.
As the bias current the highest current of all separate input currents to REF protection, that is, of
current in phase L1, phase L2, phase L3, and the current in the neutral point (designated as IN
in the figure 66 and in the figure 67).
If there are 2 feeders included in the zone of protection of the REF protection, then the respective
bias current is found as the relatively highest of the following currents:
1
current[1] = max (I3PW1CT1)
CTFactorPri1
1
current[2] = max (I3PW1CT2)
CTFactorPri2
1
current[3] = max (I3PW2CT1)
CTFactorSec1
1
current[4] = max (I3PW2CT2)
CTFactorSec2
current[5] = IN
The bias current is thus generally equal to none of the input currents. If all primary ratings of the
CTs were equal to IBase, then the bias current would be equal to the highest current in Amperes.
IBase shall be set equal to the rated current of the protected winding where the REF function is
applied.
The detection of external earth faults is based on the fact that for such a fault a high neutral cur-
rent appears first, while a false differential current only appears if and when one, or more, cur-
rent transformers saturate. An external earth fault is thus assumed to have occurred when a high
neutral current suddenly appears, while at the same time the differential current Idif remains low,
at least for a while. This condition must be detected before a trip request is placed within REF
protection. Any search for external fault is aborted if a trip request has been placed. A condition
for a successful detection is that it takes not less than 4 ms for the first CT to saturate.
139
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
For an internal earth fault, a true differential current develops immediately, while for an external
fault it only develops if a CT saturates. If a trip request comes first, before an external fault could
be positively established, then it must be an internal fault.
If an external earth fault has been detected, then the REF is temporarily desensitized.
Directional criterion
The directional criterion is applied in order to positively distinguish between internal- and ex-
ternal earth faults. This check is an additional criterion, which should prevent misoperations at
heavy external earth faults, and during the disconnection of such faults by other protections.
Earth faults on lines connecting the power transformer occur much more often than earth faults
on a power transformer winding. It is important therefore that the restricted earth fault protection
(REF) should remain secure during an external fault, and immediately after the fault has been
cleared by some other protection.
For an external earth fault with no CT saturation, the residual current in the lines (3Io in the
figure 66) and the neutral current (IN in the figure 66) are theoretically equal in magnitude and
are 180 degree out of phase. It is the current in the neutral (IN) which serves as a directional ref-
erence because it flows for all earth faults, and it has the same direction for all earth faults, both
external as well as internal. The directional criterion in REF protection makes REF a current-po-
larized relay.
If one or more CTs saturate, then the measured currents 3Io and IN may no more be equal, nor
will their positions in the complex plane be exactly 180 degree apart.There is a risk that the re-
sulting false differential current Idif enters the operate area when clearing the external fault. If
this happens, a directional test may prevent a misoperation.
1. a trip request signal has been issued, (REF function START signal set to 1)
2. if the residual current in lines (3Io) is at least 3% of the IBase current.
If a directional check is either unreliable or not possible to do, due to too small currents, then the
direction is cancelled as a condition for an eventual trip.
If a directional check is executed, the REF protection operation is only allowed if currents 3Io
and IN (see the figure 66and figure 67) are both within the operating region.
RCA = 0 degrees = constant; where RCA stands for the Relay Characteristic Angle,
ROA = 60 to 90 degrees; where ROA stands for the Relay Operate Angle.
RCA determines a direction MTA (Maximum Torque Angle) where the line residual current
3Io should lie for an internal earth fault, while ROA sets a tolerance margin.
140
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
ferential current as a result of the saturation may be so high that it reaches the operate character-
istic. A calculation of the content of 2nd harmonic in the neutral current is made when neutral
current, residual current and bias current are within some windows and some timing criteria are
fulfilled. If the ratio between second and fundamental harmonic exceeds 60%, the REF function
will be blocked.
141
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
REF1-
REFPDIF_87N
I3P TRIP
I3PW1CT1 START
I3PW1CT2 DIROK
I3PW2CT1 BLK2H
I3PW2CT2 IRES
BLOCK IN
IBIAS
IDIFF
ANGLE
I2RATIO
en06000251.vsd
Table 71: Output signals for the REFPDIF_87N (REF1-) function block
Signal Description
TRIP Trip by restricted earth fault protection function
START Start by restricted earth fault protection function
DIROK Directional Criteria has operated for internal fault
BLK2H Block due to 2-nd harmonic
IRES Magnitude of fund. freq. residual current
IN Magnitude of fund. freq. neutral current
IBIAS Magnitude of the bias current
IDIFF Magnitude of fund. freq. differential current
ANGLE Direction angle from zerosequence feature
I2RATIO Second harmonic ratio
142
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
Table 73: Advanced parameter group settings for the REFPDIF_87N (REF1-) function
Parameter Range Step Default Unit Description
ROA 60 - 90 1 60 Deg Relay operate angle for
zero sequence direc-
tional feature
143
High impedance differential protection Chapter 4
(PDIF, 87) Differential protection
3.1 Introduction
The high impedance differential protection can be used when the involved CT cores have the
same turn ratio and similar magnetizing characteristic. It utilizes an external summation of the
phases and neutral current and a series resistor and a voltage dependent resistor externally to the
relay.
144
High impedance differential protection Chapter 4
(PDIF, 87) Differential protection
HZD1-
HZPDIF_87
ISI TRIP
BLOCK ALARM
BLKTR MEASVOLT
en05000363.vsd
Table 76: Output signals for the HZPDIF_87 (HZD1-) function block
Signal Description
TRIP Trip signal
ALARM Alarm signal
MEASVOLT Measured RMS voltage on CT secondary side
145
High impedance differential protection Chapter 4
(PDIF, 87) Differential protection
146
About this chapter Chapter 5
Impedance protection
Chapter 5 Impedance
protection
147
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
1.1 Introduction
The distance protection is a five zone full scheme protection with three fault loops for phase to
phase faults and three fault loops for phase to earth fault for each of the independent zones. In-
dividual settings for each zone in resistive and reactive reach gives flexibility for use as back-up
protection for transformer connected to overhead lines and cables.
The function has a functionality for load encroachment which increases the possibility to detect
high resistive faults on heavily loaded lines.
Forward
operation
Reverse
operation
en05000034.vsd
Figure 72: Typical quadrilateral distance protection zone with load encroachment function
activated
The distance protection zones can operate, independent of each other, in directional (forward or
reverse) or non-directional mode.
148
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Figure 73 presents an outline of the different measuring loops for the basic five, imped-
ance-measuring zones l.
en05000458.vsd
Figure 73: The different measuring loops at line-earth fault and phase-phase fault.
The use of full scheme technique gives faster operation time compared to switched schemes
which mostly uses a start element to select correct voltages and current depending on fault type.
Each distance protection zone performs like one independent distance protection relay with six
measuring elements.
The distance measuring zone will essentially operate according to the non-directional imped-
ance characteristics presented in figure 74 and figure 75. The phase-to-earth characteristic is il-
lustrated with the full loop reach while the phase-to-phase characteristic presents the per-phase
reach.
149
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
X0 X1
Xn =
3
X1+Xn R0 R1
Rn =
3
f N f N
R (Ohm/loop)
RFPE RFPE
X1+Xn
Figure 74: Characteristic for the phase-to-earth measuring loops, ohm/loop domain.
150
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
X (Ohm/phase)
2X1
R (Ohm/phase)
RFPP RFPP
2X1
The fault loop reach with respect to each fault type may also be presented as in figure 76. Note
in particular the difference in definition regarding the (fault) resistive reach for phase-to-phase
faults and three-phase faults.
151
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
ILn R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IL1 R1 + j X1 Phase-to-phase
UL1 element L1-L2
Phase-to-phase
fault in phase RFPP
L1-L2 IL2
UL2 (Arc resistance)
R1 + j X1
where:
n designates anyone of the three phases (1, 2 or 3) and
m represents the phase that is leading phase n with 120 degrees (i.e. 3, 1 or 2).
The R1 and jX1 in figure 76 represents the positive sequence impedance from the measuring
point to the fault location. The RFPE and RFPP is the eventual fault resistance in the fault place.
Regarding the illustration of three-phase fault in figure 76, there is of course fault current flow-
ing also in the third phase during a three-phase fault. The illustration merely reflects the loop
measurement, which is made phase-to-phase.
152
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
The theoretical parameters p and q outline the area of operation in quadrant 1 when varied from
0 to 1.0. That is, for any combination of p and q, where both are between 0 and 1.0, the corre-
sponding impedance is within the reach of the characteristic.
The zone may be set to operate in Non-directional, Forward or Reverse direction through the
setting OperationDir. The result from respective set value is illustrated in figure 77. It may be
convenient to once again mention that the impedance reach is symmetric, in the sense that it is
conform for forward and reverse direction. Therefore, all reach settings apply to both directions.
X X X
R R R
en05000182.vsd
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-earth
loops will be blocked when IN < IMinOpIN, regardless of the phase currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector sum of the
three phase currents, i.e. residual current 3I0.
153
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
ILmLn is the RMS value of the vector difference between phase currents Lm and Ln.
Note!
All three current limits IminOpPE, IminOpIN and IMinOpPP are automatically reduced to 75%
of regular set values if the zone is set to operate in reverse direction, i.e. OperationDir=Reverse.
UL1 UL2
Zapp = -------------------------
I L1 IL2
(Equation 6)
Here U and I represent the corresponding voltage and current phasors in the respective phase Ln
(n = 1, 2, 3)
The earth return compensation applies in a conventional manner to ph-E faults (example for a
phase L1 to earth fault) according to equation 7.
U L1
Z app = ------------------------------
I L1 + I N KN
(Equation 7)
Where:
UL1, IL1 and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
X0 - X1
KN =
3X1
where X0 and X1 is zero and positive sequence reactance from the measuring point to
the fault on the protected line.
Here IN is a phasor of the residual current in relay point. This results in the same reach along the
line for all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 7 is only valid for no loaded radial feeder applications. When load
is considered in the case of single line to earth fault, conventional distance protection might
overreach at exporting end and underreach at importing end. REx670 has an adaptive load com-
pensation which increases the security in such applications.
154
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Measuring elements receive current and voltage information from the A/D converter. The check
sums are calculated and compared, and the information is distributed into memory locations. For
each of the six supervised fault loops, sampled values of voltage (U), current (I), and changes in
current between samples (I) are brought from the input memory and fed to a recursive Fourier
filter.
The filter provides two orthogonal values for each input. These values are related to the loop im-
pedance according to equation 8,
X i
U = R i + ------ -----
0 t
(Equation 8)
X Re ( I )
Re ( U ) = R Re ( I ) + ------ ------------------
0 t
(Equation 9)
X Im ( I )
Im ( U ) = R Im ( I ) + ------ -----------------
0 t
(Equation 10)
with
0 = 2 f 0
(Equation 11)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the volt-
age and substitute it in the equation for the imaginary part. The equation for the Xm measured
reactance can then be solved. The final result is equal to:
Im ( U ) Re ( I ) Re ( U ) Im ( I )
R m = ------------------------------------------------------------------------------------
Re ( I ) Im ( I ) Im ( I ) Re ( I )
(Equation 12)
155
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Re ( U ) Im ( I ) Im ( U ) Re ( I )
Xm = 0 t -------------------------------------------------------------------------------
Re ( I ) Im ( I ) Im ( I ) Re ( I )
(Equation 13)
The calculated Rm and Xm values are updated each sample and compared with the set zone reach.
The adaptive tripping counter counts the number of permissive tripping results. This effectively
removes any influence of errors introduced by the capacitive voltage transformers or by other
factors.
The directional evaluations are performed simultaneously in both forward and reverse direc-
tions, and in all six fault loops. Positive sequence voltage and a phase locked positive sequence
memory voltage are used as a reference. This ensures unlimited directional sensitivity for faults
close to the relay point.
For the L1-L2 element, the equation in forward direction is according to.
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 78.
U1L1 is positive sequence phase voltage in phase L1
U1L1M is positive sequence memorized phase voltage in phase L1
IL1 is phase current in phase L1
U1L1L2 is voltage difference between phase L1 and L2 (L2 lagging L1)
U1L1L2M is memorized voltage difference between phase L1 and L2 (L2 lagging L1)
IL1L2 is current difference between phase L1 and L2 (L2 lagging L1)
156
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115 degrees respective-
ly.(see figure 78) and it should not be changed unless system studies have shown the necessity.
The ZD gives a binary coded signal on the output STDIR depending on the evaluation where
STFWL1N=1 adds 1, STRVL1N=1 adds 2, STFWL2N=1 adds 4 etc.
ArgNegRes
ArgDir
R
en05000722.vsd
Figure 78: Setting angles for discrimination of forward and reverse fault
The polarizing voltage is available as long as the positive-sequence voltage exceeds 4% of the
set base voltage UBase. So the directional element can use it for all unsymmetrical faults includ-
ing close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same positive se-
quence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set terminal rated current IBase), the condition seals
in.
- If the fault has caused tripping, the trip endures.
- If the fault was detected in the reverse direction, the measuring element in
the reverse direction remains in operation.
157
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
If the current decreases below the minimum operating value, the memory resets
until the positive sequence voltage exceeds 10% of its rated value.
Phase-to-earth related signals are designated by LnE, where n represents the corresponding
phase number (L1E, L2E, and L3E). The phase-to-phase signals are designated by LnLm, where
n and m represent the corresponding phase numbers (L1L2, L2L3, and L3L1).
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal
for each separate measuring loop:
The STCND input signal represents a connection of six different integer values from the phase
selection function within the IED, which are converted within the zone measuring function into
corresponding boolean expressions for each condition separately. It is connected to the PHS
function block output STCDZ.
The internal input signal DIRCND is used to give condition for directionality for the distance
measuring zones. The signal contains binary coded information for both forward and reverse di-
rection. The zone measurement function filter out the relevant signals on the STDIR input de-
pending on the setting of the parameter OperationDir. It shall be configured to the STDIR output
on the ZD block.
158
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Composition of the phase starting signals for a case, when the zone operates in a non-directional
mode, is presented in figure 80.
159
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Results of the directional measurement enter the logic circuits, when the zone operates in direc-
tional (forward or reverse) mode, see figure 81.
160
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
STNDL1N
AND
DIRL1N
OR STZMPE.
&
STNDL2N
DIRL2N AND
STNDL3N 15 ms
OR STL1
& t
DIRL3N AND
STNDL1L2
DIRL1L2 AND 15 ms
OR STL2
& t
STNDL2L3
DIRL2L3 AND
15 ms
OR STL3
STNDL3L1 & t
DIRL3L1 AND
OR STZMPP
&
BLK
15 ms
OR START
& t
en05000778.vsd
Tripping conditions for the distance protection zone one are symbolically presented in figure 82.
161
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Figure 82: Tripping logic for the distance protection zone one
ZM01-
ZMQPDIS_21
I3P TRIP
U3P TRL1
BLOCK TRL2
VTSZ TRL3
BLKTR START
STCND STL1
DIRCND STL2
STL3
STND
en06000256.vsd
ZD01-
ZDRDIR
I3P STDIR
U3P
en05000681.vsd
162
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Table 80: Output signals for the ZMQPDIS_21 (ZM01-) function block
Signal Description
TRIP General Trip, issued from any phase or loop
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
START General Start, issued from any phase or loop
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
STND Non-directional start, issued from any phase or loop
Table 81: Input signals for the ZDRDIR (ZD01-) function block
Signal Description
I3P Group connection
U3P Group connection
Table 82: Output signals for the ZDRDIR (ZD01-) function block
Signal Description
STDIR All start signals binary coded
163
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
164
Distance measuring zones, quadrilateral Chapter 5
characteristic (PDIS, 21) Impedance protection
Table 84: Parameter group settings for the ZDRDIR (ZD01-) function
Parameter Range Step Default Unit Description
ArgNegRes 90 - 175 1 115 Deg Angle to blinder in sec-
ond quadrant for forward
direction
ArgDir 5 - 45 1 15 Deg Angle to blinder in fourth
quadrant for forward
direction
IMinOp 1 - 99999 1 10 %IB Minimum operate cur-
rent in % of IBase
IBase 1 - 99999 1 3000 A Base Current
UBase 0.05 - 2000.00 0.05 400.00 kV Base Voltage
165
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
2.1 Introduction
The numerical mho line distance protection is a five zone full scheme protection for detection
of short circuit and earth faults. The full scheme technique provides protection of power lines
with high sensitivity and low requirement on remote end communication. The five zones have
fully independent measuring and settings which gives high flexibility for all types of lines.
The modern technical solution offers fast operating time down to 3/4 cycles.
The IED can be used up to the highest voltage levels. It is suitable for the protection of heavily
loaded lines and multi-terminal lines where the requirement for tripping is one, two-, and/or
three pole.
The function can be used as underimpedance back-up protection for transformers and genera-
tors.
The use of full scheme technique gives faster operation time compare to switched schemes
which mostly uses a start element to select correct voltages and current depending on fault type.
So each distance protection zone performs like one independent distance protection relay with
six measuring elements.
166
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
jX X
Mho, zone4
Mho, zone3
Zs=0
Mho, zone2
R
Mho, zone1
Zs=Z1
Zs=2Z1
en06000400.vsd
Figure 85: Mho, offset Mho characteristic and the source impedance influence on the Mho
characteristic
The mho characteristic has a dynamic expansion due to the source impedance. Instead of cross-
ing the origin as for the offset mho in the left figure 85, which is only valid where the source
impedance is zero, the crossing point is moved to the coordinates of the negative source imped-
ance given an expansion of the circle shown in the right figure 85.
The polarisation quantities used for the mho circle is 100% memorized positive sequence volt-
ages. This will give a somewhat less dynamic expansion of the mho circle during faults. How-
ever, if the source impedance is high, the dynamic expansion of the mho circle might lower the
security of the function too much with high loading and mild power swing conditions.
The mho distance element has a load encroachment function which cut off a section of the char-
acteristic when enabled. The function is enabled by setting the setting parameter LoadEnchMode
to On. Enabling of the load encroachment function increases the possibility to detect high resis-
tive faults without interfering with the load impedance. The algorithm for the load encroachment
is located in the PHSM function, where also the relevant settings can be found. Information
about the load encroachment from the PHS to the zone measurement is given in binary format
to the input signal LDCND.
Each zone can also be set to Non-directional, Forward or Reverse by setting the parameter
DirMode .
The operation for phase to earth and phase to phase fault can be individually switched On and
Off by the setting parameter OpModePE and OpModePP.
167
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
For critical applications such as for lines with high SIRs as well as CVTs, it is possible to im-
prove the security by setting the parameter ReachMode to Underreach. In this mode the reach
for faults close to the zone reach is reduced by 20% and the filtering is also introduced to in-
crease the accuracy in the measuring. If the ReachMode is set to Overreach no reduction of the
reach is introduced and no extra filtering introduced. The latter setting is recommended for over-
reaching pilot zone, zone 2 or zone 3 elements and reverse zone where overreaching on tran-
sients is not a major issue either because of less likelihood of overreach with higher settings or
the fact that these elements do not initiate tripping unconditionally.
The offset mho characteristic can be set in Non-directional, Forward or Reverse by the setting
parameter OffsetMhoDir. When Forward or Reverse is selected a directional line is introduced.
Information about the directional line is given from the directional element and given to the mea-
suring element as binary coded signal to the input DIRCND.
The zone reach for phase to earth fault and phase to phase fault is set individually in polar coor-
dinates. The impedance is set by the parameters ZPE and ZPP and the corresponding arguments
by the parameters ZAngPE and ZAngPP.
Compensation for earth return path for faults involving earth is done by setting the parameter
KNMag and KNAng where KNMag is the magnitude of the earth return path and KNAng is the
difference of angles between KNMag and ZPE. KNMag and KNAng are defined according to
equation 16 and equation 17.
Z0-Z1
KNMag =
3 Z1
(Equation 16)
Z0-Z1
KNAng = ( ZAngPE ) arg
3 Z1
(Equation 17)
Where:
Z0 is the complex zero sequence impedance of the line in ohm/phase
Z1 is the complex positive sequence impedance of the line in ohm/phase
ZAngPE line angle of the positive line impedance
The phase-to-earth and phase-to-phase measuring loops can be time delayed individually by set-
ting the parameter tPE and tPP respectively. To release the time delay, the operation mode for
the timers, OpModetPE and OpModetPP, has to be set to On. This is also the case for instanta-
neous operation.
168
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
activating of the input BLKZ (fuse failure) blocks all output signals
activating of the input BLKZMTD blocks the delta based algorithm
activating of the input BLKHSIR blocks the instantaneous part of the algorithm
for high SIR values
activating of the input BLKTRIP blocks all output signals
activating the input BLKPE blocks the phase-to-earth fault loop outputs
activating the input BLKPP blocks the phase-to-phase fault loop outputs
The activation of signal BLKZ can either be by external fuse failure function or from the loss of
voltage check in the Mho supervision logic (ZSMGAPC). In both cases the output BLKZ in the
Mho supervision logic shall be connected to the input BLKZ in the Mho distance function block
(ZMHODIS 21).
The input signal BLKZMTD is activated during some ms after fault has been detected by the
Mho supervision logic to avoid unwanted operations due to transients. It shall be connected to
the BLKZMTD output signal at the Mho supervision function.
At SIR values >10, the use of electronic CVT might cause overreach due to the built in resonance
circuit in the CVT which reduce the secondary voltage for a while. The input BLKHSIR shall
be connected to the output signal HSIR on the Mho supervision logic for increasing of the fil-
tering and high SIR values. This is valid only when permissive underreach scheme is selected
by setting ReachMode=Underreach.
Phase-to-phase fault
Mho
The plain Mho circle has the characteristic as figure 86The condition for deriving the angle is
according to equation 18.
169
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
where:
the voltage vector difference between phases L1 and L2
U L1 L 2
the current vector difference between phases L1 and L2
I L1 L 2
ZPP the positive sequence impedance setting for phase to phase fault
Upol is the polarizing voltage
The polarized voltage consists of 100% memorized positive sequence voltage (UL1L2 for phase
L1 to L2 fault). The memorized voltage will prevent collapse of the Mho circle for close in
faults.
IL1L2X
Ucomp = UL1L2 - IL1L2 ZPP
IL1L2 ZPP
Upol
UL1L2
IL1L2R
en07000109.vsd
Figure 86: Simplified mho characteristic and vectordiagram for phase L1 to L2 fault.
170
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
Offset Mho
The characteristic for offset mho is a circle where two points on the circle are the setting param-
eters ZPP and ZRevPP. The vector ZPP in the impedance plane has the settable angle AngZPP
and the angle for ZRevPP is AngZPP+180.
The condition for operation at phase to phase fault is that the angle between the two compen-
sated voltages Ucomp1 and Ucomp2 is greater or equal to 90 figure 87. The angle will be 90
for fault location on the boundary of the circle.
U -IL1L2 ZPP
= arg
U-(-IL1L2 ZRevPP)
(Equation 19)
where:
= is the UL1L2 voltage
ZRevPP = is the positive sequence impedance setting for phase to phase fault in reverse direction
IL1L2jX
U
Ucomp2 = U = IFZF=UL1L2
IL1L2R
- IL1L2 Z RevPP
en07000110.vsd
Figure 87: Simplified offset mho characteristic and voltage vectors for phase L1 to L2 fault.
171
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
and
where
ArgDir is the setting parameter for directional line in fourth quadrant
ArgNegRes is the setting parameter for directional line in second quadrant
is calculated according to equation 19
The directional information is brought to the mho distance measurement from the mho direc-
tional element as binary coded information to the input DIRCND. See chapter Mho directional
element for information about the mho directionalety element.
172
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
IL1L2jX
ZPP
UL1L2
ArgNegRes f
IL1L2
ArgDir
en07000111.vsd
Figure 88: Simplified offset mho characteristic in forward direction for phase L1 to L2 fault.
and
The is derived according to equation 19 for the mho circle and is the angle between the volt-
age and current.
173
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
ZPP
ArgNegRes
IL1L2
ArgDir R
UL1L2
ZRevPP
en06000469.eps
Phase-to-earth fault
Mho
The measuring of earth faults uses earth return compensation applied in a conventional way. The
compensation voltage is derived by considering the influence from the earth return path.
For a earth fault in phase L1A, we can derive the compensation voltage Ucomp see figure 90 as
174
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
where
Upol is the polarizing voltage (memorized UL1 for Phase L1 to earth fault)
Zloop is the loop impedance, which in general terms can be expressed as
(
Z1+ZN = Z 1 1 + KN )
where
Z1 positive sequence impedance of the line (Ohm/phase)
KN zero sequence compensator factor
The angle between the Ucomp and the polarize voltage Upol for a L1 to earth fault is
( )
= arg U L1 I L1 + IN KN ZPE arg(Upol)
(Equation 25)
where:
UL1 = phase voltage in faulty phase L1
IL1 = phase current in faulty phase L1
IN = zero sequence current in faulty phase L1
Z0-Z1
= the setting parameter for the zero swquence compensation consisting of the magni-
KN 3 Z1 tude KN and the angle KNAng.
Upol = 100% of positive sequence memorized voltage UL1
It is to be noted that the angle KNAng is the difference angle between the positive sequence im-
pedance ZPE and the impedance ZN for the earth return path see figure 90
175
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
IL1X KNAng
IL1ZN
Ucomp
IL1 Zloop
IL1ZPE
Upol
f
IL1 (Ref) IL1R
en06000472.vsd
Figure 90: Simplified offset mho characteristic and vectordiagram for phase L1 to earth fault.
Operation occurs if
90 270
(Equation 26)
Offset Mho
The characteristic for offset mho at earth fault is a circle containing the two vectors from the or-
igin ZPE and ZRevPE where ZPE and ZrevPE are the settting reach for the positive sequence
impedance in forward respective reverse direction. The vector ZPE in the impedance plane has
the settable angle AngZPE and the angle for ZRevPP is AngZPE+180
The condition for operation at phase to earth fault is that the angle between the two compen-
sated voltages Ucomp1 and Ucomp2 is greater or equal to 90 see 91. The angle will be 90 for
fault location on the boundary of the circle.
176
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
where
is the phase L1 phase voltage
U L1
177
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
IL1L 2 jX
UL1
U comp2 = UL1 - (-IL1 ZRevPE)
IL1L2 R
- I L1 Z Re vPe
en 06000465. vsd
IABjX
V comp1 = VA - IA ZPE
IA ZPE
VA
V comp2 = VA - (-IA ZRevPE)
I AB R
- IA Z RevPe
en 06000465_ansi. vsd
Figure 91: Simplified offset mho characteristic and voltage vector for phase L1 to L2 fault.
Operation occurs if
178
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
90 270
(Equation 28)
where
ArgDir is the setting parameter for directional line in fourth quadrant
ArgNegRes is the setting parameter for directional line in second quadrant.
is calculated according to equation 27
IL1 jX
UL1
ArgNegRes f
IL1 IL1R
ArgDir
en 06000466.vsd
Figure 92: Simplified characteristic for offset mho in forward direction for L1 to earth fault.
179
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
The conditions for operation of offset Mho in reverse direction for L1 to earth fault will be
90<<270 and 180-Argdir<<ArgNegRes+180.
The is derived according to equation 27 for the offset Mho circle and is the angle between
the voltage and current.
180
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
ZPE
ArgNegRes
IL1
ArgDir R
UL1
ZRevPE
en06000470.eps
181
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
ZPE
ArgNegRes
IA
ArgDir R
VA
ZRevPE
en06000470_ansi.eps
Figure 93: Simplified characteristic for offset Mho in reverse direction for L1 to earth fault.
ZMH1-
ZMHPDIS_21
I3P TRIP
U3P TRL1
CURR_INP TRL2
VOLT_INP TRL3
POL_VOLT TRPE
BLOCK TRPP
BLKZ START
BLKZMTD STL1
BLKHSIR STL2
BLKTRIP STL3
BLKPE STPE
BLKPP STPP
DIRCND
STCND
LDCND
en06000423.vsd
182
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
Table 87: Output signals for the ZMHPDIS_21 (ZMH1-) function block
Signal Description
TRIP Trip General
TRL1 Trip phase L1
TRL2 Trip phase L2
TRL3 Trip phase L3
TRPE Trip phase-to-earth
TRPP Trip phase-to-phase
START Start General
STL1 Start phase L1
STL2 Start phase L2
STL3 Start phase L3
STPE Start phase-to-earth
STPP Start phase-to-phase
183
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
184
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
Table 89: Advanced parameter group settings for the ZMHPDIS_21 (ZMH1-) function
Parameter Range Step Default Unit Description
OffsetMhoDir Non-directional - Non-directional - Direction mode for offset
Forward mho
Reverse
OpModetPE Off - ON - Operation mode Off / On
ON of Zone timer, Ph-E
OpModetPP Off - ON - Operation mode Off / On
ON of Zone timer, Ph-ph
Table 90: Basic parameter group settings for the ZSMGAPC (ZSM1-) function
Parameter Range Step Default Unit Description
IBase 1 - 99999 1 3000 A Base value for current
measurement
UBase 0.05 - 2000.00 0.05 400.00 kV Base value for voltage
measurement
PilotMode Off - Off - Pilot mode Off/On
On
Zreach 0.1 - 3000.0 0.1 38.0 ohm Line impedance
IMinOp 10 - 30 1 20 %IB Minimum operating cur-
rent for SIR measure-
ment
185
Full-scheme distance measuring, Mho Chapter 5
characteristic, PDIS 21 Impedance protection
Table 91: Advanced parameter group settings for the ZSMGAPC (ZSM1-) function
Parameter Range Step Default Unit Description
DeltaI 0 - 200 1 10 %IB Current change level in
%IB for fault inception
detection
Delta3I0 0 - 200 1 10 %IB Zero seq current change
level in % of IB
DeltaU 0 - 100 1 5 %UB Voltage change level in
%UB for fault inception
detection
Delta3U0 0 - 100 1 5 %UB Zero seq voltage change
level in % of UB
SIRLevel 5 - 15 1 10 - Settable level for source
impedance ratio
186
Mho impedance supervision logic Chapter 5
Impedance protection
3.1 Introduction
The Mho impedance supervision logic includes features for fault inception detection and high
SIR detection. It also includes the functionality for loss of potential logic as well as for the pilot
channel blocking scheme.
The Mho Impedance Supervision logic can mainly be decomposed in two different parts:
The fault inception detection detects instantaneous changes in any phase currents or zero se-
quence current in combination with a change in the corresponding phase voltage or zero se-
quence voltage. If the change of any phase current and corresponding phase voltage or 3U0 and
3I0 exceeds the setting parameters DeltaI and DeltaU respectively Delta3U0 and Delta3I0 and
the input signal BLOCK is not activated, the ouput signal FLTDET is activated indicating that
a system fault has occoured.
If the setting pilotMode is set to On in Blocking scheme and the fault inception function has de-
tected a system fault, a block signal BLKCHST will be issued and send to remote end in order
to block the overreaching zones. Different criteria has to be fulfilled for sending the BLKCHST
signal:
OR
If it is later detected that it was an internal fault that made the function issue the BLKCHST sig-
nal, the function will issue a CHSTOP signal to unblock the remote end. The criteria that have
to be fulfilled for this are:
1. The function has to be in pilot mode, i.e. the setting parameter pilotMode has to
be set to On
2. The carrier send signal should be blocked, i.e. input signal BLOCKCS is On and,
187
Mho impedance supervision logic Chapter 5
Impedance protection
3. A reverse fault should not have been detected while the carrier send signal was
not blocked, i.e.input signals REVSTART and BLOCKCS is not activated.
The function has a built in loss of voltage detection based on the evaluation of the change in
phase voltage or the change in zero sequence voltage (3U0). It operates if the change in phase
voltages exceeds the setting dULevel or 3U0 exceeds the setting dU0Level.
If loss of voltage is detected, but not a fault inception, the distance protection function will be
blocked. This is also the case if a fuse failure is detected by the external fuse failure function and
activate the input FUSEFAIL. Those blocks are generated by activating the output BLKZ, which
shall be connected to the input BLKZ on the distance Mho function block.
During fault inception a lot of transients will be developed which in turn might cause the dis-
tance function to overreach. The Mho supervision logic will increase the filtering during the
most transient period of the fault. This is done by activating the output BLKZMD, which shall
be connected to the input BLKZMTD on mho distance function block.
The SIR function calculates the SIR value as the source impedance divided by the setting Zreach
and activates the output signal HSIR if the calculated value for any of the six basic shunt faults
exceed the setting parameter SIRLevel.The HSIR signal is intended to block the delta based mho
impedance function.
ZSM1-
ZSMGAPC
I3P BLKZMTD
U3P BLKCHST
BLOCK CHSTOP
REVSTART HSIR
BLOCKCS
CBOPEN
en06000426.vsd
ZSM1-
ZSMGAPC
I3P BLKZMTD
V3P BLKCHST
BLOCK CHSTOP
REVSTART HSIR
BLOCKCS
CBOPEN
en06000426_ansi.vsd
188
Mho impedance supervision logic Chapter 5
Impedance protection
Table 94: Output signals for the ZSMGAPC (ZSM1-) function block
Signal Description
BLKZMTD Block signal for blocking of time domained mho
BLKCHST Blocking signal to remote end to block overreaching zone
CHSTOP Stops the blocking signal to remote end
HSIR Indication of source impedance ratio above set limit
189
Mho impedance supervision logic Chapter 5
Impedance protection
Table 96: Advanced parameter group settings for the ZSMGAPC (ZSM1-) function
Parameter Range Step Default Unit Description
DeltaI 0 - 200 1 10 %IB Current change level in
%IB for fault inception
detection
Delta3I0 0 - 200 1 10 %IB Zero seq current change
level in % of IB
DeltaU 0 - 100 1 5 %UB Voltage change level in
%UB for fault inception
detection
Delta3U0 0 - 100 1 5 %UB Zero seq voltage change
level in % of UB
SIRLevel 5 - 15 1 10 - Settable level for source
impedance ratio
190
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
4.1 Introduction
The operation of transmission networks today is in many cases close to the stability limit. Due
to environmental considerations the rate of expansion and reinforcement of the power system is
reduced e.g. difficulties to get permission to build new power lines. The ability to accurately and
reliable classify the different types of fault so that single pole tripping and auto-reclosing can be
used plays an important roll in this matter. The phase selection function is designed to accurately
select the proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may make fault resis-
tance coverage difficult to achieve. Therefore the function has a built in algorithm for load en-
croachment, which gives the possibility to enlarge the resistive setting of both the phase
selection and the measuring zones without interfering with the load.
The extensive output signals from the phase selection gives also important information about
faulty phase(s) which can be used for fault analysis.
The difference, compared to the zone measuring elements, is in the combination of the measur-
ing quantities (currents and voltages) for different types of faults.
The characteristic is basically non-directional, but the PHS function uses information from the
directional function block to discriminate whether the fault is in forward or reverse. The direc-
tional lines are drawn as "line-dot-dot-line" in the figures below.
1. Residual current criteria, i.e. separation of faults with and without earth connec-
tion
2. Regular quadrilateral impedance characteristic
191
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
3. Load encroachment characteristics is always active but can be switched off by se-
lecting a high setting.
X X X
60
60 R
R R
60 60
en05000668.vsd
Figure 96: Characteristic for non-directional, forward and reverse operation of PHS
The setting of the load encroachment function may influence the total operating characteristic,
(for more information, refer to section 4.2.4 "Load encroachment").
The input DIRCND contains binary coded information about the directional coming from the
directionality block. It shall be connected to the STDIR output on the ZD block. This informa-
tion is also transferred to the input DIRCND on the distance measuring zones, i.e. the ZM block.
The code built up for the directionality is as follows:
192
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
STDIR=STFWL1*1+STFWL2*4+STFWL3*16+STFWL1L2*64+STFWL2L3*256+STFWL
3L1*1024+STRVL1*2+STRVL2*8+STRVL3*32+STRVL1L2*128+STRVL2L3*512+STR
VL3L1*2048
If the binary information is 1 then it will be considered that we have start in forward direction in
phase L1. If the binary code is 5 then we have start in forward direction in phase L1 and L2 etc.
The STCND (Z or I) output contains, in a similar way as DIRCND, binary coded information,
in this case information about the condition for opening correct fault loop in the distance mea-
suring element. It shall be connected to the STCND input on the ZM blocks. The code built up
for release of the measuring fault loops is as follows:
ULn
ZPHSn =
ILn
(Equation 29)
where:
n corresponds to the particular phase (n=1, 2 or 3)
The characteristic for the PHS function at phase to earth fault is according to figure 97. The char-
acteristic has a fixed angle for the resistive boundary in the first quadrant of 60.
The resistance RN and reactance XN is the impedance in the earth return path defined according
to equation 30 and equation 31.
R0 R1
RN =
3
(Equation 30)
X 0 X1
XN =
3
(Equation 31)
193
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
X (ohm/loop)
Kr(X1+XN)
RFRvPE RFFwPE
X1+XN
60 deg
RFFwPE
RFRvPE R (Ohm/loop)
60 deg
X1
1
Kr =
tan(60 deg)
RFRvPE RFFwPE
Kr(X1+XN)
en06000396.vsd
Figure 97: Characteristic of PHS for phase to earth fault (setting parameters in italic),
ohm/loop domain
Besides this, the 3I0 residual current must fulfil the conditions according to equation 32 and
equation 33.
3 I 0 0.5 IM in O p
(Equation 32)
3 I0 INReleasePE
------------------------------------ Iphmax
100
(Equation 33)
where:
IMinOp is the minimum operation current for forward zones,
INReleasePE is the setting for the minimum residual current needed to enable operation in the ph-E
fault loops (in %) and
Iphmax is the maximum phase current in any of three phases.
194
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
ULm ULn
ZPHS =
2 ILn
(Equation 34)
ULm is the leading phase voltage, ULn the lagging phase voltage and ILn the phase current in
the lagging phase n.
X (ohm/phase)
0.5FRvPP 0.5RFFwPP
KrX1
X1
0.5RFFwPP
60 deg
R (ohm/phase)
60 deg
0.5RFRvPP
X1
1
Kr =
tan(60 deg)
KrX1
0.5RFRvPP 0.5RFFwPP
en05000670.vsd
Figure 98: The operation characteristic for PHS at phase-to-phase fault (setting parameters
in Italic), ohm/phase domain
In the same way as the condition for phase-to-earth fault, there are current conditions that have
to be fulfilled in order to release the phase-to-phase loop. Those are according to equation 35 or
equation 36.
3I 0 < IN Re leasePE
(Equation 35)
195
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
where:
INRelease is 3I0 limit for releasing phase-to-earth measuring loops,
INBlockPP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
However, the reach is expanded by a factor 2/3 (approximately 1.1547) in all directions. At the
same time the apparent impedance is rotated 30 degrees, counter-clockwise. The characteristic
is shown in figure 99.
X (ohm/phase)
4 X1
3
90 deg
0.5RFFwPPK3
X1K3 4 RFFwPP
6
R (ohm/phase)
0.5RFRvPPK3
K3 = 2 / sqrt(3)
30 deg
en05000671.vsd
Figure 99: The characteristic of PHS for three phase fault (setting parameters in italic)
196
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
The outline of the characteristic is presented in figure 100. As illustrated, the resistive blinders
are set individually in forward and reverse direction while the angle of the sector is the same in
all four quadrants.
RLdFw
ARGLd ARGLd
R
ARGLd ARGLd
RLdRv
en05000196.vsd
The influence of load encroachment function depending on the operation characteristic is depen-
dent on the chosen operation mode of the PHS function. When selection mode is STCNDZ, the
characteristic for the PHS (and also zone measurement depending on settings) will be reduced
by the load encroachment characteristic (see figure 101, left illustration).
When STCNDI is selected the operation characteristic will be as the right illustration in
figure 101. The reach will in this case be limit by the minimum operation current and the dis-
tance measuring zones.
197
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
X X
R R
STCNDZ STCNDI
en05000197.vsd
Figure 101: Difference in operating characteristic depending on operation mode when load
encroachment is activated
When the "phase selection" is set to operate together with a distance measuring zone the result-
ant operate characteristic could look something like in figure 102. The figure shows a distance
measuring zone operating in forward direction. Thus, the operate area is highlighted in black.
198
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
"Phase selection"
"quadrilateral" zone
Load encroachment
characteristic
Directional line
en05000673.vsd
Figure 102: Operation characteristic in forward direction when load encroachment is enabled
Figure 102 is valid for phase-to-earth as well as phase-to-phase faults. During a three-phase
fault, or load, when the "quadrilateral" phase-to-phase characteristic is subject to enlargement
and rotation the operate area is transformed according to figure 103. Notice in particular what
happens with the resistive blinders of the "phase selection" "quadrilateral" characteristic. Due to
the 30-degree rotation, the angle of the blinder in quadrant one is now 90 degrees instead of the
original 60 degrees. The blinder that is nominally located to quadrant four will at the same time
tilt outwards and increase the resistive reach around the R-axis. Consequently, it will be more or
less necessary to use the load encroachment characteristic in order to secure a margin to the load
impedance.
199
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
X (ohm/phase)
Phase selection
Quadrilateral zone
R (ohm/phase)
en05000674.vsd
Figure 103: Operation characteristic for PHS in forward direction for three-phase fault,
ohm/phase domain
The phase-to-earth loop Ln is blocked if ILn<IMinOpPE, where ILn is the RMS value of the
current in phase Ln.
200
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
Figure 104: Phase-to-phase and phase-to-earth operating conditions (residual current crite-
ria)
A special attention is paid to correct phase selection at evolving faults. A STCNDI output signal
is created as a combination of the load encroachment characteristic and current criteria, refer to
figure 104. This signal can be configured to STCND functional input signals of the distance pro-
tection zone and this way influence the operation of the ph-ph and ph-E zone measuring ele-
ments and their phase related starting and tripping signals.
Figure 105 presents schematically the composition of non-directional phase selective signals
PHS--STNDLn. Signals ZMLnN and ZMLmLn (m and n change between one and three accord-
ing to the phase number) represent the fulfilled operating criteria for each separate loop measur-
ing element (i.e. within the "quadrilateral" characteristic.
201
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
Composition of the directional (forward and reverse) phase selective signals is presented sche-
matically in figure 107 and figure 106. The directional criteria appears as a condition for the cor-
rect phase selection in order to secure a high phase selectivity for simultaneous and evolving
faults on lines within the complex network configurations. Signals DFWLn and DFWLnLm
present the corresponding directional signals for measuring loops with phases Ln and Lm. Des-
ignation FW (figure 107) represents the forward direction as well as the designation RV
(figure 106) represents the reverse direction. All directional signals are derived within the cor-
responding digital signal processor.
Figure 106 presents additionally a composition of a STCNDZ output signal, which is created on
the basis of impedance measuring conditions. This signal can be configured to STCND function-
al input signals of the distance protection zone and this way influence the operation of the ph-ph
and ph-E zone measuring elements and their phase related starting and tripping signals.
202
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
203
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
204
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
PHS1-
FDPSPDIS_21
I3P TRIP
U3P START
BLOCK STFWL1
DIRCND STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVPE
STNDL1
STNDL2
STNDL3
STNDPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STCNDZ
STCNDI
en06000258.vsd
Table 98: Output signals for the FDPSPDIS_21 (PHS--) function block
Signal Description
STFWL1 Fault detected in phase L1 - forward direction
STFWL2 Fault detected in phase L2 - forward direction
STFWL3 Fault detected in phase L3 - forward direction
STFWPE Earth fault detected in forward direction
STRVL1 Fault detected in phase L1 - reverse direction
STRVL2 Fault detected in phase L2 - reverse direction
STRVL3 Fault detected in phase L3 - reverse direction
STRVPE Earth fault detected in reverse direction
STNDL1 Non directional start in L1
STNDL2 Non directional start in L2
205
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
Signal Description
STNDL3 Non directional start in L3
STNDPE Non directional start, phase-earth
STFW1PH Start in forward direction for single-phase fault
STFW2PH Start in forward direction for two- phase fault
STFW3PH Start in forward direction for thre-phase fault
STPE Current conditions release of phase-earth measuring elements
STPP Current conditions release of phase-phase measuring elements
STCNDZ Start condition (PHS,LE and I based)
STCNDI Start condition (LE and I based)
206
Phase selection with load encroachment Chapter 5
(PDIS, 21) Impedance protection
207
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
5.1 Introduction
The distance protection is a five zone protection with three fault loops for phase to earth fault
for each of the independent zones. Individual settings for each zone resistive and reactive reach
gives flexibility for use on overhead lines and cables of different types and lengths.
The function has a functionality for load encroachment which increases the possibility to detect
high resistive faults on heavily loaded lines (see figure 72).
The independent measurement of impedance for each fault loop together with a sensitive and
reliable built in phase selection makes the function suitable in applications with single phase au-
to-reclosing.
Built-in adaptive load compensation algorithm prevents overreaching of zone1 at load exporting
end at phase to earth faults on heavily loaded power lines.
The distance protection zones can operate, independent of each other, in directional (forward or
reverse) or non-directional mode. This makes them suitable, together with different communi-
cation schemes, for the protection of power lines and cables in complex network configurations,
such as parallel lines, multi-terminal lines etc.
Figure 109 presents an outline of the different measuring loops for the basic five, imped-
ance-measuring zones l.
208
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
en07000080.vsd
Figure 109: The different measuring loops at line-earth fault and phase-phase fault.
The distance measuring zone will essentially operate according to the non-directional imped-
ance characteristics presented in figure 110. The characteristic is illustrated with the full loop
reach.
209
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
X0 X1
Xn =
3
X1+Xn R0 R1
Rn =
3
f N f N
R (Ohm/loop)
RFPE RFPE
X1+Xn
Figure 110: Characteristic for the phase-to-earth measuring loops, ohm/loop domain.
ILn R1 + j X1
Phase-to-earth
UL1
element
Phase-to-earth
fault in phase L1 RFPE
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 ) en06000412.vsd
The R1 and jX1 in figure 111 represents the positive sequence impedance from the measuring
point to the fault location. The RFPE is presented in order to convey the fault resistance reach.
210
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
The zone may be set to operate in Non-directional, Forward or Reverse direction through the
setting OperationDir. The result from respective set value is illustrated in figure 112. It may be
convenient to once again mention that the impedance reach is symmetric, in the sense that it is
conform for forward and reverse direction. Therefore, all reach settings apply to both directions.
X X X
R R R
en05000182.vsd
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-earth
loops will be blocked when IN < IMinOpIN, regardless of the phase currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector sum of the
three phase currents, i.e. residual current 3I0.
Note!
Both current limits IminOpPE and IminOpIN are automatically reduced to 75% of regular set
values if the zone is set to operate in reverse direction, i.e. OperationDir=Reverse.
Here U and I represent the corresponding voltage and current phasors in the respective phase Ln
(n = 1, 2, 3).
211
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
U L1
Z app = ------------------------------
I L1 + I N KN
(Equation 37)
Where:
UL1, IL1 and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
X0 - X1
KN =
3X1
where X0 and X1 is zero and positive sequence reactance from the measuring point to
the fault on the protected line.
Here IN is a phasor of the residual current in relay point. This results in the same reach along the
line for all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 37 is only valid for no loaded radial feeder applications. When
load is considered in the case of single line to earth fault, conventional distance protection might
overreach at exporting end and underreach at importing end. REx670 has an adaptive load com-
pensation which increases the security in such applications.
Measuring elements receive current and voltage information from the A/D converter. The check
sums are calculated and compared, and the information is distributed into memory locations. For
each of the six supervised fault loops, sampled values of voltage (U), current (I), and changes in
current between samples (I) are brought from the input memory and fed to a recursive Fourier
filter.
The filter provides two orthogonal values for each input. These values are related to the loop im-
pedance according to equation 38,
X i
U = R i + ------ -----
0 t
(Equation 38)
212
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
X Re ( I )
Re ( U ) = R Re ( I ) + ------ ------------------
0 t
(Equation 39)
X Im ( I )
Im ( U ) = R Im ( I ) + ------ -----------------
0 t
(Equation 40)
with
0 = 2 f 0
(Equation 41)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the volt-
age and substitute it in the equation for the imaginary part. The equation for the Xm measured
reactance can then be solved. The final result is equal to:
Im ( U ) Re ( I ) Re ( U ) Im ( I )
R m = ------------------------------------------------------------------------------------
Re ( I ) Im ( I ) Im ( I ) Re ( I )
(Equation 42)
Re ( U ) Im ( I ) Im ( U ) Re ( I )
Xm = 0 t -------------------------------------------------------------------------------
Re ( I ) Im ( I ) Im ( I ) Re ( I )
(Equation 43)
The calculated Rm and Xm values are updated each sample and compared with the set zone reach.
The adaptive tripping counter counts the number of permissive tripping results. This effectively
removes any influence of errors introduced by the capacitive voltage transformers or by other
factors.
The directional evaluations are performed simultaneously in both forward and reverse direc-
tions, and in all six fault loops. Positive sequence voltage and a phase locked positive sequence
memory voltage are used as a reference. This ensures unlimited directional sensitivity for faults
close to the relay point.
213
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (= -15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 113.
U1L1 is positive sequence phase voltage in phase L1
U1L1M is positive sequence memorized phase voltage in phase L1
IL1 is phase current in phase L1
The setting of ArgDir and ArgNegRes is by default set to 15 (= -15) and 115 degrees respectively
(see figure 113) and it should not be changed unless system studies have shown the necessity.
The ZDM gives a binary coded signal on the output STDIRCND depending on the evaluation
where STFWL1N=1 adds 1, STRVL1N=1 adds 2, STFWL2N=1 adds 4 etc.
214
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
ArgNegRes
ArgDir
R
en05000722.vsd
Figure 113: Setting angles for discrimination of forward and reverse fault
The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the
set base voltage UBase. So the directional element can use it for all unsymmetrical faults includ-
ing close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same positive se-
quence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set terminal rated current IBase), the condition seals
in.
- If the fault has caused tripping, the trip endures.
- If the fault was detected in the reverse direction, the measuring element in
the reverse direction remains in operation.
215
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
If the current decreases below the minimum operating value, the memory resets
until the positive sequence voltage exceeds 10% of its rated value.
Phase-to-earth related signals are designated by LnE, where n represents the corresponding
phase number (L1E, L2E, and L3E).
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal
for each separate measuring loop:
The STCND input signal represents a connection of six different integer values from the phase
selection function within the IED, which are converted within the zone measuring function into
corresponding boolean expressions for each condition separately. It is connected to the PHS
function block output STCNDZ.
The input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The
zone measurement function filter out the relevant signals on the DIRCND input depending on
the setting of the parameter OperationDir. It shall be configured to the DIRCND output on the
ZDM block.
216
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
STCND
AND STNDL1N
L1N
AND STNDL2N
L2N
STNDL3N
L3N AND
OR STNDPE
OR
VTSZ STND
OR AND
BLOCK
BLK
en06000408.vsd
Figure 114: Conditioning by a group functional input signal STCND
Composition of the phase starting signals for a case, when the zone operates in a non-directional
mode, is presented in figure 115.
STNDL1N 15 ms
AND t STL1
STNDL2N 15 ms
AND t STL2
STNDL3N 15 ms
AND t STL3
15 ms
AND t START
OR
BLK
en06000409.vsd
Results of the directional measurement enter the logic circuits, when the zone operates in direc-
tional (forward or reverse) mode, see figure 116.
217
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
STNDL1N
DIRL1N AND
OR STZMPE.
&
STNDL2N
DIRL2N AND
STNDL3N 15 ms
STL1
& t
DIRL3N AND
15 ms
STL2
& t
15 ms
STL3
& t
BLK
15 ms
OR START
& t
en07000081.vsd
Figure 116: Composition of starting signals in directional operating mode
Tripping conditions for the distance protection zone one are symbolically presented in figure
117.
en07000082.vsd
Figure 117: Tripping logic for the distance protection zone one
218
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
ZMM1-
ZMMPDIS_21
I3P TRIP
U3P TR_A
BLOCK TR_B
BLKZ TR_C
BLKTR PICKUP
STCND PU_A
DIRCND PU_B
PU_C
PHPUND
en06000454.vsd
Table 102: Output signals for the ZMMPDIS_21 (ZMM1-) function block
Signal Description
TRIP General Trip, issued from any phase or loop
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
START General Start, issued from any phase or loop
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
STND Non-directional start, issued from any phase or loop
219
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
220
Full scheme distance protection, quadrilateral Chapter 5
for Mho Impedance protection
221
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
6.1 Introduction
The operation of transmission networks today is in many cases close to the stability limit. Due
to environmental considerations the rate of expansion and reinforcement of the power system is
reduced e.g. difficulties to get permission to build new power lines. The ability to accurate and
reliable classifying the different types of fault so that single pole tripping and auto-reclosing can
be used plays an important roll in this matter. The phase selection function is design to accurate
select the proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may in some cases in-
terfere with the distance protection zone reach and cause unwanted operation. Therefore the
function has a built in algorithm for load encroachment, which gives the possibility to enlarge
the resistive setting of the measuring zones without interfering with the load.
The output signals from the phase selection function produce important information about faulty
phase(s) which can be used for fault analysis as well.
The function can be de-activated and activated by setting the parameter Operation Off/On The
total function can be blocked by activating the input BLOCK.
222
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
The aim of the delta based phase selector is to provide very fast and reliable phase selection for
releasing of tripping from the high speed Mho element and as well as is essential to Directional
Comparison Blocking scheme (DCB), which uses Power Line Carrier (PLC) communication
system across the protected line.
The current and voltage samples for each phase passes through a notch filter that filters out the
fundamental components. Under steady state load conditions or when no fault is present, the out-
put of the filter is zero or close to zero. When a fault occurs, currents and voltages change result-
ing in sudden changes in the current and voltages resulting in non-fundamental waveforms being
introduced on the line. At this point the notch filter produces significant non-zero output. The
filter output is processed by the delta function. The algorithm uses an adaptive relationship be-
tween phases to determine if a fault has occurred, and determines the faulty phases.
The current and voltage delta phase selector gives a real output signal if the following criteria is
fulfilled (only phase L1 shown):
Max(UL1,UL2,UL3)>DeltaUMinOp
Max(IL1,IL2,IL3)>DeltaIMinOp
where:
UL1, UL2 and UL3 are the voltage change between sample t and sample t-1
DeltaUMinOp and DeltaIMinOp are the minimum harmonic level settings for the voltage and current fil-
ters to decide that a fault has occured indeed. A slow evolving fault may
not produce sufficient harmonics to detect the fault; however, in such a
case speed is no longer the issue and the sequence components phase
selector will operate.
The delta voltages ULn and delta current ILn (n prefix for phase order) are the voltage and
current between sample t and sample t-1.
The delta phase selector employs adaptive techniques to determine the fault type. The logic de-
termines the fault type by summing up all phase values and dividing by the largest value. Both
voltages and currents are filtered out and evaluated. The condition for fault type classification
for the voltage and currents can be expressed as
223
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
The output signal is 1 for single line to earth fault, 2 for phase to phase fault and 3 for three phase
fault. At this point the filer does not know if ground was involved or not.
Typically there are induced harmonics in the non-faulted lines that will affect the result. This
method allows for a significant tolerance in the evaluation of FaultType over its entire range.
When a single fault has been detected, the logic determines the largest quantity, and asserts that
phase. If phase to phase fault is detected, the two largest phase quantities will be detected and
asserted as outputs.
The faults detected by the delta based phase selector are coordinated in a separate block. Differ-
ent phases of faults may be detected at slightly different times due to differences in the angles
of incidence of fault on the waveshape. The output is forcet to wait a certain time. If the timer
expires, if no other fault detection on the other phases is not detected, the fault is deemed as
phase-to-ground. This way a premature single phase to earth fault detection is not released for a
phase-phase fault. If, however, ground current is detected before the timer expires, the phase to
ground fault is released sooner.
If another phase picks up during the delay, the wait time is reduced by a certain amount. Each
detection of either ground or additional phases further reduce the initial wait time and allow the
delta phase selector output to be asserted sooner. There is not wait time, if for example, all three
phases are faulty.
The delta function is released if the input DELTAREL is activated at the same time as input
DELTABLK is not activated. Activating the DELTABLK input will block the delta function.
The release signal has an internal pulse timer of 100 ms. When the DELTAREL signal has dis-
appeared the delta logic is reset. In order not to get too abrupt change, the reset is decayed in
pre-defined steps.
224
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
The complementary based zero sequence current function evaluates the presence of earth fault
by calculating the 3I0 and comparing the result with the setting parameter INtoMaxI. The output
signal is used to release the earth fault loop. It is a complement to the earth fault signal built-in
in the sequence based phase selector. The condition for releasing the phase to earth loop are as
follows:
|3I0|>maxIph INto Im ax
where:
|3I0| is the magnitude of the zero sequence current 3I0
maxIph is the maximum magnitude of the phase currents
INtoImax is a setting parameter for the relation between the magnitude of 3I0 and the maxi-
mum phase current
The earth fault loop is also released if the evaluation of the zero sequence current by the main
sequence function meets the following conditions:
|3I0|>IMinOp k1
|3I0|>maxIph IN RelPE
where:
IMinOp is the settings of the minimum operate phase current
INRelPE is the setting of 3I0 limit for release of phase-to-earth measuring loop in % of IBase
k1 is a design parameter
IBase is the setting of the base current (A)
225
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
In systems where the source impedance for zero sequence is high the change of zero sequence
current may not be secure. In those cases the sequence based phase selector will automatically
change from evaluation of zero sequence current to evaluation of zero and negative sequence
voltage. So the release of earth fault loop can also be done if the following conditions are ful-
filled:
|3U0|>U2*k2
|3U0|>U1*k3
|U1|>k
and
3I0<IMinOp*k5
OR
3I0<ILmax INRelPE
where:
3U0 is the magnitude of the zero sequence voltage
2 is the magnitude of the negative sequence voltage at the relay measuring point of
phase L1
k2, k3, k4 and k5 are design parameters
ILmax is the maximal phase current
IMinOp is the setting of minimum operate phase current in % of IBase
226
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
VC 60
C-A sector
VB 0
180 B-C sector
A-B sector
VA
300
en06000383_ansi.vsd
The phase to phase loop for the faulty phases will be determined if the angle between the se-
quence voltages U2 and U1 lies within the sector defined according to figure 119 and the fol-
lowing conditions are fulfilled:
|U2|>U2MinOp
|U1|>U1MinOP
where:
U1MinOP and U2MinOp are the setting parameters for positive sequence and negative sequence mini-
mum operate voltage
If there is a three phase fault, there will not be any release of the individual phase signals, even
if the general conditions for U2 and U1 are fulfilled.
The first condition determines faulty phase at single line to earth fault by determine the argument
between V2 and I0.
227
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
80
200
L1-N sector
320
en06000384.vsd
The angle is calculated in a directional function block and gives the angle in radians as input to
the V2I0 function block. The input angle is released only if the fault is in forward direction. This
is done by the directional element. The fault is classified as forward direction if the angle be-
tween U0 and I0 lies between 20 to 200 degrees see figure 121.
Forward 20
200 Reverse
en06000385.vsd
Figure 121: Directional element used to release the measured angle between U2 and I0
The input radians are summarized with an offset angle and the result evaluated. If the angle is
within the boundaries for a specific sector, the phase indication for that sector will be active see
figure 120. Only one sector signal is allowed to be activated at the same time.
228
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
The sector function for condition1 has an internal release signal which is active if the main se-
quence function has classified the angle between U0 and I0 as valid. The following conditions
must be fulfilled for activating the release signals:
|U2|>U2MinOp
|3I0|>IMinOp 0.5
|3I0|>ILmax INRelPE
where:
U2 and IN are the magnitude of the negative sequence voltage and zero sequence current (3I0)
U2MinOp is the setting parameter for minimum operate negative sequence voltage
IMinOp is the setting parameter for minimum operate phase current
INRelPE is the setting parameter for 3I0 limit for releasing phase to earth loop
The angle difference is phase shifted by 180 degrees if the fault is in reverse direction.
The condition2 looks at the angle relationship between the negative sequence voltage U2 and
the positive sequence voltage U1. Since this is a phase to phase voltage relationship, there is no
need for shifting phases if the fault is in reverse direction. A phase shift is introduced so that the
fault sectors will have the same angle boarders as for condition1. If the calculated angle between
U2 and U1 lies within one sector, the corresponding phase for that sector will be activated. The
condition2 is released if both the following conditions are fulfilled:
|U2|>U2MinOp
|U1|>U1MinOP
where:
|U1| and |U2| are the magnitude of the positive and negative sequence voltage
U1MinOP and are the setting parameter for positive sequence and negative sequence mini-
mum operate voltage.
229
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
140
L3-N sector
20
U1L1
(Ref)
L1-N sector
L2-N sector
260 en06000413.vsd
If both conditions are true and there is sector match, the fault is deemed as single phase to
ground. If the sectors, however, do not match the fault is determined to be the complement of
the second condition, i.e. a phase to phase to ground fault.
E.g.
Condition 1 Condition 2 Fault type
L3-G L3-G L3-G
L2-G L1-G L2-L3-G
The sequence phase selector is blocked when earth is not involved or if a three phase fault is
detected.
|U1|>U1Level
|I1|>I1Level
or
|I1|>IMaxLoad
where:
U1 and I1 are the positive sequence voltage and current magnitude
U1Level and I1Level are the setting of limits for positive sequence voltage and current
230
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
The output signal for detection of three phase fault is only released if not earth fault and phase
to phase fault in the main sequence function is detected.
The conditions for not detecting earth fault are the inverse of equation 5 to10.
The condition for not detecting phase to phase faults is determined by three conditions. Each of
them gives condition for not detecting phase to phase fault. Those are:
Condition1:
earth fault is detected
or
|IN|>IMinOP*k2
and
|IN|>ILmax*INRelPE
Condition2:
Condition2 for phase to earth and phase to phase faults are not fulfilled
and
ILmax<IMinOp
and
|I2|<ILmax*I2ILmax
Condition3:
|IN|>maxIL*INBlockPP
or
|I2|<maxIL*I2maxIL
where:
ILmax is the maximum of the phase currents IL1, IL2 and IL3
INRelPE is the setting parameter for 3I0 limit for release of phase to earth fault loops
|I2| is the magnitude of the negative sequence current
I2ILmax is the setting parameter for the relation between negative sequence current to the maximum
phase current in percent of IBase
INBlockPP is the setting parameter for 3I0 limit for blocking phase to phase measuring loops
231
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
a a>b FaultPriority
DeltaIL1 then c=a c Adaptive release
b else c=a dependent on result
from Delta logic
DeltaUL1
Sequence based
function a<b
a
L1L2 fault
then c=b c
OR b else c=a OR
L1N fault
3 Phase fault
STL1
IL1Valid &
BLOCK
en06000386.vsd
The outline of the characteristic is presented in figure 124. As illustrated, the resistive reach are
set individually in forward and reverse direction while the angle of the sector is the same in all
four quadrants. The reach for the phase selector will be reduced by the load encroachment func-
tion, see right figure 124.
232
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
X jX
RLd
ArgLd ArgLd
R
ArgLd R
ArgLd
RLd
Operation area
en06000414.vsd
Outputs
The output of the sequence components based phase selector and the delta logic phase selector
activates the output signal(s) STL1, STL2 and STL3PU_A, PU_B and PU_C. If the phase to
earth loop have been released, then the signal STE will be activated as well.
The phase selector also gives binary coded signals that are connected to the zone measuring el-
ement for opening the correct measuring loop(s). This is done by the signal STCNDPHS. If only
one phase is enable (L1, L2 or L3), the corresponding phase to ground element is enabled as
well. Earth is expected to be made available for two and three phase faults for the correct output
to be asserted. The fault loop is indicated by one of the decimal numbers below:
0= no faulted phases
1= L1N
2= L2N
3= L3N
4= -L1L2N
5= -L2L3N
6= -L3L1N-CAG
7= -L1L2L3N
8= -L1L2
9= -L2L3
10= -L3L1
11= L1L2L3
233
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
An additional logic is applied to handle the cases when phase to earth outputs are to be asserted
when the ground input G is not asserted.
The output signal STCNDPLE is activated when the load encroachment is operating. STCND-
PLE shall be connected to the input STCND for selected quadrilateral impedance measuring
zones (ZM0x) to be blocked. The signal STCNDLE shall be connected to the input LDCND for
selected Mho impedans measuring zones (ZMMx)
Note!
The load encroachment at the measuring zone must be activated to release the blocking from the
load encroachment function.
PHM-
FMPSPDIS
I3P STL1
U3P STL2
BLOCK STL3
ZSTART STPE
TR3PH STCNDPHS
1POLEAR STCNDPLE
STCNDLE
START
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234
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
Table 106: Output signals for the FMPSPDIS (PHM-) function block
Signal Description
STL1 Fault detected in phase L1
STL2 Fault detected in phase L2
STL3 Fault detected in phase L3
STPE Earth fault detected
STCNDPHS Binary coded starts from phase selection
STCNDPLE Binary coded starts from ph sel with load encroachment
STCNDLE Binary coded starts from load encroachment only
START Indicates that something has started
Table 108: Advanced parameter group settings for the FMPSPDIS (PHM-) function
Parameter Range Step Default Unit Description
DeltaIMinOp 5 - 100 1 10 %IB Delta current level in % of
IBase
DeltaUMinOp 5 - 100 1 20 %UB Delta voltage level in %
of UBase
U1Level 5 - 100 1 80 %UB Pos seq voltage limit for
identification of 3-ph fault
235
Faulty phase identification with load Chapter 5
enchroachment (PDIS, 21) Impedance protection
236
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
7.1 Introduction
The phase-to-earth impedance elements can be optionally supervised by a phase unselective di-
rectional function (phase unselective, because it is based on symmetrical components).
237
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
Where:
ArgDir Setting for the lower boundary of the forward directional characteristic, by default set to
15 (= -15 degrees)
ArgNegRes Setting for the upper boundary of the forward directional characteristic, by default set to
115 degrees, see figure 126
U1L1 Positive sequence phase voltage in phase L1
U1L1M Positive sequence memorized phase voltage in phase L1
IL1 Phase current in phase L1
U1L1L2 Voltage difference between phase L1 and L2 (L2 lagging L1)
U1L1L2M Memorized voltage difference between phase L1 and L2 (L2 lagging L1)
IL1L2 Current difference between phase L1 and L2 (L2 lagging L1)
The default settings for ArgDir and ArgNegRes are 15 (= -15) and 115 degrees respectively (see
figure 126) and they should not be changed unless system studies show the necessity.
The directional lines are computed by means of a comparator-type calculation, meaning that the
directional lines are based on mho-circles (of infinite radius).
X
Zset reach point
ArgNegRes
-ArgDir R
-Zs
en06000416.vsd
The reverse directional characteristic is equal to the forward characteristic rotated by 180 de-
grees.
238
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the
set base voltage UBase. So the directional element can use it for all unsymmetrical faults includ-
ing close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same positive se-
quence voltage, ensures correct directional discrimination.
The memory voltage is used for 100ms or until the positive sequence voltage is restored. After
100ms, the following occurs:
If the current is still above the set value of the minimum operating current the
condition seals in.
- If the fault has caused tripping, the trip endures.
- If the fault was detected in the reverse direction, the measuring element in
the reverse direction remains in operation.
If the current decreases below the minimum operating value, no directional indi-
cations will be given until the positive sequence voltage exceeds 10% of its rated
value.
The directional function block ZDM has the following output signals:
The STDIRCND output provides an integer signal that depends on the evaluation and is derived
from a binary coded signal as follows:
The STFW output is a logical signal with value 1 or 0. It is made up as an OR-function of all the
forward starting conditions, i.e. STFWL1N, STFWL2N, STFWL3N, STFWL1L2, STFWL2L3
and STFWL3L1. The STRV output is similar to the STFW output, the only difference being that
it is made up as an OR-function of all the reverse starting conditions, i.e. STRVL1N, STRVL2N,
STRVL3N, STRVL1L2, STRVL2L3 and STRVL3L1.
Values for the following parameters are calculated, and may be viewed as service values:
resistance phase L1
reactance phase L1
resistance phase L2
reactance phase L2
resistance phase L3
reactance phase L3
direction phase L1
239
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
direction phase L2
direction phase L3
7.2.2 Additional distance protection directional function for earth faults, ZDA
A Mho element needs a polarizing voltage for its operation. The positive-sequence memory-po-
larized elements are generally preferred. The benefits include:
The greatest amount of expansion for improved resistive coverage. These ele-
ments always expand back to the source.
Memory action for all fault types. This is very important for close-in 3-phase
faults.
A common polarizing reference for all six distance-measuring loops. This is im-
portant for single-pole tripping, during a pole-open period.
There are however some situations that can cause security problems like reverse phase to phase
faults and double phase to earth faults during high load periods. To solve these, additional direc-
tional element is used.
For phase to earth faults, directional elements using sequence components are very reliable for
directional discrimination. The directional element can be based on one of following types of
polarization:
Zero-sequence voltage
Negative-sequence voltage
Zero-sequence current
These additional directional criteria are evaluated in the function block ZDA.
Zero-sequence voltage polarization is utilizing the phase relation between the zero-sequence
voltage and the zero-sequence current at the location of the protection. The measurement prin-
ciple is illustrated in figure 127.
240
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
- 3U 0
AngleOp
AngleRCA
3I 0
en06000417.vsd
Figure 127: Principle for zero-sequence voltage polarized additional directional element
Negative-sequence voltage polarization is utilizing the phase relation between the negative-se-
quence voltage and the negative-sequence current at the location of the protection.
Zero-sequence current polarization is utilizing the phase relation between the zero-sequence cur-
rent at the location of the protection and some reference zero-sequence current, for example the
current in the neutral of a power transformer.
Z0 SA I0 I0
Z0Line Z0SB
Characteristic
angle
U0 U0
K*I0
U0 + K*I0
IF
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Figure 128: Principle for zero sequence compensation
241
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
Note that the sequence based additional directional element cannot give per phase information
about direction to fault. This is why it is an AND-function with the normal directional element
that works on a per phase base. The release signals are per phase and to have a release of a mea-
suring element in a specific phase both the additional directional element, and the normal direc-
tional element, for that phase must indicate correct direction.
Normal
directional Release of distance
element measuring element
L1N, L2N, L3N L1N, L2N, L3N
AND
Additional
directional AND per
element phase
en06000419.vsd
ZDM1-
ZDMRDIR
I3P DIR_CURR
U3P DIR_VOLT
DIR_POL
STFW
STRV
STDIRCND
en06000422.vsd
ZDA1-
ZDARDIR
I3P STFWPE
U3P STRVPE
I3PPOL DIREFCND
DIRCND
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242
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
Table 111: Output signals for the ZDMRDIR (ZDM1-) function block
Signal Description
DIR_CURR Group connection
DIR_VOLT Group connection
DIR_POL Group connection
STFW Start in forward direction
STRV Start in reverse direction
STDIRCND Binary coded directional information per measuring loop
Table 112: Input signals for the ZDARDIR (ZDA1-) function block
Signal Description
I3P Current signals
U3P Voltage signals
I3PPOL Polarisation current signals
DIRCND Binary coded directional signal
Table 113: Output signals for the ZDARDIR (ZDA1-) function block
Signal Description
STFWPE Forward start signal from phase-to-ground directional element
STRVPE Reverse start signal from phase-to-ground directional element
DIREFCND Start direction Binary coded
243
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
Table 115: Basic parameter group settings for the ZDARDIR (ZDA1-) function
Parameter Range Step Default Unit Description
IBase 1 - 99999 1 3000 A Base setting for current
values
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
level in kV
PolMode -3U0 - -3U0 - Polarization quantity for
-U2 opt dir function for P-E
IPol faults
Dual
-3U0Comp
-U2comp
AngleRCA -90 - 90 1 75 Deg Characteristic relay angle
(= MTA or base angle)
I> 1 - 200 1 5 %IB Minimum operation cur-
rent in % of IBase
UPol> 1 - 100 1 1 %UB Minimum polarizing volt-
age in % of UBase
IPol> 5 - 100 1 10 %IB Minimum polarizing cur-
rent in % of IBase
244
Directional impedance Mho (RDIR) Chapter 5
Impedance protection
Table 116: Advanced parameter group settings for the ZDARDIR (ZDA1-) function
Parameter Range Step Default Unit Description
AngleOp 90 - 180 1 160 Deg Operation sector angle
Kmag 0.50 - 3000.00 0.01 40.00 ohm Boost-factor in -U0comp
and -U2comp polariza-
tion
245
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
8.1 Introduction
Power swings may occur after disconnection of heavy loads or trip of big generation plants.
Power swing detection function is used to detect power swings and initiate block of selected dis-
tance protection zones. Occurrence of earth fault currents during a power swing can block the
power swing detection function to allow fault clearance.
Its principle of operation is based on the measurement of the time it takes for a power swing tran-
sient impedance to pass through the impedance area between the outer and the inner character-
istics. Power swings are identified by transition times longer than a transition time set on
corresponding timers. The impedance measuring principle is the same as that used for the dis-
tance protection zones. The impedance and the characteristic passing times are measured in all
three phases separately. One-out-of-three or two-out-of-three operating modes can be selected
according to the specific system operating conditions.
246
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
X1OutFw jX ZL R1LIn
X1InFw Fw
Rv
R1FInRv R1FInFw
Fw
ARGLd
Rv ARGLd
Fw
Fw
R
Fw
Rv
RLdInRv RLdInFw
Fw
Rv
RLdOutRv RLdOutFw
Rv X1InRv
X1OutRv
en05000175.vsd
The impedance measurement within the PSD function is performed by solving equation 49 and
equation 50 (n = 1, 2, 3 for each corresponding phase L1, L2 and L3).
U L1
Re Rset
I L1
(Equation 49)
U L1
Im Xset
IL1
(Equation 50)
The Rset and Xset are R and X boundaries which are more explained in the following sections.
247
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
where:
kLdRFw is a settable multiplication factor less than 1
The slope of the load encroachment inner and outer boundary is defined by setting the parameter
ARGLd.
The load encroachment in the fourth quadrant uses the same settings as in the first quadrant
(same ARGLd and RLdOutFw and calculated RLdInFw).
The quadrilateral characteristic in the first quadrant is tilted to get a better adaptation to the dis-
tance zones. The angle is the same as the line angle and derived from the setting of the reactive
reach inner boundary X1InFw and the line resistance for the inner boundary R1LIn. The fault
resistance coverage for the inner boundary is set by the parameter R1FInFw.
From the setting parameter RLdOutFw and the calculated value RLdInFw a distance between the
inner and outer boundary, Fw, is calculated. This value is valid for R direction in first and
fourth quadrant and for X direction in first and second quadrant.
From the setting parameter RLdOutRv and the calculated value RLdInRv a distance between the
inner and outer boundary, Rv, is calculated. This value is valid for R direction in second and
third quadrant and for X direction in third and fourth quadrant.
The inner resistive characteristic in the second quadrant outside the load encroachment part cor-
responds to the setting parameter R1FInRv for the inner boundary. The outer boundary is inter-
nally calculated as the sum of Rv+R1FInRv.
248
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
The inner resistive characteristic in the third quadrant outside the load encroachment zone con-
sist of the sum of the settings R1FInRv and the line resistance R1LIn. The argument of the tilted
lines outside the load encroachment is the same as the tilted lines in the first quadrant. The dis-
tance between the inner and outer boundary is the same as for the load encroachment in reverse
direction i.e. Rv.
where:
Fw = RLdOutFw - KLdRFw RLdOutFw
The inner characteristic for the reactive reach in reverse direction correspond to the setting pa-
rameter X1InRv for the inner boundary and the outer boundary is defined as X1InRv + Rv.
where:
Rv = RLdOutRv - KLdRRv RLdOutRv
The "1-of-3" operating mode is based on detection of power swing in any of the
three phases. Figure 133 presents a composition of a detection signal
PSD-DET-L1 in this particular phase.
The "2-of-3" operating mode is based on detection of power swing in at least two
out of three phases. Figure 134 presents a composition of the detection signals
DET1of3 and DET2of3.
Signals ZOUTL1ZOUT_A (external boundary) and ZINL1 (internal boundary) in figure 133 are
related to the operation of the impedance measuring elements in each phase separately (Ln rep-
resents the corresponding phase L1, L2, and L3). They are internal signals, calculated by the
PSD-function.
The tP1 timer in figure 133 serve as detection of initial power swings, which are usually not as
fast as the later swings are. The tP2 timer become activated for the detection of the consecutive
swings, if the measured impedance exit the operate area and returns within the time delay, set
on the tW waiting timer. The upper part of figure 133 (input signal ZOUTL1, ZINL1,
AND-gates and tP-timers etc.) are duplicated for phase L2 and L3. All tP1 and tP2 timers in the
figure have the same settings.
249
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
Figure 134: Detection of power-swing for 1-of-3 and 2-of-3 operating mode
250
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
ZOUTL1 ZOUT
OR
ZOUTL2 ZINL1
ZIN
ZOUTL3 AND ZINL2 OR
ZINL3
tEF
TRSP
t AND
I0CHECK
10 ms
AND t
BLKI02 OR
tR1
AND t INHIBIT
OR
-loop
tR2
BLKI01 AND t
BLOCK
-loop
DET1of3 - int.
REL1PH
AND
BLK1PH
tH
DET2of3 - int. OR t
REL2PH
AND
BLK2PH OR START
AND
EXTERNAL
en05000114.vsd
Selection of the operating mode is possible by the proper configuration of the functional input
signals REL1PH, BLK1PH, REL2PH, and BLK2PH.
The load encroachment characteristic can be switched off by setting the parameter Operation-
LdCh = Off, but notice that the Fw and Rv will still be calculated. The characteristic will in
this case be only quadrilateral.
There are four different ways to form the internal INHIBIT signal:
251
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
Logical 1 on functional input BLOCK inhibits the output START signal instan-
taneously.
The INHIBIT internal signal is activated, if the power swing has been detected
and the measured impedance remains within its operate characteristic for the
time, which is longer than the time delay set on tR2 timer. It is possible to disable
this condition by connecting the logical 1 signal to the BLKI01 functional input.
The INHIBIT internal signal is activated after the time delay, set on tR1 timer, if
an earth fault appears during the power swing (input IOCHECK is high) and the
power swing has been detected before the earth fault (activation of the signal
I0CHECK). It is possible to disable this condition by connecting the logical 1 sig-
nal to the BLKI02 functional input.
The INHIBIT logical signals becomes logical 1, if the functional input I0CHECK
appears within the time delay, set on tEF timer and the impedance has been seen
within the outer characteristic of the PSD operate characteristic in all three phas-
es. This function prevents the operation of the PSD function in cases, when the
circuit breaker closes onto persistent single-phase fault after single-pole auto-re-
closing dead time, if the initial single-phase fault and single-pole opening of the
circuit breaker causes the power swing in the remaining two phases.
PSD1-
ZMRPSB_78
I3P START
U3P ZOUT
BLOCK ZIN
BLKI01
BLKI02
BLK1PH
REL1PH
BLK2PH
REL2PH
I0CHECK
TRSP
EXTERNAL
en06000264.vsd
252
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
Signal Description
BLK1PH Block one-out-of-three-phase operating mode
REL1PH Release one-out-of-three-phase operating mode
BLK2PH Block two-out-of-three-phase operating mode
REL2PH Release two-out-of-three-phase operating mode
I0CHECK Residual current (3I0) detection used to inhibit start output
TRSP Single-pole tripping command issued by tripping function
EXTERNAL Input for external detection of power swing
Table 118: Output signals for the ZMRPSB_78 (PSD1-) function block
Signal Description
START Power swing detected
ZOUT Measured impedance within outer impedance boundary
ZIN Measured impedance within inner impedance boundary
253
Power swing detection (RPSB, 78) Chapter 5
Impedance protection
Table 120: Advanced parameter group settings for the ZMRPSB_78 (PSD1-) function
Parameter Range Step Default Unit Description
tP1 0.000 - 60.000 0.001 0.045 s Timer for detection of ini-
tial power swing
tP2 0.000 - 60.000 0.001 0.015 s Timer for detection of
subsequent power
swings
tW 0.000 - 60.000 0.001 0.250 s Waiting timer for activa-
tion of tP2 timer
tH 0.000 - 60.000 0.001 0.500 s Timer for holding power
swing START output
tR1 0.000 - 60.000 0.001 0.300 s Timer giving delay to
inhibit by the residual cur-
rent
tR2 0.000 - 60.000 0.001 2.000 s Timer giving delay to
inhibit at very slow swing
254
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
9.1 Introduction
Power Swing Logic (RPSL) is a complementary function to Power Swing Detection (PSD) func-
tion. It provides possibility for selective tripping of faults on power lines during system oscilla-
tions (power swings or pole slips), when the distance protection function should normally be
blocked. The complete logic consists of two different parts:
255
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
STDEF
AR1P1 &
STPSD tCS
CS
BLOCK & t &
CSUR
BLKZMPS
tBlkTr &
tTrip t
t
CACC TRIP
>1
CR &
en06000236.vsd
Figure 137: Simplified logic diagram power swing communication and tripping logic
The complete logic remains blocked as long as there is a logical one on the BLOCK functional
input signal. Presence of the logical one on the STDEF functional input signal also blocks the
logic as long as this block is not released by the logical one on the AR1P1 functional input sig-
nal. The functional output signal BLKZMPS remains logical one as long as the function is not
blocked externally (BLOCK is logical zero) and the earth-fault is detected on protected line
(STDEF is logical one), which is connected in three-phase mode (AR1P1 is logical zero). Timer
tBlkTr prolongs the duration of this blocking condition, if the measured impedance remains
within the operate area of the PSD function (STPSD input active). The BLKZMPS can be used
to block the operation of the power-swing zones.
Logical one on functional input CSUR, which is normally connected to the TRIP functional out-
put of a power swing carrier sending zone, activates functional output CS, if the function is not
blocked by one of the above conditions. It also activates the TRIP functional output.
Initiation of the CS functional output is possible only, if the STPSD input has been active longer
than the time delay set on the security timer tCS.
Simultaneous presence of the functional input signals PLTR_CRD and CR (local trip condition)
also activates the TRIP functional output, if the function is not blocked by one of the above con-
ditions and the STPSD signal has been present longer then the time delay set on the trip timer
tTrip.
256
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
&
BLKZMH
&
STZML tZL
STZMLL
BLOCK & t >1
&
STMZH tDZ
STZMPSD & t
>1
STPSD
&
-loop
en06000237.vsd
Figure 138: Control of underreaching distance protection (Zone 1) at power swings caused by
the faults and their clearance on adjacent lines and other system elements
The logic is disabled by a logical one on functional inputBLOCK. It can start only if the follow-
ing conditions are simultaneously fulfilled:
STPSD functional input signal must be a logical zero. This means, that the PSD
function must not detect power swinging over the protected power line.
STZMPSD functional input must be a logical one. This means that the impedance
must be detected within the external boundary of the PSD function.
STZMOR functional input must be a logical one. This means that the fault must
be detected by the overreaching distance protection zone, for example zone 2.
The STZMURPS functional output, which can be used in complete terminal logic instead of a
normal distance protection zone 1, becomes active under the following conditions:
If the STZMUR signal appears at the same time as the STZMOR or if it appears
with a time delay, which is shorter than the time delay set on timer tDZ.
If the STZMUR signal appears after the STZMOR signal with a time delay longer
than the delay set on the tDZ timer, and remains active longer than the time delay
set on the tZL timer.
The BLKZMOR functional output signal can be used to block the operation of the higher dis-
tance protection zone, if the fault has moved into the zone 1 operate area after tDZ time delay.
257
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
PSL1-
ZMRPSL
BLOCK TRIP
STZMUR STZMURPS
STZMOR BLKZMUR
STPSD BLKZMOR
STDEF CS
STZMPSD
CACC
AR1P1
CSUR
CR
en07000026.vsd
Table 123: Output signals for the ZMRPSL (PSL1-) function block
Signal Description
TRIP Trip through Power Swing Logic
STZMURPS Start of Underreaching zone controlled by PSL to be used in
configuration
BLKZMUR Block trip of underreaching impedance zone
BLKZMOR Block trip of overreaching distance protection zones
CS Carrier send signal controlled by the power swing
258
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
259
Power swing logic (RPSL, 78) Chapter 5
Impedance protection
260
About this chapter Chapter 6
Current protection
261
Instantaneous phase overcurrent protection Chapter 6
(PIOC, 50) Current protection
1.1 Introduction
The instantaneous three phase overcurrent function has a low transient overreach and short trip-
ping time to allow use as a high set short-circuit protection function, with the reach limited to
less than typical eighty percent of the fault current transformer at minimum source impedance.
There is also a possibility to activate a preset change of the set operation current (StValMult) via
a binary input (ENMULT). In some applications the operation value needs to be changed, for
example due to transformer inrush currents.
IOC1-
PHPIOC_50
I3P TRIP
BLOCK TRL1
ENMULT TRL2
TRL3
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Instantaneous phase overcurrent protection Chapter 6
(PIOC, 50) Current protection
Table 126: Output signals for the PHPIOC_50 (IOC1-) function block
Signal Description
TRIP Trip signal from any phase
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
Table 128: Advanced parameter group settings for the PHPIOC_50 (IOC1-) function
Parameter Range Step Default Unit Description
StValMult 0.5 - 5.0 0.1 1.0 - Multiplier for operate cur-
rent level
263
Instantaneous phase overcurrent protection Chapter 6
(PIOC, 50) Current protection
264
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
2.1 Introduction
The four step phase overcurrent function has an inverse or definite time delay independent for
each step separately.
All IEC and ANSI time delayed characteristics are available together with an optional user de-
fined time characteristic.
The function can be set to be directional or non-directional independently for each of the steps.
Note!
If VT inputs are not available or not connected, func parameter DirModex shall be left to default
value, Non-directional.
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Four step phase overcurrent Chapter 6
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U3P
TRIP
Harmonic harmRestrBlock
I3P Restraint
Element
enableDir
Mode Selection
enableStep1-4
DirectionalMode1-4
en05000740.vsd
A common setting for all steps, StPhaseSel, is used to specify the number of phase currents to
be high to enable operation. The settings can be chosen: 1 out of 3, 2 out of 3 or 3 out of 3.
The sampled analogue phase currents are pre-processed in a pre-processing function blocks. By
a parameter setting within the general settings for the TOC function it is then possible to select
type of measurement which shall be used by TOC function for all overcurrent stages. It is pos-
sible to select either discrete Fourier filter (DFT) or true RMS filer (RMS). If DFT option is se-
lected then only the RMS value of the fundamental frequency components of each phase current
is derived. Influence of DC current component and higher harmonic current components are al-
most completely suppressed. If RMS option is selected then the true RMS values is used. The
true RMS value in addition to the fundamental frequency component includes the contribution
from the current DC component as well as from higher current harmonic. The selected current
values are fed to the TOC function. In a comparator, for each phase current, the DFT or RMS
values are compared to the set operation current value of the function (I1>, I2>, I3> or I4>). If
a phase current is larger than the set operation current a signal from the comparator for this phase
and step is set to true. This signal will, without delay, activate the output signal Start for this
phase/step, the Start signal common for all three phases for this step and a common Start signal.
266
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
It shall be noted that the selection of measured value (i.e. DFT or RMS) do not influence the
operation of directional part of TOC function. Service value for individually measured phase
currents are available from the TOC function. This feature simplifies testing, commissioning
and in service operational checking of the function.
A harmonic restrain of the function can be chosen. A set 2nd harmonic current in relation to the
fundamental current is used. The 2nd harmonic current is taken from the pre-processing of the
phase currents and the relation is compared to a set restrain current level.
The function can use a directional option. The direction of the fault current is given as current
angle in relation to the voltage angle. The fault current and fault voltage for the directional func-
tion is dependent of the fault type. To enable directional measurement at close in faults, causing
low measured voltage, the polarization voltage is a combination of the apparent voltage (85%)
and a memory voltage (15%). The following combinations are used.
U refL1L 2 = U L1 U L 2 I dirL1L 2 = I L1 I L 2
U refL 2 L 3 = U L 2 U L 3 I dirL 2 L 3 = I L 2 I L 3
U refL 3 L1 = U L 3 U L1 I dirL 3 L1 = I L 3 I L1
U refL1 = U L1 I dirL1 = I L1
U refL 2 = U L 2 I dirL 2 = I L 2
U refL 3 = U L 3 I dirL 3 = I L 3
The directional setting is given as a characteristic angle AngleRCA for the function and an angle
window AngleROA.
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Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
Reverse
Uref
RCA
ROA
ROA Forward
Idir
en05000745.vsd
The default value of AngleRCA is 65. The parameters AngleROA gives the angle sector from
AngleRCA for directional borders.
A minimum current for directional phase start current signal can be set: IminOpPhSel.
If no blockings are given the start signals will start the timers of the step. The time characteristic
for each step can be chosen as definite time delay or some type of inverse time characteristic. A
wide range of standardized inverse time characteristics is available. It is also possible to create
a tailor made time characteristic. The possibilities for inverse time characteristics are described
in chapter 21 "Time inverse characteristics".
Different types of reset time can be selected as described in chapter21 "Time inverse character-
istics".
There is also a possibility to activate a preset change (IxMult, x= 1, 2, 3 or 4) of the set operation
current via a binary input (enable multiplier). In some applications the operation value needs to
be changed, for example due to changed network switching state. The function can be blocked
from the binary input BLOCK. The start signals from the function can be blocked from the bi-
nary input BLKST. The trip signals from the function can be blocked from the binary input
BLKTR.
268
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
TOC1-
OC4PTOC_51_67
I3P TRIP
U3P TR1
BLOCK TR2
BLKTR TR3
BLKST1 TR4
BLKST2 TRL1
BLKST3 TRL2
BLKST4 TRL3
ENMULT1 TR1L1
ENMULT2 TR1L2
ENMULT3 TR1L3
ENMULT4 TR2L1
TR2L2
TR2L3
TR3L1
TR3L2
TR3L3
TR4L1
TR4L2
TR4L3
START
ST1
ST2
ST3
ST4
STL1
STL2
STL3
ST1L1
ST1L2
ST1L3
ST2L1
ST2L2
ST2L3
ST3L1
ST3L2
ST3L3
ST4L1
ST4L2
ST4L3
2NDHARM
DIRL1
DIRL2
DIRL3
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Four step phase overcurrent Chapter 6
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Table 131: Output signals for the OC4PTOC_51_67 (TOC1-) function block
Signal Description
TRIP Trip
TR1 Common trip signal from step1
TR2 Common trip signal from step2
TR3 Common trip signal from step3
TR4 Common trip signal from step4
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
TR1L1 Trip signal from step1 phase L1
TR1L2 Trip signal from step1 phase L2
TR1L3 Trip signal from step1 phase L3
TR2L1 Trip signal from step2 phase L1
TR2L2 Trip signal from step2 phase L2
TR2L3 Trip signal from step2 phase L3
TR3L1 Trip signal from step3 phase L1
TR3L2 Trip signal from step3 phase L2
TR3L3 Trip signal from step3 phase L3
TR4L1 Trip signal from step4 phase L1
TR4L2 Trip signal from step4 phase L2
TR4L3 Trip signal from step4 phase L3
START General start signal
270
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
Signal Description
ST1 Common start signal from step1
ST2 Common start signal from step2
ST3 Common start signal from step3
ST4 Common start signal from step4
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
ST1L1 Start signal from step1 phase L1
ST1L2 Start signal from step1 phase L2
ST1L3 Start signal from step1 phase L3
ST2L1 Start signal from step2 phase L1
ST2L2 Start signal from step2 phase L2
ST2L3 Start signal from step2 phase L3
ST3L1 Start signal from step3 phase L1
ST3L2 Start signal from step3 phase L2
ST3L3 Start signal from step3 phase L3
ST4L1 Start signal from step4 phase L1
ST4L2 Start signal from step4 phase L2
ST4L3 Start signal from step4 phase L3
2NDHARM Block from second harmonic detection
DIRL1 Direction for phase1
DIRL2 Direction for phase2
DIRL3 Direction for phase3
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Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
Table 133: Basic parameter group settings for the OC4PTOC_51_67 (TOC1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
IBase 1 - 99999 1 3000 A Base current
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
AngleRCA 40 - 65 1 55 Deg Relay characteristic
angle (RCA)
AngleROA 40 - 89 1 80 Deg Relay operation angle
(ROA)
StartPhSel Not Used - 1 out of 3 - Number of phases
1 out of 3 required for op (1 of 3, 2
2 out of 3 of 3, 3 of 3)
3 out of 3
DirMode1 Off - Non-directional - Directional mode of step
Non-directional 1 (off, nodir, forward,
Forward reverse)
Reverse
Characterist1 ANSI Ext. inv. - ANSI Def. Time - Selection of time delay
ANSI Very inv. curve type for step 1
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
I1> 1 - 2500 1 1000 %IB Phase current operate
level for step1 in % of
IBase
t1 0.000 - 60.000 0.001 0.000 s Definitive time delay of
step 1
k1 0.05 - 999.00 0.01 0.05 - Time multiplier for the
inverse time delay for
step 1
t1Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
inverse curves for step 1
272
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
273
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
274
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
275
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
Table 134: Advanced parameter group settings for the OC4PTOC_51_67 (TOC1-) function
Parameter Range Step Default Unit Description
IMinOpPhSel 1 - 100 1 7 %IB Minimum current for
phase selection in % of
IBase
2ndHarmStab 5 - 100 1 20 %IB Operate level of 2nd
harm restrain op in % of
Fundamental
ResetTypeCrv1 Instantaneous - Instantaneous - Selection of reset curve
IEC Reset type for step 1
ANSI reset
tReset1 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 1
tPCrv1 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 1
tACrv1 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 1
tBCrv1 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 1
tCCrv1 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 1
tPRCrv1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 1
tTRCrv1 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 1
tCRCrv1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 1
HarmRestrain1 Off - Off - Enable block of step 1
On from harmonic restrain
ResetTypeCrv2 Instantaneous - Instantaneous - Selection of reset curve
IEC Reset type for step 2
ANSI reset
tReset2 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 2
tPCrv2 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 2
tACrv2 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 2
276
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
277
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
278
Four step phase overcurrent Chapter 6
protection (PTOC, 51_67) Current protection
279
Instantaneous residual overcurrent protection Chapter 6
(PIOC, 50N) Current protection
IN>>
3.1 Introduction
The single input overcurrent function has a low transient overreach and short tripping times to
allow use for instantaneous earth fault protection, with the reach limited to less than typical
eighty percent of the transformer at minimum source impedance. The function can be configured
to measure the residual current from the three phase current inputs or the current from a separate
current input.
There is also a possibility to activate a preset change of the set operation current via a binary
input (enable multiplier MULTEN). In some applications the operation value needs to be
changed, for example due to transformer inrush currents.
The function can be blocked from the binary input BLOCK. The trip signals from the function
can be blocked from the binary input BLKAR, that can be activated during single pole trip and
autoreclosing sequences.
280
Instantaneous residual overcurrent protection Chapter 6
(PIOC, 50N) Current protection
IEF1-
EFPIOC_50N
I3P TRIP
BLOCK
BLKAR
MULTEN
en06000269.vsd
Table 137: Output signals for the EFPIOC_50N (IEF1-) function block
Signal Description
TRIP Trip signal
Table 139: Advanced parameter group settings for the EFPIOC_50N (IEF1-) function
Parameter Range Step Default Unit Description
StValMult 0.5 - 5.0 0.1 1.0 - Multiplier for operate cur-
rent level
281
Instantaneous residual overcurrent protection Chapter 6
(PIOC, 50N) Current protection
282
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
4
alt
4
4.1 Introduction
The four step residual single input overcurrent function has an inverse or definite time delay in-
dependent for each step separately.
All IEC and ANSI time delayed characteristics are available together with an optional user de-
fined characteristic.
The function can be used as main protection for phase to earth faults.
The function can be configured to measure the residual current from the three phase current in-
puts or the current from a separate current input.
These inputs are connected from the corresponding pre-processing function blocks in the Con-
figuration Tool within PCM.
283
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
where:
IL1, IL2 and IL3 are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete Fourier filter. Thus the phasor of the funda-
mental frequency component of the residual current is derived. The phasor magnitude is used
within the TEF function to compare it with the set operation current value of the four stages
(Pickup1, Pickup2, Pickup3 or Pickup4). If the residual current is larger than the set operation
current and the step is used in non-directional mode a signal from the comparator for this step is
set to true. This signal will, without delay, activate the output signal START for this step and a
common START signal.
The function can be set to use voltage polarizing, current polarizing or dual polarizing.
When Voltage Polarizing is selected the function will use the Residual Voltage (i.e. 3Uo) as po-
larizing quantity U3P. This voltage can be:
284
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
where:
UL1, UL2 and UL3 are fundamental frequency phasors of three individual phase voltages.
Note! In order to use this all three phase-to-ground voltages must be connected to three IED 670 VT
inputs.
The residual voltage is pre-processed by a discrete Fourier filter. Thus the phasor of the funda-
mental frequency component of the residual voltage is derived. This phasor is used, together
with the phasor of the operating current, in order to determine the direction of the earth fault (i.e.
Forward/Reverse). In order to enable voltage polarizing the magnitude of polarizing voltage
shall be bigger than a minimum level defined by setting parameter UpolMin.
It shall be noted that 3Uo is used to determine the location of the earth fault.Thus the setting
parameter ROT3U0, located under General Settings for Earth Fault function, has default value
of ROT3U0=180 deg. This insures the required inversion of the polarizing voltage within the
earth fault function.
When Current Polarizing is selected the function will use the Residual Current (i.e. 3Io) as po-
larizing quantity IPol. This current can be:
I Pol = 3 Io = IL1 + IL 2 + IL 3
where:
IL1, IL2 are fundamental frequency phasors of three individual phase currents. However this option can
and IL3 be as well only used for some special line protection applications as explained in the Applica-
tion Manual.
285
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
The residual polarizing current is pre-processed by a discrete Fourier filter. Thus the phasor of
the fundamental frequency component of the residual current is derived. This phasor is then mul-
tiplied with pre-set equivalent Zero Sequence Source Impedance in order to calculate equivalent
Polarizing Voltage UIPol in accordance with the following formula:
which will be then used, together with the phasor of the operating current, in order to determine
the direction of the earth fault (i.e. Forward/Reverse). In order to enable current polarizing the
magnitude of polarizing current shall be bigger than a minimum level defined by setting param-
eter IPollMin.
When Dual Polarizing is selected the function will use the vectorial sum of the voltage based
and current based polarizing in accordance with the following formula:
U TotPol = U UPol + U IPol = 3Uo + ZoS I Pol = 3Uo + (RNPol+j XNPol) I Pol
(Equation 56)
Then the phasor of the total polarizing voltage UTotPol will be used, together with the phasor of
the operating current, to determine the direction of the earth fault (i.e. Forward/Reverse).
286
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Simplified logic diagram for one residual overcurrent stage is shown in the following figure:
287
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
BLKTR
Characteristx=DefTime tx TRINx
|IOP| AND
a OR
a>b
b
ENMULTx
STINx
INxMult AND
X T
INx> F
Inverse
BLKSTx
BLOCK Characteristx=Inverse
2ndH_BLOCK_Int
OR
HarmRestrain1=Disabled
DirModex=Off OR STAGEx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
en07000064.vsd
Figure 145: Simplified logic diagram for residual overcurrent stage x , where x=1, 2 ,3 or 4
The function can be completely blocked from the binary input BLOCK. The start signals from
the function for each stage can be blocked from the binary input BLKSTx. The trip signals from
the function can be blocked from the binary input BLKTR.
The function has integrated directional feature. As the operating quantity current IOp is always
used. The polarizing method is determined by the parameter setting polMethod. The polarizing
quantity will be selected by the function in one of the following three ways:
The operating and polarizing quantity are then used inside the directional element, as shown in
the following figure, in order to determine the direction of the earth fault.
288
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Reverse
Area
0.4*IN>Dir
Upol=-3Uo
AngleRCA
0.4*IN>Dir
Forward
Area
Iop=3Io
en07000066.vsd
Operating Current Pickup IN>Dir. However it shall be noted that the directional
element will be internally enabled to operate as soon as IOp cos( - AngleRCA)
is bigger then 40% of IN>Dir.
Relay characteristic angle AngleRCA which defines the position of Forward &
Reverse areas in the operating characteristic.
Directional Comparison stage, built-in within directional supervision element, will set EF func-
tion output binary signal:
These signals shall be used for communication based earth fault teleprotection schemes (i.e. per-
missive or blocking).
289
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Simplified logic diagram for directional supervision element with integrated directional compar-
ison stage is shown in the following figure:
|IOP|
a
a>b STRV
b AND
REVERSE_Int
0.6
X
a
a>b STFW
IN>Dir b AND
FORWARD_Int
X
0.4
FWD
AND FORWARD_Int
AngleRCA
Characteristic
PolMethod=Voltage
OR
Directional
PolMethod=Current UPolMin
UIPol
RNPol COMPLEX X T
NUMBER
XNPol 0.0 F STAGE1_DIR_Int
STAGE2_DIR_Int
OR
STAGE3_DIR_Int
STAGE4_DIR_Int
BLOCK AND
en07000067.vsd
Figure 147: Simplified logic diagram for directional supervision element with integrated di-
rectional comparison stage
290
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
In addition to the basic functionality explained above the 2nd harmonic blocking can be set in
such way to seal-in until residual current disappears. This feature might be required to stabilize
the EF function during switching of parallel transformers in the station. In case of parallel trans-
formers there is a risk of sympathetic inrush current. If one of the transformers is in operation,
and the parallel transformer is switched in, the asymmetric inrush current of the switched in
transformer will cause partial saturation of the transformer already in service. This is called
transferred saturation. The 2nd harmonic of the inrush currents of the two transformers will be
in phase opposition. The summation of the two currents will thus give a small 2nd harmonic cur-
rent. The residual fundamental current will however be significant. The inrush current of the
transformer in service before the parallel transformer energizing, will be a little delayed com-
pared to the first transformer. Therefore we will have high 2nd harmonic current component ini-
tially. After a short period this current will however be small and the normal 2nd harmonic
blocking will reset. If the BlkParTransf function is activated the 2nd harmonic restrain signal will
be latched as long as the residual current measured by the relay is larger than a selected step cur-
rent level.
This feature has been called Block for Parallel Transformers. This 2nd harmonic seal-in feature
will be activated when all of the following three conditions are simultaneously fulfilled:
Once Block for Parallel Transformers is activated the basic 2nd harmonic blocking signal will
be sealed-in until the residual current magnitude falls below a value defined by parameter setting
UseStartValue (see condition 3 above).
Simplified logic diagram for 2nd harmonic blocking feature is shown in the following figure:
291
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
BLOCK
2ndHarmStab
X
Extract second
IOP 2NDHARMD
harmonic current a OR
a>b
component
b
Extract
fundamental
q-1
current component
t=70ms OR
t AN OR 2ndH_BLOCK_Int
D
BlkParTransf=On
|IOP|
a
a>b
b
UseStartValue
IN1>
IN2>
IN3>
IN4>
en07000068.vsd
Figure 148: Simplified logic diagram for 2nd harmonic blocking feature and Block for Parallel
Transformers feature
The SOTF logic uses the start signal from step 2 or step 3 for its operation, selected by setting
parameter StepForSOTF. The SOTF logic can be activated either from change in circuit breaker
position or from circuit breaker close command pulse. The setting parameter ActivationSOTF
can be set for activation of CB position open change, CB position closed change or CB close
command. In case of a residual current start from step 2 or 3 (dependent on setting) the function
will give a trip after a set delay tSOTF. This delay is normally set to a short time (default 100
ms).
The Under-Time logic always uses the start signal from the step 4. The Under-Time logic will
normally be set to operate for a lower current level than the SOTF function. The Under-Time
logic can also be blocked by the 2nd harmonic restraint feature. This enables high sensitivity
even if power transformer inrush currents can occur at breaker closing. This logic is typically
used to detect asymmetry of CB poles immediately after switching of the circuit breaker. The
Under-Time logic is activated either from change in circuit breaker position or from circuit
292
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
breaker close and open command pulses. This selection is done by setting parameter ActUnder-
Time. In case of a start from step 4 this logic will give a trip after a set delay tUnderTime. This
delay is normally set to a relatively short time (default 300 ms). Practically the Under-Time logic
acts as circuit breaker pole-discordance protection, but it is only active immediately after break-
er switching. The Under-Time logic can only be used in solidly or low impedance grounded sys-
tems.
293
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
294
activationSOTF
Setting
tpulse
SOTF
cbPosition posClsPls
Exec AND
PwrMode
tpulse
cbClosed
NOT SOTFActive
protection (PTOC, 51N/67N)
tpulse operationMode
Four step residual overcurrent
OR
AND
step4in AND
Setting TON
harmonic2ndRestraint AND IN Q AND
Exec NOT PT ET
cbSwitchingFaultDelayTime
Exec
en06000643.vsd
295
Chapter 6
Current protection
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Figure 149: Simplified logic diagram for SOTF and Under-Time features
EF Logic Diagram Simplified logic diagram for the complete EF function is shown in the fol-
lowing Figure 1:
signal to
communication
scheme
Directional Check
Element
DirMode
enableDir
harmRestrBlock
3I0 Harmonic
Restraint 1
Element
CB
DirMode pos
or cmd
enableDir
Mode
Selection enableStep1-4
DirectionalMode1-4
en06000376.vsd
296
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
TEF1-
EF4PTOC_51N67N
I3P TRIP
U3P TRIN1
I3PPOL TRIN2
BLOCK TRIN3
BLKTR TRIN4
BLKST1 TRSOTF
BLKST2 START
BLKST3 STIN1
BLKST4 STIN2
ENMULT1 STIN3
ENMULT2 STIN4
ENMULT3 STSOTF
ENMULT4 STFW
CBPOS STRV
CLOSECB 2NDHARMD
OPENCB
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Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Table 142: Output signals for the EF4PTOC_51N67N (TEF1-) function block
Signal Description
TRIP Trip
TRIN1 Trip signal from step 1
TRIN2 Trip signal from step 2
TRIN3 Trip signal from step 3
TRIN4 Trip signal from step 4
TRSOTF Trip signal from earth fault switch onto fault function
START General start signal
STIN1 Start signal step 1
STIN2 Start signal step 2
STIN3 Start signal step 3
STIN4 Start signal step 4
STSOTF Start signal from earth fault switch onto fault function
STFW Forward directional start signal
STRV Reverse directional start signal
2NDHARMD 2nd harmonic block signal
298
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
299
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
300
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
301
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
302
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
303
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
Table 144: Advanced parameter group settings for the EF4PTOC_51N67N (TEF1-) func-
tion
Parameter Range Step Default Unit Description
ActUnderTime CB position - CB position - Select signal to activate
CB command under time (CB
Pos/CBCommand)
tUnderTime 0.000 - 60.000 0.001 0.300 s Time delay for under time
ResetTypeCrv1 Instantaneous - Instantaneous - Reset curve type for step
IEC Reset 1
ANSI reset
tReset1 0.000 - 60.000 0.001 0.020 s Reset curve type for step
1
tPCrv1 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 1
tACrv1 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 1
tBCrv1 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 1
tCCrv1 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 1
tPRCrv1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 1
tTRCrv1 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 1
tCRCrv1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 1
ResetTypeCrv2 Instantaneous - Instantaneous - Reset curve type for step
IEC Reset 2
ANSI reset
tReset2 0.000 - 60.000 0.001 0.020 s Reset curve type for step
2
tPCrv2 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 2
tACrv2 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 2
tBCrv2 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 2
304
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
305
Four step residual overcurrent Chapter 6
protection (PTOC, 51N/67N) Current protection
306
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
5.1 Introduction
In networks with high impedance earthing, the phase to earth fault current is significantly small-
er than the short circuit currents. Another difficulty for earth fault protection is that the magni-
tude of the phase to earth fault current is almost independent of the fault location in the network.
Directional residual current can be used to detect and give selective trip of phase to earth faults
in high impedance earthed networks. The protection uses the residual current component
3I0 cos , where is the angle between the residual current and the residual voltage, compensat-
ed with a characteristic angle. Alternatively the function can be set to strict 3I0 level with an
check of angle 3I0 and cos .
Directional residual power can be used to detect and give selective trip of phase to earth faults
in high impedance earthed networks. The protection uses the residual power component
3I0 3U0 cos , where is the angle between the residual current and the reference residual volt-
age, compensated with a characteristic angle.
A normal undirectional residual current function can also be used and be with definite or inverse
time delay.
A back-up neutral point voltage function is also available for undirectional sensitive back-up
protection.
In an isolated network, i.e. the network is only coupled to earth via the capacitances between the
phase conductors and earth, the residual current always has -90 phase shift compared to the ref-
erence residual voltage. The characteristic angle is chosen to -90 in such a network.
In resistance earthed networks or in Petersen coil, with a parallel resistor, the active residual cur-
rent component (in phase with the residual voltage) should be used for the earth fault detection.
In such networks the characteristic angle is chosen to 0.
As the amplitude of the residual current is independent of the fault location the selectivity of the
earth fault protection is achieved by time selectivity.
When should the sensitive directional residual overcurrent protection be used and when should
the sensitive directional residual power protection be used? We have the following facts to con-
sider:
307
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
In some power systems a medium size neutral point resistor is used. Such a resis-
tor will give a resistive earth fault current component of about 200 - 400 A at a
zero resistive phase to earth fault. In such a system the directional residual power
protection gives better possibilities for selectivity enabled by inverse time power
characteristics.
The sensitive directional earth fault protection has the following sub-functions included:
3I0
= ang(3I0) - ang(3Uref)
-3U0=Uref
3I0 cos
en06000648.vsd
308
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Uref
RCA = -90, ROA = 90
3I0
3I0 cos
= ang(3I0) ang(Uref)
-3U0
en06000649.vsd
For trip, both the residual current 3I0 cos and the release voltage 3U0, shall be larger than the
set levels: INCosPhi> and UNRel>.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function is activated binary output signals START and STDIRIN are activated. If the
activation is active after the set delay tDef the binary output signals TRIP and TRDIRIN are ac-
tivated. The trip from this sub-function has definite time delay.
There is a possibility to increase the operate level for currents where the angle is larger than a
set value as shown in the figure below. This is equivalent to blocking of the function if
> ROADir. This option is used to handle angle error for the instrument transformers.
309
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
-3U0=Uref RCA = 0
3I0 cos
ROA
en06000650.vsd
The function will indicate forward/reverse direction to the fault. Reverse direction is defined as
3I0 cos ( + 180) the set value.
It shall also be possible to tilt the characteristic to compensate for current transformer angle error
with a setting RCAComp as shown in the figure below:
310
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Operate area
-3U0=Uref RCA = 0
Instrument
transformer
RCAcomp
angle error
Characteristic after
angle compensation
en06000651.vsd
For trip, both the residual power 3I0 3U0 cos , the residual current 3I0 and the release voltage
3U0, shall be larger than the set levels (SN>, INRel> and UNRel>).
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function is activated binary output signals START and STDIRIN are activated. If the
activation is active after the set delay tDef or after the inverse time delay (setting kSN) the binary
output signals TRIP and TRDIRIN are activated.
The function shall indicate forward/reverse direction to the fault. Reverse direction is defined as
3I0 3U0 cos ( + 180) 3 the set value.
This variant has the possibility of choice between definite time delay and inverse time delay.
311
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
RCA = 0
ROA = 80
Operate area
3I0
80 -3U0
en06000652.vsd
For trip, both the residual current 3I0 and the release voltage 3U0, shall be larger than the set
levels (INDir> and UNREL>) and the angle shall be in the set sector (ROADir and RCADir).
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function is activated binary output signals START and STDIRIN are activated. If the
activation is active after the set delay tDef the binary output signals TRIP and TRDIRIN are ac-
tivated.
The function indicate forward/reverse direction to the fault. Reverse direction is defined as is
within the angle sector: RCADir + 180 ROADir
312
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Directional functions
For all the directional functions there are directional start signals STFW: fault in the forward di-
rection, and STRV: start in the reverse direction. Even if the directional function is set to operate
for faults in the forward direction a fault in the reverse direction will give the start signal STRV.
Also if the directional function is set to operate for faults in the reverse direction a fault in the
forward direction will give the start signal STFW.
If available the non-directional function is using the calculated residual current, derived as sum
of the phase currents. This will give a better ability to detect cross-country faults with high re-
sidual current, also when dedicated core balance CT for the sensitive earth fault protection will
saturate.
This variant shall have the possibility of choice between definite time delay and inverse time de-
lay. The inverse time delay shall be according to IEC 60255-3.
For trip, the residual current 3I0 shall be larger than the set levels (INNonDir>).
Trip from this function can be blocked from the binary input BLKNDN.
When the function is activated binary output signal STNDIN is activated. If the activation is ac-
tive after the set delay tINNonDir or after the inverse time delay the binary output signals TRIP
and TRNDIN are activated.
There shall also be a separate trip, with its own definite time delay, from this set voltage level.
For trip, the residual voltage 3U0 shall be larger than the set levels (UN>).
Trip from this function can be blocked from the binary input BLKUN.
When the function is activated binary output signal STUN is activated. If the activation is active
after the set delay tUNNonDir TRIP and TRUN are activated. A simplified logical diagram of
the total function is shown in figure 157.
313
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
INNonDir> STNDIN
t TRNDIN
UN> STUN
t TRUN
OpMODE=INcosPhi
IN>
&
INcosPhi>
OpMODE=INUNcosPhi
INUNcosPhi> t
SN
& TRDIRIN
Phi in RCA +- ROA
TimeChar = InvTime
&
OpMODE=IN and Phi
&
TimeChar = DefTime
DirMode = Forw
& 1
Forw STFW
DirMode = Rev
&
Rev STRV
en06000653.vsd
Figure 157: Simplified logical diagram of the sensitive earth fault current protection
314
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
SDE1-
SDEPSDE_67N
I3P TRIP
U3P TRDIRIN
BLOCK TRNDIN
BLKTR TRUN
BLKTRDIR START
BLKNDN STDIRIN
BLKUN STNDIN
STUN
STFW
STRV
STDIR
UNREL
en07000032.vsd
Table 147: Basic general settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
IBase 1 - 99999 1 100 A Base Current, in A
UBase 0.05 - 2000.00 0.05 63.50 kV Base Voltage, in kV
Phase to Neutral
SBase 0.05 - 0.05 6350.00 kVA Base Power, in kVA.
200000000.00 IBase*UBase
315
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 148: Basic parameter group settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off/On
On
OpMode 3I0Cosfi - 3I0Cosfi - Selection of operation
3I03U0Cosfi mode for protection
3I0 and fi
DirMode Forward - Forward - Direction of operation for-
Reverse ward or reverse
RCADir -179 - 180 1 -90 Deg Relay characteristic
angle RCA, in deg
RCAComp -10.0 - 10.0 0.1 0.0 Deg Relay characteristic
angle compensation
ROADir 0 - 90 1 90 Deg Relay open angle ROA
used as release in phase
mode, in deg
INCosPhi> 0.25 - 200.00 0.01 1.00 %IB Set level for 3I0cosFi,
directional res over cur-
rent, in %Ib
SN> 0.25 - 200.00 0.01 10.00 %SB Set level for
3I03U0cosFi, starting inv
time count, in %Sb
INDir> 0.25 - 200.00 0.01 5.00 %IB Set level for directional
residual over current
prot, in %Ib
tDef 0.000 - 60.000 0.001 0.100 s Definite time delay direc-
tional residual overcur-
rent, in sec
SRef 0.03 - 200.00 0.01 10.00 %SB Reference value of res
power for inverse time
count, in %Sb
kSN 0.00 - 2.00 0.01 0.10 - Time multiplier setting for
directional residual power
mode
OpINNonDir> Off - Off - Operation of non-direc-
On tional residual overcur-
rent protection
INNonDir> 1.00 - 400.00 0.01 10.00 %IB Set level for non direc-
tional residual over cur-
rent, in %Ib
tINNonDir 0.000 - 60.000 0.001 1.000 s Time delay for non-direc-
tional residual over cur-
rent, in sec
316
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 149: Advanced general settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
RotResU 0 deg - 180 deg - Setting for rotating polar-
180 deg izing quantity if neces-
sary
317
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 150: Advanced parameter group settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
tReset 0.000 - 60.000 0.001 0.040 s Time delay used for reset
of definite timers, in sec
tPCrv 0.005 - 3.000 0.001 1.000 - Setting P for customer
programmable curve
tACrv 0.005 - 200.000 0.001 13.500 - Setting A for customer
programmable curve
tBCrv 0.00 - 20.00 0.01 0.00 - Setting B for customer
programmable curve
tCCrv 0.1 - 10.0 0.1 1.0 - Setting C for customer
programmable curve
ResetTypeCrv Immediate - IEC Reset - Reset mode when cur-
IEC Reset rent drops off.
ANSI reset
tPRCrv 0.005 - 3.000 0.001 0.500 - Setting PR for customer
programmable curve
tTRCrv 0.005 - 100.000 0.001 13.500 - Setting TR for customer
programmable curve
tCRCrv 0.1 - 10.0 0.1 1.0 - Setting CR for customer
programmable curve
318
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 152: Basic parameter group settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
OpMode 3I0Cosfi - 3I0Cosfi - Selection of operation
3I03U0Cosfi mode for protection
3I0 and fi
DirMode Forward - Forward - Direction of operation for-
Reverse ward or reverse
RCADir -179 - 180 1 -90 Deg Relay characteristic
angle RCA, in deg
RCAComp -10.0 - 10.0 0.1 0.0 Deg Relay characteristic
angle compensation
ROADir 0 - 90 1 90 Deg Relay open angle ROA
used as release in phase
mode, in deg
INCosPhi> 0.25 - 200.00 0.01 1.00 %IB Set level for 3I0cosFi,
directional res over cur-
rent, in %Ib
SN> 0.25 - 200.00 0.01 10.00 %SB Set level for
3I03U0cosFi, starting inv
time count, in %Sb
INDir> 0.25 - 200.00 0.01 5.00 %IB Set level for directional
residual over current
prot, in %Ib
tDef 0.000 - 60.000 0.001 0.100 s Definite time delay direc-
tional residual overcur-
rent, in sec
SRef 0.03 - 200.00 0.01 10.00 %SB Reference value of res
power for inverse time
count, in %Sb
kSN 0.00 - 2.00 0.01 0.10 - Time multiplier setting for
directional residual power
mode
OpINNonDir> Off - Off - Operation of non-direc-
On tional residual overcur-
rent protection
INNonDir> 1.00 - 400.00 0.01 10.00 %IB Set level for non direc-
tional residual over cur-
rent, in %Ib
tINNonDir 0.000 - 60.000 0.001 1.000 s Time delay for non-direc-
tional residual over cur-
rent, in sec
319
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 153: Advanced general settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
RotResU 0 deg - 180 deg - Setting for rotating polar-
180 deg izing quantity if neces-
sary
320
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
Table 154: Advanced parameter group settings for the SDEPSDE_67N (SDE1-) function
Parameter Range Step Default Unit Description
tReset 0.000 - 60.000 0.001 0.040 s Time delay used for reset
of definite timers, in sec
tPCrv 0.005 - 3.000 0.001 1.000 - Setting P for customer
programmable curve
tACrv 0.005 - 200.000 0.001 13.500 - Setting A for customer
programmable curve
tBCrv 0.00 - 20.00 0.01 0.00 - Setting B for customer
programmable curve
tCCrv 0.1 - 10.0 0.1 1.0 - Setting C for customer
programmable curve
ResetTypeCrv Immediate - IEC Reset - Reset mode when cur-
IEC Reset rent drops off.
ANSI reset
tPRCrv 0.005 - 3.000 0.001 0.500 - Setting PR for customer
programmable curve
tTRCrv 0.005 - 100.000 0.001 13.500 - Setting TR for customer
programmable curve
tCRCrv 0.1 - 10.0 0.1 1.0 - Setting CR for customer
programmable curve
321
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
322
Sensitive directional residual overcurrent and Chapter 6
power protection (PSDE, 67N) Current protection
323
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
6.1 Introduction
If the temperature of a power transformer/generator reaches too high values the equipment might
be damaged. The insulation within the transformer/generator will have forced ageing. As a con-
sequence of this the risk of internal phase to phase or phase to earth faults will increase. High
temperature will degrade the quality of the transformer/generator oil.
The thermal overload protection estimates the internal heat content of the transformer/generator
(temperature) continuously. This estimation is made by using a thermal model of the transform-
er/generator with two time constants, which is based on current measurement.
Two warning levels are available. This enables actions in the power system to be done before
dangerous temperatures are reached. If the temperature continues to increase to the trip value,
the protection initiates trip of the protected transformer/generator.
From the largest of the three phase currents a relative final temperature (heat content) is calcu-
lated according to the expression:
2
I
final =
I ref
(Equation 58)
where:
I is the largest phase current and
Iref is a given reference current
If this calculated relative temperature is larger than the relative temperature level corresponding
to the set operate (trip) current a start output signal START is activated.
324
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
If
final > n
t
n = n 1 + ( final n1 ) 1 e
(Equation 59)
If
final < n
t
n = final ( final n 1 ) e
(Equation 60)
where:
n is the calculated present temperature,
n-1 is the calculated temperature at the previous time step,
final is the calculated final (steady state) temperature with the actual current,
t is the time step between calculation of the actual temperature and
is the set thermal time constant for the protected transformer
The calculated transformer relative temperature can be monitored as it is exported from the func-
tion as a real figure HEATCONT.
When the transformer temperature reaches any of the set alarm levels Alarm1 or Alarm2 the cor-
responding output signal ALARM1 or ALARM2 is set. When the component temperature
reaches the set trip level which corresponds to continuous current equal to ITrip the output signal
TRIP is set.
There is also a calculation of the present time to operation with the present current. This calcu-
lation is only performed if the final temperature is calculated to be above the operation temper-
ature:
operate
toperate = ln final
final n
(Equation 61)
The calculated time to trip can be monitored as it is exported from the function as a real figure
TTRIP.
325
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
After a trip, caused by the thermal overload protection function, there can be a lockout to recon-
nect the tripped circuit. The output lockout signal LOCKOUT is activated when the device tem-
perature is above the set lockout release temperature setting ResLo.
The time to lockout release is calculated, i.e. a calculation of the cooling time to a set value.
lockout _ release
tlockout _ release = ln final
final n
(Equation 62)
Here the final temperature is equal to the set or measured ambient temperature. The calculated
component temperature can be monitored as it is exported from the function as a real figure.
When the current is so high that it has given a start signal START, the estimated time to trip is
continuously calculated and given as analogue output TTRIP. If this calculated time get less than
the setting time Warning, set in minutes, the output WARNING is activated.
326
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
I3P
Calculation
of final
temperature
ALARM1
Actual Temp >
Alarm1,Alarm2
ALARM2
Temp
S LOCKOUT
Binary input:
Forced cooling Management of R
On/Off setting
parameters: Tau,
Actual Temp
IBase Tau used
< Recl
Temp
time to trip
Calculation
of time to
warning if time to trip < set value
trip
Calculation
of time to time to reset of lockout
reset of
lockout
en05000833.vsd
327
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
TTR1-
TRPTTR_49
I3P TRIP
BLOCK START
COOLING ALARM1
ENMULT ALARM2
RESET LOCKOUT
WARNING
en06000272.vsd
Table 157: Output signals for the TRPTTR_49 (TTR1-) function block
Signal Description
TRIP Trip Signal
START Start signal
ALARM1 First level alarm signal
ALARM2 Second level alarm signal
LOCKOUT Lockout signal
WARNING Warning signal: Trip within set warning time
328
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
329
Thermal overload protection, two time Chapter 6
constants (PTTR, 49) Current protection
330
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
7.1 Introduction
The circuit breaker failure function ensures fast back-up tripping of surrounding breakers. The
breaker failure protection operation can be current based, contact based or adaptive combination
between these two principles.
A current check with extremely short reset time is used as a check criteria to achieve a high se-
curity against unnecessary operation.
The breaker failure protection can be single- or three-phase initiated to allow use with single
phase tripping applications. For the three-phase version of the breaker failure protection the cur-
rent criteria can be set to operate only if two out of four e.g. two phases or one phase plus the
residual current starts. This gives a higher security to the back-up trip command.
The function can be programmed to give a single- or three phase re-trip of the own breaker to
avoid unnecessary tripping of surrounding breakers at an incorrect initiation due to mistakes dur-
ing testing.
The start signal can be phase selective or general (for all three phases). Phase selective start sig-
nals enable single pole re-trip function. This means that a second attempt to open the breaker is
done. The re-trip attempt can be made after a set time delay. For transmission lines single pole
trip and autoreclosing is often used. The re-trip function can be phase selective if it is initiated
from phase selective line protection. The re-trip function can be done with or without current
check. With the current check the re-trip is only performed if the current through the circuit
breaker is larger than the operate current level.
The start signal can be an internal or external protection trip signal. If this start signal gets high
at the same time as current is detected through the circuit breaker, the back-up trip timer is start-
ed. If the opening of the breaker is successful this is detected by the function, both by detection
of low RMS current and by a special adapted algorithm. The special algorithm enables a very
fast detection of successful breaker opening, i.e. fast resetting of the current measurement. If the
current detection has not detected breaker opening before the back-up timer has run its time a
back-up trip is initiated. There is also a possibility to have a second back-up trip output activated
after an added settable time after the first back-up trip.
331
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
The minimum length of the re-trip pulse, the back-up trip pulse and the back-up
trip pulse 2 are settable. The re-trip pulse, the back-up trip pulse and the back-up
trip pulse 2 will however sustain as long as there is an indication of closed break-
er.
In the current detection it is possible to use three different options: 1 out of 3
where it is sufficient to detect failure to open (high current) in one pole, 1 out of
4 where it is sufficient to detect failure to open (high current) in one pole or high
residual current and 2 out of 4 where at least two current (phase current and/or
residual current) shall be high for breaker failure detection.
The current detection for the residual current can be set different from the setting
of phase current detection.
It is possible to have different re-trip time delays for single phase faults and for
multi-phase faults.
The back-up trip can be made without current check. It is possible to have this
option activated for small load currents only.
It is possible to have instantaneous back-up trip function if a signal is high if the
circuit breaker is insufficient to clear faults, for example at low gas pressure.
Current
AND
BLOCK
Current & t1 tp
STIL1
Contact t TRRETL1
AND AND
START
OR
STL1
OR
TRRET
OR
AND AND
CBCLDL1
Contact
L2 L3
en05000832.vsd
Figure 161: Simplified logic scheme of the retrip function
332
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
333
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Internal logical signals STIL1, STIL2, STIL3 have logical value 1 when current in respective
phase has magnitude larger than setting parameter IP>.
Internal logical signal STN has logical value 1 when neutral current has magnitude larger than
setting parameter IN>.
t2
1 of 4 t
OR
t3 tp
t TRBU2
2 of 3
AND
CBALARM
CBFLT CBALARM
t
en06000223.vsd
Figure 163: Simplified logic scheme of the back-up trip function
BFP1-
CCRBRF_50BF
I3P TRBU
BLOCK TRBU2
START TRRET
STL1 TRRETL1
STL2 TRRETL2
STL3 TRRETL3
CBCLDL1 CBALARM
CBCLDL2
CBCLDL3
CBFLT
en06000188.vsd
334
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Table 161: Output signals for the CCRBRF_50BF (BFP1-) function block
Signal Description
TRBU Back-up trip by breaker failure protection function
TRBU2 Second back-up trip by breaker failure protection function
TRRET Retrip by breaker failure protection function
TRRETL1 Retrip by breaker failure protection function phase L1
TRRETL2 Retrip by breaker failure protection function phase L2
TRRETL3 Retrip by breaker failure protection function phase L3
CBALARM Alarm for faulty circuit breaker
335
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Table 163: Advanced parameter group settings for the CCRBRF_50BF (BFP1-) function
Parameter Range Step Default Unit Description
I>BlkCont 5 - 200 1 20 %IB Current for blocking of
CB contact operation in
% of IBase
t3 0.000 - 60.000 0.001 0.030 s Additional time delay to
t2 for a second back-up
trip
tCBAlarm 0.000 - 60.000 0.001 5.000 s Time delay for CB faulty
signal
336
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
8.1 Introduction
Single pole operated circuit breakers can due to electrical or mechanical failures end up with the
different poles in different positions (close-open). This can cause negative and zero sequence
currents which gives thermal stress on rotating machines and can cause unwanted operation of
zero sequence or negative sequence current functions.
Normally the own breaker is tripped to correct the positions. If the situation consists the remote
end can be intertripped to clear the unsymmetrical load situation.
The pole discordance function operates based on information from auxiliary contacts of the cir-
cuit breaker for the three phases with additional criteria from unsymmetrical phase current when
required.
C.B.
en05000287.vsd
337
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
This single binary signal is connected to a binary input of the IED. The appearance of this signal
will start a timer that will give a trip signal after the set delay.
There is also a possibility to connect all phase selective auxiliary contacts (phase contact open
and phase contact closed) to binary inputs of the IED. This is shown in figure 166
C.B.
+
poleOneOpened from C.B.
en05000288.vsd
In this case the logic is realized within the function. If the inputs are indicating pole discordance
the trip timer is started. This timer will give a trip signal after the set delay.
Pole discordance can also be detected by means of phase selective current measurement. The
sampled analogue phase currents are pre-processed in a discrete Fourier filter (DFT) block.
From the fundamental frequency components of each phase current the RMS value of each
phase current is derived. These phase current values are fed to the PD (RPLD) function. The dif-
ference between the smallest and the largest phase current is derived. If this difference is larger
than a set ratio the trip timer is started. This timer will give a trip signal after the set delay. The
current based pole discordance function can be set to be active either continuously or only di-
rectly in connection to breaker open or close command.
The function also has a binary input that can be configured from the autoreclosing function, so
that the pole discordance function can be blocked during sequences with a single pole open if
single pole autoreclosing is used.
The simplified block diagram of the current and contact based pole discordance function is
shown in figure 167.
338
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
BLOCK
OR
BLKDBYAR
PolPosAuxCont
AND
POLE1OPN
POLE1CL
POLE2OPN
Discordance
POLE2CL
detection
POLE3OPN
POLE3CL t 150 ms
t TRIP
AND
OR
PD Signal from CB
AND
EXTPDIND
CLOSECMD t+200 ms
OR
OPENCMD
AND
Unsymmetry current
detection
en05000747.vsd
Figure 167: Simplified block diagram of pole discordance function - contact and current based
The terminal is in TEST mode (TEST-ACTIVE is high) and the function has
been blocked from the HMI (BlockPD=Yes)
The input signal BLOCK is high
The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discordance function. It can
be connected to a binary input of the terminal in order to receive a block command from external
devices or can be software connected to other internal functions of the terminal itself in order to
receive a block command from internal functions. Through OR gate it can be connected to both
binary inputs and internal function outputs.
The BLKDBYAR signal blocks the pole discordance operation when a single phase autoreclos-
ing cycle is in progress. It can be connected to the output signal AR01-1PT1 if the autoreclosing
function is integrated in the terminal; if the autoreclosing function is an external device, then
BLKDBYAR has to be connected to a binary input of the terminal and this binary input is con-
nected to a signalization 1phase autoreclosing in progress from the external autoreclosing de-
vice.
If the pole discordance function is enabled, then two different criteria will generate a trip signal
TRIP:
339
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
any phase current is lower than CurrUnsymLevel of the highest current in the re-
maining two phases
the highest phase current is greater than CurrRelLevelof the rated current
If these conditions are true, an unsymmetrical condition is detected and the internal signal INPS
is turned high. This detection is enabled to generate a trip after a set time delay t (0-60 s) if the
detection occurs in the next 200 ms after the circuit breaker has received a command to open trip
or close and if the unbalance persists. The 200 ms limitation is for avoiding unwanted operation
during unsymmetrical load conditions.
The pole discordance function is informed that a trip or close command has been given to the
circuit breaker through the inputs CLOSECMD (for closing command information) and
OPENCMD (for opening command information). These inputs can be connected to terminal bi-
nary inputs if the information are generated from the field (i.e. from auxiliary contacts of the
close and open push buttons) or may be software connected to the outputs of other integrated
functions (i.e. close command from a control function or a general trip from integrated protec-
tions).
PD01-
CCRPLD_52PD
I3P TRIP
BLOCK START
BLKDBYAR
CLOSECMD
OPENCMD
EXTPDIND
POLE1OPN
POLE1CL
POLE2OPN
POLE2CL
POLE3OPN
POLE3CL
en06000275.vsd
340
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
Table 166: Output signals for the CCRPLD_52PD (PD01-) function block
Signal Description
TRIP Trip signal to CB
START Trip condition TRUE, waiting for time delay
341
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
342
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
9.1 Introduction
The task of a generator in a power plant is to convert mechanical energy available as a torque on
a rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that it does not
cover bearing losses and ventilation losses. Then, the synchronous generator becomes a syn-
chronous motor and starts to take electric power from the rest of the power system. This operat-
ing state, where individual synchronous machines operate as motors, implies no risk for the
machine itself. If the generator under consideration is very large and if it consumes lots of elec-
tric power, it may be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous state. The task
of the reverse power protection is to protect the turbine and not to protect the generator itself.
Figure 169 illustrates the reverse power protection with underpower relay and with overpower
relay. The underpower relay gives a higher margin and should provide better dependability. On
the other hand, the risk for unwanted operation immediately after synchronization may be high-
er. One should set the underpower relay to trip if the active power from the generator is less than
about 2%. One should set the overpower relay to trip if the power flow from the network to the
generator is higher than 1% depending on the type of turbine.
Operate
Q Q
Operate
Line Line
Margin Margin
P P
en06000315.vsd
343
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
Chosen current
phasors P
P = POWRE
Q = POWIM
en06000438.vsd
The function will use voltage and current phasors calculated in the pre-processing blocks. The
apparent complex power is calculated according to chosen formula as shown in table 169.
344
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
Arone
S = U L1L 2 I L1* U L 2 L 3 I L 3*
PosSeq
S = 3 U PosSeq I PosSeq*
L1L2
S = U L1L 2 ( I L1* I L 2* )
L2L3
S = U L 2 L 3 ( I L 2* I L 3* )
L3L1
S = U L 3 L1 ( I L 3* I L1* )
L1
S = 3 U L1 I L1*
L2
S = 3 U L 2 I L 2*
L3
S = 3 U L 3 I L 3*
NegSeq
S = 3 U NegSeq I NegSeq *
The active and reactive power is available from the function and can be used for monitoring and
fault recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this
angle is 0 the active power component P is calculated. If this angle is 90 the reactive power
component Q is calculated.
The calculated power component is compared to the power pick up setting Power1(2). A start
signal START1(2) is activated if the calculated power component is smaller than the pick up val-
ue. After a set time delay TripDelay1(2) a trip TRIP1(2) signal is activated if the start signal is
still active. At activation of any of the two stages a common signal START will be activated. At
trip from any of the two stages also a common signal TRIP will be activated.
345
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis
of the stage1(2) is Hysteresis1(2) = abs (Power1(2) + drop-power1(2)). For generator low for-
ward power protection the power setting is very low, normally down to 0.02 pu of rated gener-
ator power. The hysteresis should therefore be set to a smaller value. The drop-power value of
stage1 can be calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) +
Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-power1(2) would
be too small. In such cases, the hysteresis1 greater than (0.5 * Power1(2)) is corrected to the min-
imal value.
If the measured power drops under the drop-power1(2) value the function will reset after a set
time DropDelay1(2). The reset means that the start signal will drop out ant that the timer of the
stage will reset.
S = k SOld + (1 k ) SCalculated
(Equation 63)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalcu- is the new calculated value in the present execution cycle
lated
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately
given out without any filtering (i.e. without any additional delay). When k is set to value bigger
than 0, the filtering is enabled. A typical value for k = 0.14.
346
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
Amplitude
% of Ir compensation
-10
IAmpComp5 Measured
IAmpComp30 current
IAmpComp100
5 30 100 % of Ir
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
-10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of Ir
-10
en05000652.vsd
The first current and voltage phase in the group signals will be used as reference and the ampli-
tude and angle compensation will be used for related input signals.
Analog outputs from the function can be used for service values or in the disturbance report. The
active power is provided as a MW value: P, or in percent of base power: PPERCENT. The re-
active power is provided as a Mvar value: Q, or in percent of base power: QPERCENT.
347
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
GUP1-
GUPPDUP_37
I3P TRIP
U3P TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
en07000027.vsd
Table 171: Output signals for the GUPPDUP_37 (GUP1-) function block
Signal Description
TRIP Common trip signal
TRIP1 Trip of stage 1
TRIP2 Trip of stage 2
START Common start
START1 Start of stage 1
START2 Start of stage 2
P Active Power in MW
PPERCENT Active power in % of SBASE
Q Reactive power in Mvar
QPERCENT Reactive power in % of SBASE
348
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
Table 173: Basic parameter group settings for the GUPPDUP_37 (GUP1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
OpMode1 Off - UnderPower - Operation mode 1
UnderPower
Power1 0.0 - 500.0 0.1 1.0 %SB Power setting for stage 1
in % of Sbase
Angle1 -180.0 - 180.0 0.1 0.0 Deg Angle for stage 1
TripDelay1 0.010 - 6000.000 0.001 1.000 s Trip delay for stage 1
DropDelay1 0.010 - 6000.000 0.001 0.060 s Drop delay for stage 1
OpMode2 Off - UnderPower - Operation mode 2
UnderPower
Power2 0.0 - 500.0 0.1 1.0 %SB Power setting for stage 2
in % of Sbase
Angle2 -180.0 - 180.0 0.1 0.0 Deg Angle for stage 2
TripDelay2 0.010 - 6000.000 0.001 1.000 s Trip delay for stage 2
DropDelay2 0.010 - 6000.000 0.001 0.060 s Drop delay for stage 2
349
Directional underpower protection (PDUP, 32) Chapter 6
Current protection
Table 174: Advanced parameter group settings for the GUPPDUP_37 (GUP1-) function
Parameter Range Step Default Unit Description
TD 0.00 - 0.99 0.01 0.00 - Low pass filter coefficient
for power measurement,
P and Q
Hysteresis1 0.2 - 5.0 0.1 0.5 pu Absolute hysteresis of
stage 1
Hysteresis2 0.2 - 5.0 0.1 0.5 pu Absolute hysteresis of
stage 2
IMagComp5 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 5% of In
IMagComp30 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 30% of In
IMagComp100 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 100% of
In
VMagComp5 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 5% of Vn
VMagComp30 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 30% of
Vn
VMagComp100 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 100% of
Vn
IAngComp5 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 5% of In
IAngComp30 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 30% of In
IAngComp100 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 100% of In
350
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
10.1 Introduction
The task of a generator in a power plant is to convert mechanical energy available as a torque on
a rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that it does not
cover bearing losses and ventilation losses. Then, the synchronous generator becomes a syn-
chronous motor and starts to take electric power from the rest of the power system. This operat-
ing state, where individual synchronous machines operate as motors, implies no risk for the
machine itself. If the generator under consideration is very large and if it consumes lots of elec-
tric power, it may be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous state. The task
of the reverse power protection is to protect the turbine and not to protect the generator itself.
Figure 173 illustrates the reverse power protection with underpower relay and with overpower
relay. The underpower relay gives a higher margin and should provide better dependability. On
the other hand, the risk for unwanted operation immediately after synchronization may be high-
er. One should set the underpower relay to trip if the active power from the generator is less than
about 2%. One should set the overpower relay to trip if the power flow from the network to the
generator is higher than 1%.
Operate
Q Q
Operate
Line Line
Margin Margin
P P
en06000315.vsd
Figure 173: Reverse power protection with underpower relay and overpower relay
351
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
Chosen current
phasors P
P = POWRE
Q = POWIM
en06000567.vsd
The function will use voltage and current phasors calculated in the pre-processing blocks. The
apparent complex power is calculated according to chosen formula as shown in table 176.
352
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
Arone
S = U L1L 2 I L1* U L 2 L 3 I L 3*
PosSeq
S = 3 U PosSeq I PosSeq*
L1L2
S = U L1L 2 ( I L1* I L 2* )
L2L3
S = U L 2 L 3 ( I L 2* I L 3* )
L3L1
S = U L 3 L1 ( I L 3* I L1* )
L1
S = 3 U L1 I L1*
L2
S = 3 U L 2 I L 2*
L3
S = 3 U L 3 I L 3*
The active and reactive power is available from the function and can be used for monitoring and
fault recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this
angle is 0 the active power component P is calculated. If this angle is 90 the reactive power
component Q is calculated.
The calculated power component is compared to the power pick up setting Power1(2). A start
signal START1(2) is activated if the calculated power component is larger than the pick up val-
ue. After a set time delay TripDelay1(2) a trip TRIP1(2) signal is activated if the start signal is
still active. At activation of any of the two stages a common signal START will be activated. At
trip from any of the two stages also a common signal TRIP will be activated.
To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis
of the stage1(2) is Hysteresis1(2) = abs (Power1(2) drop-power1(2)). For generator reverse
power protection the power setting is very low, normally down to 0.02 pu of rated generator
353
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
power. The hysteresis should therefore be set to a smaller value. The drop-power value of stage1
can be calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2)
Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-power1(2) would
be too small. In such cases, the hysteresis1 greater than (0.5 * Power1(2)) is corrected to the min-
imal value.
If the measured power drops under the drop-power1(2) value the function will reset after a set
time DropDelay1(2). The reset means that the start signal will drop out ant that the timer of the
stage will reset.
S = k SOld + (1 k ) SCalculated
(Equation 64)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalcu- is the new calculated value in the present execution cycle
lated
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately
given out without any filtering (i.e. without any additional delay). When k is set to value bigger
than 0, the filtering is enabled. A typical value for k = 0.14.
354
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
Amplitude
% of Ir compensation
-10
IAmpComp5 Measured
IAmpComp30 current
IAmpComp100
5 30 100 % of Ir
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
-10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of Ir
-10
en05000652.vsd
The first current and voltage phase in the group signals will be used as reference and the ampli-
tude and angle compensation will be used for related input signals.
Analog outputs from the function can be used for service values or in the disturbance report. The
active power is provided as a MW value: P, or in percent of base power: PPERCENT. The re-
active power is provided as a Mvar value: Q, or in percent of base power: QPERCENT.
355
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
GOP1-
GOPPDOP_32
I3P TRIP
U3P TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
en07000028.vsd
Table 178: Output signals for the GOPPDOP_32 (GOP1-) function block
Signal Description
TRIP Common trip signal
TRIP1 Trip of stage 1
TRIP2 Trip of stage 2
START Common start
START1 Start of stage 1
START2 Start of stage 2
P Active Power in MW
PPERCENT Active power in % of SBASE
Q Reactive power in Mvar
QPERCENT Reactive power in % of SBASE
356
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
Table 180: Basic parameter group settings for the GOPPDOP_32 (GOP1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
OpMode1 Off - OverPower - Operation mode 1
OverPower
Power1 0.0 - 500.0 0.1 120.0 %SB Power setting for stage 1
in % of Sbase
Angle1 -180.0 - 180.0 0.1 0.0 Deg Angle for stage 1
TripDelay1 0.010 - 6000.000 0.001 1.000 s Trip delay for stage 1
DropDelay1 0.010 - 6000.000 0.001 0.060 s Drop delay for stage 1
OpMode2 Off - OverPower - Operation mode 2
OverPower
Power2 0.0 - 500.0 0.1 120.0 %SB Power setting for stage 2
in % of Sbase
Angle2 -180.0 - 180.0 0.1 0.0 Deg Angle for stage 2
TripDelay2 0.010 - 6000.000 0.001 1.000 s Trip delay for stage 2
DropDelay2 0.010 - 6000.000 0.001 0.060 s Drop delay for stage 2
357
Directional overpower protection (PDOP, 32) Chapter 6
Current protection
Table 181: Advanced parameter group settings for the GOPPDOP_32 (GOP1-) function
Parameter Range Step Default Unit Description
k 0.00 - 0.99 0.01 0.00 - Low pass filter coefficient
for power measurement,
P and Q
Hysteresis1 0.2 - 5.0 0.1 0.5 pu Absolute hysteresis of
stage 1 in % of Sbase
Hysteresis2 0.2 - 5.0 0.1 0.5 pu Absolute hysteresis of
stage 2 in % of Sbase
IMagComp5 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 5% of In
IMagComp30 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 30% of In
IMagComp100 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate current at 100% of
In
VMagComp5 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 5% of Vn
VMagComp30 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 30% of
Vn
VMagComp100 -10.000 - 10.000 0.001 0.000 % Magnitude factor to cali-
brate voltage at 100% of
Vn
IAngComp5 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 5% of In
IAngComp30 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 30% of In
IAngComp100 -10.000 - 10.000 0.001 0.000 Deg Angle calibration for cur-
rent at 100% of In
358
Broken conductor check (PTOC, 46) Chapter 6
Current protection
11.1 Introduction
Conventional protection functions can not detect the broken conductor condition. The broken
conductor monitoring function (BRC), consisting of continuous current unsymmetry check on
the line where the terminal is connected will give alarm or trip at detecting broken conductors.
The difference in currents between the phase with the lowest current and the
phase with the highest current is greater than set percentage Iub> of the highest
phase current
The highest phase current is greater than the minimum setting value IP>.
The lowest phase current is below 50% of the minimum setting value IP>
The third condition is included to avoid problems in systems involving parallel lines. If a con-
ductor breaks in one phase on one line the parallel line will experience an increase in current in
the same phase. This might result in the first two conditions being satisfied. If the unsymmetrical
detection lasts for a period longer than the set time tOper the TRIP output is activated.
The simplified logic diagram of the broken conductor check function is shown in figure 177
The IED is in TEST status and the function has been blocked from the HMI test
menu (BlockBRC=Yes).
The input signal BLOCK is high.
The BLOCK input can be connected to a binary input of the terminal in order to receive a block
command from external devices or can be software connected to other internal functions of the
terminal itself in order to receive a block command from internal functions.
The output trip signal TRIP is a three phase trip. It can be used to command a trip to the circuit
breaker or for alarm purpose only.
359
Broken conductor check (PTOC, 46) Chapter 6
Current protection
TEST
TEST-ACTIVE
&
BlockBRC = Yes
BRC--START
Function Enable
BRC--BLOCK >1
t
BRC--TRIP
& t
Unsymmetrical
Current Detection
STI
IL1<50%IP>
IL2<50%IP> 1
IL3<50%IP>
en07000122.vsd
Figure 177: Simplified logic diagram for broken conductor check function.
BRC1-
BRCPTOC_46
I3P TRIP
BLOCK START
BLKTR
en07000034.vsd
360
Broken conductor check (PTOC, 46) Chapter 6
Current protection
Table 184: Output signals for the BRCPTOC_46 (BRC1-) function block
Signal Description
TRIP Operate signal of the protection logic
START Start signal of the protection logic
Table 186: Advanced parameter group settings for the BRCPTOC_46 (BRC1-) function
Parameter Range Step Default Unit Description
tReset 0.010 - 60.000 0.001 0.100 s Time delay in reset
361
Broken conductor check (PTOC, 46) Chapter 6
Current protection
362
About this chapter Chapter 7
Voltage protection
363
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
1.1 Introduction
Undervoltages can occur in the power system during faults or abnormal conditions. The function
can be used to open circuit breakers to prepare for system restoration at power outages or as
long-time delayed back-up to primary protection.
The function has two voltage steps, each with inverse or definite time delay.
The undervoltage protection function can be set to measure phase to earth fundamental value,
phase to phase fundamental value, phase to earth RMS value or phase to phase RMS value. The
choise of the measuring is done by the parameter ConnType in PST or LHMI under Generall
Settings/Voltage protection. The voltage related settings are made in percent of base voltage
which is set i kV phase-phase voltage This means operation for phase to earth voltage under:
364
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
To avoid oscillations of the output start signal, a hysteresis has been included.
k
t=
U < U
U<
(Equation 67)
k 480
t= + 0.055
U < U
2.0
32 0.5
U<
(Equation 68)
kA +D
t=
U < U
p
B C
U<
(Equation 69)
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U< down to U< *(1.0 CrvSatn/100) the used volt-
age will be: U< *(1.0 CrvSatn/100). If the programmable curve is used this parameter must be
calculated so that:
365
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
CrvSatn
B C > 0
100
(Equation 70)
The lowest voltage is always used for the inverse time delay integration. The details of the dif-
ferent inverse time characteristics are shown in section 3 "Inverse characteristics".
Trip signal issuing requires that the undervoltage condition continues for at least the user set
time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by
some special voltage level dependent time curves for the inverse time mode (IDMT). If the start
condition, with respect to the measured voltage ceases during the delay time, and is not fulfilled
again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2pickup for the inverse time) the corresponding start output is reset. Here it should be not-
ed that after leaving the hysteresis area, the start condition must be fulfilled again and it is not
sufficient for the signal to only return back to the hysteresis area. Note that for the undervoltage
function the IDMT reset time is constant and does not depend on the voltage fluctuations during
the drop-off period. However, there are three ways to reset the timer, either the timer is reset in-
stantaneously, or the timer value is frozen during the reset time, or the timer value is linearly
decreased during the reset time. See figure 179 and figure 180.
366
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
tReset
tReset 1
Voltage 1 Measured
START Voltage
Hysteresis
TRIP
U1<
Time
START t1
TRIP
Time
Integrator Froozen Timer
t1
Time
Instantaneous
Linear Decrease
Reset en05000010.vsd
Figure 179: Voltage profile not causing a reset of the start signal for step 1, and definite time
delay
367
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
tReset1
Voltage
tReset1
START
START
Hysteresis Measured Voltage
TRIP
U1<
Time
START t1
TRIP
Time Integrator
Froozen Timer
t1
Time
Instantaneous
Linear Decrease
Reset en05000011.vsd
Figure 180: Voltage profile causing a reset of the start signal for step 1, and definite time delay
1.2.3 Blocking
The undervoltage function can be partially or totally blocked, by binary input signals or by pa-
rameter settings, where:
368
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
If the measured voltage level decreases below the setting of IntBlkStVal1, either the trip output
of step 1, or both the trip and the start outputs of step 1, are blocked. The characteristic of the
blocking is set by the IntBlkSel1 parameter. This internal blocking can also be set to "off" result-
ing in no voltage based blocking. Corresponding settings and functionality are valid also for step
2.
In case of disconnection of the high voltage component the measured voltage will get very low.
The event will start both the under voltage function and the blocking function, as seen in figure
181. The delay of the blocking function must be set less than the time delay of under voltage
function.
369
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
U Disconnection
Normal voltage
U1<
U2<
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466.vsd
Figure 181: Blocking function.
1.2.4 Design
The voltage measuring elements continuously measure the three phase-to-neutral voltages or the
three phase to phase voltages. Recursive Fourier filters or RMS filters based on one fundamental
cycle filter the input voltage signals. The voltages are individually compared to the set value,
and the lowest voltage is used for the inverse time characteristic integration. A special logic is
included to achieve the "1 out of 3", "2 out of 3" and "3 out of 3" criteria to fulfill the start con-
dition. The design of the TimeUnderVoltage function is schematically described in figure 182.
370
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
Step 1
Time integrator TR1L2
MinVoltSelect t1 TRIP
or tReset1
ResetTypeCrv1 TR1L3
TR1
OR
Comparator ST2L1
UL1 < U2< Phase 1
Voltage Phase
Selector ST2L2
Comparator OpMode2 Phase 2
UL2 < U2< 1 out of 3
2 outof 3 ST2L3
Phase 3 Start
Comparator 3 out of 3
&
UL3 < U2< Trip ST2
Output OR
Step 2
Time integrator TR2L2
MinVoltSelect t2 TRIP
or tReset2
ResetTypeCrv2 TR2L3
TR2
OR
OR START
TRIP
OR
en05000012.vsd
371
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
TUV1-
UV2PTUV_27
U3P TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
en06000276.vsd
Table 189: Output signals for the UV2PTUV_27 (TUV1-) function block
Signal Description
TRIP Trip
TR1 Common trip signal from step1
TR1L1 Trip signal from step1 phase L1
TR1L2 Trip signal from step1 phase L2
TR1L3 Trip signal from step1 phase L3
TR2 Common trip signal from step2
TR2L1 Trip signal from step2 phase L1
TR2L2 Trip signal from step2 phase L2
TR2L3 Trip signal from step2 phase L3
START General start signal
372
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
Signal Description
ST1 Common start signal from step1
ST1L1 Start signal from step1 phase L1
ST1L2 Start signal from step1 phase L2
ST1L3 Start signal from step1 phase L3
ST2 Common start signal from step2
ST2L1 Start signal from step2 phase L1
ST2L2 Start signal from step2 phase L2
ST2L3 Start signal from step2 phase L3
Table 191: Basic parameter group settings for the UV2PTUV_27 (TUV1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
OperationStep1 Off - On - Enable execution of step
On 1
Characterist1 Definite time - Definite time - Selection of time delay
Inverse curve A curve type for step 1
Inverse curve B
Prog. inv. curve
OpMode1 1 out of 3 - 1 out of 3 - Number of phases
2 out of 3 required for op (1 of 3, 2
3 out of 3 of 3, 3 of 3) from step 1
373
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
Table 192: Advanced parameter group settings for the UV2PTUV_27 (TUV1-) function
374
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
375
Two step undervoltage protection (PTUV, 27) Chapter 7
Voltage protection
376
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
2.1 Introduction
Overvoltages will occur in the power system during abnormal conditions such as sudden power
loss, tap changer regulating failures, open line ends on long lines.
The function can be used as open line end detector, normally then combined with directional re-
active over-power function or as system voltage supervision, normally then giving alarm only
or switching in reactors or switch out capacitor banks to control the voltage.
The function has two voltage steps, each of them with inverse or definite time delayed.
The overvoltage function has an extremely high reset ratio to allow setting close to system ser-
vice voltage.
The voltage related settings are made in percent of the base voltage, which is set in kV,
phase-phase.
The overvoltage protection function can be set to measure phase to earth fundamental value,
phase to phase fundamental value, phase to earth RMS value or phase to phase RMS value. The
choise of measuring is done by the parameter ConnType in PST or LHMI under Generall Set-
tings/Voltage protection. The setting of the analog inputs are given as primary phase to phase
voltage and secondary phase to phase voltage. The function will operate if the voltage gets high-
er than the set percentage of the set base voltage UBase. This means operation for phase to earth
voltage over:
377
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
To avoid oscillations of the output start signal, a hysteresis has been included.
TD
t=
V Vpickup
Vpickup
(Equation 73)
k 480
t=
U U >
2.0
32 0.5 0.035
U>
(Equation 74)
378
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
k 480
t=
U U >
3.0
32 0.5 0.035
U>
TD 480
t= 3.0
V Vpickup
32 Vpickup 0.5 0.035
(Equation 75)
kA
t= +D
U U >
p
B C
U >
(Equation 76)
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U< down to U< *(1.0 CrvSatn/100) the used volt-
age will be: U< *(1.0 CrvSatn/100). If the programmable curve is used this parameter must be
calculated so that:
CrvSatn
B C > 0
100
(Equation 77)
The highest phase (or phase to phase) voltage is always used for the inverse time delay integra-
tion, see figure 184. The details of the different inverse time characteristics are shown in section
3 "Inverse characteristics".
379
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
Voltage
IDMT Voltage
UL1
UL2
UL3
Time
en05000016.vsd
Figure 184: Voltage used for the inverse time characteristic integration
Trip signal issuing requires that the overvoltage condition continues for at least the user set time
delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by se-
lected voltage level dependent time curves for the inverse time mode (IDMT). If the start con-
dition, with respect to the measured voltage ceases during the delay time, and is not fulfilled
again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2 for the inverse time) the corresponding start output is reset, after that the defined reset
time has elapsed. Here it should be noted that after leaving the hysteresis area, the start condition
must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis
area. The hysteresis value for each step is settable (HystAbs2) to allow an high and accurate reset
of the function. It is also remarkable that for the overvoltage function the IDMT reset time is
constant and does not depend on the voltage fluctuations during the drop-off period. However,
there are three ways to reset the timer, either the timer is reset instantaneously, or the timer value
is frozen during the reset time, or the timer value is linearly decreased during the reset time..
2.2.3 Blocking
The overvoltage function can be partially or totally blocked, by binary input signals where:
380
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
2.2.4 Design
The voltage measuring elements continuously measure the three phase-to-earth voltages or the
three phase to phasel voltages. Recursive Fourier filters filter the input voltage signals. The
phase voltages are individually compared to the set value, and the highest voltage is used for the
inverse time characteristic integration. A special logic is included to achieve the "1 out of 3", "2
out of 3" and "3 out of 3" criteria to fulfill the start condition. The design of the TimeOverVolt-
age function is schematically described in figure 185.
381
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
OR TR1
Comparator ST2L1
UL1 > U2> Phase 1
Voltage Phase
Selector ST2L2
Comparator OpMode2 Phase 2
UL2 > U2> 1 out of 3
2 outof 3 ST2L3
Phase 3 Start
3 out of 3
Comparator &
UL3 > U2> Trip ST2
OR
Output
START Logic TR2L1
Step 2
Time integrator TR2L2
MaxVoltSelect t2 TRIP
or tReset2
ResetTypeCrv2 TR2L3
TR2
OR
START
OR
TRIP
OR
en05000013.vsd
382
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
TOV1-
OV2PTOV_59
U3P TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
en06000277.vsd
Table 195: Output signals for the OV2PTOV_59 (TOV1-) function block
Signal Description
TRIP Trip
TR1 Common trip signal from step1
TR1L1 Trip signal from step1 phase L1
TR1L2 Trip signal from step1 phase L2
TR1L3 Trip signal from step1 phase L3
TR2 Common trip signal from step2
TR2L1 Trip signal from step2 phase L1
TR2L2 Trip signal from step2 phase L2
TR2L3 Trip signal from step2 phase L3
383
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
Signal Description
START General start signal
ST1 Common start signal from step1
ST1L1 Start signal from step1 phase L1
ST1L2 Start signal from step1 phase L2
ST1L3 Start signal from step1 phase L3
ST2 Common start signal from step2
ST2L1 Start signal from step2 phase L1
ST2L2 Start signal from step2 phase L2
ST2L3 Start signal from step2 phase L3
Table 197: Basic parameter group settings for the OV2PTOV_59 (TOV1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
OperationStep1 Off - On - Enable execution of step
On 1
Characterist1 Definite time - Definite time - Selection of time delay
Inverse curve A curve type for step 1
Inverse curve B
Inverse curve C
Prog. inv. curve
OpMode1 1 out of 3 - 1 out of 3 - Number of phases
2 out of 3 required for op (1 of 3, 2
3 out of 3 of 3, 3 of 3) from step 1
384
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
Table 198: Advanced parameter group settings for the OV2PTOV_59 (TOV1-) function
Parameter Range Step Default Unit Description
tReset1 0.000 - 60.000 0.001 0.025 s Reset time delay used in
IEC Definite Time curve
step 1
ResetTypeCrv1 Instantaneous - Instantaneous - Selection of reset curve
Frozen timer type for step 1
Linearly decreased
tIReset1 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 1
ACrv1 0.005 - 200.000 0.001 1.000 - Parameter A for cus-
tomer programmable
curve for step 1
BCrv1 0.50 - 100.00 0.01 1.00 - Parameter B for cus-
tomer programmable
curve for step 1
385
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
386
Two step overvoltage protection (PTOV, 59) Chapter 7
Voltage protection
387
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
3.1 Introduction
Residual voltages will occur in the power system during earth faults.
The function can be configured to calculate the residual voltage from the three phase voltage in-
put transformers or from a single phase voltage input transformer fed from an open delta or neu-
tral point voltage transformer.
The function has two voltage steps, each with inverse or definite time delayed.
The voltage related settings are made in percent of the base voltage, which is set in kV,
phase-phase.
To avoid oscillations of the output start signal, a hysteresis has been included.
388
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
TD
t=
V Vpickup
Vpickup
(Equation 78)
k 480
t=
U U >
2.0
32 0.5 0.035
U>
(Equation 79)
k 480
t=
U U >
3.0
32 0.5 0.035
U>
(Equation 80)
kA
t= +D
U U >
p
B C
U>
TD A
t= +D
V Vpickup
P
B C
Vpickup
(Equation 81)
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U> up to U> *(1.0 + CrvSatn/100) the used voltage
will be: U> *(1.0 + CrvSatn/100). If the programmable curve is used this parameter must be cal-
culated so that:
389
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
CrvSatn
B C > 0
100
(Equation 82)
The details of the different inverse time characteristics are shown in chapter 3 "Inverse charac-
teristics".
Trip signal issuing requires that the residual overvoltage condition continues for at least the user
set time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and
by some special voltage level dependent time curves for the inverse time mode (IDMT). If the
start condition, with respect to the measured voltage ceases during the delay time, and is not ful-
filled again within a user defined reset time (tReset1 and tReset2 for the definite time and
tIReset1 and tIReset2 for the inverse time) the corresponding start output is reset, after that the
defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the
start condition must be fulfilled again and it is not sufficient for the signal to only return back to
the hysteresis area. It is also remarkable that for the overvoltage function the IDMT reset time
is constant and does not depend on the voltage fluctuations during the drop-off period. However,
there are three ways to reset the timer, either the timer is reset instantaneously, or the timer value
is frozen during the reset time, or the timer value is linearly decreased during the reset time. See
figure 187 and figure 188.
390
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
tReset
1
tReset1
Voltage
START
TRIP
U1>
Hysteresis
Measured
Voltage
Time
START t1
TRIP
Time
Integrator Linear Decrease
Froozen Timer
t1
Instantaneous Time
Reset en05000019.vsd
Figure 187: Voltage profile not causing a reset of the start signal for step 1, and definite time
delay
391
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
tReset1
Voltage tReset1
START TRIP
START
Hysteresis
U1>
Measured Voltage
Time
START t1
TRIP
Time Integrator
Froozen Timer
t1
Time
Instantaneous
Linear Decrease en05000020.vsd
Reset
Figure 188: Voltage profile causing a reset of the start signal for step 1, and definite time delay
3.2.3 Blocking
The residual overvoltage function can be partially or totally blocked, by binary input signals
where:
392
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
3.2.4 Design
The voltage measuring elements continuously measure the residual voltage. Recursive Fourier
filters filter the input voltage signal. The single input voltage is compared to the set value, and
is also used for the inverse time characteristic integration. The design of the TRV function is
schematically described in figure 189.
ST2
Comparator Phase 1
UN > U2> TR2
Start
START &
Trip START
Output OR
Time integrator
Logic
t2 TRIP
tReset2
Step 2
ResetTypeCrv2 TRIP
OR
en05000748.vsd
393
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
TRV1-
ROV2PTOV_59N
U3P TRIP
BLOCK TR1
BLKTR1 TR2
BLKST1 START
BLKTR2 ST1
BLKST2 ST2
en06000278.vsd
Table 201: Output signals for the ROV2PTOV_59N (TRV1-) function block
Signal Description
TRIP Trip
TR1 Common trip signal from step1
TR2 Common trip signal from step2
START General start signal
ST1 Common start signal from step1
ST2 Common start signal from step2
394
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
395
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
Table 203: Advanced parameter group settings for the ROV2PTOV_59N (TRV1-) function
Parameter Range Step Default Unit Description
tReset1 0.000 - 60.000 0.001 0.025 s Reset time delay used in
IEC Definite Time curve
step 1
ResetTypeCrv1 Instantaneous - Instantaneous - Selection of reset curve
Frozen timer type for step 1
Linearly decreased
tIReset1 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 1
ACrv1 0.005 - 200.000 0.001 1.000 - Parameter A for cus-
tomer programmable
curve for step 1
BCrv1 0.50 - 100.00 0.01 1.00 - Parameter B for cus-
tomer programmable
curve for step 1
CCrv1 0.0 - 1.0 0.1 0.0 - Parameter C for cus-
tomer programmable
curve for step 1
DCrv1 0.000 - 60.000 0.001 0.000 - Parameter D for cus-
tomer programmable
curve for step 1
PCrv1 0.000 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 1
CrvSat1 0 - 100 1 0 % Tuning param for prog.
over voltage IDMT curve,
step 1
tReset2 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 2
ResetTypeCrv2 Instantaneous - Instantaneous - Selection of reset curve
Frozen timer type for step 2
Linearly decreased
tIReset2 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 2
ACrv2 0.005 - 200.000 0.001 1.000 - Parameter A for cus-
tomer programmable
curve for step 2
396
Two step residual overvoltage Chapter 7
protection (PTOV, 59N) Voltage protection
397
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
4.1 Introduction
When the laminated core of a power transformer or generator is subjected to a magnetic flux
density beyond its design limits, stray flux will flow into non-laminated components not de-
signed to carry flux and cause eddy currents to flow. The eddy currents can cause excessive heat-
ing and severe damage to insulation and adjacent parts in a relatively short time. Function has
settable inverse operating curve and independent alarm stage.
Modern design transformers are more sensitive to overexcitation than earlier types. This is a re-
sult of the more efficient designs and designs which rely on the improvement in the uniformity
of the excitation level of modern systems. Thus, if emergency that includes overexcitation does
occur, transformers may be damaged unless corrective action is promptly taken. Transformer
manufacturers recommend an overexcitation protection as a part of the transformer protection
system.
Overexcitation results from excessive applied voltage, possibly in combination with below-nor-
mal frequency. Such condition may occur when a unit is on load, but are more likely to arise
when it is on open circuit, or at a loss of load occurrence. Transformers directly connected to
generators are in particular danger to experience overexcitation condition. It follows from the
fundamental transformer equation, see equation 83, that peak flux density Bmax is directly pro-
portional to induced voltage E, and inversely proportional to frequency f, and turns n.
E = 4.44 f n B max A
(Equation 83)
Ef
M = relative ------- = ------------------------
V
Hz ( Ur ) ( fr )
(Equation 84)
398
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Disproportional variations in quantities E and f may give rise to core overfluxing. If the core flux
density Bmax increases to a point above saturation level (typically 1.9 Tesla), the flux will no
longer be contained within the core only but will extend into other (non-laminated) parts of the
power transformer and give rise to Eddy current circulations. Overexcitation will result in:
Protection against overexcitation is based on calculation of the relative Volts per Hertz (V / Hz)
ratio. The action of the protection is usually to initiate a reduction of excitation and, if this should
fail, or is not possible, to trip the transformer after a delay which can be from seconds to minutes,
typically 5 - 10 seconds.
The IEC 60076 - 1 standard requires that transformers shall be capable of operating continuously
at 10% above rated voltage at no load, and rated frequency. At no load, the ratio of the actual
generator terminal voltage to the actual frequency should not exceed 1.1 times the ratio of trans-
former rated voltage to the rated frequency on a sustained basis, see equation 85.
E
---- 1.1 Ur
------
f fr
(Equation 85)
E V/Hz>
---- ---------------------
f fr
(Equation 86)
where:
V/Hz> is the maximum continuously allowed voltage at no load, and rated frequency.
V/Hz> is an OEX setting parameter. The setting range is 100% to 150%. If the user does not
know exactly what to set, then the standard IEC 60076 - 1, section 4.4, the default value V/Hz>
= 1.10 pu shall be used.
In OEX protection function the relative excitation M (relative V/Hz) is expressed according to
equation 87.
399
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Ef
M = relative ------- = --------------
V
Hz Ur fr
(Equation 87)
It is clear from the above formula that, for an unloaded power transformer, M = 1 for any E and
f, where the ratio E / f is equal to Ur / fr. A power transformer is not overexcited as long as the
relative excitation is M V/Hz>, V/Hz> expressed in %. The relative overexcitation is thus de-
fined as shown in equation 88.
overexcitation = M V/Hz>
(Equation 88)
The overexcitation protection algorithm is fed with an input voltage U which is in general not
the induced voltage E from the fundamental transformer equation. For no load condition, these
two voltages are the same, but for a loaded power transformer the internally induced voltage E
may be lower or higher than the voltage U which is measured and fed to OEX, depending on the
direction of the power flow through the power transformer, the power transformer side where
OEX is applied, and the power transformer leakage reactance of the winding. It is important to
specify on the OEX function block in CAP 531 configuration tool worksheet on which side of
the power transformer OEX is placed
As an example, at a transformer with a 15% short circuit impedance Xsc, the full load, 0.8 power
factor, 105% voltage on the load side, the actual flux level in the transformer core, will not be
significantly different from that at the 110% voltage, no load, rated frequency, provided that the
short circuit impedance X can be equally divided between the primary and the secondary wind-
ing: Xleak = Xleak1 = Xleak2 = Xsc / 2 = 0.075 pu..
OEX calculates the internal induced voltage E if Xleak (meaning the leakage reactance of the
winding where OEX is connected) is known to the user. The assumption taken for 2-winding
power transformers that Xleak = Xsc / 2 is unfortunately most often not true. For a 2-winding
power transformer the leakage reactances of the two windings depend on how the windings are
located on the core with respect to each other. In the case of three-winding power transformers
the situation is still more complex. If a user has the knowledge on the leakage reactance, then it
should applied. If a user has no idea about it, Xleak can be set to Xc/2. The OEX protection will
then take the given measured terminal voltage U, as the induced voltage E.
400
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Note!
It is extremely important that MeasuredU and MeasuredI is set to same value!
If, for example, voltage Uab is fed to OEX, then currents Ia, and Ib must be applied, etc. From
these two input currents, current Iab = Ia - Ib is calculated internally by the OEX protection al-
gorithm. The phase-to-phase voltage must be higher than 70% of the rated value, otherwise the
OEX protection algorithm is exited without calculating the excitation. ERROR output is set to
1, and the displayed value of relative excitation V / Hz shows 0.000.
If three phase-to-earth voltages are available from the side where OEX is connected, then OEX
protection function block shall be set to measure positive sequence voltage. In this case the pos-
itive sequence voltage and the positive sequence current are used by OEX protection. A check
is made within OEX protection if the positive sequence voltage is higher than 70% rated
phase-to-earth voltage; below this value, OEX is exited immediately, and no excitation is calcu-
lated. ERROR output is set to 1, and the displayed value of relative excitation V / Hz shows
0.000.
The frequency value is received from the pre-processing block. The function is in operation for
frequencies within the range of 33-60 Hz and of 42-75 Hz for 50 and 60 Hz respectively.
OEX protection function can be connected to any power transformer side, inde-
pendent from the power flow.
The side with a possible On-Load-Tap-Changer (OLTC) must not be used.
The so called IEEE law approximates a square law and has been chosen based on analysis of the
various transformers overexcitation capability characteristics. They can match well a trans-
former core capability.
401
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
0.18 k 0.18 k
t o p = --------------------------------------------
2
- = ---------------------------------------
-
2
( M V/Hz> ) overexcitation
(Equation 89)
where:
M is excitation, mean value in the interval from t = 0 to t = top
V/Hz> is maximum continuously allowed voltage at no load, and rated frequency, in pu and
k is time multiplier setting for inverse time functions, see figure 192.
Parameter k (time multiplier setting) selects one delay curve from the family of curves.
An analog overexcitation relay would have to evaluate the following integral expression, which
means to look for the instant of time t = top according to equation 90.
t op
2
( M(t) V/Hz> ) dt 0.18 k
0
(Equation 90)
A digital, numerical relay will instead look for the lowest j (i.e. j = n) where it becomes true that:
( M(j)
2
t V/Hz> ) 0.18 k
j=k
(Equation 91)
where:
t is the time interval between two successive executions of overexcitation function
and
M(j) - V/Hz> is the relative excitation at (time j) in excess of the normal (rated) excitation which
is given as Ur/fr.
As long as M > V/Hz> (i.e. overexcitation condition), the above sum can only be larger with
time, and if the overexcitation persists, the protected transformer will be tripped at j = n.
Inverse delays as per figure 192, can be modified (limited) by two special definite delay settings,
namely tMax and tMin, see figure 191.
402
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
delay in s
tMax
overexcitation
tMin
0 M max - V/Hz> Overexcitation M-V/Hz>
99001067.vsd
A definite maximum time, tMax, can be used to limit the operate time at low degrees of overex-
citation. Inverse delays longer than tMax will not be allowed. In case the inverse delay is longer
than tMax, OEX trips after tMaxt_MaxTripDelay seconds.
A definite minimum time, tMin, can be used to limit the operate time at high degrees of overex-
citation. In case the inverse delay is shorter than tMin, OEX function trips after
tMint_MinTripDelay seconds. Also, the inverse delay law is no more valid beyond excitation
Mmax. Beyond Mmax (beyond overexcitation Mmax - V/Hz>), the delay will always be tMin,
no matter what overexcitation.
403
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
1000
100
k = 60
k = 20
k = 10
10 k=9
k=8
k=7
k=6
k=5
k=4
k=3
k=2
k=1
1
1 2 3 4 5 10 20 30 40
OVEREXCITATION IN % (M-Emaxcont)*100)
en01000373.vsd
The critical value of excitation Mmax is determined indirectly via OEX protection function set-
ting V/Hz>>. V/Hz>> can be thought of as a no-load-rated-frequency voltage, where the inverse
law should be replaced by a short definite delay, tMin. If, for example, V/Hz>> = 140 %, then
Mmax is according to equation 92.
(V/Hz>>) f
Mmax = -------------------------
- = 1.40
Ur fr
(Equation 92)
404
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
The Tailor-Made law allows a user to design an arbitrary delay characteristic. In this case the
interval between M = V/Hz>, and M = Mmax is automatically divided into five equal subinter-
vals, with six delays. (settings t1, t2, t3, t4, t5, and t6) as shown in the figure 193. These times
should be set so that t1 => t2 => t3 => t4 => t5 => t6.
delay in s
tMax
under- tMin
excitation Overexcitation M-Emaxcont
0 Mmax - Emaxcont Excitation M
Emaxcont Mmax
99001068.vsd
Delays between two consecutive points, for example t3 and t4, are obtained by linear interpola-
tion.
Should it happen that tMax be lower than, for example, delays t1, and t2, the actual delay would
be tMax. Above Mmax, the delay can only be tMin.
4.2.3 Cooling
The overexcitation protection OEX is basically a thermal protection; therefore a cooling process
has been introduced. Exponential cooling process is applied. Parameter Tcool is an OEX setting,
with a default time constant tCooling of 20 minutes. This means that if the voltage and frequency
return to their previous normal values (no more overexcitation), the normal temperature is as-
sumed to be reached not before approximately 5 times tCooling minutes. If an overexcitation
condition would return before that, the time to trip will be shorter than it would be otherwise.
The displayed relative excitation M, designated on the display by V/Hz is calculated from the
expression:
405
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Ef
M = relative ------- = --------------
V
Hz Uf fr
(Equation 93)
If less than V / Hz = V/Hz> (in pu) is shown on the HMI display (or read via SM/RET521), the
power transformer is underexcited. If the value of V/Hz is shown which is equal to V/Hz> (in
pu), it means that the excitation is exactly equal to the power transformer continuous capability.
If a value higher than the value of V/Hz> is shown, the protected power transformer is overex-
cited. For example, if V/Hz = 1.100 is shown, while V/Hz> = 110 %, then the power transformer
is exactly on its maximum continuous excitation limit.
The third item of the OEX protection service report is the thermal status of the protected power
transformer iron core, designated on the display by ThermalStatus. This gives the thermal status
in % of the trip value which corresponds to 100%. Thermal Status should reach 100% at the
same time, when tTRIP reaches 0 seconds. If the protected power transformer is then for some
reason not switched off, the ThermalStaus shall go over 100%.
If the delay as per IEEE law, or Tailor-made Law, is limited by tMax, and/or TMin, then the
Thermal Status will generally not reach 100% at the same time, when tTRIP reaches 0 seconds.
For example, if, at low degrees of overexcitation, the very long delay is limited by tMax, then
the OEX TRIP output signal will be set to 1 before the Thermal status reaches 100%.
406
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
OVEX: FS = 1 = 2*SI + SU
BLOCK AlarmLevel
ALARM
SIDE t>tAlarm &
t
Prepool I tAlarm
M>V/Hz>
SI1 t>tMin TRIP
t &
V/Hz> tMin
SI2 Calculation
Ei k
of internal M= M
induced (Ei / f) M IEEE law
SU1 voltage Ei (Ur / fr)
Prepool O 1
2 M t
Tailor-made law
M>V/Hz>> tMax
Xleak
ERROR
V/Hz>>
en05000162.vsd
Figure 194: A logic diagram over Overexcitation protection function.
407
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Simplification of the diagram is in the way the IEEE and Tailor-made delays are calculated. The
cooling process is not shown. It is not shown that voltage and frequency are separately checked
against their respective limit values.
OEX1-
OEXPVPH_24
I3P TRIP
U3P START
BLOCK ALARM
RESET
en05000329.vs
d
Table 206: Output signals for the OEXPVPH_24 (OEX1-) function block
Signal Description
TRIP Trip from overexcitation function
START Overexcitation above set operate level (instantaneous)
ALARM Overexcitation above set alarm level (delayed)
408
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Table 208: Basic parameter group settings for the OEXPVPH_24 (OEX1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
IBase 1 - 99999 1 3000 A Base current (rated
phase current) in A
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage (main volt-
age) in kV
V/Hz> 100.0 - 180.0 0.1 110.0 %UB/f Operate level of V/Hz at
no load and rated freq in
% of (Ubase/frated)
V/Hz>> 100.0 - 200.0 0.1 140.0 %UB/f High level of V/Hz above
which tMin is used, in %
of (Ubase/frated)
XLeak 0.000 - 200.000 0.001 0.000 ohm Winding leakage reac-
tance in primary ohms
TrPulse 0.000 - 60.000 0.001 0.100 s Length of the pulse for
trip signal (in sec)
tMin 0.000 - 60.000 0.001 7.000 s Minimum trip delay for
V/Hz inverse curve, in
sec
tMax 0.00 - 9000.00 0.01 1800.00 s Maximum trip delay for
V/Hz inverse curve, in
sec
tCooling 0.10 - 9000.00 0.01 1200.00 s Transformer magnetic
core cooling time con-
stant, in sec
CurveType IEEE - IEEE - Inverse time curve selec-
Tailor made tion, IEEE/Tailor made
kForIEEE 1 - 60 1 1 - Time multiplier for IEEE
inverse type curve
AlarmLevel 50.0 - 120.0 0.1 100.0 % Alarm operate level as %
of operate level
tAlarm 0.00 - 9000.00 0.01 5.00 s Alarm time delay, in sec
409
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Table 209: Advanced parameter group settings for the OEXPVPH_24 (OEX1-) function
Parameter Range Step Default Unit Description
t1Tailor 0.00 - 9000.00 0.01 7200.00 s Time delay t1 (longest)
for tailor made curve, in
sec
t2Tailor 0.00 - 9000.00 0.01 3600.00 s Time delay t2 for tailor
made curve, in sec
t3Tailor 0.00 - 9000.00 0.01 1800.00 s Time delay t3 for tailor
made curve, in sec
t4Tailor 0.00 - 9000.00 0.01 900.00 s Time delay t4 for tailor
made curve, in sec
t5Tailor 0.00 - 9000.00 0.01 450.00 s Time delay t5 for tailor
made curve, in sec
t6Tailor 0.00 - 9000.00 0.01 225.00 s Time delay t6 (shortest)
for tailor made curve, in
sec
(0.18 k )
IEEE : t =
( M 1) 2
where M = relative (V/Hz) =
(E/f)/(Ur/fr)
Minimum time delay for inverse (0.00060.000) s 0.5% 10 ms
function
Maximum time delay for inverse (0.009000.00) s 0.5% 10 ms
function
Alarm time delay (0.00060.000) s 0.5% 10 ms
410
Voltage differential protection (PTOV, 60) Chapter 7
Voltage protection
5.1 Introduction
A voltage differential monitoring function is available. It compares the voltages from two three
phase sets of voltage transformers and has one sensitive alarm step and one trip step. It can be
used to supervise the voltage from two fuse groups or two different voltage transformers fuses
as a fuse/MCB supervision function.
Loss of one U1or all U2 voltages will block the differential measurement. This blocking can be
switched off with setting BlkDiffAtULow=No.
The function can be blocked from an external condition with the binary BLOCK input. It can
e.g. be activated from a fuse failure supervision function block.
To allow easy commissioning the measured differential voltage is available as service value.
This allows simple setting of the ratio correction factor to achieve full balance in normal service.
411
Voltage differential protection (PTOV, 60) Chapter 7
Voltage protection
UDTripL1>
AND
UDTripL1>
AND
AND START
UDAlarmL1>
AND
UDAlarmL1> O tAlarm
AND
R t AND ALARM
UDAlarmL1>
AND
U1<L1
tAlarm
U1<L2 OR t U1LOW
AND
AND
U1<L3
OR
BlkDiffAtULow
U2<L1
t1
U2<L2 AND t U2LOW
AND
U2<L3
BLOCK
en06000382.vsd
Figure 197: Principle logic for voltage differential function
412
Voltage differential protection (PTOV, 60) Chapter 7
Voltage protection
VDC1-
VDCPTOV_60
U3P1 TRIP
U3P2 START
BLOCK ALARM
U1LOW
U2LOW
UL1DIFF
UL2DIFF
UL3DIFF
en06000528.vsd
Table 212: Output signals for the VDCPTOV_60 (VDC1-) function block
Signal Description
TRIP Voltage differential protection operated
START Start of voltage differential protection
ALARM Voltage differential protection alarm
U1LOW Loss of U1 voltage
U2LOW Loss of U2 voltage
UL1DIFF Differential Voltage phase L1
UL2DIFF Differential Voltage phase L2
UL3DIFF Differential Voltage phase L3
413
Voltage differential protection (PTOV, 60) Chapter 7
Voltage protection
Table 214: Advanced parameter group settings for the VDCPTOV_60 (VDC1-) function
Parameter Range Step Default Unit Description
RFL1 0.000 - 3.000 0.001 1.000 - Ratio compensation fac-
tor phase L1
UCap*RFL1=UL1Bus
RFL2 0.000 - 3.000 0.001 1.000 - Ratio compensation fac-
tor phase L2
UCap*RFL2=UL2Bus
RFL3 0.000 - 3.000 0.001 1.000 - Ratio compensation fac-
tor phase L3
UCap*RFL3=UL3Bus
414
Voltage differential protection (PTOV, 60) Chapter 7
Voltage protection
415
Loss of voltage check (PTUV, 27) Chapter 7
Voltage protection
6.1 Introduction
The loss of voltage detection, (PTUV, 27), is suitable for use in networks with an automatic Sys-
tem restoration function. The function issues a three-pole trip command to the circuit breaker, if
all three phase voltages fall below the set value for a time longer the set time and the circuit
breaker remains closed.
Additionally, the function is automatically blocked if only one or two phase voltages have been
detected low for more than tBlock.
The LOVPTUV function operates again only if the line has been restored to full voltage for at
least tRestore. Operation of the function is also inhibited by fuse failure and open circuit breaker
information signals, by their connection to dedicated inputs of the function block.
Due to undervoltage conditions being continuous the trip pulse is limited to a length set by set-
ting tPulse.
The operation of the function is supervised by the fuse-failure function (VTSU input) and the
information about the open position (CBOPEN) of the associated circuit breaker.
The BLOCK input can be connected to a binary input of the terminal in order to receive a block
command from external devices or can be software connected to other internal functions of the
terminal itself in order to receive a block command from internal functions. The function is also
blocked when the IED is in TEST status and the function has been blocked from the HMI test
menu. (BlockLOV=Yes).
416
Loss of voltage check (PTUV, 27) Chapter 7
Voltage protection
TEST-ACTIVE
&
BlockLOV = Yes
LOV-START
LOV--BLOCK >1
Function Enable tTrip tPulse LOVTRIP
STUL1N & t
STUL2N &
only 1 or 2 phases are low for
Latched at least 10 s (not three)
STUL3N Enable
&
tBlock
>1 t
tRestore
>1 Set Enable
t
>1
Line restored for
at least 3 s
en07000089.vsd
Figure 199: Simplified diagram of loss of voltage check protection function
417
Loss of voltage check (PTUV, 27) Chapter 7
Voltage protection
LOV1-
LOVPTUV_27
U3P TRIP
BLOCK START
CBOPEN
VTSU
en07000039.vsd
Table 217: Output signals for the LOVPTUV_27 (LOV1-) function block
Signal Description
TRIP Trip signal
START Start signal
418
Loss of voltage check (PTUV, 27) Chapter 7
Voltage protection
Table 219: Advanced parameter group settings for the LOVPTUV_27 (LOV1-) function
Parameter Range Step Default Unit Description
tPulse 0.050 - 60.000 0.001 0.150 s Duration of TRIP pulse
tBlock 0.000 - 60.000 0.001 5.000 s Time delay to block when
all 3ph voltages are not
low
tRestore 0.000 - 60.000 0.001 3.000 s Time delay for enable the
function after restoration
419
Loss of voltage check (PTUV, 27) Chapter 7
Voltage protection
420
About this chapter Chapter 8
Frequency protection
Chapter 8 Frequency
protection
421
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
1.1 Introduction
Underfrequency occurs as a result of lack of generation in the network.
The function can be used for load shedding systems, remedial action schemes, gas turbine
start-up etc.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
To avoid oscillations of the output start signal, a hysteresis has been included.
422
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
For the voltage dependent time delay the measured voltage level and the settings UNom, UMin,
Exponent, tMax and tMin set the time delay according to figure 201 and equation 94. The setting
TimerOperation is used to decide what type of time delay to apply. The output STARTDUR,
gives the time elapsed from the issue of the start output, in percent of the total operation time
available in PST.
Trip signal issuing requires that the underfrequency condition continues for at least the user set
time delay. If the start condition, with respect to the measured frequency ceases during the delay
time, and is not fulfilled again within a user defined reset time, tReset, the start output is reset,
after that the defined reset time has elapsed. Here it should be noted that after leaving the hys-
teresis area, the start condition must be fulfilled again and it is not sufficient for the signal to
only return back to the hysteresis area.
On the output of the underfrequency function a 100 ms pulse is issued, after a time delay corre-
sponding to the setting of TimeDlyRestore, when the measured frequency returns to the level
corresponding to the setting RestoreFreq.
Exponent
U UMin
t= ( tMax tMin ) + tMin
UNom UMin
(Equation 94)
where:
t is the voltage dependent time delay (at constant voltage),
U is the measured voltage
Exponent is a setting,
UMin, UNom are voltage settings corresponding to
tMax, tMin are time settings.
423
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
UMin = 90%
UNom = 100%
tMax = 1.0 s
tMin = 0.0 s
Exponent = 0, 1, 2, 3 and 4
1
0
1
TimeDlyOperate [s]
Exponenent
2
3
0.5 4
0
90 95 100
U [% of UBase]
en05000075.vsd
Figure 201: Voltage dependent inverse time characteristics for the underfrequency function.
The time delay to operate is plotted as a function of the measured voltage, for the
Exponent = 0, 1, 2, 3, 4 respectively.
1.2.4 Blocking
The underfrequency function can be partially or totally blocked, by binary input signals or by
parameter settings, where:
If the measured voltage level decreases below the setting of IntBlkStVal, both the start and the
trip outputs, are blocked.
1.2.5 Design
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting StartFrequency. The frequency signal is filtered to avoid
transients due to switchings and faults. The time integrator can operate either due to a definite
424
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
delay time or to the special voltage dependent delay time. When the frequency has returned back
to the setting of RestoreFreq, the RESTORE output is issued after the time delay TimeDlyRe-
store. The design of the underfrequency function is schematically described in figure 202.
Block
BLOCK BLKDMAGN
OR
Comparator
U < IntBlockLevel
TimeDlyReset TRIP
100 ms
Comparator RESTORE
TimeDlyRestore
f > RestoreFreq
en05000726.vsd
Figure 202: Schematic design of the underfrequency function
TUF1-
SAPTUF_81
U3P TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
Frequency
en06000279.vsd
425
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
Table 221: Output signals for the SAPTUF_81 (TUF1-) function block
Signal Description
TRIP Operate/trip signal for frequency.
START Start/pick-up signal for frequency.
RESTORE Restore signal for load restoring purposes.
BLKDMAGN Blocking indication due to low amplitude.
Frequency Measured frequency
426
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
427
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
2.1 Introduction
Overfrequency will occur at sudden load drops or shunt faults in the power network. In some
cases close to generating part governor problems can also cause overfrequency.
The function can be used for generation shedding, remedial action schemes etc. It can also be
used as a sub-nominal frequency stage initiating load restoring.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
Trip signal issuing requires that the overfrequency condition continues for at least the user set
time delay. If the start condition, with respect to the measured frequency ceases during the delay
time, and is not fulfilled again within a user defined reset time, tReset, the start output is reset,
428
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
after that the defined reset time has elapsed. Here it should be noted that after leaving the hys-
teresis area, the start condition must be fulfilled again and it is not sufficient for the signal to
only return back to the hysteresis area.
2.2.3 Blocking
The overfrequency function can be partially or totally blocked, by binary input signals or by pa-
rameter settings, where:
If the measured voltage level decreases below the setting of IntBlkStVal, both the start and the
trip outputs, are blocked.
2.2.4 Design
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting StartFrequency. The frequency signal is filtered to avoid
transients due to switchings and faults in the power system. The time integrator operates due to
a definite delay time. The design of the overfrequency function is schematically described in
figure 204.
BLOCK
BLKTRIP BLOCK
OR BLKDMAGN
Comparator
U < IntBlockLevel
Start
&
Trip
Voltage Time integrator Output
Logic
Definite Time Delay START START
Frequency Comparator
f > StartFrequency TimeDlyOperate
TRIP
TimeDlyReset
TRIP
en05000735.vsd
429
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
TOF1-
SAPTOF_81
U3P TRIP
BLOCK START
BLKTRIP BLKDMAGN
Frequency
en06000280.vsd
Table 225: Output signals for the SAPTOF_81 (TOF1-) function block
Signal Description
TRIP Operate/trip signal for frequency.
START Start/pick-up signal for frequency.
BLKDMAGN Blocking indication due to low amplitude.
Frequency Measured frequency
430
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
431
Rate-of-change frequency Chapter 8
protection (PFRC, 81) Frequency protection
3.1 Introduction
Rate of change of frequency function gives an early indication of a main disturbance in the sys-
tem.
The function can be used for generation shedding, load shedding, remedial action schemes etc.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
432
Rate-of-change frequency Chapter 8
protection (PFRC, 81) Frequency protection
To avoid oscillations of the output start signal, a hysteresis has been included.
Trip signal issuing requires that the rate-of-change of frequency condition continues for at least
the user set time delay, tTrip. If the start condition, with respect to the measured frequency ceas-
es during the delay time, and is not fulfilled again within a user defined reset time, tReset, the
start output is reset, after that the defined reset time has elapsed. Here it should be noted that
after leaving the hysteresis area, the start condition must be fulfilled again and it is not sufficient
for the signal to only return back into the hysteresis area.
The RESTORE output of the rate-of-change of frequency function is set, after a time delay equal
to the setting of tRestore, when the measured frequency has returned to the level corresponding
to RestoreFreq, after an issue of the TRIP output signal. If tRestore is set to 0.000 s the restore
functionality is disabled, and no output will be given. The restore functionality is only active for
lowering frequency conditions and the restore sequence is disabled if a new negative frequency
gradient is detected during the restore period, defined by the settings RestoreFreq and tRestore.
3.2.3 Blocking
The rate-of-change of frequency function can be partially or totally blocked, by binary input sig-
nals or by parameter settings, where:
If the measured voltage level decreases below the setting of IntBlockLevel, both the start and the
trip outputs, are blocked.
3.2.4 Design
The rate-of-change of frequency measuring element continuously measures the frequency of the
selected voltage and compares it to the setting StartFreqGrad. The frequency signal is filtered
to avoid transients due to power system switchings and faults. The time integrator operates with
a definite delay time. When the frequency has returned back to the setting of RestoreFreq, the
RESTORE output is issued after the time delay tRestore, if the TRIP signal has earlier been is-
sued. The sign of the setting StartFreqGrad is essential, and controls if the function is used for
raising or lowering frequency conditions. The design of the rate-of-change of frequency function
is schematically described in figure 206.
433
Rate-of-change frequency Chapter 8
protection (PFRC, 81) Frequency protection
BLOCK
BLKTRIP
BLKRESET BLOCK
OR
Start
Rate-of-Change Time integrator &
Comparator
of Frequency Trip
If
Definite Time Delay Output
[StartFreqGrad<0 START START
Logic
AND
TimeDlyOperate
df/dt < StartFreqGrad]
OR
TimeDlyReset
[StartFreqGrad>0
AND
TRIP
df/dt > StartFreqGrad]
Then
START
100 ms
en05000835.vsd
Figure 206: Schematic design of the rate-of-change of frequency function
RCF1-
SAPFRC_81
U3P TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
en06000281.vsd
434
Rate-of-change frequency Chapter 8
protection (PFRC, 81) Frequency protection
Table 229: Output signals for the SAPFRC_81 (RCF1-) function block
Signal Description
TRIP Operate/trip signal for frequencyGradient
START Start/pick-up signal for frequencyGradient
RESTORE Restore signal for load restoring purposes.
BLKDMAGN Blocking indication due to low amplitude.
435
Rate-of-change frequency Chapter 8
protection (PFRC, 81) Frequency protection
436
About this chapter Chapter 9
Multipurpose protection
Chapter 9 Multipurpose
protection
437
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
I< I>
U< U>
1.1 Introduction
The protection module is recommended as a general backup protection with many possible ap-
plication areas due to its flexible measuring and setting facilities.
The built-in overcurrent protection feature has two settable current levels. Both of them can be
used either with definite time or inverse time characteristic. The overcurrent protection steps can
be made directional with selectable voltage polarizing quantity. Additionally they can be voltage
and/or current controlled/restrained. 2nd harmonic restraining facility is available as well. At too
low polarizing voltage the overcurrent feature can be either blocked, made non directional or or-
dered to use voltage memory in accordance with a parameter setting.
Additionally two overvoltage and two undervoltage steps, either with definite time or inverse
time characteristic, are available within each function.
The general function suits applications with underimpedance and voltage controlled overcurrent
solutions. The general function can also be utilized for generator transformer protection appli-
cations where positive, negative or zero sequence components of current and voltage quantities
is typically required.
To prevent damages on the generator or turbine, it is essential that high speed tripping is provid-
ed in case of inadvertent energization of the generator. This tripping should be almost instanta-
neous (< 100 ms).
438
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
There is a risk that the current into the generator at inadvertent energization will be limited so
that the normal overcurrent or underimpedance protection will not detect the dangerous situ-
ation. The delay of these protection functions might be too long. For big and important ma-
chines, fast protection against inadvertent energizing should, therefore, be included in the
protective scheme.
The user can select to measure one of the current quantities shown in table 232.
439
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
The user can select to measure one of the voltage quantities shown in table 233:
440
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
It is important to notice that the voltage selection from table 233 is always applicable regardless
the actual external VT connections. The three-phase VT inputs can be connected to IED as either
three phase-to-ground voltages UL1, UL2 & UL3 or three phase-to-phase voltages UL1L2, UL2L3
& UL3L1). This information about actual VT connection is entered as a setting parameter for the
pre-processing block, which will then take automatic care about it.
The user can select one of the current quantities shown in table 234 for built-in current restraint
feature:
1. rated phase current of the protected object in primary amperes, when the mea-
sured Current Quantity is selected from 1 to 9, as shown in table 232.
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
1. rated phase-to-ground voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 1 to 9, as shown in table 233.
2. rated phase-to-phase voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 10 to 15, as shown in table 233.
Overcurrent step simply compares the magnitude of the measured current quantity
(see table 232) with the set pickup level. Non-directional overcurrent step will pickup if the
magnitude of the measured current quantity is bigger than this set level. Reset ratio is settable,
with default value of 0.96. However depending on other enabled built-in features this overcur-
rent pickup might not cause the overcurrent step start signal. Start signal will only come if all of
the enabled built-in features in the overcurrent step are fulfilled at the same time.
This feature will simple prevent overcurrent step start if the second-to-first harmonic ratio in the
measured current exceeds the set level.
Directional feature
The overcurrent protection step operation can be can be made dependent on the relevant phase
angle between measured current phasor (see table 232) and measured voltage phasor
(see table 233). In protection terminology it means that the PGPF function can be made direc-
tional by enabling this built-in feature. In that case overcurrent protection step will only operate
if the current flow is in accordance with the set direction (i.e. Forward, which means towards
the protected object, or Reverse, which means from the protected object). For this feature it is of
the outmost importance to understand that the measured voltage phasor (see table 233) and mea-
sured current phasor (see table 232) will be used for directional decision. Therefore it is the sole
responsibility of the end user to select the appropriate current and voltage signals in order to get
a proper directional decision. The PGPF function will NOT do this automatically. It will just
simply use the current and voltage phasors selected by the end user to check for the directional
criteria.
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Table 235 gives an overview of the typical choices (but not the only possible ones) for these two
quantities for traditional directional relays.
Table 235: Typical current and voltage choices for directional feature
Set value for Set value for
the parameter Cur- the parameter Volt-
Comment
rentInput ageInput
PosSeq PosSeq Directional positive sequence overcurrent function is
obtained. Typical setting for RCADir is from -45 to -90
depending on the power
NegSeq -NegSeq Directional negative sequence overcurrent function is
obtained. Typical setting for RCADir is from -45 to -90
depending on the power system voltage level (i.e. X/R
ratio)
3ZeroSeq -3ZeroSeq Directional zero sequence overcurrent function is
obtained. Typical setting for RCADir is from
0 to -90 depending on the power system earthing (i.e.
solidly earthed, earthed via resistor, etc.)
Phase1 Phase2-Phase3 Directional overcurrent function for the first phase is
obtained. Typical setting for RCADir is +30 or +45
Phase2 Phase3-Phase1 Directional overcurrent function for the second phase is
obtained. Typical setting for RCADir is +30 or +45
Phase3 Phase1-Phase2 Directional overcurrent function for the third phase is
obtained. Typical setting for RCADir is +30 or +45
Unbalance current or voltage measurement shall not be used when the directional feature is en-
abled.
Two types of directional measurement principles are available, I & U and IcosPhi&U. The first
principle, referred to as "I & U" in the parameter setting tool, checks that:
the magnitude of the measured current is bigger than the set pick-up level
the phasor of the measured current is within the operating region (defined by the
relay operate angle, ROADir parameter setting; see figure 208).
443
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
U=-3U0
RCADir
Operate region
mta line
en05000252.vsd
where:
RCADir is -75
ROADir is 50
The second principle, referred to as "IcosPhi&U" in the parameter setting tool, checks that:
that the product Icos() is bigger than the set pick-up level, where is angle
between the current phasor and the mta line
that the phasor of the measured current is within the operating region (defined by
the Icos() straight line and the relay operate angle, ROADir parameter setting;
see figure 208).
444
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
U=-3U0
RCADir
Operate region
mta line
en05000253.vsd
where:
RCADir is -75
ROADir is 50
Note that it is possible to decide by a parameter setting how the directional feature shall behave
when the magnitude of the measured voltage phasor falls below the pre-set value. User can select
one of the following three options:
Non-directional (i.e. operation allowed for low magnitude of the reference volt-
age)
Block (i.e. operation prevented for low magnitude of the reference voltage)
Memory (i.e. memory voltage shall be used to determine direction of the current)
It shall also be noted that the memory duration is limited in the algorithm to 100 ms. After that
time the current direction will be locked to the one determined during memory time and it will
re-set only if the current fails below set pickup level or voltage goes above set voltage memory
limit.
445
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
ULowLimit_OC1 UHighLimit_OC1
Selected Voltage
Magnitude
en05000324.vsd
Figure 210: Example for OC1 step current pickup level variation as function of measured volt-
age magnitude in Slope mode of operation
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
en05000323.vsd
Figure 211: Example for OC1 step current pickup level variation as function of measured volt-
age magnitude in Step mode of operation
446
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
This feature will simple change the set overcurrent pickup level in accordance with magnitude
variations of the measured voltage. It shall be noted that this feature will as well affect the pickup
current value for calculation of operate times for IDMT curves (i.e. overcurrent with IDMT
curve will operate faster during low voltage conditions).
IMeasured
ea ain
ar str
e Ire
at ff*
per e
O Co
es tr
I>R
IsetHigh
IsetLow
atan(RestrCoeff)
Restraint
en05000255.vsd
This feature will simple prevent overcurrent step to start if the magnitude of the measured cur-
rent quantity is smaller than the set percentage of the restrain current magnitude. However this
feature will not affect the pickup current value for calculation of operate times for IDMT curves.
This means that the IDMT curve operate time will not be influenced by the restrain current mag-
nitude.
When set, the start signal will start definite time delay or inverse (i.e. IDMT) time delay in ac-
cordance with the end user setting. If the start signal has value one for longer time than the set
time delay, the overcurrent step will set its trip signal to one. Reset of the start and trip signal
can be instantaneous or time delay in accordance with the end user setting.
447
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
value one for longer time than the set time delay the undercurrent step will set its trip signal to
one. Reset of the start and trip signal can be instantaneous or time delay in accordance with the
setting.
Overvoltage step simply compares the magnitude of the measured voltage quantity
(see table 233) with the set pickup level. The overvoltage step will pickup if the magnitude of
the measured voltage quantity is bigger than this set level. Reset ratio is settable, with default
value of 0.99.
The start signal will start definite time delay or inverse (i.e. IDMT) time delay in accordance
with the end user setting. If the start signal has value one for longer time than the set time delay,
the overvoltage step will set its trip signal to one. Reset of the start and trip signal can be instan-
taneous or time delay in accordance with the end user setting.
Undervoltage step simply compares the magnitude of the measured voltage quantity
(see table 233 with the set pickup level. The undervoltage step will pickup if the magnitude of
the measured voltage quantity is smaller than this set level. Reset ratio is settable, with default
value of 1.01.
The start signal will start definite time delay or inverse (i.e. IDMT) time delay in accordance
with the end user setting. If the start signal has value one for longer time than the set time delay,
the undervoltage step will set its trip signal to one. Reset of the start and trip signal can be in-
stantaneous or time delay in accordance with the end user setting.
448
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
CVGAPC
3IP
3UP TROC1
TROV1
1
TRUV1
BLKOC1
en06000497.vsd
The setting of the general current and voltage function (typical values) is done as shown in
table 236.
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Table 236: The setting of the general current and voltage function
Measured Pickup in % Time delay in
Quantity of generator seconds
rating
Undervolt- Maximum < 70% 10.0 s
age U< generator
Phase to
Phase voltage
Overvoltage Maximum > 85% 1.0 s
U> generator
Phase to
Phase voltage
Overcurrent Maximum > 50% 0.05 s
I> generator
Phase current
In normal operation the overvoltage trip signal is activated and the undervotage trip signal is de-
activated. This means that the overcurrent function is blocked.
When the generator is taken out of service the generator voltage gets low. The overvoltage trip
signal will be deactivated and the undervoltage trip signal will be activated after the set delay.
At this moment the block signal to the overcurrent function will be deactivated.
It the generator is energized at stand still conditions, i.e. when the voltage is zero, the overcurrent
function will operate after the short set delay if the generator current is larger than the set value.
When the generator is started the overvoltage trip signal will be activared the set time delay after
the moment when the voltage has reached the set value. At this moment the blocking of the over-
current function is activated.
The delay of the undervoltage function will prevent false operation at short circuits in the exter-
nal power grid.
450
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
REx670
ADM PGPF function
Phasor calculation of
scaling with CT ratio
individual currents
A/D conversion Selection of which current Selected current
Phasors &
and voltage shall be given to
samples
the built-in protection Selected voltage
elements
Phasors &
samples
en05000169.vsd
Figure 214: Treatment of measured currents within IED for PGPF function
Figure 214 shows how internal treatment of measured currents is done for multipurpose protec-
tion function
The following currents and voltages are inputs to the multipurpose protection function. They
must all be expressed in true power system (primary) Amperes and kilovolts.
1. Instantaneous values (samples) of currents & voltages from one three-phase cur-
rent and one three-phase voltage input.
2. Fundamental frequency phasors from one three-phase current and one
three-phase voltage input calculated by the pre-processing modules.
3. Sequence currents & voltages from one three-phase current and one three-phase
voltage input calculated by the pre-processing modules.
1. Selects one current from the three phase input system (see table 237) for internal-
ly measured current.
2. Selects one voltage from the three phase input system (see table 238) for inter-
nally measured voltage.
3. Selects one current from the three phase input system (see table 238) for internal-
ly measured restraint current.
451
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
CURRENT
UC1
TRUC1
2nd Harmonic
Selected current restraint
STUC2
UC2
nd
TRUC2
2 Harmonic
restraint
STOC1
OC1 TROC1
STOC2
OC2 TROC2
2nd Harmonic
restraint
Current restraint 1
UDIRLOW
Directionality DIROC2
Voltage control /
restraint
STOV1
OV1 TROV1
STOV2
OV2 TROV2
STUV1
Selected voltage
UV1 TRUV1
STUV2
UV2 TRUV2
VOLTAGE
en05000170.vsd
Figure 215: PGPF function main logic diagram for built in protection elements
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
1. The selected currents and voltage are given to built-in protection elements. Each
protection element and step makes independent decision about status of its
START and TRIP output signals.
2. More detailed internal logic for every protection element is given in the following
four figures
3. Common START and TRIP signals from all built-in protection elements & steps
(internal OR logic) are available from multipurpose function as well.
Enable
second
harmonic Second
harmonic check
1 DEF time BLKTROC
selected DEF 1 TROC1
AND
OR
Selected current a
a>b
b
OC1=On STOC1
AND
StartCurr_OC1 BLKOC1
X
Inverse
Selected voltage
Current
Restraint
Feature
Selected restrain current Imeasured > k Irestraint
en05000831.vsd
Figure 216: Simplified internal logic diagram for built-in first overcurrent step i.e. OC1 (step
OC2 has the same internal logic)
453
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Operation_UC1=On
STUC1
en05000750.vsd
Figure 217: Simplified internal logic diagram for built-in first undercurrent step i.e. UC1 (step
UC2 has the same internal logic)
Inverse
Operation_OV1=On
Inverse time
BLKOV1 selected
en05000751.vsd
Figure 218: Simplified internal logic diagram for built-in first overvoltage step i.e.OV1 (step
OV2 has the same internal logic)
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Inverse
Operation_UV1=On
Inverse time
BLKUV1 selected
en05000752.vsd
Figure 219: Simplified internal logic diagram for built-in first undervoltage step i.e.UV1 (step
UV2 has the same internal logic)
GF01-
CVGAPC
I3P TRIP
U3P TROC1
BLOCK TROC2
BLKOC1 TRUC1
BLKOC1TR TRUC2
ENMLTOC1 TROV1
BLKOC2 TROV2
BLKOC2TR TRUV1
ENMLTOC2 TRUV2
BLKUC1 START
BLKUC1TR STOC1
BLKUC2 STOC2
BLKUC2TR STUC1
BLKOV1 STUC2
BLKOV1TR STOV1
BLKOV2 STOV2
BLKOV2TR STUV1
BLKUV1 STUV2
BLKUV1TR BLK2ND
BLKUV2 DIROC1
BLKUV2TR DIROC2
UDIRLOW
CURRENT
ICOSFI
VOLTAGE
UIANGLE
en05000372.vsd
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Table 238: Output signals for the CVGAPC (GF01-) function block
Signal Description
TRIP General trip signal
TROC1 Trip signal from overcurrent function OC1
TROC2 Trip signal from overcurrent function OC2
TRUC1 Trip signal from undercurrent function UC1
TRUC2 Trip signal from undercurrent function UC2
TROV1 Trip signal from overvoltage function OV1
TROV2 Trip signal from overvoltage function OV2
TRUV1 Trip signal from undervoltage function UV1
TRUV2 Trip signal from undervoltage function UV2
START General start signal
STOC1 Start signal from overcurrent function OC1
STOC2 Start signal from overcurrent function OC2
456
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Signal Description
STUC1 Start signal from undercurrent function UC1
STUC2 Start signal from undercurrent function UC2
STOV1 Start signal from overvoltage function OV1
STOV2 Start signal from overvoltage function OV2
STUV1 Start signal from undervoltage function UV1
STUV2 Start signal from undervoltage function UV2
BLK2ND Block from second harmonic detection
DIROC1 Directional mode of OC1 (nondir, forward,reverse)
DIROC2 Directional mode of OC2 (nondir, forward,reverse)
UDIRLOW Low voltage for directional polarization
CURRENT Measured current value
ICOSFI Measured current multiplied with cos (Phi)
VOLTAGE Measured voltage value
UIANGLE Angle between voltage and current
457
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
458
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
459
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
460
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
461
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
462
General current and voltage Chapter 9
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General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
Table 240: Advanced parameter group settings for the CVGAPC (GF01-) function
Parameter Range Step Default Unit Description
CurrMult_OC1 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
OC1
ResCrvType_OC1 Instantaneous - Instantaneous - Selection of reset curve
IEC Reset type for OC1
ANSI reset
tResetDef_OC1 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
OC1
P_OC1 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OC1
A_OC1 0.0000 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OC1
B_OC1 0.0000 - 99.0000 0.0001 0.0000 - Parameter B for cus-
tomer programmable
curve for OC1
C_OC1 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for OC1
PR_OC1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for OC1
TR_OC1 0.005 - 600.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for OC1
CR_OC1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for OC1
CurrMult_OC2 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
OC2
ResCrvType_OC2 Instantaneous - Instantaneous - Selection of reset curve
IEC Reset type for OC2
ANSI reset
tResetDef_OC2 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
OC2
P_OC2 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OC2
A_OC2 0.0000 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OC2
464
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
465
General current and voltage Chapter 9
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466
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
467
General current and voltage Chapter 9
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468
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
469
General current and voltage Chapter 9
protection (GAPC) Multipurpose protection
470
About this chapter Chapter 10
Secondary system supervision
471
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
1.1 Introduction
Open or short circuited current transformer cores can cause unwanted operation of many protec-
tion functions such as differential, earth fault current and negative sequence current functions.
The current circuit supervision function compares the residual current from a three phase set of
current transformer cores with the neutral point current on a separate input taken from another
set of cores on the current transformer.
A detection of a difference indicates a fault in the circuit and is used as alarm or to block protec-
tion functions expected to give unwanted tripping.
The FAIL output will be set to a logical one when the following criteria are fulfilled:
The numerical value of the difference |Iphase| |Iref| is higher than 80% of the
numerical value of the sum |Iphase| + |Iref|.
The numerical value of the current |Iphase| |Iref| is equal to or higher than the
set operate value IMinOp.
No phase current has exceeded Ip>Block during the last 10 ms.
The current circuit supervision is enabled by setting Operation = On.
The FAIL output remains activated 100 ms after the AND-gate resets when being activated for
more than 20 ms. If the FAIL lasts for more than 150 ms a ALARM will be issued. In this case
the FAIL and ALARM will remain activated 1 s after the AND-gate resets. This prevents un-
wanted resetting of the blocking function when phase current supervision element(s) operate,
e.g. during a fault.
472
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
Figure 221: Simplified logic diagram for the current circuit supervision
473
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
| I phase | - | I ref |
Slope = 1
Operation
Slope = 0.8
area
I MinOp
| I phase | + | I ref |
99000068.vsd
Note!
Due to the formulas for the axis compared, |Iphase | - |I ref | and | I phase | + | I ref | respec-
tively, the slope can not be above 2.
CCS1-
CCSRDIF
I3P FAIL
IREF ALARM
BLOCK
en05000389.vsd
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Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
Table 243: Output signals for the CCSRDIF (CCS1-) function block
Signal Description
FAIL Detection of current circuit failure
ALARM Alarm for current circuit failure
Table 245: Advanced parameter group settings for the CCSRDIF (CCS1-) function
Parameter Range Step Default Unit Description
Ip>Block 5 - 500 1 150 %IB Block of the function at
high phase current, in %
of IBase
475
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
2.1 Introduction
The aim of the fuse failure supervision function (FSD) is to block voltage measuring functions
at failures in the secondary circuits between the voltage transformer and the IED in order to
avoid unwanted operations that otherwise might occur.
The fuse failure supervision function basically has two different algorithms, negative sequence
and zero sequence based algorithm and an additional delta voltage and delta current algorithm.
The negative sequence detection algorithm is recommended for IEDs used in isolated or
high-impedance earthed networks. It is based on the negative-sequence measuring quantities, a
high value of voltage 3U2 without the presence of the negative-sequence current 3I2.
The zero sequence detection algorithm is recommended for IEDs used in directly or low imped-
ance earthed networks. It is based on the zero sequence measuring quantities, a high value of
voltage 3U0 without the presence of the residual current 3I0.
A criterion based on delta current and delta voltage measurements can be added to the fuse fail-
ure supervision function in order to detect a three phase fuse failure, which in practice is more
associated with voltage transformer switching during station operations.
For better adaptation to system requirements, an operation mode setting has been introduced
which makes it possible to select the operating conditions for negative sequence and zero se-
quence based function. The selection of different operation modes makes it possible to choose
different interaction possibilities between the negative sequence and zero sequence based algo-
rithm.
The measured signals are compared with their respective set values 3U0< and 3I0>.
The function enable the internal signal fuseFailDetected if the measured zero sequence voltage
is higher than the set value 3U0>, the measured zero sequence current is below the set value
3I0< and the operation mode selector (OpMode is set to 2 (zero sequence mode). This will ac-
476
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
tivate the output signal BLKU, intended to block voltage related protection functions in the IED.
The output signal BLKZ will be activated as well if not the internal dead line detection is acti-
vaded at the same time.
If the fuseFailDetected signal is present for more than 5 seconds at the same time as all phase
voltages are below the set value UPh> and the setting parameter ISealIn is set to On, the function
will activate the output signals 3PH, BLKU and BLKZ. The same signals will aslo be activated
if all phase voltages are below the value UPh>, SealIn=On and any of the phase voltages below
the setting value for more than 5 seconds.
It is recommended to always set SealIn to On since this will secure that no unwanted operation
of fuse failure will occur at closing command of breaker when the line is already energized from
the other end. The system voltages shall be normal before fuse failure is allowed to be activated
and initiate block of different protection functions.
The output signal BLKU can also be activated if no phase voltages is below the setting UPh>
for more than 60 seconds at the same time as the zero sequence voltage is above the set value
3U0> for more than 5 seconds, all phase currents are below the setting IDLD< (operate level for
dead line detection) and the circuit breaker is closed (input CBCLOSED is activated). This con-
dition covers for fuse failure at open breaker position.
Fuse failure condition is unlatched when the normal voltage conditions are restored.
Fuse failure condition is stored in the non volatile memory in the IED. In the new start-up pro-
cedure the IED checks the stored value in its non volatile memory and establishes the corre-
sponding starting conditions.
477
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
TEST
TEST ACTIVE
AND
BlocFuse = Yes
BLOCK
OR
BLKTRIP
fufailStarted AND
OR
All UL less
than Uph>
3PH
AND
SealIn = On AND
5s
Any UL less AND
OR t
than Uph>
setLatch U I
BLKZ
200 ms AND
AND OR
deadLineCondition t
150 ms
MCBOP
t
60 sec
All UL> UPh> t
AND
UN > 3U0> for
t>5 s AND
en06000394.vsd
Figure 224: Simplified logic diagram for fuse failure supervision function, zero sequence
based
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Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
The input BLOCK signal is a general purpose blocking signal of the fuse failure supervision
function. It can be connected to a binary input of the IED in order to receive a block command
from external devices or can be software connected to other internal functions of the IED itself
in order to receive a block command from internal functions. Through OR gate it can be con-
nected to both binary inputs and internal function outputs.
The input BLKSP is intended to be connected to the trip output at any of the protection functions
included in the IED. When activated for more than 20 ms, the operation of the fuse failure is
blocked during a fixed time of 100 ms. The aim is to increase the security against unwanted op-
erations during the opening of the breaker, which might cause unbalance conditions for which
the fuse failure might operate.
The output signal BLKZ will also be blocked if the internal dead line detection is activated. The
block signal has a 200 ms drop-off time delay.
The input signal MCBOP is supposed to be connected via a terminal binary input to the N.C.
auxiliary contact of the miniature circuit breaker protecting the VT secondary circuit. The
MCBOP signal sets the output signals BLKU and BLKZ in order to block all the voltage related
functions when the MCB is open independent of the setting of OpMode selector. The additional
drop-off timer of 150 ms prolongs the presence of MCBOP signal to prevent the unwanted op-
eration of voltage dependent function due to non simultaneous closing of the main contacts of
the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input to the N.C.
auxiliary contact of the line disconnector. The DISCPOS signal sets the output signal BLKU in
order to block the voltage related functions when the line disconnector is open. The impedance
protection function is not affected by the position of the line disconnector since there will be no
line currents that can cause maloperation of the distance protection. If DISCPOS=0 it signifies
that the line is connected to the system and when the DISCPOS=1 it signifies that the line is dis-
connected from the system and the block signal BLKU is generated.
The output BLKU can be used for blocking the voltage related measuring functions (undervolt-
age protection, synchro-check etc.) except for the impedance protection.
The function output BLKZ can be used for blocking the impedance protection function.
The BLKZ will only be activated if not the internal dead line detection is activated at the same
time.
The fuse failure condition is unlatched when the normal voltage conditions are restored.
When the output 3PH is activated, all three voltage are low.
479
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
The function enable the internal signal fuseFailDetected if the measured negative sequence volt-
age is higher than the set value 3U2>, the measured negative sequence current is below the value
3I2< and the operation mode selector (OpMode) is set to 1 (negative sequence mode).
The current and voltage is continuously measured in all three phases and the following quantities
are calculated:
The calculated delta quantities are compared with their respective set values DI< and DU>.
The delta current and delta voltage algorithm, detects a fuse failure if a sufficient negative
change in voltage amplitude without a sufficient change in current amplitude is detected in each
phase separately. This check is performed if the circuit breaker is closed. Information about the
circuit breaker position is brought to the function input CBCLOSED through a binary input of
the IED.
There are two conditions for activating the internal STDU signal and set the latch:
The magnitude of U is higher than the corresponding setting DU> and I is be-
low the setting DI> in any phase at the same time as the circuit breaker is closed
(CBCLOSED = 1)
The magnitude U is higher than the setting DU> and the magnitude of I is be-
low the setting DI> in any phase at the same time as the magnitude of the phase
current in the same phase is higher than the setting IPh>.
The first criterion requires that the delta condition shall be fulfilled in any phase at the same time
as circuit breaker is closed. Opening circuit breaker at one end and energizing the line from other
end onto a fault could lead to wrong start of the fuse failure function at the end with the open
breaker. If this is considering to bee an important disadvantage, connect the CBCLOSED input
to FALSE. In this way only the second criterion can activate the delta function.
The second criterion means that detection of failure in one phase together with high current for
the same phase will set the latch. The measured phase current is used to reduce the risk of false
fuse failure detection. If the current on the protected line is low, a voltage drop in the system (not
caused by fuse failure) is not by certain followed by current change and a false fuse failure might
occur. To prevent that the phase current criterion is introduced.
480
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
If the signal setLatchUI is set (see figure 224) and if all measured voltages are low (lower
than the setting UPh>) the output 3PH will be activated indicating fuse failure in all three phas-
es. The output BLKU and BLKZ will be activated as well.
If the signal setLatchUI is activated but not all three phases are below the setting UPh> only
BLKU will be activated.
The BLKZ will be activated as well if not the internal dead line detection is activated.
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Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
FSD1-
SDDRFUF
I3P BLKZ
U3P BLKU
BLOCK 3PH
CBCLOSED DLD1PH
MCBOP DLD3PH
DISCPOS
BLKTRIP
en05000700.vsd
Table 248: Output signals for the SDDRFUF (FSD1-) function block
Signal Description
BLKZ Start of current and voltage controlled function
BLKU General start of function
3PH Three-phase start of function
DLD1PH Dead line condition in at least one phase
DLD3PH Dead line condition in all three phases
482
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
483
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
484
About this chapter Chapter 11
Control
Chapter 11 Control
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
1.1 Introduction
The Synchronizing function allows closing of asynchronous networks at the correct moment in-
cluding the breaker closing time. The systems can thus be reconnected after an auto-reclose or
manual closing which improves the network stability.
The synchrocheck function checks that the voltages on both sides of the circuit breaker are in
synchronism, or with at least one side dead to ensure that closing can be done safely.
The function includes a built-in voltage selection scheme for double bus and one- and a half or
ring busbar arrangements.
Manual closing as well as automatic reclosing can be checked by the function and can have dif-
ferent settings.
For systems which are running asynchronous a synchronizing function is provided. The main
purpose of the synchronizing function is to provide controlled closing of circuit breakers when
two asynchronous systems are going to be connected. It is used for slip frequencies that are larg-
er than those for synchrocheck and lower than a set maximum level for the synchronizing func-
tion.
The energizing check function measures the bus and line voltages and compares them to both
high and low threshold detectors. The output is only given when the actual measured quantities
match the set conditions.
The synchronizing measures the conditions across the circuit breaker, and it also determines the
angle change occurring during the closing delay of the circuit breaker, from the measured slip
frequency. The output is only given when all measured conditions are simultaneously within
their set limits. The issue of the output is timed to give closure at the optimal time including the
time for the circuit breaker and the closing circuit.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
For single circuit breaker and 1 1/2 circuit breaker arrangements, the SYN function blocks have
the capability to make the necessary voltage selection. For single circuit breaker arrangements,
selection of the correct voltage is made using auxiliary contacts of the bus disconnectors. For 1
1/2 circuit breaker arrangements, correct voltage selection is made using auxiliary contacts of
the bus disconnectors as well as the circuit breakers
The internal logic for each function block as well as the Input and Outputs and the setting pa-
rameters with default setting and setting ranges is described in this document. For application
related information, please refer to the Application manual.
Synchronism check
The voltage difference, frequency difference and phase angle difference values are measured in
the IED centrally and are available for the Synchrocheck function for evaluation. If the bus volt-
age is connected as phase-phase and the line voltage as phase-neutral (or the opposite), this need
to be compensated. This is done with a setting, which scales up the line voltage to a level equal
to the bus voltage.
When the function is set to OperationSC = On, the measuring will start.
The function will compare the bus and line voltage values with the set values for UHighBusSC
and UHighLineSC.
If both sides are higher than the set values the measured values are compared with the set values
for acceptable frequency, phase angle and voltage difference FreqDiff, PhaseDiff and UDiff. If
a compensation factor is set due to the use of different voltages on the Bus and Line, the factor
is deducted from the line voltage before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not
deviate from the rated frequency more than +/-5Hz. The frequency difference between the bus
frequency and the line frequency is measured and may not exceed the set value.
Two sets of settings for frequency difference and phase angle difference are available and used
for the Manual closing and Auto-Reclose functions respectively as required.
The inputs BLOCK and BLKSC are available for total block of the complete Synchrocheck
function and block of the Synchronism check function respectively. TSTSC will allow testing
of the function where the fulfilled conditions are connected to a separate test output
Two outputs MANSYOK resp. AUTOSYOK are activated when the actual measured conditions
match the set conditions for the respective output. The output signal can be delayed independent-
ly for MANSYOK conditions and for AUTOSYOK.
A number of outputs are available as information about fulfilled checking conditions. UOKSC
shows that the voltages are high, UDIFFSC, FRDIFFM/A, PHDIFFM/A shows when the volt-
age difference, frequency difference and phase angle difference conditions are met.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
Synchronizing
When the function is set to OperationSynch=On the measuring will be performed.
The function will compare the values for the bus and line voltage with the set values for UHigh-
BusSynch and UHighLineSynch which is a supervision that the voltages are both live. If both
sides are higher than the set values the measured values are compared with the set values for ac-
ceptable frequency, rate of change of frequency, phase angle and voltage difference FreqDiff-
Max, FreqDiffMin and UDiffSynch.
Measured frequencies between the settings for the maximum and minimum frequency will ini-
tiate the measuring and the evaluation of the angle change to allow operation to be sent in the
right moment including the set tBreaker time. There is a phase angle release internally to block
any incorrect closing pulses. At operation the SYNOK output will be activated with a pulse
tClosePulse and the function reset. The function will also reset if the syncronizing conditions
are not fulfilled within the set tMaxSynch time. This will then prevent that the functions is by
mistake maintained in operation a long time waiting for conditions to be fulfilled.
The inputs BLOCK and BLKSYNCH are available for total block of the complete function resp.
of the Synchronizing part.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
SYN1
OPERATION SYNCH
OFF
ON
TEST MODE
OFF
ON
STARTSYN SYNPROGR
AND
AND
S
BLKSYNCH
OR R
UDiffSynch
50 ms SYNOK
AND
UHighBusSynch AND t
UHighLineSynch OR
FreqDiffMax
AND
TSTSYNOK
FreqDiffMin OR
tClose
FreqRateChange Pulse
AND
fBus&fLine 5 Hz tMax
AND
Synch
PhaseDiff < 15 deg SYNFAIL
PhaseDiff=closing angle
en06000636.vsd
Figure 226: Simplified logic diagram for the synchronizing function
Energizing check
Voltage values are measured in the IED centrally and are available for evaluation by the Synch-
rocheck function. If the bus voltage is connected as phase-phase and the line voltage as
phase-neutral, (or the opposite) this needs to be compensated. This is done with a setting, which
scales the line voltage to a level equal to the bus voltage.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
The function measures voltages on the busbar and the line to verify whether they are live or dead.
This is done by comparing with the set values UHighBusEnerg and ULowBusEnerg for bus en-
ergizing and UHighBusEnergand ULowBusEnerg for line energizing.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not
deviate from the rated frequency more than +/-5Hz. The frequency difference between the bus
frequency and the line frequency is measured and shall not exceed a set value.
The Energizing direction can be selected individually for the Manual and the Automatic func-
tions respectively. When the conditions are met the outputs AUTOENOK and MANENOK re-
spectively will be activated if the fuse supervision conditions are fulfilled. The output signal can
be delayed independently for MANENOK conditions and for AUTOENOK. The Energizing di-
rection can also be selected by an integer input AENMODE resp MENMODE, which e.g. can
be connected to a Binary to Integer function block BI 16 (BAxx or BBxx). Integers supplied
shall be 1=off, 2=DLLB, 3=DBLL and 4= Both. Not connected input with connection of INTZ-
ERO output from Fixed Signals function block will mean that the setting is done from PST tool.
The active position can be read on outputs MODEAEN resp MODEMEN. The modes are
0=OFF, 1=DLLB, 2=DBLL and 3=Both.
The inputs BLOCK and BLKENERG are available for total block of the complete Synchrocheck
function resp. block of the Energizing check function. TSTENOK will allow testing of the func-
tion where the fulfilled conditions are connected to a separate test output.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
OperationSC = On
AND TSTAUTOSY
AND
TSTSC
BLKSC AND
BLOCK OR
AUTOSYOK
AND
0-60 s
AND t
tSCA
UDiffSC 50 ms
AND t
UHighBusSC
UOKSC
AND
UHighLineSC
UDIFFSC
1
FRDIFFA
FreqDiffA 1
PHDIFFA
PhaseDiffA 1
UDIFFME
voltageDifferenceValue
FRDIFFME
frequencyDifferenceValue
PHDIFFME
phaseAngleDifferenceValue
en07000114.vsd
Figure 227: Simplified logic diagram for the Synchrocheck function
Voltage selection
The voltage selection module including supervision of included voltage transformer fuses for
the different arrangements is a basic part of the Synchrocheck function and determines the pa-
rameters fed to the Synchronism check and Energizing check functions. This includes the selec-
tion of the appropriate Line and Bus voltages and fuse supervision.
The voltage selection type to be used is set with the parameter CBConfig. The different alterna-
tives are described below.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
If NoVoltageSel is set the default voltages used will be ULine1 and UBus1. This is also the case
when external voltage selection is provided. Fuse failure supervision for the used inputs must
also be connected.
The voltage selection function selected voltages and fuse conditions are the Synchronism check
and Energizing check inputs.
For the disconnector positions it is advisable to use (NO) a and (NC) b type contacts to supply
Disconnector Open and Closed positions but it is of course also possible to use an inverter for
one of the positions.
The SYN1(2)-UB1/2OK and SYN1(2)-UB1/2FF inputs are related to the busbar voltage and the
SYN1(2)-ULN1/2OK and SYN1(2)-ULN1/2FF inputs are related to the line voltage. Configure
them to the binary inputs or function outputs that indicate the status of the external fuse failure
of the busbar and line voltages. In the event of a fuse failure, the energizing check functions are
blocked. The synchronism check requires full voltage on both sides and will be blocked auto-
matically in the event of fuse failures.
The function also checks the fuse-failure signals for bus 1, bus 2 and line voltage transformers.
Inputs UB1OK-UB1FF supervise the fuse for Bus 1. UB2OK-UB2FF supervises the fuse for
Bus 2 and ULN1OK-ULN1FF supervises the fuse for the Line voltage transformer. The inputs
fail (FF) or healthy (OK) can alternatively be used dependent on the available signal. If a
fuse-failure is detected in the selected voltage source an output signal USELFAIL is set. This
output signal is true if the selected bus or line voltages have a fuse failure. This output as well
as the function can be blocked with the input signal BLOCK. The function logic diagram is
shown in figure 228.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
B1QOPEN
B1SEL
B1QCLD AND
B2QOPEN B2SEL
1
B2QCLD AND
AND invalidSelection
bus1Voltage
busVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR
AND selectedFuseOK
UB2OK AND
UB2FF OR USELFAIL
AND
ULN1OK
ULN1FF OR
BLOCK
en05000779.vsd
Figure 228: Logic diagram for the voltage selection function of a single circuit breaker with
double busbars
This voltage selection function uses the binary inputs from the disconnectors and circuit break-
ers auxiliary contacts to select the right voltage for the Synchrocheck (Synchronism and Ener-
gizing check) function. For the bus circuit breaker one side of the circuit breaker is connected to
the busbar and the other side is connected either to line 1, line 2 or the other busbar depending
on the arrangement.
The fuse supervision is connected to ULNOK-ULNFF etc. and with alternative Healthy or Fail-
ing fuse signals depending on what is available for each of fuse (MCB).
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
The tie circuit breaker is connected either to bus 1 or line 1 on one side and the other side is con-
nected either to bus 2 or line 2. Four different output combinations are possible, bus to bus, bus
to line, line to bus and line to line.
The function also checks the fuse-failure signals for bus 1, bus 2, line 1 and line 2. If a fuse-fail-
ure is detected in the selected voltage an output signal USELFAIL is set. This output signal is
true if the selected bus or line voltages have a fuse failure. This output as well as the function
can be blocked with the input signal BLOCK.The function block diagram for the voltage selec-
tion of a bus circuit breaker is shown in Figure 229: and for the tie circuit breaker in Figure 230:
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
LN1QOPEN
AND
LN1SEL
LN1QCLD
B1QOPEN
LN2SEL
B1QCLD AND AND
OR
B2SEL
LN2QOPEN
LN2QCLD AND
AND invalidSelection
AND
B2QOPEN
B2QCLD AND
line1Voltage
lineVoltage
line2Voltage
bus2Voltage
UB1OK
UB1FF OR
OR
UB2OK AND
AND selectedFuseOK
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000780.vsd
Figure 229: Simplified logic diagram for the voltage selection function for a bus circuit break-
er in a 1 1/2 breaker arrangement.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
LN1QOPEN
LN1SEL
LN1QCLD AND
B1SEL
1
B1QOPEN AND
AND
B1QCLD AND
line1Voltage
busVoltage
bus1Voltage
LN2QOPEN
LN2SEL
LN2QCLD AND
B2SEL
1
OR invalidSelection
B2QOPEN AND
AND
B2QCLD AND
line2Voltage
lineVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR
UB2OK AND selectedFuseOK
AND
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000781.vsd
Figure 230: Simplified logic diagram for the voltage selection function for the tie circuit break-
er in 1 1/2 breaker arrangement.
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Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
SYN1-
SESRSYN_25
U3PBB1 SYNOK
U3PBB2 AUTOSYOK
U3PLN1 AUTOENOK
U3PLN2 MANSYOK
BLOCK MANENOK
BLKSYNCH TSTSYNOK
BLKSC TSTAUTSY
BLKENERG TSTMANSY
B1QOPEN TSTENOK
B1QCLD USELFAIL
B2QOPEN B1SEL
B2QCLD B2SEL
LN1QOPEN LN1SEL
LN1QCLD LN2SEL
LN2QOPEN SYNPROGR
LN2QCLD SYNFAIL
UB1OK UOKSYN
UB1FF UDIFFSYN
UB2OK FRDIFSYN
UB2FF FRDIFFOK
ULN1OK FRDERIVA
ULN1FF UOKSC
ULN2OK UDIFFSC
ULN2FF FRDIFFA
STARTSYN PHDIFFA
TSTSYNCH FRDIFFM
TSTSC PHDIFFM
TSTENERG UDIFFME
AENMODE FRDIFFME
MENMODE PHDIFFME
MODEAEN
MODEMEN
en06000534.vsd
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Synchronizing, synchrocheck and energizing Chapter 11
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Signal Description
B2QCLD Close status for CB or disconnector connected to bus2
LN1QOPEN Open status for CB or disconnector connected to line1
LN1QCLD Close status for CB or disconnector connected to line1
LN2QOPEN Open status for CB or disconnector connected to line2
LN2QCLD Close status for CB or disconnector connected to line2
UB1OK Bus1 voltage transformer OK
UB1FF Bus1 voltage transformer fuse failure
UB2OK Bus2 voltage transformer OK
UB2FF Bus2 voltage transformer fuse failure
ULN1OK Line1 voltage transformer OK
ULN1FF Line1 voltage transformer fuse failure
ULN2OK Line2 voltage transformer OK
ULN2FF Line2 voltage transformer fuse failure
STARTSYN Start synchronizing
TSTSYNCH Set synchronizing in test mode
TSTSC Set synchro check in test mode
TSTENERG Set energizing check in test mode
AENMODE Input for setting of automatic energizing mode
MENMODE Input for setting of manual energizing mode
Table 252: Output signals for the SESRSYN_25 (SYN1-) function block
Signal Description
SYNOK Synchronizing OK output
AUTOSYOK Auto synchro check OK
AUTOENOK Automatic energizing check OK
MANSYOK Manual synchro check OK
MANENOK Manual energizing check OK
TSTSYNOK Synchronizing OK test output
TSTAUTSY Auto synchro check OK test output
TSTMANSY Manual synchro check OK test output
TSTENOK Energizing check OK test output
USELFAIL Selected voltage transformer fuse failed
B1SEL Bus1 selected
B2SEL Bus2 selected
LN1SEL Line1 selected
LN2SEL Line2 selected
SYNPROGR Synchronizing in progress
SYNFAIL Synchronizing failed
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Signal Description
UOKSYN Voltage amplitudes for synchronizing above set limits
UDIFFSYN Voltage difference out of limit for synchronizing
FRDIFSYN Frequency difference out of limit for synchronizing
FRDIFFOK Frequency difference in band for synchronizing
FRDERIVA Frequency derivative out of limit for synchronizing
UOKSC Voltage amplitudes above set limits
UDIFFSC Voltage difference out of limit
FRDIFFA Frequency difference out of limit for Auto operation
PHDIFFA Phase angle difference out of limit for Auto operation
FRDIFFM Frequency difference out of limit for Manual operation
PHDIFFM Phase angle difference out of limit for Manual Operation
UDIFFME Calculated difference in voltage
FRDIFFME Calculated difference in frequency
PHDIFFME Calculated difference of phase angle
MODEAEN Selected mode for automatic energizing
MODEMEN Selected mode for manual energizing
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check (RSYN, 25) Control
501
Synchronizing, synchrocheck and energizing Chapter 11
check (RSYN, 25) Control
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Synchronizing, synchrocheck and energizing Chapter 11
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Apparatus control (APC) Chapter 11
Control
2.1 Introduction
The apparatus control is a function for control and supervision of circuit breakers, disconnectors
and earthing switches within a bay. Permission to operate is given after evaluation of conditions
from other functions such as interlocking, synchrocheck, operator place selection and external
or internal blockings.
The function sends information about the Permitted Source To Operate (PSTO) and blocking
conditions to other functions within the bay e.g. switch control functions, voltage control func-
tions and measurement functions.
When the local panel switch is in Off position all commands from remote and local level will be
ignored. If the position for the local/remote switch is not valid the PSTO output will always be
set to faulty state (3), which means no possibility to operate.
To adapt the signals from the local HMI or from an external local/remote switch, the function
blocks LocalRemote and LocRemControl are needed and connected to QCBAY. For more in-
formation, see section 2.3 "Local/Remote switch (LocalRemote, LocRemControl)".
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Apparatus control (APC) Chapter 11
Control
Table 255: PSTO values for different Local panel switch positions
Local panel switch PSTO value AllPSTOValid Possible locations that shall be able
positions (configuration to operate
parameter)
0 = Off 0 -- Not possible to operate
1 = Local 1 FALSE Local Panel
1 = Local 5 TRUE Local or Remote level without any priority
2 = Remote 2 FALSE Remote level
2 = Remote 5 TRUE Local or Remote level without any priority
3 = Faulty 3 -- Not possible to operate
Blockings
The blocking states for position indications and commands are intended to provide the possibil-
ity for the user to make common blockings for the functions configured within a complete bay.
The blocking facilities provided by the bay control function are the following:
Blocking of position indications, BL_UPD. This input will block all inputs relat-
ed to apparatus positions for all configured functions within the bay.
Blocking of commands, BL_CMD. This input will block all commands for all
configured functions within the bay.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC
6185081). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
The switching of the Local/Remote switch requires at least system operator level. The password
will be requested at an attempt to operate if authority levels have been defined in the IED. Oth-
erwise the default authority level, SuperUser, can handle the control without LogOn. The users
and passwords are defined with the UMT.
CB01-
QCBAY
LR_OFF PSTO
LR_LOC UPD_BLKD
LR_REM CMD_BLKD
LR_VALID
BL_UPD
BL_CMD
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Table 257: Output signals for the QCBAY (CB01-) function block
Signal Description
PSTO The value for the operator place allocation
UPD_BLKD The update of position is blocked
CMD_BLKD The function is blocked for commands
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Apparatus control (APC) Chapter 11
Control
LR01- CB01-
LocalRemote QCBAY
CTRLOFF OFF LR_OFF PSTO
LOCCTRL LOCAL LR_LOC UPD_BLKD
REMCTRL REMOTE LR_REM CMD_BLKD
LHMICTRL VALID LR_VALID
BL_UPD
BL_CMD
LR02- CB02-
LocalRemote QCBAY
CTRLOFF OFF LR_OFF PSTO
LOCCTRL LOCAL LR_LOC UPD_BLKD
REMCTRL REMOTE LR_REM CMD_BLKD
LHMICTRL VALID LR_VALID
BL_UPD
BL_CMD
LRC1-
LocRemControl
PSTO1 HMICTR1
PSTO2 HMICTR2
PSTO3 HMICTR3
PSTO4 HMICTR4
PSTO5 HMICTR5
PSTO6 HMICTR6
PSTO7 HMICTR7
PSTO8 HMICTR8
PSTO9 HMICTR9
PSTO10 HMICTR10
PSTO11 HMICTR11
PSTO12 HMICTR12
en05000250.vsd
Figure 233: Configuration for the local/remote handling for a local LCD HMI with two bays
and two screen pages
If the IED contains control functions for several bays, the local/remote position can be different
for the included bays. When the local LCD HMI is used the position of the local/remote switch
can be different depending on which single line diagram screen page that is presented on the lo-
cal HMI. The function block LocRemControl controls the presentation of the LEDs for the lo-
cal/remote position to applicable bay and screen page.
The switching of the Local/Remote switch requires at least system operator level. The password
will be requested at an attempt to operate if authority levels have been defined in the IED. Oth-
erwise the default authority level, SuperUser, can handle the control without LogOn. The users
and passwords are defined with the UMT.
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Apparatus control (APC) Chapter 11
Control
LR01-
LocalRemote
CT RLOFF OFF
LOCCT RL LOCAL
REMCT RL REMOT E
LHMICT RL VALID
en05000360.vsd
LRC1-
LocRemControl
PST O1 HMICT R1
PST O2 HMICT R2
PST O3 HMICT R3
PST O4 HMICT R4
PST O5 HMICT R5
PST O6 HMICT R6
PST O7 HMICT R7
PST O8 HMICT R8
PST O9 HMICT R9
PST O10 HMICT R10
PST O11 HMICT R11
PST O12 HMICT R12
en05000361.vsd
Table 260: Output signals for the LocalRemote (LR01-) function block
Signal Description
OFF Control is disabled
LOCAL Local control is activated
REMOTE Remote control is activated
VALID Outputs are valid
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Table 261: Input signals for the LocRemControl (LRC1-) function block
Signal Description
PSTO1 PSTO input channel 1
PSTO2 PSTO input channel 2
PSTO3 PSTO input channel 3
PSTO4 PSTO input channel 4
PSTO5 PSTO input channel 5
PSTO6 PSTO input channel 6
PSTO7 PSTO input channel 7
PSTO8 PSTO input channel 8
PSTO9 PSTO input channel 9
PSTO10 PSTO input channel 10
PSTO11 PSTO input channel 11
PSTO12 PSTO input channel 12
Table 262: Output signals for the LocRemControl (LRC1-) function block
Signal Description
HMICTR1 Bitmask output 1 to local remote LHMI input
HMICTR2 Bitmask output 2 to local remote LHMI input
HMICTR3 Bitmask output 3 to local remote LHMI input
HMICTR4 Bitmask output 4 to local remote LHMI input
HMICTR5 Bitmask output 5 to local remote LHMI input
HMICTR6 Bitmask output 6 to local remote LHMI input
HMICTR7 Bitmask output 7 to local remote LHMI input
HMICTR8 Bitmask output 8 to local remote LHMI input
HMICTR9 Bitmask output 9 to local remote LHMI input
HMICTR10 Bitmask output 10 to local remote LHMI input
HMICTR11 Bitmask output 11 to local remote LHMI input
HMICTR12 Bitmask output 12 to local remote LHMI input
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Apparatus control (APC) Chapter 11
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Command handling
Two types of command models can be used. The two command models are "direct with en-
hanced security" and "SBO (Select-Before-Operate) with enhanced security". Which one of
these two command models that are used is defined by the parameter CtlModel. The meaning
with "direct with enhanced security" model is that no select is required. The meaning with "SBO
with enhanced security" model is that a select is required before execute.
In this function only commands with enhanced security is supported regarding changing of the
position. With enhanced security means that the command sequence is supervised in three steps,
the selection, command evaluation and the supervision of position. Each step ends up with a
pulsed signal to indicate that the respective step in the command sequence is finished. If an error
occurs in one of the steps in the command sequence, the sequence is terminated and the error is
mapped into the enumerated variable "cause" attribute belonging to the pulsed response signal
for the IEC61850 communication. The last cause L_CAUSE can be read from the function block
and used for example at commissioning. The meaning of the cause signals can be found in table
2.
Note!
There is not any relation between the command direction and the actual position. For example,
if the switch is in close position it is possible to execute a close command.
Before an executing command, an evaluation of the position is done. If the parameter PosDe-
pendent is true and the position is in intermediate state or in bad state no executing command is
send. If the parameter is false the execution command is send independent of the position value.
Evaluation of position
In the case when there are three one-phase switches connected to the switch control function, the
switch control will "merge" the position of the three switches to the resulting three-phase posi-
tion. In the case when the position differ between the one-phase switches, following principles
will be applied:
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Apparatus control (APC) Chapter 11
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The time stamp of the output three-phase position from switch control will have the time stamp
of the last changed phase when it goes to end position. When it goes to intermediate position or
bad state, it will get the time stamp of the first changed phase.
In addition, there is also the possibility that one of the one-phase switches will change position
at any time due to a trip. Such situation is here called pole discordance and is supervised by this
function. In case of a pole discordance situation, i.e. the position of the one-phase switches are
not equal for a time longer than the setting tPoleDiscord, an error signal POLEDISC will be set.
In the supervision phase, the switch controller function evaluates the "cause" values from the
switch modules XCBR/XSWI. At error the "cause" value with highest priority is shown.
Blocking principles
The blocking signals are normally coming from the bay control function (QCBAY) and via the
IEC61850 communication from the operator place.
Note!
The different block conditions will only affect the operation of this function, i.e. no blocking sig-
nals will be "forwarded" to other functions. The above blocking outputs are stored in a non-vol-
atile memory.
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When there is no positive confirmation from the synchrocheck function, the SCSWI will send a
start signal START_SY to the synchronizing function, which will send the closing command to
the SXCBR when the synchronizing conditions are fulfilled, see figure 236. If no synchronizing
function is included, the timer for supervision of the "synchronizing in progress signal" is set to
0, which means no start of the synchronizing function. The SCSWI will then set the attribute
"blocked-by-synchrocheck" in the "cause" signal. See also the time diagram in figure 240.
SCSWI SXCBR
EXE_CL
OR CLOSE
SYNC_OK
START_SY
SY_INPRO
SECRSYN
CLOSE. CB
Synchro Synchronizing
Check function
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Figure 236: Example of interaction between SCSWI, SECRSYN (synchrocheck and synchroniz-
ing function) and SXCBR function
Time diagrams
The SCSWI function has timers for evaluating different time supervision conditions. These tim-
ers are explained here.
The timer tSelect is used for supervising the time between the select and the execute command
signal, i.e. the time the operator has to perform the command execution after the selection of the
object to operate.
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Apparatus control (APC) Chapter 11
Control
select
execute command
tSelect
timer t1 t1>tSelect, then long-
operation-time in 'cause'
is set
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The parameter tResResponse is used to set the maximum allowed time to make the reservation,
i.e. the time between reservation request and the feedback reservation granted from all bays in-
volved in the reservation function.
select
command termination
tResResponse t1>tResResponse, then
timer 1-of-n-control in 'cause'
t1 is set
en05000093.vsd
The timer tExecutionFB supervises the time between the execute command and the command
termination, see figure 239.
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execute command
position L1 open
close
position L2 open
close
position L3 open
close
cmd termination L1
cmd termination L2
cmd termination L3
cmd termination *
position open
close
The parameter tSynchrocheck is used to define the maximum allowed time between the execute
command and the input SYNC_OK to become true. If SYNC_OK=true at the time the execute
command signal is received, the timer "tSynchrocheck" will not start. The start signal for the
synchronizing is obtained if the synchrocheck conditions are not fulfilled.
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Control
execute command
SYNC_OK
tSynchrocheck
t1
START_SY
SY_INPRO
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Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table 264 describes vendor specific cause values in addition to these specified in
IEC 61850-8-1 standard. The list of values of the cause are in order of priority. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
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CS01-
SCSWI
BLOCK EXE_OP
PSTO EXE_CL
L_SEL SELECTED
L_OPEN RES_RQ
L_CLOSE START_SY
AU_OPEN POSITION
AU_CLOSE OPENPOS
BL_CMD CLOSEPOS
RES_GRT POLEDISC
RES_EXT CMD_BLK
SY_INPRO L_CAUSE
SYNC_OK XOUT
EN_OPEN
EN_CLOSE
XPOS1
XPOS2
XPOS3
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Table 266: Output signals for the SCSWI (CS01-) function block
Signal Description
EXE_OP Execute command for open direction
EXE_CL Execute command for close direction
SELECTED The select conditions are fulfilled
RES_RQ Request signal to the reservation function
START_SY Starts the synchronizing function
POSITION Position indication
OPENPOS Open position indication
CLOSEPOS Closed position indication
POLEDISC The positions for poles L1-L3 are not equal after a set time
CMD_BLK Commands are blocked
L_CAUSE Latest value of the error indication during command
XOUT Execution information to XCBR/XSWI
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The function has an operation counter for closing and opening commands. The counter value
can be read remotely from the operator place. The value is reset from a binary input or remotely
from the operator place.
Local/Remote switch
One binary input signal LR_SWI is included in this function to indicate the local/remote switch
position from switchyard provided via the I/O board. If this signal is set to TRUE it means that
change of position is allowed only from switchyard level. If the signal is set to FALSE it means
that command from IED or higher level is permitted. When the signal is set to TRUE all com-
mands (for change of position) from internal IED clients are rejected, even trip commands from
protection functions are rejected. The functionality of the local/remote switch is described in
figure 242.
Local= Operation at
UE switch yard level
TR
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Blocking principles
The function includes several blocking principles. The basic principle for all blocking signals is
that they will affect commands from all other clients e.g. operators place, protection functions,
autoreclosure etc.
Block/deblock for open command. It is used to block operation for open com-
mand. Note that this block signal also affects the input OPEN for immediate com-
mand.
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Block/deblock for close command. It is used to block operation for close com-
mand. Note that this block signal also affects the input CLOSE for immediate
command.
Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior
(IEC61850). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
Substitution
The substitution part in this function is used for manual set of the position for the switch. The
typical use of substitution is that an operator enters a manual value because that the real process
value is erroneous of some reason. The function will then use the manually entered value instead
of the value for positions determined by the process.
Note!
It is always possible to make a substitution, independently of the position indication and the sta-
tus information of the I/O board. When substitution is enabled, the position values are blocked
for updating and other signals related to the position are reset. The substituted values are stored
in a non-volatile memory.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStart-
Move supervises that the primary device starts moving after the execute output pulse is sent. tIn-
termediate defines the maximum allowed time for intermediate position. Figure 243 explains
these two timers during the execute phase.
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OPENPOS
CLOSEPOS
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The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to
the primary equipment. Note that the output pulses for open and close command can have dif-
ferent pulse lengths. The pulses can also be set to be adaptive with the configuration parameter
AdaptivePulse. Figure 244 shows the principle of the execute output pulse. The adaptively pa-
rameter will have affect on both execute output pulses.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
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If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or
tClosePulse.
the new expected final position is reached and the configuration parameter Adap-
tivePulse is set to true
the timer tOpenPulse or tClosePulse has elapsed
an error occurs due to the switch does not start moving, i.e. tStartMove has
elapsed.
Note!
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is
executed the execute output pulse resets only when timer "tOpenPulse" or "tClosePulse" has
elapsed.
There is one exception from the first item above. If the primary device is in open position and
an open command is executed or if the primary device is in close position and a close command
is executed. In these cases, with the additional condition that the configuration parameter Adap-
tivePulse is true, the execute output pulse is always activated and resets when tStartMove has
elapsed. If the configuration parameter AdaptivePulse is set to false the execution output re-
mains active until the pulse duration timer has elapsed.
An example of when a primary device is open and an open command is executed is shown in
figure 245 .
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
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Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table 268 describes vendor specific cause values in addition to these specified in
IEC 61850-8-1 standard. The list of values of the cause are in order of priority. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
Table 268: Vendor specific cause values for Apparatus control in priority order
Apparatus control Description
function
22 wrongCTLModel
23 blockedForCommand
24 blocked-for-open-command
25 blocked-for-close-command
30 longOperationTime
31 switch-not-start-moving
32 persistent-intermediate-state
33 switch-returned-to-initial-position
34 switch-in-bad-state
35 not-expected-final-position
XC01-
SXCBR
BLOCK GRPConABS1
LR_SWI EXE_OP
OPEN GRPConABS2
CLOSE EXE_CL
BL_OPEN SUBSTED
BL_CLOSE OP_BLKD
BL_UPD CL_BLKD
POSOPEN UPD_BLKD
POSCLOSE POSITION
TR_OPEN OPENPOS
TR_CLOSE CLOSEPOS
RS_CNT TR_POS
XIN CNT_VAL
TERVALUE L_CAUSE
OSEVALUE
PENVALUE
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Table 270: Output signals for the SXCBR (XC01-) function block
Signal Description
XPOS Group signal for XCBR output
EXE_OP Executes the command for open direction
EXE_CL Executes the command for close direction
SUBSTED Indication that the position is substituted
OP_BLKD Indication that the function is blocked for open commands
CL_BLKD Indication that the function is blocked for close commands
UPD_BLKD The update of position indication is blocked
POSITION Apparatus position indication
OPENPOS Apparatus open position
CLOSEPOS Apparatus closed position
TR_POS Truck position indication
CNT_VAL The value of the operation counter
L_CAUSE Latest value of the error indication during command
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The function has an operation counter for closing and opening commands. The counter value
can be read remotely from the operator place. The value is reset from a binary input or remotely
from the operator place.
Local/Remote switch
One binary input signal LR_SWI is included in this function to indicate the local/remote switch
position from switchyard provided via the I/O board. If this signal is set to TRUE it means that
change of position is allowed only from switchyard level. If the signal is set to FALSE it means
that command from IED or higher level is permitted. When the signal is set to TRUE all com-
mands (for change of position) from internal IED clients are rejected, even trip commands from
protection functions are rejected. The functionality of the local/remote switch is described in
figure 247.
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Apparatus control (APC) Chapter 11
Control
Local= Operation at
UE switch yard level
TR
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Blocking principles
The function includes several blocking principles. The basic principle for all blocking signals is
that they will affect commands from all other clients e.g. operators place, protection functions,
autoreclosure etc.
Block/deblock for open command. It is used to block operation for open com-
mand. Note that this block signal also affects the input OPEN for immediate com-
mand.
Block/deblock for close command. It is used to block operation for close com-
mand. Note that this block signal also affects the input CLOSE for immediate
command.
Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior
(IEC61850). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
Substitution
The substitution part in this function is used for manual set of the position for the switch. The
typical use of substitution is that an operator enters a manual value because that the real process
value is erroneous of some reason. The function will then use the manually entered value instead
of the value for positions determined by the process.
Note!
It is always possible to make a substitution, independently of the position indication and the sta-
tus information of the I/O board. When substitution is enabled, the position values are blocked
for updating and other signals related to the position are reset. The substituted values are stored
in a non-volatile memory.
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Apparatus control (APC) Chapter 11
Control
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStart-
Move supervises that the primary device starts moving after the execute output pulse is sent. tIn-
termediate defines the maximum allowed time for intermediate position. Figure 248 explains
these two timers during the execute phase.
OPENPOS
CLOSEPOS
en05000097.vsd
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to
the primary equipment. Note that the output pulses for open and close command can have dif-
ferent pulse lengths. The pulses can also be set to be adaptive with the configuration parameter
AdaptivePulse. Figure 249 shows the principle of the execute output pulse. The adaptively pa-
rameter will have affect on both execute output pulses.
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Apparatus control (APC) Chapter 11
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OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
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If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or
tClosePulse.
the new expected final position is reached and the configuration parameter Adap-
tivePulse is set to true
the timer tOpenPulse or tClosePulse has elapsed
an error occurs due to the switch does not start moving, i.e. tStartMove has
elapsed.
Note!
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is
executed the execute output pulse resets only when timer "tOpenPulse" or "tClosePulse" has
elapsed.
There is one exception from the first item above. If the primary device is in open position and
an open command is executed or if the primary device is in close position and a close command
is executed. In these cases, with the additional condition that the configuration parameter Adap-
tivePulse is true, the execute output pulse is always activated and resets when tStartMove has
elapsed. If the configuration parameter AdaptivePulse is set to false the execution output re-
mains active until the pulse duration timer has elapsed.
An example when a primary device is open and an open command is executed is shown in
figure 250.
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Apparatus control (APC) Chapter 11
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OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
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Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table 272 describes vendor specific cause values in addition to these specified in
IEC 61850-8-1 standard. The list of values of the cause are in order of priority. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
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Apparatus control (APC) Chapter 11
Control
XS01-
SXSWI
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE SUBSTED
BL_OPEN OP_BLKD
BL_CLOSE CL_BLKD
BL_UPD UPD_BLKD
POSOPEN POSITION
POSCLOSE OPENPOS
RS_CNT CLOSEPOS
XIN CNT_VAL
L_CAUSE
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Table 274: Output signals for the SXSWI (XS01-) function block
Signal Description
XPOS Group signal for XSWI output
EXE_OP Executes the command for open direction
EXE_CL Executes the command for close direction
SUBSTED Indication that the position is substituted
OP_BLKD Indication that the function is blocked for open commands
CL_BLKD Indication that the function is blocked for close commands
UPD_BLKD The update of position indication is blocked
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Signal Description
POSITION Apparatus position indication
OPENPOS Apparatus open position
CLOSEPOS Apparatus closed position
CNT_VAL The value of the operation counter
L_CAUSE Latest value of the error indication during command
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Apparatus control (APC) Chapter 11
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The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay only (TRUE)
or other bays (FALSE). To reserve the own bay only means that no reservation request
RES_BAYS is created.
If the RESERVED output is not set, the selection is made with the output RES_GRTx (where
x=1-8 is the number of the requesting apparatus), which is connected to switch controller SC-
SWI. If the bay already is reserved the command sequence will be reset and the SCSWI will set
the attribute "1-of-n-control" in the "cause" signal.
When it receives acknowledge from the bays via the input RES_DATA, it sets the output
RES_GRTx (where x=1-8 is the number of the requesting apparatus). If not acknowledgement
from all bays is received within a certain time defined in SCSWI (tResResponse), the SCSWI
will reset the reservation and set the attribute "1-of-n-control" in the "cause" signal.
The reservation function can also be overridden in the own bay with the OVERRIDE input sig-
nal, i.e. reserving the own bay without waiting for the external acknowledge.
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Apparatus control (APC) Chapter 11
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If there are more than eight apparatuses in the bay there has to be one additional QCRSV. The
both functions QCRSV have to communicate and this is done through the input EXCH_IN and
EXCH_OUT according to figure 10. If more then one QCRSV are used, the execution order is
very important. The execution order must be in the way that the first QCRSV has a lower number
than the next one.
CR01-
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLK_RES ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
CR02-
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_BAYS
RES_RQ2 RES_GRT3 1
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6 ACK_TO_B
RES_RQ6 RES_GRT7 1
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLK_RES ACK_TO_B
1 RESERVED
OVERRIDE RESERVED
RES_DATA EXCH_OUT
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CR01-
QCRSV
EXCH_IN RES_GRT 1
RES_RQ1 RES_GRT 2
RES_RQ2 RES_GRT 3
RES_RQ3 RES_GRT 4
RES_RQ4 RES_GRT 5
RES_RQ5 RES_GRT 6
RES_RQ6 RES_GRT 7
RES_RQ7 RES_GRT 8
RES_RQ8 RES_BAYS
BLK_RES ACK_T O_B
OVERRIDE RESERVED
RES_DAT A EXCH_OUT
en05000340.vsd
Table 277: Output signals for the QCRSV (CR01-) function block
Signal Description
RES_GRT1 Reservation is made and the app. 1 is allowed to operate
RES_GRT2 Reservation is made and the app. 2 is allowed to operate
RES_GRT3 Reservation is made and the app. 3 is allowed to operate
RES_GRT4 Reservation is made and the app. 4 is allowed to operate
RES_GRT5 Reservation is made and the app. 5 is allowed to operate
RES_GRT6 Reservation is made and the app. 6 is allowed to operate
RES_GRT7 Reservation is made and the app. 7 is allowed to operate
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Apparatus control (APC) Chapter 11
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Signal Description
RES_GRT8 Reservation is made and the app. 8 is allowed to operate
RES_BAYS Request for reservation of other bays
ACK_TO_B Acknowledge to other bays that this bay is reserved
RESERVED Indicates that the bay is reserved
EXCH_OUT Used for exchange signals between different BayRes blocks
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Apparatus control (APC) Chapter 11
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EXCH_IN INT
BIN
ACK_F_B
&
FutureUse
1
ANY_ACK
BAY_ACK 1
VALID_TX
&
BAY_VAL 1
RE_RQ_B
1
BAY_RES &
V _RE_RQ
1
BIN
EXCH_OUT
INT
en05000089.vsd
Figure 255 describes the principle of the data exchange between all RESIN modules in the cur-
rent bay. There is one RESIN function block per "other bay" used in the reservation mechanism.
The output signal EXCH_OUT in the last RESIN functions block are connected to the module
QCRSV that handles the reservation function in the own bay. The value to the input EXCH_IN
on the first RESIN module in the chain has the integer value 5. This is provided by the use of
instance number one of the function block RESIN (RE01-), where the input EXCH_IN is set to
#5, but is hidden for the user.
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Apparatus control (APC) Chapter 11
Control
RE01-
RESIN
BAY_ACK ACK_F_B
Bay 1 BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RE02-
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay 2 BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
REnn-
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
CR01-
Bay n BAY_VAL VALID_TX
BAY_RES RE_RQ_B QCRSV
V_RE_RQ
EXCH_OUT RES_DATA
en05000090.vsd
RE01-
RESIN
BAY_ACK ACK_F_B
BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
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Table 280: Output signals for the RESIN (RE01-) function block
Signal Description
ACK_F_B All other bays have acknow. the reserv. req. from this bay
ANY_ACK Any other bay has acknow. the reserv. req. from this bay
VALID_TX The reserv. and acknow. signals from other bays are valid
RE_RQ_B Request from other bay to reserve this bay
V_RE_RQ Check if the request of reserving this bay is valid
EXCH_OUT Used for exchange signals between different ResIn blocks
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Interlocking Chapter 11
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3 Interlocking
3.1 Introduction
The interlocking function blocks the possibility to operate high-voltage switching devices, for
instance when a disconnector is under load, in order to prevent material damage and/or acciden-
tal human injury.
Each control IED has interlocking functions for different switchyard arrangements, each han-
dling the interlocking of one bay. The function is distributed to each control IED and not depen-
dent on any central function. For the station-wide interlocking, the IEDs communicate via the
station bus or by using hard wired binary inputs/outputs.
The interlocking conditions depend on the circuit configuration and status of the installation at
any given time.
The reservation function (see section 2 "Apparatus control (APC)") is used to ensure that HV
apparatuses that might affect the interlock are blocked during the time gap, which arises between
position updates. This can be done by means of the communication system, reserving all HV ap-
paratuses that might influence the interlocking condition of the intended operation. The reserva-
tion is maintained until the operation is performed.
After the selection and reservation of an apparatus, the function has complete data on the status
of all apparatuses in the switchyard that are affected by the selection. Other operators cannot in-
terfere with the reserved apparatus or the status of switching devices that may affect it.
The open or closed positions of the HV apparatuses are inputs to software modules distributed
in the control IEDs. Each module contains the interlocking logic for a bay. The interlocking log-
ic in a module is different, depending on the bay function and the switchyard arrangements, that
is, double-breaker or 1 1/2 breaker bays have different modules. Specific interlocking conditions
and connections between standard interlocking modules are performed with an engineering tool.
Bay-level interlocking signals can include the following kind of information:
The interlocking module is connected to the surrounding functions within a bay as shown in fig-
ure 257.
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Interlocking Chapter 11
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Apparatus control
Interlocking
modules
modules in
SCILO SCSWI SXSWI
other bays
Apparatus control
modules
Interlocking SCILO SCSWI SXCBR
module
Apparatus control
modules
en04000526.vsd SCILO SCSWI SXSWI
Bays communicate via the station bus and can convey information regarding the following:
Unearthed busbars
Busbars connected together
Other bays connected to a busbar
Received data from other bays is valid
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Interlocking Chapter 11
Control
Station bus
Disc QB1 and QB2 closed Disc QB1 and QB2 closed WA1 unearthed
WA1 unearthed
WA1 and WA2 interconn
WA1 not earthed WA1 not earthed
WA2 not earthed
WA1 and WA2 interconn
... WA2 not earthed
WA1 and WA2 interconn
WA1 and WA2 interconn
in other bay
..
WA1
WA2
QB1 QB2 QB1 QB2 QB1 QB2 QC1 QC2
QB9 QB9
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Figure 258: Data exchange between interlocking modules.
When invalid data such as intermediate position, loss of a control terminal, or input board error
are used as conditions for the interlocking condition in a bay, a release for execution of the func-
tion will not be given.
On the station HMI an override function exists, which can be used to bypass the interlocking
function in cases where not all the data required for the condition is valid.
540
Interlocking Chapter 11
Control
To make the implementation of the interlocking function easier, a number of standardized and
tested software interlocking modules containing logic for the interlocking conditions are avail-
able:
The interlocking conditions can be altered, to meet the customers specific requirements, by add-
ing configurable logic by means of the graphical configuration tool PCM 600. The inputs
Qx_EXy on the interlocking modules are used to add these specific conditions.
The input signals EXDU_xx shall be set to true if there is no transmission error at the transfer
of information from other bays. Required signals with designations ending in TR are intended
for transfer to other bays.
541
Interlocking Chapter 11
Control
POSOPEN SCILO
POSCLOSE =1 1
EN_OPEN
&
>1
&
OPEN_EN
CLOSE_EN & EN_CLOSE
>1
&
en04000525.vsd
CI01-
SCILO
POSOPEN EN_OPEN
POSCLOSE EN_CLOSE
OPEN_EN
CLOSE_EN
en05000359.vsd
Table 283: Output signals for the SCILO (CI01-) function block
Signal Description
EN_OPEN Open operation at closed or interm. or bad pos. is enabled
EN_CLOSE Close operation at open or interm. or bad pos. is enabled
542
Interlocking Chapter 11
Control
W A1 (A)
W A2 (B)
W A7 (C)
QB1 QB2 QB7
QC1
QA1
QC2
QB9
QC9
en04000478.vsd
543
Interlocking Chapter 11
Control
IF01-
ABC_LINE
QA1_OP QA1CLREL
QA1_CL QA1CLIT L
QB9_OP QB9REL
QB9_CL QB9IT L
QB1_OP QB1REL
QB1_CL QB1IT L
QB2_OP QB2REL
QB2_CL QB2IT L
QB7_OP QB7REL
QB7_CL QB7IT L
QC1_OP QC1REL
QC1_CL QC1IT L
QC2_OP QC2REL
QC2_CL QC2IT L
QC9_OP QC9REL
QC9_CL QC9IT L
QC11_OP QB1OPT R
QC11_CL QB1CLT R
QC21_OP QB2OPT R
QC21_CL QB2CLT R
QC71_OP QB7OPT R
QC71_CL QB7CLT R
BB7_D_OP QB12OPT R
BC_12_CL QB12CLT R
BC_17_OP VPQB1T R
BC_17_CL VPQB2T R
BC_27_OP VPQB7T R
BC_27_CL VPQB12T R
VOLT _OFF
VOLT _ON
VP_BB7_D
VP_BC_12
VP_BC_17
VP_BC_27
EXDU_ES
EXDU_BPB
EXDU_BC
QB9_EX1
QB9_EX2
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QB7_EX1
QB7_EX2
QB7_EX3
QB7_EX4
en05000357.vsd
544
Interlocking Chapter 11
Control
ABC_LINE
QA1_OP
QA1_CL =1 VPQA1
QB9_OP
QB9_CL =1 VPQB9
QA1CLREL
QB1_OP
QB1_CL =1 VPQB1 QA1CLITL
& 1
QB2_OP
QB2_CL =1 VPQB2
QB7_OP
QB7_CL =1 VPQB7
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC9_OP
QC9_CL =1 VPQC9
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQC1 QB9REL
VPQC2 & >1
QB9ITL
1
VPQC9
QA1_OP
QC1_OP
QC2_OP
QC9_OP
QB9_EX1
VPQC2
VPQC9
&
QC2_CL
QC9_CL
QB9_EX2
en04000527.vsd
545
Interlocking Chapter 11
Control
QB1REL
VPQA1 & 1
VPQB2
VPQC1 1 QB1ITL
VPQC2
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2 &
VP_BC_12
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1 &
VPQC11
QC1_CL
QC11_CL
EXDU_ES
QB1EX3
en04000528.vsd
546
Interlocking Chapter 11
Control
QB2REL
VPQA1 & 1
VPQB1
VPQC1 1 QB2ITL
VPQC2
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1 &
VP_BC_12
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1 &
VPQC21
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000529.vsd
547
Interlocking Chapter 11
Control
VPQC9 QB7REL
& >1
VPQC71
VP_BB7_D 1 QB7ITL
VP_BC_17
VP_BC_27
QC9_OP
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_OP
BC_27_OP
EXDU_BC
QB7_EX1
VPQA1
VPQB1
VPQC9
&
VPQB9
VPQC71
VP_BB7_D
VP_BC_17
QA1_CL
QB1_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_CL
EXDU_BC
QB7_EX2
548
Interlocking Chapter 11
Control
VPQA1
VPQB2
& >1
VPQC9
VPQB9
VPQC71
VP_BB7_D
VP_BC_27
QA1_CL
QB2_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_27_CL
EXDU_BC
QB7_EX3
VPQC9
VPQC71
&
QC9_CL
QC71_CL
EXDU_ES
QB7_EX4
VPQB1 QC1REL
VPQB2 QC1ITL
VPQB9 & 1
QC2REL
QB1_OP
QB2_OP QC2ITL
1
QB9_OP
VPQB7
VPQB9 QC9REL
VPVOLT &
QC9ITL
QB7_OP 1
QB9_OP
VOLT_OFF
en04000531.vsd
549
Interlocking Chapter 11
Control
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000532.vsd
550
Interlocking Chapter 11
Control
Signal Description
QC71_OP Earthing switch QC71 on busbar WA7 is in open position
QC71_CL Earthing switch QC71 on busbar WA7 is in closed position
BB7_D_OP Disconnectors on busbar WA7 except in the own bay are open
BC_12_CL A bus coupler connection exists between busbar WA1 and WA2
BC_17_OP No bus coupler connection exists between busbar WA1 and
WA7
BC_17_CL A bus coupler connection exists between busbar WA1 and WA7
BC_27_OP No bus coupler connection exists between busbar WA2 and
WA7
BC_27_CL A bus coupler connection exists between busbar WA2 and WA7
VOLT_OFF There is no voltage on the line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
VP_BB7_D Switch status of the disconnectors on busbar WA7 are valid
VP_BC_12 Status of the bus coupler app. between WA1 and WA2 are valid
VP_BC_17 Status of the bus coupler app. between WA1 and WA7 are valid
VP_BC_27 Status of the bus coupler app. between WA2 and WA7 are valid
EXDU_ES No transm error from any bay containing earthing switches
EXDU_BPB No transm error from any bay with disconnectors on WA7
EXDU_BC No transmission error from any bus coupler bay
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB1_EX3 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB2_EX3 External condition for apparatus QB2
QB7_EX1 External condition for apparatus QB7
QB7_EX2 External condition for apparatus QB7
QB7_EX3 External condition for apparatus QB7
QB7_EX4 External condition for apparatus QB7
551
Interlocking Chapter 11
Control
Table 285: Output signals for the ABC_LINE (IF01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QB7REL Switching of QB7 is allowed
QB7ITL Switching of QB7 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
QB7OPTR QB7 is in open position
QB7CLTR QB7 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
VPQB7TR Switch status of QB7 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
552
Interlocking Chapter 11
Control
WA1 (A)
WA2 (B)
WA7 (C)
QB1 QB2 QB20 QB7
QC1
QA1
QC2
en04000514.vsd
553
Interlocking Chapter 11
Control
IG01-
ABC_BC
QA1_OP QA1OPREL
QA1_CL QA1OPIT L
QB1_OP QA1CLREL
QB1_CL QA1CLIT L
QB2_OP QB1REL
QB2_CL QB1IT L
QB7_OP QB2REL
QB7_CL QB2IT L
QB20_OP QB7REL
QB20_CL QB7IT L
QC1_OP QB20REL
QC1_CL QB20IT L
QC2_OP QC1REL
QC2_CL QC1IT L
QC11_OP QC2REL
QC11_CL QC2IT L
QC21_OP QB1OPT R
QC21_CL QB1CLT R
QC71_OP QB220OT R
QC71_CL QB220CT R
BBT R_OP QB7OPT R
BC_12_CL QB7CLT R
VP_BBT R QB12OPT R
VP_BC_12 QB12CLT R
EXDU_ES BC12OPT R
EXDU_12 BC12CLT R
EXDU_BC BC17OPT R
QA1O_EX1 BC17CLT R
QA1O_EX2 BC27OPT R
QA1O_EX3 BC27CLT R
QB1_EX1 VPQB1T R
QB1_EX2 VQB220T R
QB1_EX3 VPQB7T R
QB2_EX1 VPQB12T R
QB2_EX2 VPBC12T R
QB2_EX3 VPBC17T R
QB20_EX1 VPBC27T R
QB20_EX2
QB7_EX1
QB7_EX2
en05000350.vsd
554
Interlocking Chapter 11
Control
ABC_BC
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB20_OP
QB20_CL =1 VPQB20
QB7_OP
QB7_CL =1 VPQB7
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VPQB1
QB1_OP QA1OPREL
& >1 QA1OPITL
QA1O_EX1 1
VPQB20
QB20_OP &
QA1O_EX2
VP_BBTR
BBTR_OP &
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQB7 & 1
VPQB20
en04000533.vsd
555
Interlocking Chapter 11
Control
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VP_BC_12
&
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000534.vsd
556
Interlocking Chapter 11
Control
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VP_BC_12
&
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000535.vsd
557
Interlocking Chapter 11
Control
VPQA1
VPQB20 QB7REL
& >1
VPQC1 QB7ITL
VPQC2 1
VPQC71
QA1_OP
QB20_OP
QC1_OP
QC2_OP
QC71_OP
EXDU_ES
QB7_EX1
VPQC2
VPQC71
&
QC2_CL
QC71_CL
EXDU_ES
QB7_EX2
VPQA1
VPQB7 QB20REL
& >1
VPQC1 QB20ITL
VPQC2 1
VPQC21
QA1_OP
QB7_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB20_EX1
VPQC2
VPQC21
&
QC2_CL
QC21_CL
EXDU_ES
QB20_EX2
en04000536.vsd
558
Interlocking Chapter 11
Control
VPQB1 QC1REL
VPQB20 QC1ITL
& 1
VPQB7
QC2REL
VPQB2
QB1_OP QC2ITL
1
QB20_OP
QB7_OP
QB2_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB20_OP QB220OTR
QB2_OP & QB220CTR
VPQB20 1
VQB220TR
VPQB2 &
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
QA1_OP BC12OPTR
QB1_OP >1 BC12CLTR
QB20_OP 1
VPQA1
VPBC12TR
VPQB1 &
VPQB20
QA1_OP BC17OPTR
QB1_OP >1 BC17CLTR
QB7_OP 1
VPQA1
VPBC17TR
VPQB1 &
VPQB7
QA1_OP BC27OPTR
QB2_OP >1 BC27CLTR
QB7_OP 1
VPQA1
VPBC27TR
VPQB2 &
VPQB7
en04000537.vsd
559
Interlocking Chapter 11
Control
560
Interlocking Chapter 11
Control
Signal Description
QB2_EX3 External condition for apparatus QB2
QB20_EX1 External condition for apparatus QB20
QB20_EX2 External condition for apparatus QB20
QB7_EX1 External condition for apparatus QB7
QB7_EX2 External condition for apparatus QB7
Table 287: Output signals for the ABC_BC (IG01-) function block
Signal Description
QA1OPREL Opening of QA1 is allowed
QA1OPITL Opening of QA1 is forbidden
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QB7REL Switching of QB7 is allowed
QB7ITL Switching of QB7 is forbidden
QB20REL Switching of QB20 is allowed
QB20ITL Switching of QB20 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB220OTR QB2 and QB20 are in open position
QB220CTR QB2 or QB20 or both are not in open position
QB7OPTR QB7 is in open position
QB7CLTR QB7 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
BC12OPTR No connection via the own bus coupler between WA1 and WA2
BC12CLTR Conn. exists via the own bus coupler between WA1 and WA2
BC17OPTR No connection via the own bus coupler between WA1 and WA7
BC17CLTR Conn. exists via the own bus coupler between WA1 and WA7
BC27OPTR No connection via the own bus coupler between WA2 and WA7
BC27CLTR Conn. exists via the own bus coupler between WA2 and WA7
561
Interlocking Chapter 11
Control
Signal Description
VPQB1TR Switch status of QB1 is valid (open or closed)
VQB220TR Switch status of QB2 and QB20 are valid (open or closed)
VPQB7TR Switch status of QB7 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
VPBC12TR Status of the bus coupler app. between WA1 and WA2 are valid
VPBC17TR Status of the bus coupler app. between WA1 and WA7 are valid
VPBC27TR Status of the bus coupler app. between WA2 and WA7 are valid
WA1 (A)
WA2 (B)
QB1 QB2
QC1
QA1
AB_TRAFO
QC2
QC3
QA2
QA2 and QC4 are not
QC4 used in this interlocking
QB3 QB4
en04000515.vsd
562
Interlocking Chapter 11
Control
IE01-
AB_TRAFO
QA1_OP QA1CLREL
QA1_CL QA1CLIT L
QB1_OP QB1REL
QB1_CL QB1IT L
QB2_OP QB2REL
QB2_CL QB2IT L
QC1_OP QC1REL
QC1_CL QC1IT L
QC2_OP QC2REL
QC2_CL QC2IT L
QB3_OP QB1OPT R
QB3_CL QB1CLT R
QB4_OP QB2OPT R
QB4_CL QB2CLT R
QC3_OP QB12OPT R
QC3_CL QB12CLT R
QC11_OP VPQB1T R
QC11_CL VPQB2T R
QC21_OP VPQB12T R
QC21_CL
BC_12_CL
VP_BC_12
EXDU_ES
EXDU_BC
QA1_EX1
QA1_EX2
QA1_EX3
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
en05000358.vsd
563
Interlocking Chapter 11
Control
AB_TRAFO
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB3_OP
QB3_CL =1 VPQB3
QB4_OP
QB4_CL =1 VPQB4
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQC1 & 1
VPQC2
VPQB3
VPQB4
VPQC3
QA1_EX2
QC3_OP
QA1_EX3
QC1_CL >1
QC2_CL
QC3_CL &
QA1_EX1
en04000538.vsd
564
Interlocking Chapter 11
Control
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC3
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC3_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VPQC3
&
VP_BC_12
QB2_CL
QC3_OP
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC2
&
VPQC3
VPQC11
QC1_CL
QC2_CL
QC3_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000539.vsd
565
Interlocking Chapter 11
Control
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC3
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC3_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VPQC3
&
VP_BC_12
QB1_CL
QC3_OP
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC2
&
VPQC3
VPQC21
QC1_CL
QC2_CL
QC3_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000540.vsd
566
Interlocking Chapter 11
Control
VPQB1 QC1REL
VPQB2 QC1ITL
& 1
VPQB3
QC2REL
VPQB4
QB1_OP QC2ITL
1
QB2_OP
QB3_OP
QB4_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000541.vsd
567
Interlocking Chapter 11
Control
Signal Description
QC11_CL QC11 on busbar WA1 is in closed position
QC21_OP QC21 on busbar WA2 is in open position
QC21_CL QC21 on busbar WA2 is in closed position
BC_12_CL A bus coupler connection exists between busbar WA1 and WA2
VP_BC_12 Status of the bus coupler app. between WA1 and WA2 are valid
EXDU_ES No transm error from any bay containing earthing switches
EXDU_BC No transmission error from any bus coupler bay
QA1_EX1 External condition for apparatus QA1
QA1_EX2 External condition for apparatus QA1
QA1_EX3 External condition for apparatus QA1
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB1_EX3 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB2_EX3 External condition for apparatus QB2
Table 289: Output signals for the AB_TRAFO (IE01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
568
Interlocking Chapter 11
Control
IH01-
A1A2_BS
QA1_OP QA1OPREL
QA1_CL QA1OPIT L
QB1_OP QA1CLREL
QB1_CL QA1CLIT L
QB2_OP QB1REL
QB2_CL QB1IT L
QC3_OP QB2REL
QC3_CL QB2IT L
QC4_OP QC3REL
QC4_CL QC3IT L
S1QC1_OP QC4REL
S1QC1_CL QC4IT L
S2QC2_OP S1S2OPT R
S2QC2_CL S1S2CLT R
BBT R_OP QB1OPT R
VP_BBT R QB1CLT R
EXDU_12 QB2OPT R
EXDU_ES QB2CLT R
QA1O_EX1 VPS1S2T R
QA1O_EX2 VPQB1T R
QA1O_EX3 VPQB2T R
QB1_EX1
QB1_EX2
QB2_EX1
QB2_EX2
en05000348.vsd
569
Interlocking Chapter 11
Control
A1A2_BS
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC3_OP
QC3_CL =1 VPQC3
QC4_OP
QC4_CL =1 VPQC4
S1QC1_OP
S1QC1_CL =1 VPS1QC1
S2QC2_OP
S2QC2_CL =1 VPS2QC2
VPQB1
QB1_OP QA1OPREL
& >1
QA1O_EX1 QA1OPITL
1
VPQB2
QB2_OP
&
QA1O_EX2
VP_BBTR
BBTR_OP
&
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 & QA1CLITL
1
VPQA1
VPQC3 QB1REL
& >1
VPQC4 QB1ITL
1
VPS1QC1
QA1_OP
QC3_OP
QC4_OP
S1QC1_OP
EXDU_ES
QB1_EX1
VPQC3
VPS1QC1
&
QC3_CL
S1QC1_CL
EXDU_ES
QB1_EX2
en04000542.vsd
570
Interlocking Chapter 11
Control
VPQA1
VPQC3 QB2REL
VPQC4 & >1
QB2ITL
VPS2QC2 1
QA1_OP
QC3_OP
QC4_OP
S2QC2_OP
EXDU_ES
QB2_EX1
VPQC4
VPS2QC2
&
QC4_CL
S2QC2_CL
EXDU_ES
QB2_EX2
VPQB1 QC3REL
VPQB2 QC3ITL
QB1_OP & 1
QC4REL
QB2_OP
QC4ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP S1S2OPTR
QB2_OP >1 S1S2CLTR
QA1_OP 1
VPQB1
VPS1S2TR
VPQB2 &
VPQA1
en04000543.vsd
571
Interlocking Chapter 11
Control
Signal Description
QB2_CL QB2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
S1QC1_OP QC1 on bus section 1 is in open position
S1QC1_CL QC1 on bus section 1 is in closed position
S2QC2_OP QC2 on bus section 2 is in open position
S2QC2_CL QC2 on bus section 2 is in closed position
BBTR_OP No busbar transfer is in progress
VP_BBTR Status are valid for app. involved in the busbar transfer
EXDU_12 No transm error from any bay connected to busbar 1 and 2
EXDU_ES No transm error from bays containing earth. sw. QC1 or QC2
QA1O_EX1 External open condition for apparatus QA1
QA1O_EX2 External open condition for apparatus QA1
QA1O_EX3 External open condition for apparatus QA1
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
Table 291: Output signals for the A1A2_BS (IH01-) function block
Signal Description
QA1OPREL Opening of QA1 is allowed
QA1OPITL Opening of QA1 is forbidden
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QC4REL Switching of QC4 is allowed
QC4ITL Switching of QC4 is forbidden
S1S2OPTR No bus section connection between bus section 1 and 2
S1S2CLTR Bus coupler connection between bus section 1 and 2 exists
QB1OPTR QB1 is in open position
572
Interlocking Chapter 11
Control
Signal Description
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPS1S2TR Status of the app. between bus section 1 and 2 are valid
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
QB
WA1 (A1) WA2 (A2)
QC1 QC2
A1A2_DC en04000492.vsd
573
Interlocking Chapter 11
Control
II01-
A1A2_DC
QB_OP QBOPREL
QB_CL QBOPIT L
S1QC1_OP QBCLREL
S1QC1_CL QBCLIT L
S2QC2_OP DCOPT R
S2QC2_CL DCCLT R
S1DC_OP VPDCT R
S2DC_OP
VPS1_DC
VPS2_DC
EXDU_ES
EXDU_BB
QBCL_EX1
QBCL_EX2
QBOP_EX1
QBOP_EX2
QBOP_EX3
en05000349.vsd
574
Interlocking Chapter 11
Control
A1A2_DC
QB_OP
VPQB VPDCTR
QB_CL =1
DCOPTR
DCCLTR
S1QC1_OP
VPS1QC1
S1QC1_CL =1
S2QC2_OP
VPS2QC2
S2QC2_CL =1
VPS1QC1
VPS2QC2
VPS1_DC & >1 QBOPREL
S1QC1_OP QBOPITL
1
S2QC2_OP
S1DC_OP
EXDU_ES
EXDU_BB
QBOP_EX1
VPS1QC1
VPS2QC2
VPS2_DC &
S1QC1_OP
S2QC2_OP
S2DC_OP
EXDU_ES
EXDU_BB
QBOP_EX2
VPS1QC1
VPS2QC2
S1QC1_CL &
S2QC2_CL
EXDU_ES
QBOP_EX3
en04000544.vsd
575
Interlocking Chapter 11
Control
576
Interlocking Chapter 11
Control
Table 293: Output signals for the A1A2_DC (II01-) function block
Signal Description
QBOPREL Opening of QB is allowed
QBOPITL Opening of QB is forbidden
QBCLREL Closing of QB is allowed
QBCLITL Closing of QB is forbidden
DCOPTR The bus section disconnector is in open position
DCCLTR The bus section disconnector is in closed position
VPDCTR Switch status of QB is valid (open or closed)
QC
en04000504.vsd
IJ01-
BB_ES
QC_OP QCREL
QC_CL QCITL
BB_DC_OP BBESOPTR
VP_BB_DC BBESCLTR
EXDU_BB
en05000347.vsd
577
Interlocking Chapter 11
Control
BB_ES
VP_BB_DC QCREL
BB_DC_OP QCITL
EXDU_BB & 1
QC_OP BBESOPTR
QC_CL BBESCLTR
en04000546.vsd
Table 295: Output signals for the BB_ES (IJ01-) function block
Signal Description
QCREL Switching of QC is allowed
QCITL Switching of QC is forbidden
BBESOPTR QC on this busbar part is in open position
BBESCLTR QC on this busbar part is in closed position
578
Interlocking Chapter 11
Control
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC4
QA1 QA2
DB_BUS_A DB_BUS_B
QC2 QC5
QB61 QB62
QC3
QB9
DB_LINE
QC9
en04000518.vsd
Three types of interlocking modules per double circuit breaker bay are defined. DB_LINE is the
connection from the line to the circuit breaker parts that are connected to the busbars.
DB_BUS_A and DB_BUS_B are the connections from the line to the busbars.
579
Interlocking Chapter 11
Control
IB01-
DB_BUS_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB1_OP QB61REL
QB1_CL QB61ITL
QB61_OP QB1REL
QB61_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QB1OPTR
QC3_CL QB1CLTR
QC11_OP VPQB1TR
QC11_CL
EXDU_ES
QB61_EX1
QB61_EX2
QB1_EX1
QB1_EX2
en05000354.vsd
IA01-
DB_LINE
QA1_OP QB9REL
QA1_CL QB9ITL
QA2_OP QC3REL
QA2_CL QC3ITL
QB61_OP QC9REL
QB61_CL QC9ITL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QB62_OP
QB62_CL
QC4_OP
QC4_CL
QC5_OP
QC5_CL
QB9_OP
QB9_CL
QC3_OP
QC3_CL
QC9_OP
QC9_CL
VOLT_OFF
VOLT_ON
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
en05000356.vsd
580
Interlocking Chapter 11
Control
IC01-
DB_BUS_B
QA2_OP QA2CLREL
QA2_CL QA2CLITL
QB2_OP QB62REL
QB2_CL QB62ITL
QB62_OP QB2REL
QB62_CL QB2ITL
QC4_OP QC4REL
QC4_CL QC4ITL
QC5_OP QC5REL
QC5_CL QC5ITL
QC3_OP QB2OPTR
QC3_CL QB2CLTR
QC21_OP VPQB2TR
QC21_CL
EXDU_ES
QB62_EX1
QB62_EX2
QB2_EX1
QB2_EX2
en05000355.vsd
581
Interlocking Chapter 11
Control
DB_BUS_A
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB1_OP
QB1_CL =1 VPQB1
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
VPQB61 QA1CLREL
VPQB1 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB61_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB61_EX2
VPQA1
VPQC1 QB1REL
& >1
VPQC2 QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
en04000547.vsd
582
Interlocking Chapter 11
Control
VPQB61 QC1REL
VPQB1 QC1ITL
& 1
QB61_OP QC2REL
QB1_OP QC2ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
en04000548.vsd
583
Interlocking Chapter 11
Control
DB_LINE
QA1_OP
QA1_CL =1 VPQA1
QA2_OP
QA2_CL =1 VPQA2
QB61_OP
QB61_CL =1 VPQB61
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB62_OP
QB62_CL =1 VPQB62
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QB9_OP
QB9_CL =1 VPQB9
QC3_OP
QC3_CL =1 VPQC3
QC9_OP
QC9_CL =1 VPQC9
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQA2 QB9REL
VPQC1 & >1
QB9ITL
1
VPQC2
VPQC3
VPQC4
VPQC5
VPQC9
QA1_OP
QA2_OP
QC1_OP
QC2_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX1
& en04000549.vsd
584
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQC2 & >1
VPQC3
VPQC9
VPQB62
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QC9_OP
QB62_OP
QB9_EX2
VPQA2
VPQB61
&
VPQC3
VPQC4
VPQC5
VPQC9
QA2_OP
QB61_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX3
VPQC3
VPQC9
&
VPQB61
VPQB62
QC3_OP
QC9_OP
QB61_OP
QB62_OP
QB9_EX4
VPQC3
VPQC9
&
QC3_CL
QC9_CL
QB9_EX5
en04000550.vsd
585
Interlocking Chapter 11
Control
VPQB61
VPQB62 QC3REL
VPQB9 &
QC3ITL
1
QB61_OP
QB62_OP
QB9_OP
VPQB9
VPVOLT QC9REL
QB9_OP &
QC9ITL
1
VOLT_OFF
en04000551.vsd
586
Interlocking Chapter 11
Control
DB_BUS_B
QA2_OP
QA2_CL =1 VPQA2
QB62_OP
QB62_CL =1 VPQB62
QB2_OP
QB2_CL =1 VPQB2
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QC3_OP
QC3_CL =1 VPQC3
QC21_OP
QC21_CL =1 VPQC21
VPQB62 QA2CLREL
VPQB2 & QA2CLITL
1
VPQA2
VPQC4 QB62REL
& >1
VPQC5 QB62ITL
1
VPQC3
QA2_OP
QC4_OP
QC5_OP
QC3_OP
QB62_EX1
VPQC5
VPQC3
&
QC5_CL
QC3_CL
QB62_EX2
VPQA2
VPQC4 QB2REL
& >1
VPQC5 QB2ITL
1
VPQC21
QA2_OP
QC4_OP
QC5_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC4
VPQC21
&
QC4_CL
QC21_CL
EXDU_ES
QB2_EX2
en04000552.vsd
587
Interlocking Chapter 11
Control
VPQB62 QC4REL
VPQB2 QC4ITL
& 1
QB62_OP QC5REL
QB2_OP QC5ITL
1
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
en04000553.vsd
588
Interlocking Chapter 11
Control
Table 297: Output signals for the DB_BUS_A (IB01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB61REL Switching of QB61 is allowed
QB61ITL Switching of QB61 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
VPQB1TR Switch status of QB1 is valid (open or closed)
Table 298: Input signals for the DB_LINE (IA01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QA2_OP QA2 is in open position
QA2_CL QA2 is in closed position
QB61_OP QB61 is in open position
QB61_CL QB61 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
QC5_OP QC5 is in open position
QC5_CL QC5 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC9_OP QC9 is in open position
589
Interlocking Chapter 11
Control
Signal Description
QC9_CL QC9 is in closed position
VOLT_OFF There is no voltage on the line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
Table 299: Output signals for the DB_LINE (IA01-) function block
Signal Description
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
Table 300: Input signals for the DB_BUS_B (IC01-) function block
Signal Description
QA2_OP QA2 is in open position
QA2_CL QA2 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
QC5_OP QC5 is in open position
QC5_CL QC5 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
590
Interlocking Chapter 11
Control
Signal Description
EXDU_ES No transm error from bay containing earthing switch QC21
QB62_EX1 External condition for apparatus QB62
QB62_EX2 External condition for apparatus QB62
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
Table 301: Output signals for the DB_BUS_B (IC01-) function block
Signal Description
QA2CLREL Closing of QA2 is allowed
QA2CLITL Closing of QA2 is forbidden
QB62REL Switching of QB62 is allowed
QB62ITL Switching of QB62 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC4REL Switching of QC4 is allowed
QC4ITL Switching of QC4 is forbidden
QC5REL Switching of QC5 is allowed
QC5ITL Switching of QC5 is forbidden
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPQB2TR Switch status of QB2 is valid (open or closed)
591
Interlocking Chapter 11
Control
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC1
QA1 QA1
QC2 QC2
QB6 QB6
QC3 QC3
BH_LINE_A BH_LINE_B
QB9 QB9
QC1 QC2
QC9 QC9
BH_CONN
en04000513.vsd
Three types of interlocking modules per diameter are defined. BH_LINE_A and BH_LINE_B
are the connections from a line to a busbar. BH_CONN is the connection between the two lines
of the diameter in the breaker and a half switchyard layout.
592
Interlocking Chapter 11
Control
IL01-
BH_LINE_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB6_OP QB6REL
QB6_CL QB6ITL
QB1_OP QB1REL
QB1_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QC3REL
QC3_CL QC3ITL
QB9_OP QB9REL
QB9_CL QB9ITL
QC9_OP QC9REL
QC9_CL QC9ITL
CQA1_OP QB1OPTR
CQA1_CL QB1CLTR
CQB61_OP VPQB1TR
CQB61_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC11_OP
QC11_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB1_EX1
QB1_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
en05000352.vsd
593
Interlocking Chapter 11
Control
IM01-
BH_LINE_B
QA1_OP QA1CLREL
QA1_CL QA1CLIT L
QB6_OP QB6REL
QB6_CL QB6IT L
QB2_OP QB2REL
QB2_CL QB2IT L
QC1_OP QC1REL
QC1_CL QC1IT L
QC2_OP QC2REL
QC2_CL QC2IT L
QC3_OP QC3REL
QC3_CL QC3IT L
QB9_OP QB9REL
QB9_CL QB9IT L
QC9_OP QC9REL
QC9_CL QC9IT L
CQA1_OP QB2OPT R
CQA1_CL QB2CLT R
CQB62_OP VPQB2T R
CQB62_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC21_OP
QC21_CL
VOLT _OFF
VOLT _ON
EXDU_ES
QB6_EX1
QB6_EX2
QB2_EX1
QB2_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
en05000353.vsd
594
Interlocking Chapter 11
Control
IK01-
BH_CONN
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB61_OP QB61REL
QB61_CL QB61ITL
QB62_OP QB62REL
QB62_CL QB62ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
1QC3_OP
1QC3_CL
2QC3_OP
2QC3_CL
QB61_EX1
QB61_EX2
QB62_EX1
QB62_EX2
en05000351.vsd
595
Interlocking Chapter 11
Control
BH_LINE_A
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB61_OP
CQB61_CL =1 VPCQB61
QC11_OP
QC11_CL =1 VPQC11
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB1 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
en04000554.vsd
596
Interlocking Chapter 11
Control
VPQA1
VPQC1 QB1REL
VPQC2 & >1
QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
VPQB1 QC1REL
VPQB6 QC1ITL
QB1_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB61 &
QC3ITL
1
QB6_OP
QB9_OP
CQB61_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB61
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
en04000555.vsd
597
Interlocking Chapter 11
Control
CQB61_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
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BH_LINE_B
QA1_OP
QA1_CL =1 VPQA1
QB2_OP
QB2_CL =1 VPQB2
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB62_OP
CQB62_CL =1 VPCQB62
QC21_OP
QC21_CL =1 VPQC21
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB2 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
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Interlocking Chapter 11
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VPQA1
VPQC1 QB2REL
VPQC2 & >1
QB2ITL
1
VPQC21
QA1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX2
VPQB2 QC1REL
VPQB6 QC1ITL
QB2_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB62 &
QC3ITL
1
QB6_OP
QB9_OP
CQB62_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB62
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
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Interlocking Chapter 11
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CQB62_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
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BH_CONN
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB62_OP
QB62_CL =1 VPQB62
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
1QC3_OP
1QC3_CL =1 VP1QC3
2QC3_OP
2QC3_CL =1 VP2QC3
VPQB61 QA1CLREL
VPQB62 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VP1QC3
QA1_OP
QC1_OP
QC2_OP
1QC3_OP
QB61_EX1
VPQC1
VP1QC3
&
QC1_CL
1QC3_CL
QB61_EX2
VPQA1
VPQC1 QB62REL
& >1
VPQC2 QB62ITL
1
VP2QC3
QA1_OP
QC1_OP
QC2_OP
2QC3_OP
QB62_EX1
VPQC2
VP2QC3
&
QC2_CL
2QC3_CL
QB62_EX2
VPQB61 QC1REL
VPQB62 QC1ITL
& 1
QB61_OP QC2REL
QB62_OP QC2ITL
1
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Signal Description
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
QB9_EX6 External condition for apparatus QB9
QB9_EX7 External condition for apparatus QB9
Table 303: Output signals for the BH_LINE_A (IL01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB6REL Switching of QB6 is allowed
QB6ITL Switching of QB6 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
VPQB1TR Switch status of QB1 is valid (open or closed)
Table 304: Input signals for the BH_LINE_B (IM01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB6_OP QB6 is in open position
QB6_CL QB6 is in close position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QC1_OP QC1 is in open position
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Signal Description
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QC9_OP QC9 is in open position
QC9_CL QC9 is in closed position
CQA1_OP QA1 in module BH_CONN is in open position
CQA1_CL QA1 in module BH_CONN is in closed position
CQB62_OP QB62 in module BH_CONN is in open position
CQB62_CL QB62 in module BH_CONN is in closed position
CQC1_OP QC1 in module BH_CONN is in open position
CQC1_CL QC1 in module BH_CONN is in closed position
CQC2_OP QC2 in module BH_CONN is in open position
CQC2_CL QC2 in module BH_CONN is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
VOLT_OFF There is no voltage on line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
EXDU_ES No transm error from bay containing earthing switch QC21
QB6_EX1 External condition for apparatus QB6
QB6_EX2 External condition for apparatus QB6
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
QB9_EX6 External condition for apparatus QB9
QB9_EX7 External condition for apparatus QB9
Table 305: Output signals for the BH_LINE_B (IM01-) function block
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Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB6REL Switching of QB6 is allowed
QB6ITL Switching of QB6 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPQB2TR Switch status of QB2 is valid (open or closed)
Table 306: Input signals for the BH_CONN (IK01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB61_OP QB61 is in open position
QB61_CL QB61 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
1QC3_OP QC3 on line 1 is in open position
1QC3_CL QC3 on line 1 is in closed position
2QC3_OP QC3 on line 2 is in open position
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Signal Description
2QC3_CL QC3 on line 2 is in closed position
QB61_EX1 External condition for apparatus QB61
QB61_EX2 External condition for apparatus QB61
QB62_EX1 External condition for apparatus QB62
QB62_EX2 External condition for apparatus QB62
Table 307: Output signals for the BH_CONN (IK01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB61REL Switching of QB61 is allowed
QB61ITL Switching of QB61 is forbidden
QB62REL Switching of QB62 is allowed
QB62ITL Switching of QB62 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
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Interlocking Chapter 11
Control
GR01-
IntlReceive
BLOCK RESREQ
INSTNAME RESGRANT
RESRENAM APP1_OP
RESGRNAM APP1_CL
APP1NAME APP1VAL
APP2NAME APP2_OP
APP3NAME APP2_CL
APP4NAME APP2VAL
APP5NAME APP3_OP
APP6NAME APP3_CL
APP7NAME APP3VAL
APP8NAME APP4_OP
APP9NAME APP4_CL
APP10NAM APP4VAL
APP11NAM APP5_OP
APP12NAM APP5_CL
APP13NAM APP5VAL
APP14NAM APP6_OP
APP15NAM APP6_CL
APP6VAL
APP7_OP
APP7_CL
APP7VAL
APP8_OP
APP8_CL
APP8VAL
APP9_OP
APP9_CL
APP9VAL
APP10_OP
APP10_CL
APP10VAL
APP11_OP
APP11_CL
APP11VAL
APP12_OP
APP12_CL
APP12VAL
APP13_OP
APP13_CL
APP13VAL
APP14_OP
APP14_CL
APP14VAL
APP15_OP
APP15_CL
APP15VAL
COM_VAL
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Interlocking Chapter 11
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Table 309: Output signals for the IntlReceive (GR01-) function block
Signal Description
RESREQ Reservation request
RESGRANT Reservation granted
APP1_OP Apparatus 1 position is open
APP1_CL Apparatus 1 position is closed
APP1VAL Apparatus 1 position is valid
APP2_OP Apparatus 2 position is open
APP2_CL Apparatus 2 position is closed
APP2VAL Apparatus 2 position is valid
APP3_OP Apparatus 3 position is open
APP3_CL Apparatus 3 position is closed
APP3VAL Apparatus 3 position is valid
APP4_OP Apparatus 4 position is open
APP4_CL Apparatus 4 position is closed
APP4VAL Apparatus 4 position is valid
APP5_OP Apparatus 5 position is open
APP5_CL Apparatus 5 position is closed
APP5VAL Apparatus 5 position is valid
APP6_OP Apparatus 6 position is open
APP6_CL Apparatus 6 position is closed
APP6VAL Apparatus 6 position is valid
APP7_OP Apparatus 7 position is open
APP7_CL Apparatus 7 position is closed
APP7VAL Apparatus 7 position is valid
APP8_OP Apparatus 8 position is open
APP8_CL Apparatus 8 position is closed
APP8VAL Apparatus 8 position is valid
APP9_OP Apparatus 9 position is open
APP9_CL Apparatus 9 position is closed
APP9VAL Apparatus 9 position is valid
APP10_OP Apparatus 10 position is open
APP10_CL Apparatus 10 position is closed
APP10VAL Apparatus 10 position is valid
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Interlocking Chapter 11
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Signal Description
APP11_OP Apparatus 11 position is open
APP11_CL Apparatus 11 position is closed
APP11VAL Apparatus 11 position is valid
APP12_OP Apparatus 12 position is open
APP12_CL Apparatus 12 position is closed
APP12VAL Apparatus 12 position is valid
APP13_OP Apparatus 13 position is open
APP13_CL Apparatus 13 position is closed
APP13VAL Apparatus 13 position is valid
APP14_OP Apparatus 14 position is open
APP14_CL Apparatus 14 position is closed
APP14VAL Apparatus 14 position is valid
APP15_OP Apparatus 15 position is open
APP15_CL Apparatus 15 position is closed
APP15VAL Apparatus 15 position is valid
COM_VAL Receive communication status is valid
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Voltage control (VCTR) Chapter 11
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4.1 Introduction
The voltage control function is used for control of power transformers with a motor driven
on-load tap changer. The function provides automatic regulation of the voltage on the secondary
side of transformers or alternatively on a load point further out in the network. Control of a single
transformer, as well as control of up to eight transformers in parallel is possible. For parallel con-
trol of power transformers, three alternative methods are available, the master-follower method,
the circulating current method and the reverse reactance method. The two former methods re-
quire exchange of information between the parallel transformers and this is provided for within
IEC 61850-8-1.
The voltage control includes many extra features such as possibility to avoid simultaneous tap-
ping of parallel transformers, hot stand by regulation of a transformer in a group which regulates
it to a correct tap position even though the LV CB is open, compensation for a possible capacitor
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Voltage control (VCTR) Chapter 11
Control
bank on the LV side bay of a transformer, extensive tap changer monitoring including contact
wear and hunting detection, monitoring of the power flow in the transformer so that e.g. the volt-
age control can be blocked if the power reverses etc.
Automatic Tap Changer Control (ATCC) is a function designed to automatically maintain the
voltage at the LV-side side of a power transformer within given limits around a set target volt-
age. A raise or lower command is generated whenever the measured voltage, for a given period
of time, deviates from the set target value by more than the preset deadband value (i.e. degree of
insensitivity). A time delay (inverse or definite time) is set to avoid unnecessary operation dur-
ing shorter voltage deviations from the target value, and in order to coordinate with other auto-
matic voltage controllers in the system.
Tap Changer (YLTC) is an interface between the tap changer controller (ATCC) and the trans-
former OLTC itself. More specifically this means that it receives information from the ATCC,
and based on this it gives command-pulses to a power transformer motor driven on-load tap
changer (OLTC) and also receives information from the OLTC regarding tap position, progress
of given commands etc.
YLTC also serves the purpose of giving information about tap position to the transformer dif-
ferential protection (PDIF) when this option is used in PDIF.
In addition, all three phase currents from the HV-winding (i.e. usually the winding where the tap
changer is situated) are used by the ATCC function for over current blocking.
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Voltage control (VCTR) Chapter 11
Control
The analog input signals are normally common with other functions in the terminal, such as e.g.
protection functions.
The LV-busbar voltage will from here on be designated UB. Similarly the notation IL for load
current and UL for load point voltage will be used in the text to follow.
The ATCC function then compares this voltage with the set voltage, Uset and decides which ac-
tion should be taken. To avoid unnecessary switching around the setpoint, a deadband (i.e. de-
gree of insensitivity) is introduced. The deadband is symmetrical around Uset (see figure 281),
and it is arranged in such a way that there is an outer and an inner deadband. Measured voltages
outside the outer deadband start the timer to initiate tap commands, whilst the sequence resets
when the measured voltage is once again back inside the inner deadband. One half of the outer
deadband will be denoted as U from here on. The setting of U, (i.e. setting parameter Udead-
band in the setting tool under the ATCC function) should be set to a value near to the power
transformers tap changer voltage step (typically 75125% of the tap changer step).
S e c u rity R a n g e
*) *)
R a is e C m d U U Low er C m d
*)
U in U in
e n 0 6 0 0 0 4 8 9 .v s d
During normal operating conditions the busbar voltage UB, stays within the outer deadband (i.e.
interval between U1 and U2 in figure 281). In that case no actions will be taken by the ATCC.
However, if UB becomes smaller than U1, or greater than U2, an appropriate lower or raise timer
will start. The timer will run as long as the measured voltage stays outside the inner deadband.
If this condition persists longer than the preset time delay, ATCC will initiate that the appropri-
ate ULOWER or URAISE command will be sent from YLTC to the transformer OLTC. If nec-
essary, the procedure will be repeated until the magnitude of the busbar voltage again falls
within the inner deadband. One half of the inner deadband will be denoted as Uin from here on.
The inner deadband Uin, (i.e. parameter UDeadbandInner in the setting tool under the ATCC
function) should be set to a value smaller than U. It is recommended to set the inner deadband
to 25-70% of the U value.
This way of working is used by the ATCC while the busbar voltage is within the security range
[Umin ,Umax]
A situation where UB falls outside this range will be regarded as an abnormal situation.
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Voltage control (VCTR) Chapter 11
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Instead of controlling the voltage at the LV busbar in the same substation as the transformer it-
self, it is possible to control the voltage at a load point out in the network, downstream from the
transformer. The Line Voltage Drop Compensation (LDC) can be selected by a setting parame-
ter, and it works such that the voltage drop from the transformer location to the load point is cal-
culated based on the measured load current and the known line impedance.
In order to prevent unnecessary OLTC operations caused by temporary voltage fluctuations and
to coordinate OLTC operations in radial networks, a time delay is used for the tapping command
to the OLTC. The time delay can be either definite time or inverse time and two time settings
are used, the first (t1) for the initial delay of a tap command, and the second (t2) for consecutive
tap commands.
Three alternative methods can be used for parallel control with the ATCC function: the mas-
ter-follower method, the reverse reactance method and the circulating current method.
The followers can act in one of two alternative ways selected by a setting parameter:
1. Raise and lower commands (URAISE and ULOWER) generated by the master,
initiates the corresponding command in all follower ATCCs simultaneously, and
consequently they will blindly follow the master irrespective of their individual
tap positions
2. The followers read the tap position of the master and adapt to the same tap posi-
tion or to a tap position with an offset relative to the master. In this mode, the fol-
lowers can also be time delayed relative to the master.
When the voltage at a load point is controlled by using LDC, the line impedance from the trans-
former to the load point must be given as a setting parameter. If a negative reactance is entered
instead of the normal positive line reactance, parallel transformers will act in such a way that the
transformer with a higher tap position will be the first to tap down when the busbar voltage in-
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Voltage control (VCTR) Chapter 11
Control
creases, and the transformer with a lower tap position will be the first to tap up when the busbar
voltage decreases. The overall performance will then be that a runaway tap situation will be
avoided and that the circulating current will be minimized.
The main objectives of the circulating current method for parallel voltage control are:
The busbar voltage UB is measured individually for each transformer in the parallel group by its
associated ATCC function. These measured values will then be exchanged between the trans-
formers, and in each ATCC block, the mean value of all UB values will be calculated. The re-
sulting value UBmean will then be used in each terminal instead of UB for the voltage regulation,
thus assuring that the same value is used by all ATCC functions, and thereby avoiding that one
erroneous measurement in one transformer could upset the voltage regulation. At the same time,
supervision of the VT mismatch is also performed.
Figure 282 shows an example with two transformers connected in parallel. If transformer T1 on
this picture has higher no load voltage it will drive a circulating current which adds to the load
current in T1 and subtracts from the load current in T2.
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Voltage control (VCTR) Chapter 11
Control
U T1 I U T2
cc....T2
I
cc....T2
+ +
T1 T2 ZT1 ZT2
IT1 IT2
I
cc....T1
I
cc....T1
IT1 IT2
UB
IL IL
UL Load Load
UL
en06000484.vsd
It can be shown that the magnitude of the circulating current in this case can be approximately
calculated with the formula:
UT 1 UT 2
I cc _ T 1 = I cc _ T 2 =
ZT 1 + ZT 2
(Equation 95)
Because the transformer impedance is dominantly inductive, it is possible to use just the trans-
former reactances in the above formula. At the same time this means that T1 circulating current
lags the busbar voltage by almost 90, whilst T2 circulating current leads the busbar voltage by
almost 90, see figure 283.
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Voltage control (VCTR) Chapter 11
Control
UT1 CT1*ICC_T1*ZT1
UB
CT2*ICC_T2*ZT2
UT2
IL
IT2 IT1
2*Udeadband
ICC_T2 ICC_T1
T2 Receives Cir_Curr T1 Produces Cir_Curr
IL = IT1+ IT2
Icc_T1 = Imag {IT1- (ZT2/(ZT1+ZT2)) * IL}
Icc_T2 = Imag {IT2- (ZT1/(ZT1+ZT2)) * IL}
en06000525.vsd
Figure 283: Vector diagram for two power transformers working in parallel
Thus, by minimizing the circulating current flow through transformers, the total reactive power
flow is optimized as well. In the same time, at this optimum state the apparent power flow is
distributed among the transformers in the group in proportion to their rated power.
In order to calculate the circulating current, measured current values for the individual trans-
formers must be communicated between the participating ATCC functions. It should be noted
that the Fourier filters in different IEDs run asynchronously, which means that current and volt-
age phasors cannot be exchanged and used for calculation directly between the IEDs. In order
to synchronize measurements within all IEDs in the parallel group, a common reference must
be chosen. The most suitable reference quantity for all transformers, belonging to the same par-
allel group, is the busbar voltage. This means that the measured busbar voltage is used as a ref-
erence phasor in all IEDs, and the position of the current phasors in a complex plane is calculated
in respect to this reference. This is a simple and effective solution, which eliminates any addi-
tional need for synchronization between the IEDs regarding the ATCC function.
At each transformer bay, the real and imaginary parts of the current on the secondary side of the
transformer are calculated from measured values, and distributed to the ATCC functions belong-
ing to the same parallel group.
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Voltage control (VCTR) Chapter 11
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As mentioned before, only the imaginary part (i.e. reactive current component) of the individual
transformer current is needed for the circulating current calculations. The real part of the current
will, however, be used to calculate the total through load current and will be used for the line
voltage drop compensation.
The total load current is defined as the sum of all individual transformer currents:
k
I L = Ii
i =1
(Equation 96)
where the subscript i signifies the transformer bay number and k the number of parallel trans-
formers in the group (k 8). Next step is to extract the circulating current Icc_i that flows in bay
i. It is possible to identify a term in the bay current which represents the circulating current. The
magnitude of the circulating current in bay i, Icc_i , can be calculated as:
I cc _ i = Im( I i K i I L )
(Equation 97)
where Im signifies the imaginary part of the expression in brackets and Ki is a constant which
depends on the number of transformers in the parallel group and their short-circuit reactances.
The ATCC function automatically calculates this constant based on the transformer reactances
which are setting parameters, and shall be given in primary ohms calculated from each trans-
former rating plate. The minus sign is added in the above equation in order to get a positive val-
ue of the circulating current for the transformer that generates it.
In this way each ATCC function calculates the circulating current of its own bay.
A plus sign means that the transformer produces circulating current whilst a minus sign means
that the transformer receives circulating current.
As a next step, it is necessary to estimate the value of the no-load voltage in each transformer.
To do that the magnitude of the circulating current in each bay is first converted to a voltage de-
viation, Udi, with the following formula:
U di = Ci I cc _ i X i
(Equation 98)
where Xi is the short-circuit reactance for transformer i and Ci, is a setting parameter named
Comp which serves the purpose of alternatively increasing or decreasing the impact of the cir-
culating current in the ATCC control calculations. It should be noted that Udi will have positive
values for transformers that produce circulating current and negative values for transformers that
receive circulating current.
Now the magnitude of the no-load voltage for each transformer can be approximated with:
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Voltage control (VCTR) Chapter 11
Control
U i = U Bmean + U di
(Equation 99)
Generally speaking, this value for the no-load voltage can then be put into the voltage control
function in a similar way as for the single transformer described previously. Ui would then be
regarded similarly to the single transformer measured busbar voltage, and further control actions
taken.
For the transformer producing/receiving the circulating current, the calculated no-load voltage
will be greater/smaller than the measured voltage UBmean. The calculated no-load voltage will
thereafter be compared with the set voltage Uset. A steady deviation which is outside the outer
deadband will result in ULOWER or URAISE being initiated alternatively. In this way the over-
all control action will always be correct since the position of a tap changer is directly related to
the transformer no-load voltage. The sequence resets when UBmean is inside the inner deadband
at the same time as the calculated no-load voltages for all transformers in the parallel group are
inside the outer deadband. The example in figure 284,is a fabricated case and not very realistic,
but it illustrates some details on how the described regulation works.
T1 T2 T3 T4
UBmean
T1 No-load voltage
DB1
DB2
Uset
DB2
DB1
en06000526.vsd
Figure 284: Selection of transformer to tap
619
Voltage control (VCTR) Chapter 11
Control
In the figure 284, voltage is considered as increasing above the line denoted Uset, and decreasing
below that line.
In the ATCC function for T1 and T4, the calculated no-load voltage for T1 and T4 respectively,
is above the upper limit of DB1 and thus outside the deadband.
In the ATCC function for T2, the calculated no-load voltage for T2, viewed from the upper DB1,
is not outside (above) the deadband, but as viewed from the lower DB1 it is outside (below) the
deadband. However, there is a restriction in a situation like this, when the measured busbar volt-
age, UBmean, is on the opposite side of the Uset line (in figure 284), then UBmean must be inside
DB1 if the calculated no-load voltage for that transformer shall qualify as a candidate for tap-
ping. Thus in the example above, the calculated no-load voltage for T2, although below DB1,
would not be considered for tapping in this case.
In the ATCC function for T3, the calculated no-load voltage for T3, is above the upper limit of
DB1 and thus outside the deadband. However, viewed from the upper limit DB1, transformers
with negative voltage deviation, Udi, are disregarded and similarly, viewed from the lower limit
DB1, transformers with positive voltage deviation, Udi, are disregarded. Thus in the example
above, the calculated no-load voltage for T3, although above DB1, would not be considered in
this case..Thus in the example above, the calculated no-load voltage for T3, although above
DB1, would not be considered for tapping in this case.
It is possible to avoid simultaneous tapping, and to distribute tapping actions evenly among the
parallel transformers in a busbar group. This is a selected by a setting parameter, and the algo-
rithm in the ATCC function will then select the transformer with the greatest voltage deviation
Udi to tap first, i.e. after time delay t1. Thereafter, the transformer with the then greatest value
of Udi amongst the remaining transformers in the group will tap after a further time delay t2, and
so on. This is made possible as the calculation of Icc is updated every time the measured values
are exchanged on the horizontal communication (every 300 ms). If two transformers have equal
magnitude of Udi, then there is a predetermined order governing which one is going to tap first.
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Voltage control (VCTR) Chapter 11
Control
Logic diagrams
AUTO
UL a
a<b
< &
U1 INNER DB b &
a
a>b
>
U2 INNER DB b &
a
a<b
>1 URAISE
<
U1 DB b
a
a>b
>1
> >1 ULOWER
U2 DB b
UB a
a>b
>
U MAX b &
FSD &
en06000509.vsd
Figure 285: Simplified logic for automatic control in single mode operation
621
Voltage control (VCTR) Chapter 11
Control
AUTO
PARALLEL START
&
OPERSIMTAP
UL a
a<b
< &
U1 INNER DB b &
&
a
a>b
>
U2 INNER DB b &
U CIRCCOMP
&
MIN a
a<b
>1 URAISE
<
U1 DB b >1
U CIRCCOMP
MAX a
a>b
>1
> >1 ULOWER
U2 DB b >1
UB a
a>b
>
U MAX b &
FSD &
en06000511.vsd
Figure 286: Simplified logic for parallel control in the circulating current mode
622
Voltage control (VCTR) Chapter 11
Control
UCCT4 a
a=b
b &
T4PG &
T4
UCCT3 a 1
a=b & 1
b & & &
T3
1
T3PG SIMLOWER
UCCT2 a
a=b
1 &
b & &
T2
T2PG
UCCT1 a &
a=b
1 &
& T1
b
MAX
T1PG
a
a=b
b &
&
T1
a 1
a=b & 1
b & & &
T2PG T2
1
SIMRAISE
a
a=b
1 &
b & &
T3
T3PG
a &
a=b
1 &
T4
b &
T4PG
MIN
ADAPT
a
1
a=b
ActualUser b
1 1
1
Udeadband a
a=b
b
LoadVoltage
HOMING
OperSimTap
1
en06000521.vsd
Figure 287: Simplified logic for simultaneous tapping prevention
623
Voltage control (VCTR) Chapter 11
Control
relativePosition a
a<b
<
raiseVoltageOut
b &
&
lowerVoltageOut
a
a>b
> =
b & URAISE
& 1
Follow Tap
&
& = ULOWER
1 1
YLTCOUT ATCCIN
tapPosition &
&
tapInHighVoltPos
tapInLowVoltPos
en06000510.vsd
1. Via binary input signals, one per tap position (max. 32 positions).
2. Via coded binary (Binary), decimal binary coded (BCD) signals or Gray coded
binary signals.
3. Via a mA input signal.
First option: Via binary input signals, one per tap position.
In this option, each tap position has a separate contact that is hard wired to a binary input in the
IED670. Via the Signal Matrix TOOL (SMT) and CAP configuration, the contacts on the binary
input card are then directly connected to the inputs B1 B32 on he YLTC function block.
624
Voltage control (VCTR) Chapter 11
Control
Second option: Via coded binary (Binary), decimal binary coded (BCD) signals or Gray
coded binary signals.
The YLTC function decodes binary data from up to six binary inputs to an integer value. The
input pattern may be decoded either as BIN, BCD or GRAY format depending on the setting of
the parameter CodeType which can be set in PST or at the HMI.
It is also possible to use even parity check of the input binary signal. Whether the parity check
shall be used or not is set in PST/HMI with the setting parameter UseParity.
The input BIERR of the YLTC function block can be used as supervisory input for indication of
any external error (e.g. Binary Input Module) in the system for reading of tap changer position.
Likewise, the input OUTERR can be used as a supervisory of the Binary Output Module.
The truth table below shows the conversion for Binary coded, BCD coded and Gray coded sig-
nals.
625
Voltage control (VCTR) Chapter 11
Control
626
Voltage control (VCTR) Chapter 11
Control
The Gray code conversion above is not complete and therefore the conversion from decimal
numbers to Gray code is given below.
627
Voltage control (VCTR) Chapter 11
Control
The measurement of the tap changer position via MIM card is based on the principle that the
specified mA input signal range (usually 4-20 mA) is divided into N intervals corresponding to
the number of positions available on the tap changer. All mA values within one interval are then
associated with one tap changer position value.
The number of available tap changer positions N is defined by the setting parameters LowVolt-
Tap and HighVoltTap which define the tap position for lowest voltage and highest voltage re-
spectively.
On the MIM card the parameter Operation shall be set On and the parameter RepInt shall be set
to a non-zero value (for example 1 second).
628
Voltage control (VCTR) Chapter 11
Control
(Rmk. In case
of parallel
TVC1-(7296,100) TTC1-(7304,100) control, this
TCYLTC_84 signal shall
TR8ATCC_90
also be
I3P1 ATCCOUT YLTCIN URAISE
TCINPRO connected to
I3P2 MAN ULOWER HORIZx input
G
U3P2 AUTO INERR HIPOSAL of the parallel
transformer
BLOCK IBLK RESETERR LOPOSAL ATCC function
MANCTRL PGTFWD OUTERR POSERRAL block)
AUTOCTRL PLTREV RS_CLCNT CMDERRAL
PSTO QGTFWD RS_OPCNT TCERRAL
RAISEV QLTREV PARITY POSOUT
LOWERV REVACBLK BIERR CONVERR
EAUTOBLK UHIGH B1 NEWPOS
DEBLKAUT ULOW B2 HIDIFPOS
LVA1 UBLK B3 INVALPOS
LVA2 HOURHUNT B4 TCPOS
LVA3 DAYHUNT B5 YLTCOUT
LVA4 HUNTING B6
LVARESET SINGLE B7
RSTERR PARALLEL B8
DISC HOMING B9
Q1ON ADAPT B10
Q2ON TOTBLK B11
Q3ON AUTOBLK B12
SNGLMODE MASTER B13
T1INCLD FOLLOWER B14
T2INCLD MFERR B15
T3INCLD OUTOFPOS B16
T4INCLD COMMERR B17
T5INCLD ICIRC B18
T6INCLD TRFDISC B19
T7INCLD VTALARM B20
T8INCLD T1PG B21
FORCMAST T2PG B22
RSTMAST T3PG B23
ATCCIN T4PG B24
HORIZ1 T5PG B25
HORIZ2 T6PG B26
HORIZ3 T7PG B27
HORIZ4 T8PG B28
HORIZ5 B29
HORIZ6 B30
HORIZ7 B31
HORIZ8 B32
MA
en06000507.vsd
The ATCC function block has an output ATCCOUT. This output contains two sets of signals.
One is the data set that needs to be sent to the YLTC input YLTCIN and the other is the data
set that needs to be sent to other ATCC blocks in the same parallel group in case of parallel con-
trol with the master-follower or circulating current mode.
629
Voltage control (VCTR) Chapter 11
Control
The data set sent from ATCCOUT to YLTCIN contains 5 binary signals, one word containing
10 binary signals and 1 analog signal.
In case of parallel control of transformers, the data set sent from ATCCOUT to other ATCC
blocks input HORIZx contains one "word" containing 10 binary signals and 6 analog signals:
630
Voltage control (VCTR) Chapter 11
Control
The YLTC function block has an output "YLTCOUT". As shown in figure 289, this output shall
be connected to the input "ATCCIN" and it contains 10 binary signals and 4 integer signals:
631
Voltage control (VCTR) Chapter 11
Control
Signal Description
tapChgError This is set high when the tap changer has not carried through a raise/lower com-
mand within the expected max. time, or if the tap changer starts tapping without a
given command.
cmdError This is set high if a given raise/lower command is not followed by a tap position
change within the expected max. time
raiseVoltageFb Feedback to the ATCC that a raise command shall be executed
lowerVoltageFb Feedback to the ATCC that a lower command shall be executed
timeOutTC Setting value of timer tTCTimeout
VCS1-
TR1ATCC_90
I3P1 ATCCOUT
I3P2 MAN
U3P2 AUTO
BLOCK IBLK
MANCTRL PGTFWD
AUTOCTRL PLTREV
PSTO QGTFWD
RAISEV QLTREV
LOWERV REVACBLK
EAUTOBLK UHIGH
DEBLKAUT ULOW
LVA1 UBLK
LVA2 HOURHUNT
LVA3 DAYHUNT
LVA4 HUNTING
LVARESET TOTBLK
RSTERR AUTOBLK
ATCCIN
en07000041.vsd
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Voltage control (VCTR) Chapter 11
Control
VCP1-
TR8ATCC_90
I3P1 ATCCOUT
I3P2 MAN
U3P2 AUTO
BLOCK IBLK
MANCTRL PGTFWD
AUTOCTRL PLTREV
PSTO QGTFWD
RAISEV QLTREV
LOWERV REVACBLK
EAUTOBLK UHIGH
DEBLKAUT ULOW
LVA1 UBLK
LVA2 HOURHUNT
LVA3 DAYHUNT
LVA4 HUNTING
LVARESET SINGLE
RSTERR PARALLEL
DISC HOMING
Q1ON ADAPT
Q2ON TOTBLK
Q3ON AUTOBLK
SNGLMODE MASTER
T1INCLD FOLLOWER
T2INCLD MFERR
T3INCLD OUTOFPOS
T4INCLD COMMERR
T5INCLD ICIRC
T6INCLD TRFDISC
T7INCLD VTALARM
T8INCLD T1PG
FORCMAST T2PG
RSTMAST T3PG
ATCCIN T4PG
HORIZ1 T5PG
HORIZ2 T6PG
HORIZ3 T7PG
HORIZ4 T8PG
HORIZ5
HORIZ6
HORIZ7
HORIZ8
en07000040.vsd
633
Voltage control (VCTR) Chapter 11
Control
TCM1-
TCMYLTC_84
YLTCIN URAISE
TCINPROG ULOWER
INERR HIPOSAL
RESETERR LOPOSAL
OUTERR POSERRAL
RS_CLCNT CMDERRAL
RS_OPCNT TCERRAL
PARITY POSOUT
BIERR CONVERR
B1 NEWPOS
B2 HIDIFPOS
B3 INVALPOS
B4 TCPOS
B5 YLTCOUT
B6
MA
en07000038.vsd
634
Voltage control (VCTR) Chapter 11
Control
TCL1-
TCLYLTC_84
YLTCIN URAISE
TCINPROG ULOWER
INERR HIPOSAL
RESETERR LOPOSAL
OUTERR POSERRAL
RS_CLCNT CMDERRAL
RS_OPCNT TCERRAL
PARITY POSOUT
BIERR CONVERR
B1 NEWPOS
B2 HIDIFPOS
B3 INVALPOS
B4 TCPOS
B5 YLTCOUT
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
MA
en07000037.vsd
VCR1-
VCTRReceive
BLOCK VCTR_REC
NAME
GRPNAME
en07000045.vsd
635
Voltage control (VCTR) Chapter 11
Control
Table 321: Output signals for the TR1ATCC_90 (VCS1-) function block
Signal Description
ATCCOUT Group connection to horizontal communication and YLTCIN
MAN The control is in manual mode
AUTO Automatic control mode is active
IBLK One phase current is above the settable limit
PGTFWD Active power above the settable limit powerActiveForw
PLTREV Active power below the settable limit powerActiveRev
QGTFWD Reactive power above the settable limit powerReactiveForw
QLTREV Reactive power below the settable limit powerReactiveRev
REVACBLK Block caused by reversed action
UHIGH Busbar voltage above the settable limit voltBusbMaxLimit
ULOW Busbar voltage below the settable limit voltBusbMinLimit
UBLK Busbar voltage below the settable limit voltBusbBlockLimit
636
Voltage control (VCTR) Chapter 11
Control
Signal Description
HOURHUNT Alarm for to many commands within the latest hour
DAYHUNT Alarm for to many commands within the latest day
HUNTING Alarm from to many commands in opposite direction
TOTBLK Block of auto and manual commands
AUTOBLK Block of auto commands
Table 322: Input signals for the TR8ATCC_90 (VCP1-) function block
Signal Description
I3P1 Input group for current on HV side
I3P2 Input group for current on LV side
U3P2 Input group for voltage on LV side
BLOCK Block of function
MANCTRL Binary "MAN" command
AUTOCTRL Binary "AUTO" command
PSTO Operator place selection
RAISEV Binary "UP" command
LOWERV Binary "DOWN" command
EAUTOBLK Block the voltage control in automatic control mode
DEBLKAUT Binary "Deblock Auto" command
LVA1 Activation of load voltage adjust. factor 1
LVA2 Activation of load voltage adjust. factor 2
LVA3 Activation of load voltage adjust. factor 3
LVA4 Activation of load voltage adjust. factor 4
LVARESET Reset LVA adjustment to 0
RSTERR Resets the automatic control commands raise and lower
DISC Disconnected transformer
Q1ON Capacitor or reactor bank 1 connected
Q2ON Capacitor or reactor bank 2 connected
Q3ON Capacitor or reactor bank 3 connected
SNGLMODE The voltage control in single control
T1INCLD Transformer1 included in parallel group
T2INCLD Transformer2 included in parallel group
T3INCLD Transformer3 included in parallel group
T4INCLD Transformer4 included in parallel group
T5INCLD Transformer5 included in parallel group
T6INCLD Transformer6 included in parallel group
T7INCLD Transformer7 included in parallel group
T8INCLD Transformer8 included in parallel group
637
Voltage control (VCTR) Chapter 11
Control
Signal Description
FORCMAST Force transformer to master
RSTMAST Reset forced master transformer to default
ATCCIN Group connection from YLTCOUT
HORIZ1 Group connection for horizontal communication from T1
HORIZ2 Group connection for horizontal communication from T2
HORIZ3 Group connection for horizontal communication from T3
HORIZ4 Group connection for horizontal communication from T4
HORIZ5 Group connection for horizontal communication from T5
HORIZ6 Group connection for horizontal communication from T6
HORIZ7 Group connection for horizontal communication from T7
HORIZ8 Group connection for horizontal communication from T8
Table 323: Output signals for the TR8ATCC_90 (VCP1-) function block
Signal Description
ATCCOUT Group connection to horizontal communication and YLTCIN
MAN The control is in manual mode
AUTO Automatic control mode is active
IBLK One phase current is above the settable limit
PGTFWD Active power above the settable limit powerActiveForw
PLTREV Active power below the settable limit powerActiveRev
QGTFWD Reactive power above the settable limit powerReactiveForw
QLTREV Reactive power below the settable limit powerReactiveRev
REVACBLK Block caused by reversed action
UHIGH Busbar voltage above the settable limit voltBusbMaxLimit
ULOW Busbar voltage below the settable limit voltBusbMinLimit
UBLK Busbar voltage below the settable limit voltBusbBlockLimit
HOURHUNT Alarm for to many commands within the latest hour
DAYHUNT Alarm for to many commands within the latest day
HUNTING Alarm from to many commands in opposite direction
SINGLE The transformer operates in single mode
PARALLEL The transformer operates in parallel mode
HOMING Transformer is in homing conditions
ADAPT The transformer is adapting
TOTBLK Block of auto and manual commands
AUTOBLK Block of auto commands
MASTER The transformer is master
FOLLOWER This transformer is a follower
MFERR The number of masters is different from one
638
Voltage control (VCTR) Chapter 11
Control
Signal Description
OUTOFPOS To high difference in tap positions
COMMERR Communication error
ICIRC Block from high circulating current
TRFDISC The transformer is disconnected
VTALARM VT supervision alarm
T1PG Transformer1 included in parallel group
T2PG Transformer2 included in parallel group
T3PG Transformer3 included in parallel group
T4PG Transformer4 included in parallel group
T5PG Transformer5 included in parallel group
T6PG Transformer6 included in parallel group
T7PG Transformer7 included in parallel group
T8PG Transformer8 included in parallel group
Table 324: Input signals for the TCMYLTC_84 (TCM1-) function block
Signal Description
YLTCIN Input group connection for YLTC
TCINPROG Indication that tap is moving
INERR Supervision signal of the input board
RESETERR Reset of command and tap error
OUTERR Supervision off the digital output board
RS_CLCNT Reset of the contact life counter
RS_OPCNT Resets the operation counter
PARITY Parity bit from tap changer for the tap position
BIERR Error bit from tap changer for the tap position
B1 Bit 1 from tap changer for the tap position
B2 Bit 2 from tap changer for the tap position
B3 Bit 3 from tap changer for the tap position
B4 Bit 4 from tap changer for the tap position
B5 Bit 5 from tap changer for the tap position
B6 Bit 6 from tap changer for the tap position
MA mA from tap changer for the tap position
639
Voltage control (VCTR) Chapter 11
Control
Table 325: Output signals for the TCMYLTC_84 (TCM1-) function block
Signal Description
URAISE Raise voltage command to tap changer
ULOWER Lower voltage command to tap changer
HIPOSAL Alarm for tap in highest volt position
LOPOSAL Alarm for tap in lowest volt position
POSERRAL Alarm that indicates a problem with the position indication
CMDERRAL Alarm for a command without an expected position change
TCERRAL Alarm for none or illegal tap position change
POSOUT Tap position outside min and max position
CONVERR General tap position conversion error
NEWPOS A new tap position is reported, 1 sec pulse
HIDIFPOS Tap position has changed more than one position
INVALPOS Last position change was an invalid change
TCPOS Integer value corresponding to actual tap position
YLTCOUT Group connection to ATCCIN
Table 326: Input signals for the TCLYLTC_84 (TCL1-) function block
Signal Description
YLTCIN Input group connection for YLTC
TCINPROG Indication that tap is moving
INERR Supervision signal of the input board
RESETERR Reset of command and tap error
OUTERR Supervision off the digital output board
RS_CLCNT Reset of the contact life counter
RS_OPCNT Resets the operation counter
PARITY Parity bit from tap changer for the tap position
BIERR Error bit from tap changer for the tap position
B1 Bit 1 from tap changer for the tap position
B2 Bit 2 from tap changer for the tap position
B3 Bit 3 from tap changer for the tap position
B4 Bit 4 from tap changer for the tap position
B5 Bit 5 from tap changer for the tap position
B6 Bit 6 from tap changer for the tap position
B7 Bit 7 from tap changer for the tap position
B8 Bit 8 from tap changer for the tap position
B9 Bit 9 from tap changer for the tap position
B10 Bit 10 from tap changer for the tap position
B11 Bit 11 from tap changer for the tap position
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Voltage control (VCTR) Chapter 11
Control
Signal Description
B12 Bit 12 from tap changer for the tap position
B13 Bit 13 from tap changer for the tap position
B14 Bit 14 from tap changer for the tap position
B15 Bit 15 from tap changer for the tap position
B16 Bit 16 from tap changer for the tap position
B17 Bit 17 from tap changer for the tap position
B18 Bit 18 from tap changer for the tap position
B19 Bit 19 from tap changer for the tap position
B20 Bit 20 from tap changer for the tap position
B21 Bit 21 from tap changer for the tap position
B22 Bit 22 from tap changer for the tap position
B23 Bit 23 from tap changer for the tap position
B24 Bit 24 from tap changer for the tap position
B25 Bit 25 from tap changer for the tap position
B26 Bit 26 from tap changer for the tap position
B27 Bit 27 from tap changer for the tap position
B28 Bit 28 from tap changer for the tap position
B29 Bit 29 from tap changer for the tap position
B30 Bit 30 from tap changer for the tap position
B31 Bit 31 from tap changer for the tap position
B32 Bit 32 from tap changer for the tap position
MA mA from tap changer for the tap position
Table 327: Output signals for the TCLYLTC_84 (TCL1-) function block
Signal Description
URAISE Raise voltage command to tap changer
ULOWER Lower voltage command to tap changer
HIPOSAL Alarm for tap in highest volt position
LOPOSAL Alarm for tap in lowest volt position
POSERRAL Alarm that indicates a problem with the position indication
CMDERRAL Alarm for a command without an expected position change
TCERRAL Alarm for none or illegal tap position change
POSOUT Tap position outside min and max position
CONVERR General tap position conversion error
641
Voltage control (VCTR) Chapter 11
Control
Signal Description
NEWPOS A new tap position is reported, 1 sec pulse
HIDIFPOS Tap position has changed more than one position
INVALPOS Last position change was an invalid change
TCPOS Integer value corresponding to actual tap position
YLTCOUT Group connection to ATCCIN
Table 328: Input signals for the VCTRReceive (VCR1-) function block
Signal Description
BLOCK Block of function
GRPNAME User define string for IN signal 0
Table 329: Output signals for the VCTRReceive (VCR1-) function block
Signal Description
VCTR_REC Received data from horizontal communication
642
Voltage control (VCTR) Chapter 11
Control
Table 331: Basic parameter group settings for the TR1ATCC_90 (VCS1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
I1Base 1 - 99999 1 3000 A Base setting for HV cur-
rent level in A
I2Base 1 - 99999 1 3000 A Base setting for LV cur-
rent level in A
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
level in kV
MeasMode L1 - PosSeq - Selection of measured
L2 voltage and current
L3
L1L2
L2L3
L3L1
PosSeq
TotalBlock Off - Off - Total block of the voltage
On control function
AutoBlock Off - Off - Block of the automatic
On mode in voltage control
function
FSDMode Off - Off - Fast step down function
Auto activation mode
AutoMan
tFSD 1.0 - 100.0 0.1 15.0 s Time delay for lower
command when FSD is
activated
USet 85.0 - 120.0 0.1 100.0 %UB Voltage control set volt-
age, % of rated voltage
643
Voltage control (VCTR) Chapter 11
Control
644
Voltage control (VCTR) Chapter 11
Control
Table 332: Basic general settings for the TCMYLTC_84 (TCM1-) function
Parameter Range Step Default Unit Description
LowVoltTap 1 - 63 1 1 - Tap position for lowest
voltage
HighVoltTap 1 - 63 1 33 - Tap position for highest
voltage
mALow 0.000 - 25.000 0.001 4.000 mA mA for lowest voltage tap
position
mAHigh 0.000 - 25.000 0.001 20.000 mA mA for highest voltage
tap position
CodeType BIN - BIN - Type of code conversion
BCD
GRAY
SINGLE
mA
645
Voltage control (VCTR) Chapter 11
Control
Table 333: Basic parameter group settings for the TCMYLTC_84 (TCM1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
IBase 1 - 99999 1 3000 A Base current in primary
Ampere for the HV-side
tTCTimeout 1 - 120 1 5 s Tap changer constant
time-out
tPulseDur 0.5 - 10.0 0.1 1.5 s Raise/lower command
output pulse duration
Table 334: Basic general settings for the TCLYLTC_84 (TCL1-) function
Parameter Range Step Default Unit Description
LowVoltTap 1 - 63 1 1 - Tap position for lowest
voltage
HighVoltTap 1 - 63 1 33 - Tap position for highest
voltage
mALow 0.000 - 25.000 0.001 4.000 mA mA for lowest voltage tap
position
mAHigh 0.000 - 25.000 0.001 20.000 mA mA for highest voltage
tap position
CodeType BIN - BIN - Type of code conversion
BCD
GRAY
SINGLE
mA
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Voltage control (VCTR) Chapter 11
Control
Table 335: Basic parameter group settings for the TCLYLTC_84 (TCL1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
On
IBase 1 - 99999 1 3000 A Base current in primary
Ampere for the HV-side
tTCTimeout 1 - 120 1 5 s Tap changer constant
time-out
tPulseDur 0.5 - 10.0 0.1 1.5 s Raise/lower command
output pulse duration
647
Voltage control (VCTR) Chapter 11
Control
648
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
5.1 Introduction
The SLGGIO function block (or the selector switch function block) is used within the CAP tool
in order to get a selector switch functionality similar with the one provided by a hardware selec-
tor switch. Hardware selector switches are used extensively by utilities, in order to have different
functions operating on pre-set values. Hardware switches are however sources for maintenance
issues, lower system reliability and extended purchase portfolio. The virtual selector switches
eliminate all these problems.
Besides the inputs visible in CAP configuration tool, there are other executable inputs that
will allow an user to set the desired position directly (without activating the intermediate posi-
tions), either locally or remotely, using a select before execute dialog. One can block the func-
tion operation, by activating the BLOCK input. In this case, the present position will be kept and
further operation will be blocked. The operator place (local or remote) is specified through the
PSTO input. If any operation is allowed the signal INTONE from the Fixed signal function block
can be connected. The SLGGIO function block has also an integer value output, that generates
the actual position number. The positions and the block names are fully settable by the user.
These names will appear in the menu, so the user can see the position names instead of a number.
649
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
1 2 3
../Ctrl/Com/Sel Sw ../Com/Sel Sw/SL03 ../Com/Sel Sw/SL03
SL01 Damage ctrl Damage ctrl
4 4
SL02
..
..
SL15
OK Cancel
4
5
The dialog window that appears
../Com/Sel Sw/ shows the present position (P:)
DmgCtrl 7
and the new position (N:), both
Damage ctrl: in clear names, given by the
user (max. 13 characters).
E
Modify the position with arrows.
The pos will not be modified (outputs
will not be activated) until you press
the E-button for O.K. en06000420.vsd
Figure 295: Example 1 on handling the switch from the local HMI.
650
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
if it is used just for the monitoring, the switches will be listed with their actual
position names, as defined by the user (max. 13 characters);
if it is used for control, the switches will be listed with their actual positions, but
only the first three letters of the name will be used;
In both cases, the switch full name will be shown, but the user has to redefine it when building
the Graphical Display Editor, under the "Caption". If used for the control, the following se-
quence of commands will ensue:
651
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
../Control/SLD/Switch O I ../Control/SLD/Switch
AR control AR control
WFM Select switch. Press the
WFM
I or O key. A dialog box
Pilot setup appears.
Pilot setup
OFF OFF
Damage control E P: Disc N: Disc Fe
DAL
The pos will not be modified
(outputs will not be activated) until OK Cancel
you press the E-button for O.K.
../Control/SLD/Switch
AR control
WFM
Pilot setup
OFF
Damage control
DFW
en06000421.vsd
Figure 296: Example 2 on handling the switch from the local HMI.
652
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
653
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
SL01-
SLGGIO
BLOCK SWPOS01
PSTO SWPOS02
UP SWPOS03
DOWN SWPOS04
SWPOS05
SWPOS06
SWPOS07
SWPOS08
SWPOS09
SWPOS10
SWPOS11
SWPOS12
SWPOS13
SWPOS14
SWPOS15
SWPOS16
SWPOS17
SWPOS18
SWPOS19
SWPOS20
SWPOS21
SWPOS22
SWPOS23
SWPOS24
SWPOS25
SWPOS26
SWPOS27
SWPOS28
SWPOS29
SWPOS30
SWPOS31
SWPOS32
SWPOSN
INSTNAME
NAME1
NAME2
NAME3
NAME4
NAME5
NAME6
NAME7
NAME8
NAME9
NAME10
NAME11
NAME12
NAME13
NAME14
NAME15
NAME16
NAME17
NAME18
NAME19
NAME20
NAME21
NAME22
NAME23
NAME24
NAME25
NAME26
NAME27
NAME28
NAME29
NAME30
NAME31
NAME32
en05000658.vsd
654
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
Table 338: Output signals for the SLGGIO (SL01-) function block
Signal Description
SWPOS01 Selector switch position 1
SWPOS02 Selector switch position 2
SWPOS03 Selector switch position 3
SWPOS04 Selector switch position 4
SWPOS05 Selector switch position 5
SWPOS06 Selector switch position 6
SWPOS07 Selector switch position 7
SWPOS08 Selector switch position 8
SWPOS09 Selector switch position 9
SWPOS10 Selector switch position 10
SWPOS11 Selector switch position 11
SWPOS12 Selector switch position 12
SWPOS13 Selector switch position 13
SWPOS14 Selector switch position 14
SWPOS15 Selector switch position 15
SWPOS16 Selector switch position 16
SWPOS17 Selector switch position 17
SWPOS18 Selector switch position 18
SWPOS19 Selector switch position 19
SWPOS20 Selector switch position 20
SWPOS21 Selector switch position 21
SWPOS22 Selector switch position 22
SWPOS23 Selector switch position 23
SWPOS24 Selector switch position 24
SWPOS25 Selector switch position 25
SWPOS26 Selector switch position 26
655
Logic rotating switch for function selection Chapter 11
and LHMI presentation (SLGGIO) Control
Signal Description
SWPOS27 Selector switch position 27
SWPOS28 Selector switch position 28
SWPOS29 Selector switch position 29
SWPOS30 Selector switch position 30
SWPOS31 Selector switch position 31
SWPOS32 Selector switch position 32
SWPOSN Switch position (integer)
656
Selector mini switch (VSGGIO) Chapter 11
Control
6.1 Introduction
The VSGGIO function block (or the versatile switch function block) is a multipurpose function
used within the CAP tool for a variety of applications, as a general purpose switch.
The switch can be controlled from the menu or from a symbol on the SLD of the LHMI.
for indication, receiving position through the IPOS1 and IPOS2 inputs and dis-
tributing it in the configuration through the POS1 and POS2 outputs or to
IEC61850 through reporting or GOOSE
for command, receiving commands via the HMI. HMI symbols Select button or
Indication button from menu (Control / Commands / Versatile Switch) or
IEC61850 and sending them in the configuration and especially to the outputs
(through a SMBO function block)
The PSTO input is connected to the Local remote switch to have a selection of operators place
, operation from local HMI (Local pos) or through IEC 61850 (Remote pos). An INTONE con-
nection from Fixed signal function block will allow operation from any operators place.
As it can be seen, both indications and commands are done in double-bit representation, where
a combination of signals on both inputs/outputs generate the desired result:
657
Selector mini switch (VSGGIO) Chapter 11
Control
VS01-
VSGGIO
BLOCK BLOCKED
PSTO POSITION
IPOS1 POS1
IPOS2 POS2
NAME_UND CMDPOS12
NAM_POS1 CMDPOS21
NAM_POS2
NAME_BAD
en06000508.vsd
Table 341: Output signals for the VSGGIO (VS01-) function block
Signal Description
BLOCKED The function is active but the functionality is blocked
POSITION Position indication, integer
POS1 Position 1 indication, logical signal
POS2 Position 2 indication, logical signal
CMDPOS12 Execute command from position 1 to position 2
CMDPOS21 Execute command from position 2 to position 1
658
Selector mini switch (VSGGIO) Chapter 11
Control
659
Single point generic control 8 signals Chapter 11
(SPC8GGIO) Control
7.1 Introduction
The SC function block is a collection of 8 single point commands, designed to bring in com-
mands from REMOTE (SCADA) or LOCAL (HMI) to those parts of the logic configuration that
do not need complicated function blocks that have the capability to receive commands (for ex-
ample SCSWI). In this way, simple commands can be sent directly to the IED outputs, without
confirmation. Confirmation (status) of the result of the commands is supposed to be achieved by
other means, such as binary inputs and SPGGIO function blocks.
SC01-
SPC8GGIO
BLOCK OUT1
PSTO OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
en07000143.vsd
660
Single point generic control 8 signals Chapter 11
(SPC8GGIO) Control
Table 344: Output signals for the SPC8GGIO (SC01-) function block
Signal Description
OUT1 Output 1
OUT2 Output2
OUT3 Output3
OUT4 Output4
OUT5 Output5
OUT6 Output6
OUT7 Output7
OUT8 Output8
661
Single point generic control 8 signals Chapter 11
(SPC8GGIO) Control
662
About this chapter Chapter 12
Scheme communication
Chapter 12 Scheme
communication
Also Local acceleration logic (ZCLC) is discussed which is a function that can generate instan-
taneous tripping as a result of remote end faults without any telecommunication.
The chapter contains a short description of the design, simplified logical block diagrams, figure
of the function block, input and output signals and setting parameters.
663
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
1.1 Introduction
To achieve fast fault clearance of earth faults on the part of the line not covered by the instanta-
neous step of the residual overcurrent protection, the directional residual overcurrent protection
can be supported with a logic that uses communication channels.
In the directional scheme, information of the fault current direction must be transmitted to the
other line end. With directional comparison, an operate time of the protection of 50 60 ms in-
cluding a channel transmission time of 20 ms, can be achieved. This short operate time enables
rapid autoreclosing function after the fault clearance.
The communication logic module for directional residual current protection enables blocking as
well as permissive under/overreach schemes. The logic can also be supported by additional logic
for weak-end-infeed and current reversal, included in the EFCA function.
In addition to this a signal from the autoreclosing function should be configured to the BLKCS
input for blocking of the function at a single phase reclosing cycle.
664
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
One advantage of the blocking scheme is that only one channel (carrier frequency) is needed if
the ratio of source impedances at both end is approximately equal for zero and positive sequence
source impedances, the channel can be shared with the impedance-measuring system, if that sys-
tem also works in the blocking mode. The power line carrier communication signal is transmit-
ted on a healthy line and no signal attenuation will occur due to the fault.
Blocking schemes are particular favorable for three-terminal applications if there is no zero-se-
quence outfeed from the tapping. The blocking scheme is immune to current reversals because
the received carrier signal is maintained long enough to avoid unwanted operation due to current
reversal. There is never any need for weak-end-infeed logic, because the strong end trips for an
internal fault when no blocking signal is received from the weak end. The fault clearing time is
however generally longer for a blocking scheme than for a permissive scheme.
If the fault is on the line, the forward direction measuring element operates. If no blocking signal
comes from the other line end via the CR binary input (carrier receive) the TRIP output is acti-
vated after the tCoord set time delay.
665
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
An impedance measuring relay which works in the same type of permissive mode, with one
channel in each direction, can share the channels with the communication scheme for residual
overcurrent protection. If the impedance measuring relay works in the permissive overreach
mode, common channels can be used in single-line applications. In case of double lines connect-
ed to a common bus at both ends, use common channels only if the ratio Z1S/Z0S (positive
through zero-sequence source impedance) is about equal at both ends. If the ratio is different,
the impedance measuring and the directional earth-fault current system of the healthy line may
detect a fault in different directions, which could result in unwanted tripping.
Common channels cannot be used when the weak-end-infeed function is used in the distance or
earth fault protection.
In case of an internal earth fault, the forward directed measuring element operates and sends a
permissive signal to the remote end via the CS output (carrier send). Local tripping is permitted
when the forward direction measuring element operates and a permissive signal is received via
the CR binary input (carrier receive).
The permissive scheme can of either underreach or overreach type. In the underreach alternative
an underreach directional residual overcurrent measurement element will be used as sending cri-
terion of the permissive send signal CSUR.
666
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
The unblocking function uses a carrier guard signal CRG, which must always be present, even
when no CR signal is received. The absence of the CRG signal for a time longer than the setting
tSecurity time is used as a CR signal, see figure 301. This also enables a permissive scheme to
operate when the line fault blocks the signal transmission.
The carrier received signal created by the unblocking function is reset 150 ms after the security
timer has elapsed. When that occurs an output signal LCG is activated for signalling purpose.
The unblocking function is reset 200 ms after that the guard signal is present again.
CR
tSecurity CRL
t >1
1
CRG
200 ms 150 ms
t OR t AND
AND
LCG
en05000746.vsd
The unblocking function can be set in three operation modes (setting Unblock):
667
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
EFC1-
ECPSCH_85
BLOCK TRIP
BLKTR CS
BLKCS CRL
CSBLK LCG
CACC
CSOR
CSUR
CR
CRG
en06000288.vsd
Table 346: Output signals for the ECPSCH_85 (EFC1-) function block
Signal Description
TRIP Trip by Communication Scheme Logic
CS Carrier Send by Communication Scheme Logic
CRL Carrier Receive from Communication Scheme Logic
LCG loss of carrier guard signal
668
Scheme communication logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
Table 348: Advanced parameter group settings for the ECPSCH_85 (EFC1-) function
Parameter Range Step Default Unit Description
Unblock Off - Off - Operation mode of
NoRestart unblocking logic
Restart
tSecurity 0.000 - 60.000 0.001 0.035 s Security timer for loss of
carrier guard detection
669
Current reversal and weak-end infeed logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
2.1 Introduction
The EFCA additional communication logic is a supplement to the EFC scheme communication
logic for the residual overcurrent protection.
To achieve fast fault clearing for all earth faults on the line, the directional earth-fault protection
function can be supported with logic, that uses communication channels. REx670 terminals have
for this reason available additions to scheme communication logic.
If parallel lines are connected to common busbars at both terminals, overreaching permissive
communication schemes can trip unselectively due to fault current reversal. This unwanted trip-
ping affects the healthy line when a fault is cleared on the other line. This lack of security can
result in a total loss of interconnection between the two buses. To avoid this type of disturbance,
a fault current-reversal logic (transient blocking logic) can be used.
Permissive communication schemes for residual overcurrent protection, can basically operate
only when the protection in the remote terminal can detect the fault. The detection requires a suf-
ficient minimum residual fault current, out from this terminal. The fault current can be too low
due to an opened breaker or high positive and/or zero sequence source impedance behind this
terminal. To overcome these conditions, weak end infeed (WEI) echo logic is used.
The circuits for the permissive overreach scheme contain logic for current reversal and weak end
infeed functions. These functions are not required for the blocking overreach scheme.
Use the independent or inverse time functions in the directional earth-fault protection module to
get back-up tripping in case the communication equipment malfunctions and prevents operation
of the directional comparison logic.
Connect the necessary signal from the auto-recloser for blocking of the directional comparison
scheme, during a single-phase auto-reclosing cycle, to the BLOCK input of the directional com-
parison module.
670
Current reversal and weak-end infeed logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
When the fault current is reversed on the non faulty line, IRV is deactivated and IRVBLK is ac-
tivated. The reset of IRVL is delayed by the tDelay time, see figure 303. This ensures the reset
of the carrier receive CR signal.
The weak end infeed logic uses normally a reverse and a forward direction element, connected
to WEIBLK via an OR-gate. See figure 304. If neither the forward nor the reverse directional
measuring element is activated during the last 200 ms. The weak-end-infeed logic echoes back
the received permissive signal. See figure 304.
If the forward or the reverse directional measuring element is activated during the last 200 ms,
the fault current is sufficient for the IED to detect the fault with the earth-fault function that is
in operation.
With the Trip setting, the logic sends an echo according to above. Further, it activates the TR-
WEI signal to trip the breaker if the echo conditions are fulfilled and the neutral point voltage is
above the set operate value for 3U0>
671
Current reversal and weak-end infeed logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
The voltage signal that is used to calculate the zero sequence voltage is set in the earth-fault
function that is in operation.
The weak end infeed echo sent to the strong line end has a maximum duration of 200 ms. When
this time period has elapsed, the conditions that enable the echo signal to be sent are set to zero
for a time period of 50 ms. This avoids ringing action if the weak end echo is selected for both
line ends.
EFCA-
ECRWPSCH_85
U3P IRVL
BLOCK TRWEI
IRVBLK ECHO
IRV CR
WEIBLK1
WEIBLK2
VTSZ
CBOPEN
CRL
en06000289.vsd
672
Current reversal and weak-end infeed logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
Table 351: Output signals for the ECRWPSCH_85 (EFCA-) function block
Signal Description
IRVL Operation of current reversal logic
TRWEI Trip of WEI logic
ECHO Carrier send by WEI logic
CR POR Carrier signal received from remote end
673
Current reversal and weak-end infeed logic Chapter 12
for residual overcurrent protection (PSCH, 85) Scheme communication
674
About this chapter Chapter 13
Logic
Chapter 13 Logic
675
Tripping logic (PTRC, 94) Chapter 13
Logic
1.1 Introduction
A function block for protection tripping is provided for each circuit breaker involved in the trip-
ping of the fault. It provides the pulse prolongation to ensure a trip pulse of sufficient length, as
well as all functionality necessary for correct co-operation with autoreclosing functions.
The trip function block includes functionality for evolving faults and breaker lock-out.
For three-pole tripping, TRPx function has a single input (TRIN) through which all trip output
signals from the protection functions within the IED, or from external protection functions via
one or more of the IEDs binary inputs, are routed. It has a single trip output (TRIP) for connec-
tion to one or more of the IEDs binary outputs, as well as to other functions within the IED re-
quiring this signal.
BLOCK
tTripMin TRIP
TRIN OR
AND t
Operation Mode = On
Program = 3Ph
en05000789.vsd
The TRPx function for single- and two-pole tripping has additional phase segregated inputs for
this, as well as inputs for faulted phase selection. The latter inputs enable single- and two-pole
tripping for those functions which do not have their own phase selection capability, and there-
676
Tripping logic (PTRC, 94) Chapter 13
Logic
fore which have just a single trip output and not phase segregated trip outputs for routing through
the phase segregated trip inputs of the expanded TRPx function. Examples of such protection
functions are the residual overcurrent protections. The expanded TRPx function has two inputs
for these functions, one for impedance tripping (e.g. carrier-aided tripping commands from the
scheme communication logic), and one for earth fault tripping (e.g. tripping output from a resid-
ual overcurrent protection). Additional logic secures a three-pole final trip command for these
protection functions in the absence of the required phase selection signals.
The expanded TRPx function has three trip outputs TRL1, TRL2, TRL3 (besides the trip output
TRIP), one per phase, for connection to one or more of the IEDs binary outputs, as well as to
other functions within the IED requiring these signals. There are also separate output signals in-
dicating single pole, two pole or three pole trip. These signals are important for cooperation with
the auto-reclosing function.
The expanded TRPx function is equipped with logic which secures correct operation for evolv-
ing faults as well as for reclosing on to persistent faults. A special input is also provided which
disables single- and two-pole tripping, forcing all tripping to be three-pole.
In multi-breaker arrangements, one TRPx function block is used for each breaker. This can be
the case if single pole tripping and auto-reclosing is used.
The breaker close lockout function can be activated from an external trip signal from another
protection function via input (SETLKOUT) or internally at a three pole trip, if desired.
It is possible to lockout seal in the tripping output signals or use blocking of closing only the
choice is by setting TripLockout.
TRINL1
TRINL2
OR
TRINL3
1PTRZ OR
1PTREF
OR
TRIN RSTTRIP - cont.
AND
Program = 3ph
en05000517.vsd
677
Tripping logic (PTRC, 94) Chapter 13
Logic
TRIN
TRINL1
PSL1 L1TRIP
OR
AND
TRINL2
PSL2 L2TRIP
OR
AND
TRINL3
PSL3 L3TRIP
OR
AND
OR
OR OR
-loop
-loop
OR
AND AND
AND
1PTREF AND 50 ms
1PTRZ OR t
en05000518.vsd
Figure 309: Phase segregated front logic
678
Tripping logic (PTRC, 94) Chapter 13
Logic
150 ms
L1TRIP OR
t RTRIP
OR
2000 ms
t
OR
AND
150 ms
L2TRIP OR
t STRIP
OR
2000 ms
t
OR
AND
150 ms
L3TRIP OR
t TTRIP
OR
2000 ms
t
OR
AND
OR
OR AND
P3PTR
OR
-loop
en05000519.vsd
Figure 310: Additional logic for the 1ph/3ph operating mode
679
Tripping logic (PTRC, 94) Chapter 13
Logic
150 ms
L1TRIP - cont.
t OR RTRIP
OR
2000 ms
t
AND
150 ms
L2TRIP
t OR STRIP
OR
2000 ms
t AND
AND
150 ms
L3TRIP
t OR TTRIP
OR
2000 ms
t
AND
OR
AND
TRIP OR
OR
-loop
en05000520.vsd
680
Tripping logic (PTRC, 94) Chapter 13
Logic
BLOCK
RTRIP TRL1
AND
OR
STRIP TRL2
AND
OR
TTRIP TRL3
AND
OR
RSTTRIP
TRIP
OR
TR3P
AND AND
OR
-loop
AND 10 ms
TR1P
AND t
AND 5 ms
TR2P
AND t
OR
AND
-loop
en05000521.vsd
Figure 312: Final tripping circuits
681
Tripping logic (PTRC, 94) Chapter 13
Logic
TRP1-
SMPPTRC_94
BLOCK TRIP
BLKLKOUT TRL1
TRIN TRL2
TRINL1 TRL3
TRINL2 TR1P
TRINL3 TR2P
PSL1 TR3P
PSL2 CLLKOUT
PSL3
1PTRZ
1PTREF
P3PTR
SETLKOUT
RSTLKOUT
en05000707.vsd
682
Tripping logic (PTRC, 94) Chapter 13
Logic
Table 355: Output signals for the SMPPTRC_94 (TRP1-) function block
Signal Description
TRIP General trip output signal
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
TR1P Tripping single-pole
TR2P Tripping two-pole
TR3P Tripping three-pole
CLLKOUT Circuit breaker lockout output (set until reset)
Table 357: Advanced parameter group settings for the SMPPTRC_94 (TRP1-) function
Parameter Range Step Default Unit Description
TripLockout Off - Off - On: activate output
On (CLLKOUT) and trip
latch, Off: only outp
AutoLock Off - Off - On: lockout from input
On (SETLKOUT) and trip,
Off: only inp
683
Trip matrix logic (GGIO) Chapter 13
Logic
2.1 Introduction
Twelve trip matrix logic blocks are included in the IED. The function blocks are used in the con-
figuration of the IED to route trip signals and/or other logical output signals to the different out-
put relays.
The matrix and the physical outputs will be seen in the PCM 600 engineering tool and this allows
the user to adapt the signals to the physical tripping outputs according to the specific application
needs.
Internal built-in OR logic is made in accordance with the following three rules:
1. when any one of first 16 inputs signals (i.e. INPUT1 to INPUT16) has logical val-
ue 1 (i.e. TRUE) the first output signal (i.e. OUTPUT1) will get logical value 1
(i.e. TRUE). Additional time delays can be introduced for OUTPUT1 via setting
parameters "PulseTime1", "OnDelayTime1" & "OffDelayTime1".
2. when any one of second 16 inputs signals (i.e. INPUT17 to INPUT32) has logical
value 1 (i.e. TRUE) the second output signal (i.e. OUTPUT2) will get logical val-
ue 1 (i.e. TRUE). Additional time delays can be introduced for OUTPUT2 via
setting parameters "PulseTime2", "OnDelayTime2" & "OffDelayTime2"
3. when any one of all 32 input signals (i.e. INPUT1 to INPUT32) has logical value
1 (i.e. TRUE) the third output signal (i.e. OUTPUT3) will get logical value 1 (i.e.
TRUE). Additional time delays can be introduced for OUTPUT3 via setting pa-
rameters "PulseTime3", "OnDelayTime3" & "OffDelayTime3".
684
Trip matrix logic (GGIO) Chapter 13
Logic
Pulse Time 1
&
Pulse t pulse
Input 1 Output 1
On Delay Time 1
&
1
Input 2
Input 16
1
t on t off
Off Delay Time 1
Pulse Time 2
&
t pulse
Pulse
Input 17 Output 2
Input 18
On Delay Time 2
&
1
Input 32
1
t on t off
Off Delay Time 2
Pulse Time 3
&
Pulse t pulse
Output 3
On Delay Time 3
&
1
1
t on t off
Off Delay Time 3
en06000514.vsd
Figure 314: Tripping Matrix Internal Logic.
Output signals from this function block are typically connected to other logic blocks or directly
to output contacts from the IED. When used for direct tripping of the circuit breaker(s) the pulse
time delay on that output signal shall be set to approximately 0,150s in order to obtain satisfac-
tory minimum duration of the trip pulse to the circuit breaker trip coils.
685
Trip matrix logic (GGIO) Chapter 13
Logic
T R01-
TRMGGIO
INPUT 1 OUT PUT 1
INPUT 2 OUT PUT 2
INPUT 3 OUT PUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
INPUT 8
INPUT 9
INPUT 10
INPUT 11
INPUT 12
INPUT 13
INPUT 14
INPUT 15
INPUT 16
INPUT 17
INPUT 18
INPUT 19
INPUT 20
INPUT 21
INPUT 22
INPUT 23
INPUT 24
INPUT 25
INPUT 26
INPUT 27
INPUT 28
INPUT 29
INPUT 30
INPUT 31
INPUT 32
en05000370.vsd
686
Trip matrix logic (GGIO) Chapter 13
Logic
Signal Description
INPUT12 Binary input 12
INPUT13 Binary input 13
INPUT14 Binary input 14
INPUT15 Binary input 15
INPUT16 Binary input 16
INPUT17 Binary input 17
INPUT18 Binary input 18
INPUT19 Binary input 19
INPUT20 Binary input 20
INPUT21 Binary input 21
INPUT22 Binary input 22
INPUT23 Binary input 23
INPUT24 Binary input 24
INPUT25 Binary input 25
INPUT26 Binary input 26
INPUT27 Binary input 27
INPUT28 Binary input 28
INPUT29 Binary input 29
INPUT30 Binary input 30
INPUT31 Binary input 31
INPUT32 Binary input 32
Table 360: Output signals for the TMAGGIO (TR01-) function block
Signal Description
OUTPUT1 OR function betweeen inputs 1 to 16
OUTPUT2 OR function between inputs 17 to 32
OUTPUT3 OR function between inputs 1 to 32
687
Trip matrix logic (GGIO) Chapter 13
Logic
688
Configurable logic blocks (LLD) Chapter 13
Logic
3.1 Introduction
A number of logic blocks and timers are available for user to adapt the configuration to the spe-
cific application needs.
I001-
INV
INPUT OUT
en04000404.vsd
Table 362: Input signals for the INV (I001-) function block
Signal Description
INPUT Input
Table 363: Output signals for the INV (I001-) function block
Signal Description
OUT Output
O001-
OR
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
INPUT5
INPUT6
en04000405.vsd
689
Configurable logic blocks (LLD) Chapter 13
Logic
A001-
AND
INPUT 1 OUT
INPUT 2 NOUT
INPUT 3
INPUT 4N
en04000406.vsd
Table 366: Input signals for the AND (A001-) function block
Signal Description
INPUT1 Input 1
INPUT2 Input 2
INPUT3 Input 3
INPUT4N Input 4 inverted
Table 367: Output signals for the AND (A001-) function block
Signal Description
OUT Output
NOUT Output inverted
690
Configurable logic blocks (LLD) Chapter 13
Logic
T M01-
Timer
INPUT ON
T OFF
en04000378.vsd
Table 368: Input signals for the Timer (TM01-) function block
Signal Description
INPUT Input to timer
Table 369: Output signals for the Timer (TM01-) function block
Signal Description
ON Output from timer , pick-up delayed
OFF Output from timer, drop-out delayed
TP01-
Pulse
INPUT OUT
en04000407.vsd
Table 371: Input signals for the Pulse (TP01-) function block
Signal Description
INPUT Input to pulse timer
691
Configurable logic blocks (LLD) Chapter 13
Logic
Table 372: Output signals for the Pulse (TP01-) function block
Signal Description
OUT Output from pulse timer
XO01-
XOR
INPUT 1 OUT
INPUT 2 NOUT
en04000409.vsd
Table 374: Input signals for the XOR (XO01-) function block
Signal Description
INPUT1 Input 1 to XOR gate
INPUT2 Input 2 to XOR gate
Table 375: Output signals for the XOR (XO01-) function block
Signal Description
OUT Output from XOR gate
NOUT Inverted output from XOR gate
692
Configurable logic blocks (LLD) Chapter 13
Logic
Table 376: Truth table for the Set-Reset (SRM) function block
SET RESET OUT NOUT
1 0 1 0
0 1 0 1
1 1 0 1
0 0 0 1
SM01-
SRM
SET OUT
RESET NOUT
en04000408.vsd
Table 377: Input signals for the SRM (SM01-) function block
Signal Description
SET Set input
RESET Reset input
Table 378: Output signals for the SRM (SM01-) function block
Signal Description
OUT Output
NOUT Output inverted
Table 379: Parameter group settings for the SRM (SM01-) function
Parameter Range Step Default Unit Description
Memory Off - Off - Operating mode of the
On memory function
693
Configurable logic blocks (LLD) Chapter 13
Logic
GT 01-
GT
INPUT OUT
en04000410.vsd
TS01-
TimerSet
INPUT ON
OFF
en04000411.vsd
Table 383: Input signals for the TimerSet (TS01-) function block
Signal Description
INPUT Input to timer
694
Configurable logic blocks (LLD) Chapter 13
Logic
Table 384: Output signals for the TimerSet (TS01-) function block
Signal Description
ON Output from timer, pick-up delayed
OFF Output from timer, drop-out delayed
Table 385: Parameter group settings for the TimerSet (TS01-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off/On
On
t 0.000 - 90000.000 0.001 0.000 s Delay for settable timer n
695
Fixed signal function block (FIXD) Chapter 13
Logic
4.1 Introduction
The fixed signals function block generates a number of pre-set (fixed) signals that can be used
in the configuration of an IED, either for forcing the unused inputs in the other function blocks
to a certain level/value, or for creating a certain logic.
FIXD-
FixedSignals
OFF
ON
INTZERO
INTONE
REALZERO
STRNULL
ZEROSMPL
GRP_OFF
en05000445.vsd
696
Fixed signal function block (FIXD) Chapter 13
Logic
697
Boolean 16 to Integer conversion B16I Chapter 13
Logic
5.1 Introduction
The B16I function block (or the Boolean 16 to Integer conversion function block) is used within
the CAP tool to transform a set of 16 binary (logical) signals into an integer.
BB01-
B16I
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
en07000128.vsd
698
Boolean 16 to Integer conversion B16I Chapter 13
Logic
Table 389: Output signals for the B16I (BB01-) function block
Signal Description
OUT Output value
699
Boolean 16 to Integer conversion with logic Chapter 13
node representation (B16IGGIO) Logic
6.1 Introduction
The B16IGGIO function block (or the Boolean 16 to integer conversion with logic node repre-
sentation function block) is used within CAP tool to transform an integer to 16 binary (logic)
signals.
TheIB16IGGIO can receive it's value from remote like IEC61850 depending on the PSTO input.
The PSTO input determines the operator place. The integer number can be written to the block
while in Remote. If PSTO is in Off or Local then no change is applied to the outputs.
BA01-
B16IGGIO
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
en07000129.vsd
700
Boolean 16 to Integer conversion with logic Chapter 13
node representation (B16IGGIO) Logic
Table 391: Output signals for the B16IGGIO (BA01-) function block
Signal Description
OUT Output value
701
Integer to Boolean 16 conversion (IB16) Chapter 13
Logic
7.1 Introduction
The IB16 function block (or the integer to Boolean 16 conversion function block) is used within
the CAP tool to transform a set of 16 binary (logical) signals into an integer.
IY01-
IB16
BLOCK OUT1
IN OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
en06000501.vsd
702
Integer to Boolean 16 conversion (IB16) Chapter 13
Logic
Table 393: Output signals for the IB16 (IY01-) function block
Signal Description
OUT1 Output 1
OUT2 Output 2
OUT3 Output 3
OUT4 Output 4
OUT5 Output 5
OUT6 Output 6
OUT7 Output 7
OUT8 Output 8
OUT9 Output 9
OUT10 Output 10
OUT11 Output 11
OUT12 Output 12
OUT13 Output 13
OUT14 Output 14
OUT15 Output 15
OUT16 Output 16
703
Integer to Boolean 16 conversion with logic Chapter 13
node representation (IB16GGIO) Logic
8.1 Introduction
The IB16GGIO function block (or the integer to Boolean conversion with logic node represen-
tation function block) is used within CAP tool to transform an integer to 16 binary (logic) sig-
nals.
The IB16GGIO can receive it's value from remote like IEC61850 depending on the PSTO input.
IX01-
IB16GGIO
BLOCK OUT1
PSTO OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
en06000502.vsd
704
Integer to Boolean 16 conversion with logic Chapter 13
node representation (IB16GGIO) Logic
Table 395: Output signals for the IB16GGIO (IX01-) function block
Signal Description
OUT1 Output 1
OUT2 Output 2
OUT3 Output 3
OUT4 Output 4
OUT5 Output 5
OUT6 Output 6
OUT7 Output 7
OUT8 Output 8
OUT9 Output 9
OUT10 Output 10
OUT11 Output 11
OUT12 Output 12
OUT13 Output 13
OUT14 Output 14
OUT15 Output 15
OUT16 Output 16
705
Integer to Boolean 16 conversion with logic Chapter 13
node representation (IB16GGIO) Logic
706
About this chapter Chapter 14
Monitoring
Chapter 14 Monitoring
707
Measurements (MMXU) Chapter 14
Monitoring
1 Measurements (MMXU)
708
Measurements (MMXU) Chapter 14
Monitoring
1.1 Introduction
Measurement functions is used for power system measurement, supervision and reporting to the
local HMI, monitoring tool within PCM 600 or to station level e.g.via IEC61850). The possibil-
ity to continuously monitor measured values of active power, reactive power, currents, voltages,
frequency, power factor etc. is vital for efficient production, transmission and distribution of
electrical energy. It provides to the system operator fast and easy overview of the present status
of the power system. Additionally it can be used during testing and commissioning of protection
and control IEDs in order to verify proper operation and connection of instrument transformers
(i.e. CTs & VTs). During normal service by periodic comparison of the measured value from the
IED with other independent meters the proper operation of the IED analog measurement chain
can be verified. Finally it can be used to verify proper direction orientation for distance or direc-
tional overcurrent protection function.
Note!
The available measured values of an IED are depending on the actual hardware (TRM) and the
logic configuration made in PCM 600.
All measured values can be supervised with four settable limits, i.e. low-low limit, low limit,
high limit and high-high limit. A zero clamping reduction is also supported, i.e the measured val-
ue below a settable limit is forced to zero which reduces the impact of noise in the inputs.
Dead-band supervision can be used to report measured signal value to station level when change
in measured value is above set threshold limit or time integral of all changes since the last time
value updating exceeds the threshold limit. Measure value can also be based on periodic report-
ing.
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Measurements (MMXU) Chapter 14
Monitoring
The measuring function, SVR (CVMMXU), provides the following power system quantities:
It is possible to calibrate the measuring function above to get better then class 0.5 presentation.
This is accomplished by angle and amplitude compensation at 5, 30 and 100% of rated current
and at 100% of rated voltage.
Note!
The power system quantities provided, depends on the actual hardware, (TRM) and the logic
configuration made in PCM 600.
The measuring functions CSQ (CMSQI) and VSQ (VMSQI) provides sequential quantities:
The SVR function calculates three-phase power quantities by using fundamental frequency pha-
sors (i.e. DFT values) of the measured current respectively voltage signals. The measured power
quantities are available either as instantaneously calculated quantities or averaged values over a
period of time (i.e. low pass filtered) depending on the selected settings.
The information on measured quantities is available for the user at different locations:
710
Measurements (MMXU) Chapter 14
Monitoring
Overfunction, when the measured current exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
Underfunction, when the measured current decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
en05000657.vsd
Figure 330: Presentation of operating limits
711
Measurements (MMXU) Chapter 14
Monitoring
Each analog output has one corresponding supervision level output (X_RANGE). The output
signal is an integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: High-high limit ex-
ceeded, 2: below Low limit and 4: below Low-low limit). The output may be connected to a
measurement expander block (XP (RANGE_XP)) to get measurement supervision as binary sig-
nals.
The logical value of the functional output signals changes according to figure 330.
The user can set the hysteresis (XLimHyst), which determines the difference between the oper-
ating and reset value at each operating point, in wide range for each measuring channel separate-
ly. The hysteresis is common for all operating values within one channel.
Cyclic reporting
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp).
The measuring channel reports the value independent of amplitude or integral dead-band report-
ing.
712
Measurements (MMXU) Chapter 14
Monitoring
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
en05000500.vsd
(*)Set value for t: XDbRepInt
Figure 331: Periodic reporting
713
Measurements (MMXU) Chapter 14
Monitoring
Value Reported
Y
99000529.vsd
After the new value is reported, the Y limits for dead-band are automatically set around it.
The new value is reported only if the measured quantity changes more than defined by the Y
set limits.
The last value reported, Y1 in figure 333 serves as a basic value for further measurement. A dif-
ference is calculated between the last reported and the newly measured value and is multiplied
by the time increment (discrete integral). The absolute values of these integral values are added
until the pre-set value is exceeded. This occurs with the value Y2 that is reported and set as a
new base for the following measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals with small
variations that can last for relatively long periods.
714
Measurements (MMXU) Chapter 14
Monitoring
Y A1 >=
A >= pre-set value
A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
(1st) Value
Value Reported Y5
A Reported Value
Reported Value
Y1 Reported
t
99000530.vsd
Figure 333: Reporting with integral dead-band supervision
Mode of operation
The measurement function must be connected to three-phase current and three-phase voltage in-
put in the configuration tool (group signals), but it is capable to measure and calculate above
mentioned quantities in nine different ways depending on the available VT inputs connected to
the IED. The end user can freely select by a parameter setting, which one of the nine available
measuring modes shall be used within the function. Available options are summarized in the fol-
lowing table:
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Measurements (MMXU) Chapter 14
Monitoring
Set value Formula used for complex, Formula used for voltage Comment
for parame- three-phase power calculation and current magnitude cal-
ter Mode culation
1 L1, L2, L3 Used when three
phase-to-earth
S = U L1 I
*
L1 + U L2 I
*
L2 + U L3 I
*
L3
U = ( U L1 + U L 2 + U L 3 ) / 3 voltages are
available
I = ( I L1 + I L 2 + I L 3 ) / 3
716
Measurements (MMXU) Chapter 14
Monitoring
It shall be noted that only in the first two operating modes (i.e. 1 & 3) the measurement function
calculates exact three-phase power. In other operating modes (i.e. from 3 to 9) it calculates the
three-phase power under assumption that the power system is fully symmetrical. Once the com-
plex apparent power is calculated then the P, Q, S, & PF are calculated in accordance with the
following formulas:
P = Re( S )
(Equation 100)
Q = Im( S )
(Equation 101)
S = S = P +Q
2 2
(Equation 102)
PF = cos = P
S
(Equation 103)
Additionally to the power factor value the two binary output signals from the function are pro-
vided which indicates the angular relationship between current and voltage phasors. Binary out-
put signal ILAG is set to one when current phasor is lagging behind voltage phasor. Binary
output signal ILEAD is set to one when current phasor is leading the voltage phasor.
Each analog output has a corresponding supervision level output (X_RANGE). The output sig-
nal is an integer in the interval 0-4, see section 1.2.1 "Measurement supervision".
717
Measurements (MMXU) Chapter 14
Monitoring
Amplitude
% of Ir compensation
-10
IAmpComp5 Measured
IAmpComp30 current
IAmpComp100
5 30 100 % of Ir
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
-10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of Ir
-10
en05000652.vsd
The first current and voltage phase in the group signals will be used as reference and the ampli-
tude and angle compensation will be used for related input signals.
X = k X Old + (1 k ) X Calculated
(Equation 104)
where:
X is a new measured value (i.e. P, Q, S, U, I or PF) to be given out from the function
XOld is the measured value given from the measurement function in previous execution cycle
XCalculated is the new calculated value in the present execution cycle
k is settable parameter by the end user which influence the filter properties
718
Measurements (MMXU) Chapter 14
Monitoring
Default value for parameter k is 0.00. With this value the new calculated value is immediately
given out without any filtering (i.e. without any additional delay). When k is set to value bigger
than 0, the filtering is enabled. Appropriate value of k shall be determined separately for every
application. Some typical value for k =0.14.
Compensation facility
In order to compensate for small magnitude and angular errors in the complete measurement
chain (i.e. CT error, VT error, IED input transformer errors etc.) it is possible to perform on site
calibration of the power measurement. This is achieved by setting the complex constant which
is then internally used within the function to multiply the calculated complex apparent power S.
This constant is set as magnitude (i.e. setting parameter PowAmpFact, default value 1.000) and
angle (i.e. setting parameter PowAngComp, default value 0.0 degrees). Default values for these
two parameters are done in such way that they do not influence internally calculated value (i.e.
complex constant has default value 1). In this way calibration, for specific operating range (e.g.
around rated power) can be done at site. However to perform this calibration it is necessary to
have external power meter of the high accuracy class available.
Directionality
In CT earthing parameter is set as described in section 1 "Analog inputs", active and reactive
power will be measured always towards the protected object. This is shown in the following
figure 335.
719
Measurements (MMXU) Chapter 14
Monitoring
Busbar
P Q
Protected
Object
en05000373.vsd
That practically means that active and reactive power will have positive values when they flow
from the busbar towards the protected object and they will have negative values when they flow
from the protected object towards the busbar.
In some application, like for example when power is measured on the secondary side of the pow-
er transformer it might be desirable, from the end client point of view, to have actually opposite
directional convention for active and reactive power measurements. This can be easily achieved
by setting parameter PowAngComp to value of 180.0 degrees. With such setting the active and
reactive power will have positive values when they flow from the protected object towards the
busbar.
Frequency
Frequency is actually not calculated within measurement block. It is simply obtained from the
pre-processing block and then just given out from the measurement block as an output.
Phase currents (amplitude and angle) are available on the outputs and each amplitude output has
a corresponding supervision level output (ILx_RANG). The supervision output signal is an in-
teger in the interval 0-4, see section 1.2.1 "Measurement supervision".
720
Measurements (MMXU) Chapter 14
Monitoring
The voltages (phase or phase-phase voltage, amplitude and angle) are available on the outputs
and each amplitude output has a corresponding supervision level output (ULxy_RANG). The
supervision output signal is an integer in the interval 0-4, see section 1.2.1 "Measurement super-
vision".
Positive, negative and three times zero sequence quantities are available on the outputs (voltage
and current, amplitude and angle). Each amplitude output has a corresponding supervision level
output (X_RANGE). The output signal is an integer in the interval 0-4, see section 1.2.1 "Mea-
surement supervision".
SVR1-
CVMMXU
I3P S
U3P S_RANGE
P_INST
P
P_RANGE
Q_INST
Q
Q_RANGE
PF
PF_RANGE
ILAG
ILEAD
U
U_RANGE
I
I_RANGE
F
F_RANGE
en05000772.vsd
721
Measurements (MMXU) Chapter 14
Monitoring
CP01-
CMMXU
I3P IL1
IL1RANG
IL1ANGL
IL2
IL2RANG
IL2ANGL
IL3
IL3RANG
IL3ANGL
en05000699.vsd
VP01-
VMMXU
U3P UL12
UL12RANG
UL23
UL23RANG
UL31
UL31RANG
en05000701.vsd
CSQ1-
CMSQI
I3P 3I0
3I0RANG
I1
I1RANG
I2
I2RANG
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Measurements (MMXU) Chapter 14
Monitoring
VSQ1-
VMSQI
U3P 3U0
3U0RANG
U1
U1RANG
U2
U2RANG
en05000704.vsd
VSQ1-
VMSQI
V3P 3V0
3V0RANG
V1
V1RANG
V2
V2RANG
en05000704_ansi.vsd
Table 397: Output signals for the CVMMXU (SVR1-) function block
Signal Description
S Apparent Power magnitude of deadband value
S_RANGE Apparent Power range
P_INST Active Power
P Active Power magnitude of deadband value
P_RANGE Active Power range
Q_INST Reactive Power
Q Active Power magnitude of deadband value
Q_RANGE Reactive Power range
PF Power Factor magnitude of deadband value
PF_RANGE Power Factor range
ILAG Current is lagging voltage
ILEAD Current is leading voltage
U Calculate voltage magnitude of deadband value
723
Measurements (MMXU) Chapter 14
Monitoring
Signal Description
U_RANGE Calcuate voltage range
I Calculated current magnitude of deadband value
I_RANGE Calculated current range
F System frequency magnitude of deadband value
F_RANGE System frequency range
Table 398: Input signals for the CMMXU (CP01-) function block
Signal Description
I3P Group connection abstract block 1
Table 399: Output signals for the CMMXU (CP01-) function block
Signal Description
IL1 IL1 Amplitude, magnitude of reported value
IL1RANG IL1 Amplitude range
IL1ANGL IL1 Angle, magnitude of reported value
IL2 IL2 Amplitude, magnitude of reported value
IL2RANG IL2 Amplitude range
IL2ANGL IL2 Angle, magnitude of reported value
IL3 IL3 Amplitude, magnitude of reported value
IL3RANG IL3 Amplitude range
IL3ANGL IL3 Angle, magnitude of reported value
Table 400: Input signals for the VNMMXU (VN01-) function block
Signal Description
U3P Group connection abstract block 5
Table 401: Output signals for the VNMMXU (VN01-) function block
Signal Description
UL1 UL1 Amplitude, magnitude of reported value
UL1RANG UL1 Amplitude range
UL1ANGL UL1 Angle, magnitude of reported value
UL2 UL2 Amplitude, magnitude of reported value
724
Measurements (MMXU) Chapter 14
Monitoring
Signal Description
UL2RANG UL2 Amplitude range
UL2ANGL UL2 Angle, magnitude of reported value
UL3 UL3 Amplitude, magnitude of reported value
UL3RANG UL3 Amplitude range
UL3ANGL UL3 Angle, magnitude of reported value
Table 402: Input signals for the VMMXU (VP01-) function block
Signal Description
U3P Group connection abstract block 2
Table 403: Output signals for the VMMXU (VP01-) function block
Signal Description
UL12 UL12 Amplitude, magnitude of reported value
UL12RANG UL12 Amplitude range
UL23 UL23 Amplitude, magnitude of reported value
UL23RANG UL23 Amplitude range
UL31 UL31 Amplitude, magnitude of reported value
UL31RANG UL31 Amplitude range
Table 404: Input signals for the CMSQI (CSQ1-) function block
Signal Description
I3P Group connection abstract block 3
Table 405: Output signals for the CMSQI (CSQ1-) function block
Signal Description
3I0 3I0 Amplitude, magnitude of reported value
3I0RANG 3I0 Amplitude range
I1 I1 Amplitude, magnitude of reported value
I1RANG I1 Amplitude range
I2 I2 Amplitude, magnitude of reported value
I2RANG I2 Amplitude range
Table 406: Input signals for the VMSQI (VSQ1-) function block
Signal Description
U3P Group connection abstract block 4
725
Measurements (MMXU) Chapter 14
Monitoring
Table 407: Output signals for the VMSQI (VSQ1-) function block
Signal Description
3U0 3U0 Amplitude, magnitude of reported value
3U0RANG 3U0 Amplitude range
U1 U1 Amplitude, magnitude of reported value
U1RANG U1 Amplitude range
U2 U2 Amplitude, magnitude of reported value
U2RANG U2 Amplitude range
Table 408: Basic general settings for the CVMMXU (SVR1-) function
Parameter Range Step Default Unit Description
SLowLim 0.000 - 0.001 0.000 VA Low limit (physical value)
10000000000.000
SLowLowLim 0.000 - 0.001 0.000 VA Low Low limit (physical
10000000000.000 value)
SMin 0.000 - 0.001 0.000 VA Minimum value
10000000000.000
SMax 0.000 - 0.001 1000000000.000 VA Maximum value
10000000000.000
SRepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
PMin -10000000000.000 0.001 -1000000000.000 W Minimum value
-
10000000000.000
PMax -10000000000.000 0.001 1000000000.000 W Maximum value
-
10000000000.000
PRepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
QMin -10000000000.000 0.001 -1000000000.000 VAr Minimum value
-
10000000000.000
Operation Off - Off - Operation Off / On
On
IBase 1 - 99999 1 3000 A Base setting for current
level in A
QMax -10000000000.000 0.001 1000000000.000 VAr Maximum value
-
10000000000.000
726
Measurements (MMXU) Chapter 14
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727
Measurements (MMXU) Chapter 14
Monitoring
Table 409: Advanced general settings for the CVMMXU (SVR1-) function
Parameter Range Step Default Unit Description
SDbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
SZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
SHiHiLim 0.000 - 0.001 900000000.000 VA High High limit (physical
10000000000.000 value)
SHiLim 0.000 - 0.001 800000000.000 VA High limit (physical value)
10000000000.000
SLimHyst 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range (common for all
limits)
PDbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
PZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
PHiHiLim -10000000000.000 0.001 900000000.000 W High High limit (physical
- value)
10000000000.000
PHiLim -10000000000.000 0.001 800000000.000 W High limit (physical value)
-
10000000000.000
PLowLim -10000000000.000 0.001 -800000000.000 W Low limit (physical value)
-
10000000000.000
728
Measurements (MMXU) Chapter 14
Monitoring
729
Measurements (MMXU) Chapter 14
Monitoring
730
Measurements (MMXU) Chapter 14
Monitoring
Table 410: Basic general settings for the CMMXU (CP01-) function
Parameter Range Step Default Unit Description
IL1DbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
Operation Off - Off - Operation Mode On / Off
On
IBase 1 - 99999 1 3000 A Base setting for current
level in A
IL1Max 0.000 - 0.001 1000.000 A Maximum value
10000000000.000
IL1RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
731
Measurements (MMXU) Chapter 14
Monitoring
Table 411: Advanced general settings for the CMMXU (CP01-) function
Parameter Range Step Default Unit Description
IL1ZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
IL1HiHiLim 0.000 - 0.001 900.000 A High High limit (physical
10000000000.000 value)
IL1HiLim 0.000 - 0.001 800.000 A High limit (physical value)
10000000000.000
IAmpComp5 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate current at 5% of Ir
IAmpComp30 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate current at 30% of Ir
IL1LowLim 0.000 - 0.001 0.000 A Low limit (physical value)
10000000000.000
IL1LowLowLim 0.000 - 0.001 0.000 A Low Low limit (physical
10000000000.000 value)
IAmpComp100 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate current at 100% of
Ir
732
Measurements (MMXU) Chapter 14
Monitoring
733
Measurements (MMXU) Chapter 14
Monitoring
Table 412: Basic general settings for the VNMMXU (VN01-) function
Parameter Range Step Default Unit Description
UL1DbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
Operation Off - Off - Operation Mode On / Off
On
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
level in kV
UL1Max 0.000 - 0.001 300000.000 V Maximum value
10000000000.000
UL1RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
UL1LimHys 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range and is common for
all limits
UL1AnDbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
UL2DbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
UL2Max 0.000 - 0.001 300000.000 V Maximum value
10000000000.000
UL2RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
UL2LimHys 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range and is common for
all limits
UL2AnDbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
UL3DbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
UL3Max 0.000 - 0.001 300000.000 V Maximum value
10000000000.000
UL3RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
UL3LimHys 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range and is common for
all limits
UL3AnDbRepInt 1 - 300 1 10 Type Cycl: Report interval (s),
Db: In % of range, Int Db:
In %s
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Measurements (MMXU) Chapter 14
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Table 413: Advanced general settings for the VNMMXU (VN01-) function
Parameter Range Step Default Unit Description
UL1ZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
UL1HiHiLim 0.000 - 0.001 260000.000 V High High limit (physical
10000000000.000 value)
UL1HiLim 0.000 - 0.001 240000.000 V High limit (physical value)
10000000000.000
UL1LowLim 0.000 - 0.001 220000.000 V Low limit (physical value)
10000000000.000
UL1LowLowLim 0.000 - 0.001 200000.000 V Low Low limit (physical
10000000000.000 value)
UAmpComp100 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate voltage at 100% of
Ur
UL1Min 0.000 - 0.001 0.000 V Minimum value
10000000000.000
UL2ZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
UL2HiHiLim 0.000 - 0.001 260000.000 V High High limit (physical
10000000000.000 value)
UL2HiLim 0.000 - 0.001 240000.000 V High limit (physical value)
10000000000.000
UL2LowLim 0.000 - 0.001 220000.000 V Low limit (physical value)
10000000000.000
UL2LowLowLim 0.000 - 0.001 200000.000 V Low Low limit (physical
10000000000.000 value)
UL2Min 0.000 - 0.001 0.000 V Minimum value
10000000000.000
UL3ZeroDb 0 - 100000 1 0 m% Zero point clamping in
0,001% of range
UL3HiHiLim 0.000 - 0.001 260000.000 V High High limit (physical
10000000000.000 value)
UL3HiLim 0.000 - 0.001 240000.000 V High limit (physical value)
10000000000.000
UL3LowLim 0.000 - 0.001 220000.000 V Low limit (physical value)
10000000000.000
UL3LowLowLim 0.000 - 0.001 200000.000 V Low Low limit (physical
10000000000.000 value)
UL3Min 0.000 - 0.001 0.000 V Minimum value
10000000000.000
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Measurements (MMXU) Chapter 14
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Table 414: Basic general settings for the VMMXU (VP01-) function
Parameter Range Step Default Unit Description
UL12DbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
Operation Off - On - Operation Mode On / Off
On
UL12ZeroDb 0 - 100000 1 0 1/1000 Zero point clamping in
% 0,001% of range
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
level in kV
UL12HiHiLim -10000000000.000 0.001 460000.000 V High High limit (physical
- value)
10000000000.000
UL12HiLim -10000000000.000 0.001 450000.000 V High limit (physical value)
-
10000000000.000
UAmpComp5 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate voltage at 5% of Ur
UAmpComp30 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate voltage at 30% of
Ur
UL12LowLim -10000000000.000 0.001 380000.000 V Low limit (physical value)
-
10000000000.000
UL12LowLowLim -10000000000.000 0.001 350000.000 V Low Low limit (physical
- value)
10000000000.000
UAmpComp100 -10.000 - 10.000 0.001 0.000 % Amplitude factor to cali-
brate voltage at 100% of
Ur
UL12Min -10000000000.000 0.001 0.000 V Minimum value
-
10000000000.000
UL12Max -10000000000.000 0.001 450000.000 V Maximum value
-
10000000000.000
UL12RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
UL12LimHys 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range and is common for
all limits
UL12AnDbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
UL12AngRepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
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Measurements (MMXU) Chapter 14
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Measurements (MMXU) Chapter 14
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Table 415: Basic general settings for the CMSQI (CSQ1-) function
Parameter Range Step Default Unit Description
3I0DbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
3I0ZeroDb 0 - 100000 1 0 1/1000 Zero point clamping in
% 0,001% of range
3I0HiHiLim -10000000000.000 0.001 900.000 A High High limit (physical
- value)
10000000000.000
3I0HiLim -10000000000.000 0.001 800.000 A High limit (physical value)
-
10000000000.000
3I0LowLim -10000000000.000 0.001 -800.000 A Low limit (physical value)
-
10000000000.000
3I0LowLowLim -10000000000.000 0.001 -900.000 A Low Low limit (physical
- value)
10000000000.000
3I0Min -10000000000.000 0.001 0.000 A Minimum value
-
10000000000.000
738
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Table 416: Basic general settings for the VMSQI (VSQ1-) function
Parameter Range Step Default Unit Description
3U0DbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
3U0ZeroDb 0 - 100000 1 0 1/1000 Zero point clamping in
% 0,001% of range
3U0HiHiLim -10000000000.000 0.001 460000.000 V High High limit (physical
- value)
10000000000.000
3U0HiLim -10000000000.000 0.001 450000.000 V High limit (physical value)
-
10000000000.000
3U0LowLim -10000000000.000 0.001 380000.000 V Low limit (physical value)
-
10000000000.000
3U0LowLowLim -10000000000.000 0.001 350000.000 V Low Low limit (physical
- value)
10000000000.000
3U0Min -10000000000.000 0.001 0.000 V Minimum value
-
10000000000.000
3U0Max -10000000000.000 0.001 450000.000 V Maximum value
-
10000000000.000
3U0RepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
3U0LimHys 0.000 - 100.000 0.001 5.000 % Hysteresis value in % of
range and is common for
all limits
3U0AngDbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
Operation Off - Off - Operation Mode On / Off
On
3U0AngRepTyp Cyclic - Cyclic - Reporting type
Dead band
Int deadband
U1DbRepInt 1 - 300 1 10 s,%,% Cycl: Report interval (s),
s Db: In % of range, Int Db:
In %s
U1ZeroDb 0 - 100000 1 0 1/1000 Zero point clamping in
% 0,001% of range
U1HiHiLim -10000000000.000 0.001 460000.000 V High High limit (physical
- value)
10000000000.000
741
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Measurements (MMXU) Chapter 14
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743
Event counter (GGIO) Chapter 14
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2.1 Introduction
The function consists of six counters which are used for storing the number of times each counter
input has been activated.
The function block also has an input BLOCK. At activation of this input all six counters are
blocked. The input can for example be used for blocking the counters at testing.
All inputs are configured via PCM 600, CAP531 Application configuration tool.
2.2.1 Reporting
The content of the counters can be read in the local HMI. Refer to Operators manual for pro-
cedure.
Reset of counters can be performed in the local HMI and a binary input. Refer to Operators
manual for procedure.
Reading of content can also be performed remotely, for example from MicroSCADA. The value
can also be presented as a measuring value on the local HMI graphical display.
2.2.2 Design
The function block has six inputs for increasing the counter values for each of the six counters
respectively. The content of the counters are stepped one step for each positive edge of the input
respectively.
The function block also has an input BLOCK. At activation of this input all six counters are
blocked and are not updated. Valid number is held.
The function block has an input RESET. At activation of this input all six counters are set to 0.
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Event counter (GGIO) Chapter 14
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CNT1-
CNTGGIO
BLOCK
COUNTER1
COUNTER2
COUNTER3
COUNTER4
COUNTER5
COUNTER6
RESET
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Event function (EV) Chapter 14
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3.1 Introduction
When using a Substation Automation system with LON or SPA communication, time-tagged
events can be sent at change or cyclically from the IED to the station level. These events are cre-
ated from any available signal in the IED that is connected to the Event function block. The event
function block is used for LON and SPA communication.
Analog and double indication values are also transferred through the event block.
Each event function block has 16 inputs INPUT1 - INPUT16. Each input can be given a name
from the CAP configuration tool. The inputs are normally used to create single events, but are
also intended for double indication events.
The function also has an input BLOCK to block the generation of events.
The events that are sent from the IED can originate from both internal logical signals and binary
input channels. The internal signals are time-tagged in the main processing module, while the
binary input channels are time-tagged directly on the input module. The time-tagging of the
events that are originated from internal logical signals have a resolution corresponding to the ex-
ecution cyclicity of the event function block. The time-tagging of the events that are originated
from binary input signals have a resolution of 1 ms.
The outputs from the event function block are formed by the reading of status, events and alarms
by the station level on every single input. The user-defined name for each input is intended to
be used by the station level.
All events according to the event mask are stored in a buffer, which contains up to 1000 events.
If new events appear before the oldest event in the buffer is read, the oldest event is overwritten
and an overflow alarm appears.
The events are produced according to the set-event masks. The event masks are treated common-
ly for both the LON and SPA communication. The event mask can be set individually for each
input channel. These settings are available:
NoEvents
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Event function (EV) Chapter 14
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OnSet
OnReset
OnChange
AutoDetect
It is possible to define which part of the event function block that shall generate events. This can
be performed individually for the LON and SPA communication respectively. For each commu-
nication type these settings are available:
Off
Channel 1-8
Channel 9-16
Channel 1-16
For LON communication the events normally are sent to station level at change. It is possibly
also to set a time for cyclic sending of the events individually for each input channel.
To protect the SA system from signals with a high change rate that can easily saturate the event
system or the communication subsystems behind it, a quota limiter is implemented. If an input
creates events at a rate that completely consume the granted quota then further events from the
channel will be blocked. This block will be removed when the input calms down and the accu-
mulated quota reach 66% of the maximum burst quota. The maximum burst quota per input
channel equals 3 times the configurable setting MaxEvPerSec.
747
Event function (EV) Chapter 14
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EV01-
Event
BLOCK
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
NAME1
NAME2
NAME3
NAME4
NAME5
NAME6
NAME7
NAME8
NAME9
NAME10
NAME11
NAME12
NAME13
NAME14
NAME15
NAME16
en05000697.vsd
748
Event function (EV) Chapter 14
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Signal Description
INPUT12 Input 12
INPUT13 Input 13
INPUT14 Input 14
INPUT15 Input 15
INPUT16 Input 16
749
Event function (EV) Chapter 14
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Event function (EV) Chapter 14
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751
Measured value expander block Chapter 14
Monitoring
4.1 Introduction
The functions MMXU (SVR, CP and VP), MSQI (CSQ and VSQ) and MVGGIO (MV) are pro-
vided with measurement supervision functionality. All measured values can be supervised with
four settable limits, i.e. low-low limit, low limit, high limit and high-high limit. The measure val-
ue expander block (XP) has been introduced to be able to translate the integer output signal from
the measuring functions to 5 binary signals i.e. below low-low limit, below low limit, normal,
above high-high limit or above high limit. The output signals can be used as conditions in the
configurable logic.
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Measured value expander block Chapter 14
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XP01-
RANGE_XP
RANGE HIGHHIGH
HIGH
NORMAL
LOW
LOWLOW
en05000346.vsd
Table 424: Output signals for the RANGE_XP (XP01-) function block
Signal Description
HIGHHIGH Measured value is above high-high limit
HIGH Measured value is between high and high-high limit
NORMAL Measured value is between high and low limit
LOW Measured value is between low and low-low limit
LOWLOW Measured value is below low-low limit
753
Disturbance report (RDRE) Chapter 14
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Function block name: DRP--, DRA1- DRA4-, IEC 60617 graphical symbol:
DRB1- DRB6-
ANSI number:
IEC 61850 logical node name:
ABRDRE
5.1 Introduction
Complete and reliable information about disturbances in the primary and/or in the secondary
system together with continuous event-logging is accomplished by the disturbance report func-
tionality.
The disturbance report, always included in the IED, acquires sampled data of all selected analog
input and binary signals connected to the function block i.e. maximum 40 analog and 96 binary
signals.
The function is characterized by great flexibility regarding configuration, starting conditions, re-
cording times and large storage capacity.
Every disturbance report recording is saved in the IED in the standard Comtrade format. The
same applies to all events, which are continuously saved in a ring-buffer. The Local Human Ma-
chine Interface (LHMI) is used to get information about the recordings, but the disturbance re-
port files may be uploaded to the PCM 600 (Protection and Control IED Manager) and further
analysis using the disturbance handling tool.
754
Disturbance report (RDRE) Chapter 14
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Indications (IND)
Event recorder (ER)
Event list (EL)
Trip values (phase values) (TVR)
Disturbance recorder (DR)
Figure 343 shows the relations among Disturbance Report, included functions and function
blocks. EL, ER and IND uses information from the binary input function blocks (DRB1- 6).
TVR uses analog information from the analog input function blocks (DRA1-3). The DR func-
tion acquires information from both DRAx and DRBx.
DRP- -
A4RADR RDRE
Analog signals
Trip Value Rec
DRB1-- 6- Disturbance
Recorder
Binary signals
B6RBDR
Event List
Event Recorder
Indications
en05000160.vsd
The whole disturbance report can contain information for a number of recordings, each with the
data coming from all the parts mentioned above. The event list function is working continuously,
independent of disturbance triggering, recording time etc. All information in the disturbance re-
port is stored in non-volatile flash memories. This implies that no information is lost in case of
loss of auxiliary power. Each report will get an identification number in the interval from 0-999.
755
Disturbance report (RDRE) Chapter 14
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Disturbance report
en05000161.vsd
Up to 100 disturbance reports can be stored. If a new disturbance is to be recorded when the
memory is full, the oldest disturbance report is over-written by the new one. The total recording
capacity for the disturbance recorder is depending of sampling frequency, number of analog and
binary channels and recording time. The figure 345 shows number of recordings vs total record-
ing time tested for a typical configuration, i.e. in a 50 Hz system its possible to record 100 where
the average recording time is 3.4 seconds. The memory limit does not affect the rest of the dis-
turbance report (IND, ER, EL and TVR).
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Disturbance report (RDRE) Chapter 14
Monitoring
Number of recordings
100
3,4 s
80 3,4 s 20 analog
96 binary
40 analog
96 binary
60 6,3 s
6,3 s
6,3 s 50 Hz
40
60 Hz
Total recording time
en05000488.vsd
Disturbance information
Date and time of the disturbance, the indications, events, fault location and the trip values are
available on the local human-machine interface (LHMI). To acquire a complete disturbance re-
port the use of a PC and PCM600 is required. The PC may be connected to the IED-front, rear
or remotely via the station bus (Ethernet ports).
Indications (IND)
Indications is a list of signals that were activated during the total recording time of the distur-
bance (not time-tagged). (See section 7 "Indications (RDRE)" for more detailed information.)
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Disturbance report (RDRE) Chapter 14
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Time tagging
The IED has a built-in real-time calendar and clock. This function is used for all time tagging
within the disturbance report
Recording times
The disturbance report (DRP) records information about a disturbance during a settable time
frame. The recording times are valid for the whole disturbance report. The disturbance recorder
(DR), the event recorder (ER) and indication function register disturbance data and events dur-
ing tRecording, the total recording time.
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Disturbance report (RDRE) Chapter 14
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Trig point
TimeLimit
PreFaultRecT PostFaultRecT
1 2 3
en05000487.vsd
Analog signals
Up to 40 analog signals can be selected for recording by the Disturbance recorder and triggering
of the Disturbance report function. Out of these 40, 30 are reserved for external analog signals,
i.e. signals from the analog input modules (TRM) and line differential communication module
(LDCM) via preprocessing function blocks (SMAI) and summation block (Sum3Ph). The last
10 channels may be connected to internally calculated analog signals available as function block
output signals (mA input signals, phase differential currents, bias currents etc.).
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Disturbance report (RDRE) Chapter 14
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PRxx- DRA1-
SMAI A1RADR DRA2-
GRPNAME AI3P A2RADR DRA3-
External analog AI1NAME AI1 INPUT1 A3RADR
signals
AI2NAME AI2 INPUT2
TRM, LDCM AI3NAME AI3 INPUT3
SUxx
AI4NAME AI4 INPUT4
AIN INPUT5
INPUT6
...
A4RADR
INPUT31
Internal analog signals
T2Dx, T3Dx, INPUT32
REFx, HZDx, INPUT33
L3D, L6D,
LT3D, LT6D INPUT34
INPUT35
SVRx, CPxx, VP0x,
CSQx, VSQx, MVxx INPUT36
...
INPUT40
en05000653.vsd
The external input signals will be acquired, filtered and skewed and (after configuration) avail-
able as an input signal on the DRAx- function block via the PRxx function block. The informa-
tion is saved at the Disturbance report base sampling rate (1000 or 1200 Hz). Internally
calculated signals are updated according to the cycle time of the specific function. If a function
is running at lower speed than the base sampling rate, the Disturbance recorder will use the latest
updated sample until a new updated sample is available.
If the IED is preconfigured the only tool needed for analog configuration of the Disturbance re-
port is the Signal Matrix Tool (SMT, external signal configuration). In case of modification of
a preconfigured IED or general internal configuration the Application Configuration tool within
PCM600 is used.
The preprocessor function block (PRxx) calculates the residual quantities in cases where only
the three phases are connected (AI4-input not used). PRxx makes the information available as a
group signal output, phase outputs and calculated residual output (AIN-output). In situations
where AI4-input is used as a input signal the corresponding information is available on the
non-calculated output (AI4) on the PRxx-block. Connect the signals to the DRAx accordingly.
For each of the analog signals, Operation = On means that it is recorded by the disturbance re-
corder. The trigger is independent of the setting of Operation, and triggers even if operation is
set to Off. Both undervoltage and overvoltage can be used as trigger conditions. The same ap-
plies for the current signals.
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Disturbance report (RDRE) Chapter 14
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The analog signals are presented only in the disturbance recording, but they affect the entire dis-
turbance report when being used as triggers.
Binary signals
Up to 96 binary signals can be selected to be handled by the disturbance report.The signals can
be selected from internal logical and binary input signals. A binary signal is selected to be re-
corded when:
Each of the 96 signals can be selected as a trigger of the disturbance report (operationON/OFF).
A binary signal can be selected to activate the red LED on the local HMI (setLED=On/Off).
The selected signals are presented in the event recorder, event list and the disturbance recording.
But they affect the whole disturbance report when they are used as triggers. The indications are
also selected from these 96 signals with the LHMI IndicationMask=Show/Hide.
Trigger signals
The trigger conditions affect the entire disturbance report, except the event list, which runs con-
tinuously. As soon as at least one trigger condition is fulfilled, a complete disturbance report is
recorded. On the other hand, if no trigger condition is fulfilled, there is no disturbance report, no
indications, and so on. This implies the importance of choosing the right signals as trigger con-
ditions.
Manual trigger
Binary-signal trigger
Analog-signal trigger (over/under function)
Manual trigger
A disturbance report can be manually triggered from the local HMI, from PCM600 or via station
bus (IEC61850). When the trigger is activated, the manual trigger signal is generated. This fea-
ture is especially useful for testing. Refer to Operators manual for procedure.
Binary-signal trigger
Any binary signal state (logic one or a logic zero) can be selected to generate a trigger (Triglevel
= Trig on 0/Trig on 1). When a binary signal is selected to generate a trigger from a logic zero,
the selected signal will not be listed in the indications list of the disturbance report.
Analog-signal trigger
All analog signals are available for trigger purposes, no matter if they are recorded in the distur-
bance recorder or not. The settings are OverTrigOp, UnderTrigOp, OverTrigLe and UnderTri-
gLe.
The check of the trigger condition is based on peak-to-peak values. When this is found, the ab-
solute average value of these two peak values is calculated. If the average value is above the
threshold level for an overvoltage or overcurrent trigger, this trigger is indicated with a greater
than (>) sign with the user-defined name.
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Disturbance report (RDRE) Chapter 14
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If the average value is below the set threshold level for an undervoltage or undercurrent trigger,
this trigger is indicated with a less than (<) sign with its name. The procedure is separately per-
formed for each channel.
This method of checking the analog start conditions gives a function which is insensitive to DC
offset in the signal. The operate time for this start is typically in the range of one cycle, 20 ms
for a 50 Hz network.
All under/over trig signal information is available on the LHMI and PCM600, see table 426
"Output signals for the RDRE (DRP--) function block".
Post Retrigger
The disturbance report function does not respond to any new trig condition, during a recording.
Under certain circumstances the fault condition may reoccur during the post-fault recording, for
instance by automatic reclosing to a still faulty power line.
In order to capture the new disturbance it is possible to allow retriggering (PostRetrig = On)dur-
ing the post-fault time. In this case a new, complete recording will start and, during a period, run
in parallel with the initial recording.
When the retrig parameter is disabled (PostRetrig = Off), a new recording will not start until the
post-fault (PostFaultrecT or TimeLimit) period is terminated. If a new trig occurs during the
post-fault period and lasts longer than the proceeding recording a new complete recording will
be fetched.
The disturbance report function can handle maximum 3 simultaneous disturbance recordings.
DRP--
RDRE
DRPOFF
RECSTART
RECMADE
CLEARED
MEMUSED
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Disturbance report (RDRE) Chapter 14
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DRA1-
A1RADR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
NAME1
NAME2
NAME3
NAME4
NAME5
NAME6
NAME7
NAME8
NAME9
NAME10
en05000430.vsd
Figure 349: DRA1 function block, analog inputs, example for DRA1DRA3
DRA4-
A4RADR
INPUT31
INPUT32
INPUT33
INPUT34
INPUT35
INPUT36
INPUT37
INPUT38
INPUT39
INPUT40
NAME31
NAME32
NAME33
NAME34
NAME35
NAME36
NAME37
NAME38
NAME39
NAME40
en05000431.vsd
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Disturbance report (RDRE) Chapter 14
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DRB1-
B1RBDR
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
INPUT 8
INPUT 9
INPUT 10
INPUT 11
INPUT 12
INPUT 13
INPUT 14
INPUT 15
INPUT 16
NAME1
NAME2
NAME3
NAME4
NAME5
NAME6
NAME7
NAME8
NAME9
NAME10
NAME11
NAME12
NAME13
NAME14
NAME15
NAME16
en05000432.vsd
Figure 351: DRB1 function block, binary inputs, example for DRB1DRB6
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Disturbance report (RDRE) Chapter 14
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Table 427: Input signals for the A1RADR (DRA1-) function block
Signal Description
INPUT1 Group signal for input 1
INPUT2 Group signal for input 2
INPUT3 Group signal for input 3
INPUT4 Group signal for input 4
INPUT5 Group signal for input 5
INPUT6 Group signal for input 6
INPUT7 Group signal for input 7
INPUT8 Group signal for input 8
INPUT9 Group signal for input 9
INPUT10 Group signal for input 10
Table 428: Input signals for the A4RADR (DRA4-) function block
Signal Description
INPUT31 Analogue channel 31
INPUT32 Analogue channel 32
INPUT33 Analogue channel 33
INPUT34 Analogue channel 34
INPUT35 Analogue channel 35
INPUT36 Analogue channel 36
INPUT37 Analogue channel 37
INPUT38 Analogue channel 38
INPUT39 Analogue channel 39
INPUT40 Analogue channel 40
Table 429: Input signals for the B1RBDR (DRB1-) function block
Signal Description
INPUT1 Binary channel 1
INPUT2 Binary channel 2
INPUT3 Binary channel 3
INPUT4 Binary channel 4
INPUT5 Binary channel 5
INPUT6 Binary channel 6
INPUT7 Binary channel 7
INPUT8 Binary channel 8
INPUT9 Binary channel 9
INPUT10 Binary channel 10
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Disturbance report (RDRE) Chapter 14
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Signal Description
INPUT11 Binary channel 11
INPUT12 Binary channel 12
INPUT13 Binary channel 13
INPUT14 Binary channel 14
INPUT15 Binary channel 15
INPUT16 Binary channel 16
Table 431: Basic general settings for the A1RADR (DRA1-) function
Parameter Range Step Default Unit Description
Operation01 Off - Off - Operation On/Off
On
NomValue01 0.0 - 999999.9 0.1 0.0 - Nominal value for ana-
logue channel 1
UnderTrigOp01 Off - Off - Use under level trig for
On analogue cha 1 (on) or
not (off)
UnderTrigLe01 0 - 200 1 50 % Under trigger level for
analogue cha 1 in % of
signal
OverTrigOp01 Off - Off - Use over level trig for
On analogue cha 1 (on) or
not (off)
OverTrigLe01 0 - 5000 1 200 % Over trigger level for ana-
logue cha 1 in % of signal
Operation02 Off - Off - Operation On/Off
On
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Table 432: Basic general settings for the A4RADR (DRA4-) function
Parameter Range Step Default Unit Description
Operation31 Off - Off - Operation On/off
On
NomValue31 0.0 - 999999.9 0.1 0.0 - Nominal value for ana-
logue channel 31
UnderTrigOp31 Off - Off - Use under level trig for
On analogue cha 31 (on) or
not (off)
UnderTrigLe31 0 - 200 1 50 % Under trigger level for
analogue cha 31 in % of
signal
OverTrigOp31 Off - Off - Use over level trig for
On analogue cha 31 (on) or
not (off)
OverTrigLe31 0 - 5000 1 200 % Over trigger level for ana-
logue cha 31 in % of sig-
nal
Operation32 Off - Off - Operation On/off
On
NomValue32 0.0 - 999999.9 0.1 0.0 - Nominal value for ana-
logue channel 32
UnderTrigOp32 Off - Off - Use under level trig for
On analogue cha 32 (on) or
not (off)
UnderTrigLe32 0 - 200 1 50 % Under trigger level for
analogue cha 32 in % of
signal
OverTrigOp32 Off - Off - Use over level trig for
On analogue cha 32 (on) or
not (off)
OverTrigLe32 0 - 5000 1 200 % Over trigger level for ana-
logue cha 32 in % of sig-
nal
Operation33 Off - Off - Operation On/off
On
NomValue33 0.0 - 999999.9 0.1 0.0 - Nominal value for ana-
logue channel 33
UnderTrigOp33 Off - Off - Use under level trig for
On analogue cha 33 (on) or
not (off)
UnderTrigLe33 0 - 200 1 50 % Under trigger level for
analogue cha 33 in % of
signal
OverTrigOp33 Off - Off - Use over level trig for
On analogue cha 33 (on) or
not (off)
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Table 433: Basic general settings for the B1RBDR (DRB1-) function
Parameter Range Step Default Unit Description
Operation01 Off - Off - Trigger operation On/Off
On
TrigLevel01 Trig on 0 - Trig on 1 - Trig on positiv (1) or neg-
Trig on 1 ative (0) slope for binary
inp 1
IndicationMa01 Hide - Hide - Indication mask for
Show binary channel 1
SetLED01 Off - Off - Set red-LED on HMI for
On binary channel 1
Operation02 Off - Off - Trigger operation On/Off
On
TrigLevel02 Trig on 0 - Trig on 1 - Trig on positiv (1) or neg-
Trig on 1 ative (0) slope for binary
inp 2
IndicationMa02 Hide - Hide - Indication mask for
Show binary channel 2
SetLED02 Off - Off - Set red-LED on HMI for
On binary channel 2
Operation03 Off - Off - Trigger operation On/Off
On
TrigLevel03 Trig on 0 - Trig on 1 - Trig on positiv (1) or neg-
Trig on 1 ative (0) slope for binary
inp 3
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Event list (RDRE) Chapter 14
Monitoring
6.1 Introduction
Continuous event-logging is useful for monitoring of the system from an overview perspective
and is a complement to specific disturbance recorder functions.
The event list logs all binary input signals connected to the Disturbance report function. The list
may contain of up to 1000 time-tagged events stored in a ring-buffer.
The event list information is available in the IED and is reported to higher control systems via
the station bus together with other logged events in the IED. In absence of any software tool the
information seeker may use the local HMI to view the event list.
The list can be configured to show oldest or newest events first with a setting on the LHMI.
The event list function runs continuously, in contrast to the event recorder function, which is
only active during a disturbance.
The name of the binary input signal that appears in the event recording is the user-defined name
assigned when the IED is configured. The same name is used in the disturbance recorder func-
tion (DR), indications (IND) and the event recorder function (ER).
The event list is stored and managed separate from the disturbance report information (ER, DR,
IND, TVR and FL).
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7 Indications (RDRE)
7.1 Introduction
To get fast, condensed and reliable information about disturbances in the primary and/or in the
secondary system it is important to know e.g. binary signals that have changed status during a
disturbance. This information is used in the short perspective to get information via the LHMI
in a straightforward way.
There are three LEDs on the LHMI (green, yellow and red), which will display status informa-
tion about the IED and the Disturbance Report function (trigged).
The Indication list function shows all selected binary input signals connected to the Disturbance
Report function that have changed status during a disturbance.
The indication information is available for each of the recorded disturbances in the IED and the
user may use the Local Human Machine Interface (LHMI) to get the information.
Green LED:
Yellow LED:
Red LED:
Indication list:
The possible indicated signals are the same as the ones chosen for the disturbance report function
and disturbance recorder
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The indication function tracks 0 to 1 changes of binary signals during the recording period of the
collection window. This means that constant logic zero, constant logic one or state changes from
logic one to logic zero will not be visible in the list of indications. Signals are not time tagged.
In order to be recorded in the list of indications the:
Indications are selected with the indication mask (IndicationMask) when configuring the binary
inputs.
The name of the binary input signal that appears in the Indication function is the user-defined
name assigned at configuration of the IED. The same name is used in disturbance recorder func-
tion (DR), indications (IND) and event recorder function (ER).
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8.1 Introduction
Quick, complete and reliable information about disturbances in the primary and/or in the sec-
ondary system is vital e.g. time tagged events logged during disturbances. This information is
used for different purposes in the short term (e.g. corrective actions) and in the long term (e.g.
Functional Analysis).
The event recorder logs all selected binary input signals connected to the Disturbance Report
function. Each recording can contain up to 150 time-tagged events.
The event recorder information is available for the disturbances locally in the IED.
The information may be uploaded to the PCM 600 (Protection and Control IED Manager) and
further analyzed using the Disturbance Handling tool.
The event recording information is an integrated part of the disturbance record (Comtrade file).
In case of overlapping recordings, due to PostRetrig = On and a new trig signal appears during
post-fault time, events will be saved in both recording files.
The name of the binary input signal that appears in the event recording is the user-defined name
assigned when configuring the IED. The same name is used in the disturbance recorder function
(DR), indications (IND) and event recorder function (ER).
The event record is stored as a part of the disturbance report information (ER, DR, IND, TVR
and FL) and managed via the LHMI or PCM 600.
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9.1 Introduction
Information about the pre-fault and fault values for currents and voltages are vital for the distur-
bance evaluation.
The Trip value recorder calculates the values of all selected analog input signals connected to
the Disturbance report function. The result is magnitude and phase angle before and during the
fault for each analog input signal.
The trip value recorder information is available for the disturbances locally in the IED.
The information may be uploaded to the PCM 600 (Protection and Control IED Manager) and
further analyzed using the Disturbance Handling tool.
The trip value recorder information is an integrated part of the disturbance record (Comtrade
file).
When the disturbance report function is triggered the sample for the fault interception is
searched for, by checking the non-periodic changes in the analog input signals. The channel
search order is consecutive, starting with the analog input with the lowest number.
When a starting point is found, the Fourier estimation of the pre-fault values of the complex val-
ues of the analog signals starts 1.5 cycle before the fault sample. The estimation uses samples
during one period. The post-fault values are calculated using the Recursive Least Squares (RLS)
method. The calculation starts a few samples after the fault sample and uses samples during 1/2
- 2 cycles depending on the shape of the signals.
If no starting point is found in the recording, the disturbance report trig sample is used as the
start sample for the Fourier estimation. The estimation uses samples during one cycle before the
trig sample. In this case the calculated values are used both as pre-fault and fault values.
The name of the analog input signal that appears in the Trip value recorder function is the us-
er-defined name assigned when the IED is configured. The same name is used in the Disturbance
recorder function (DR).
The trip value record is stored as a part of the disturbance report information (ER, DR, IND,
TVR and FLOC) and managed in via the LHMI or PCM 600.
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10.1 Introduction
The Disturbance Recorder function supplies fast, complete and reliable information about dis-
turbances in the power system. It facilitates understanding system behavior and related primary
and secondary equipment during and after a disturbance. Recorded information is used for dif-
ferent purposes in the short perspective (e.g. corrective actions) and long perspective (e.g. Func-
tional Analysis).
The Disturbance Recorder acquires sampled data from all selected analog input and binary sig-
nals connected to the Disturbance Report function (maximum 40 analog and 96 binary signals).
The binary signals are the same signals as available under the event recorder function.
The function is characterized by great flexibility and is not dependent on the operation of pro-
tection functions. It can record disturbances not detected by protection functions.
The disturbance recorder information for the last 100 disturbances are saved in the IED and the
Local Human Machine Interface (LHMI) is used to view the list of recordings.
The disturbance recording information can be uploaded to the PCM 600 (Protection and Control
IED Manager) and further analyzed using the Disturbance Handling tool.
DR collects analog values and binary signals continuously, in a cyclic buffer. The pre-fault buff-
er operates according to the FIFO principle; old data will continuously be overwritten as new
data arrives when the buffer is full. The size of this buffer is determined by the set pre-fault re-
cording time.
Upon detection of a fault condition (triggering), the disturbance is time tagged and the data stor-
age continues in a post-fault buffer. The storage process continues as long as the fault condition
prevails - plus a certain additional time. This is called the post-fault time and it can be set in the
disturbance report.
The above mentioned two parts form a disturbance recording. The whole memory, intended for
disturbance recordings, acts as a cyclic buffer and when it is full, the oldest recording is over-
written. The last 100 recordings are stored in the IED.
The time tagging refers to the activation of the trigger that starts the disturbance recording. A
recording can be trigged by, manual start, binary input and/or from analog inputs (over-/under-
level trig).
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A user-defined name for each of the signals can be set. These names are common for all func-
tions within the disturbance report functionality.
Saving the data for analog channels with corresponding data for binary signals
Add relevant data to be used by the Disturbance Handling tool (part of PCM 600)
Compression of the data, which is performed without losing any data accuracy
Storing the compressed data in a non-volatile memory (flash memory)
The recording files comply with the Comtrade standard IEC 60255-24 and are divided into three
files; a header file (HDR), a configuration file (CFG) and a data file (DAT).
The header file (optional in the standard) contains basic information about the disturbance i.e.
information from the Disturbance Report functions (ER, TVR). The Disturbance Handling tool
use this information and present the recording in a user-friendly way.
General:
Analog:
Binary:
Signal names
Status of binary input signals
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The configuration file is a mandatory file containing information needed to interpret the data
file. For example sampling rate, number of channels, system frequency, channel info etc.
The data file, which also is mandatory, containing values for each input channel for each sample
in the record (scaled value). The data file also contains a sequence number and time stamp for
each set of samples.
The last 8 recordings, out of maximum 100, are available for transfer to the master. When the
last one is transferred and acknowledged new recordings in the IED will appear, in the master
points of view (even if they already where stored in the IED).
To be able to report 40 analog channels from the IED using IEC 60870-5-103 the first
8 channels are placed in the public range and the next 32 are placed in the private range. To com-
ply the standard the first 8 must be configured according to table 439.
The binary signals connected to DRB1-DRB6 are reported by polling. The function blocks in-
clude function type and information number.
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792
About this chapter Chapter 15
Metering
Chapter 15 Metering
793
Pulse counter logic (GGIO) Chapter 15
Metering
1.1 Introduction
The pulse counter logic function counts externally generated binary pulses, for instance pulses
coming from an external energy meter, for calculation of energy consumption values. The pulses
are captured by the binary input module and then read by the pulse counter function. A scaled
service value is available over the station bus. The special Binary input module with enhanced
pulse counting capabilities must be ordered to achieve this functionality.
The integration time period can be set in the range from 30 seconds to 60 minutes and is syn-
chronized with absolute system time. Interrogation of additional pulse counter values can be
done with a command (intermediate reading) for a single counter. All active counters can also
be read by the LON General Interrogation command (GI) or IEC 61850.
The pulse counter in REx670 supports unidirectional incremental counters. That means only
positive values are possible. The counter uses a 32 bit format, that is, the reported value is a
32-bit, signed integer with a range 0...+2147483647. The counter is reset at initialization of the
IED.
The reported value to station HMI over the station bus contains Identity, Value, Time, and Pulse
Counter Quality. The Pulse Counter Quality consists of:
The transmission of the counter value by SPA can be done as a service value, that is, the value
frozen in the last integration cycle is read by the station HMI from the database. The pulse
counter function updates the value in the database when an integration cycle is finished and ac-
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Pulse counter logic (GGIO) Chapter 15
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tivates the NEW_VAL signal in the function block. This signal can be connected to an Event
function block, be time tagged, and transmitted to the station HMI. This time corresponds to the
time when the value was frozen by the function.
Note!
The pulse counter function requires a binary input card, BIMp, that is specially adapted to the
pulse counter function.
Figure 352 shows the pulse counter function block with connections of the inputs and outputs.
The BLOCK and READ_VAL inputs can be connected to Single Command blocks, which are
intended to be controlled either from the station HMI or/and the local HMI. As long as the
BLOCK signal is set, the pulse counter is blocked. The signal connected to READ_VAL per-
forms one additional reading per positive flank. The signal must be a pulse with a length >1 sec-
ond.
The BI_PULSE input is connected to the used input of the function block for the Binary Input
Module (BIM).
Each pulse counter function block has four binary output signals that can be connected to an
Event function block for event recording: INVALID, RESTART, BLOCKED and NEW_VAL.
The SCAL_VAL signal can be connected to the IEC Event function block.
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The INVALID signal is a steady signal and is set if the Binary Input Module, where the pulse
counter input is located, fails or has wrong configuration.
The RESTART signal is a steady signal and is set when the reported value does not comprise a
complete integration cycle. That is, in the first message after IED start-up, in the first message
after deblocking, and after the counter has wrapped around during last integration cycle.
The BLOCKED signal is a steady signal and is set when the counter is blocked. There are two
reasons why the counter is blocked:
The NEW_VAL signal is a pulse signal. The signal is set if the counter value was updated since
last report.
PC01-
PCGGIO
BLOCK INVALID
READ_VAL RESTART
BI_PULSE BLOCKED
RS_CNT NEW_VAL
NAME SCAL_VAL
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Table 442: Output signals for the PCGGIO (PC01-) function block
Signal Description
INVALID The pulse counter value is invalid
RESTART The reported value does not comprise a complete integration
cycle
BLOCKED The pulse counter function is blocked
NEW_VAL A new pulse counter value is generated
SCAL_VAL Scaled value with time and status information
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Energy metering and demand handling Chapter 15
(MMTR) Metering
2.1 Introduction
Outputs from measurement function (MMXU) can be used to calculate energy. Active as well
as reactive values are calculated in import respectively export direction. Values can be read or
generated as pulses. Maximum demand power values are also calculated by the function.
The maximum demand values for active and reactive power are calculated for the set time tEn-
ergy and the maximum value is stored in a register available over communication and from out-
puts MAXPAFD, MAXPARD, MAXRAFD, MAXRARD for the active and reactive power
forward and reverse direction until reset with input RSTDMD or from the LHMI reset menu.
SVR1 ETP1
CVMMXU ETPMMTR
PINST P
QINST Q
STACC
TRUE
RSTACC
FALSE
RSTDMD
FALSE
en07000121.vsd
Figure 354: Connection of the energy metering function to the outputs of the measuring func-
tion
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Energy metering and demand handling Chapter 15
(MMTR) Metering
ETP1-
ETPMMTR
P ACCST
Q EAFPULSE
STACC EARPULSE
RSTACC ERFPULSE
RSTDMD ERRPULSE
EAFALM
EARALM
ERFALM
ERRALM
EAFACC
EARACC
ERFACC
ERRACC
MAXPAFD
MAXPARD
MAXPRFD
MAXPRRD
en07000120.vsd
Table 446: Output signals for the ETPMMTR (ETP1-) function block
Signal Description
ACCST Start of accumulating energy values.
EAFPULSE Accumulated forward active energy pulse
EARPULSE Accumulated reverse active energy pulse
ERFPULSE Accumulated forward reactive energy pulse
ERRPULSE Accumulated reverse reactive energy pulse
EAFALM Alarm for active forward energy exceed limit in set interval
EARALM Alarm for active reverse energy exceed limit in set interval
ERFALM Alarm for reactive forward energy exceed limit in set interval
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Signal Description
ERRALM Alarm for reactive reverse energy exceed limit in set interval
EAFACC Accumulated forward active energy value in KWh
EARACC Accumulated reverse active energy value in kWh
ERFACC Accumulated forward reactive energy value in kVArh
ERRACC Accumulated reverse reactive energy value in kVArh
MAXPAFD Maximum forward active power demand value for set interval
MAXPARD Maximum reverse active power demand value for set interval
MAXPRFD Maximum forward reactive power demand value for set interval
MAXPRRD Maximum reactive power demand value in reverse direction
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Energy metering and demand handling Chapter 15
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Table 448: Advanced general settings for the ETPMMTR (ETP1-) function
Parameter Range Step Default Unit Description
EALim 0.001 - 0.001 1000000.000 MWh Active energy limit
10000000000.000
ERLim 0.001 - 0.001 1000.000 MVArh Reactive energy limit
10000000000.000
DirEnergyAct Forward - Forward - Direction of active energy
Reverse flow Forward/Reverse
DirEnergyReac Forward - Forward - Direction of reactive
Reverse energy flow For-
ward/Reverse
EnZeroClamp Off - On - Enable of zero point
On clamping detection func-
tion
LevZeroClampP 0.001 - 10000.000 0.001 10.000 MW Zero point clamping level
at active Power
LevZeroClampQ 0.001 - 10000.000 0.001 10.000 MVAr Zero point clamping level
at reactive Power
EAFPrestVal 0.000 - 10000.000 0.001 0.000 MWh Preset Initial value for for-
ward active energy
EARPrestVal 0.000 - 10000.000 0.001 0.000 MWh Preset Initial value for
reverse active energy
ERFPresetVal 0.000 - 10000.000 0.001 0.000 MVArh Preset Initial value for for-
ward reactive energy
ERVPresetVal 0.000 - 10000.000 0.001 0.000 MVArh Preset Initial value for
reverse reactive energy
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Energy metering and demand handling Chapter 15
(MMTR) Metering
802
About this chapter Chapter 16
Station communication
Chapter 16 Station
communication
803
Overview Chapter 16
Station communication
1 Overview
Each IED is provided with a communication interface, enabling it to connect to one or many sub-
station level systems or equipment, either on the Substation Automation (SA) bus or Substation
Monitoring (SM) bus.
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
SP01-
SPGGIO
BLOCK
IN
NAME
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
MP01-
SP16GGIO
BLOCK NAMEOR
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
NAME1
NAME2
NAME3
NAME4
NAME5
NAME6
NAME7
NAME8
NAME9
NAME10
NAME11
NAME12
NAME13
NAME14
NAME15
NAME16
en07000125.vsd
Table 450: Input signals for the SP16GGIO (MP01-) function block
Signal Description
BLOCK Block of function
IN1 Input 1 status
IN2 Input 2 status
IN3 Input 3 status
IN4 Input 4 status
IN5 Input 5 status
IN6 Input 6 status
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
Signal Description
IN7 Input 7 status
IN8 Input 8 status
IN9 Input 9 status
IN10 Input 10 status
IN11 Input 11 status
IN12 Input 12 status
IN13 Input 13 status
IN14 Input 14 status
IN15 Input 15 status
IN16 Input 16 status
Table 451: Output signals for the SP16GGIO (MP01-) function block
Signal Description
NAMEOR User define string for logic OR output signal
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
DP01-
DPGGIO
OPEN
CLOSE
VALID
en05000771.vsd
MV01-
MVGGIO
IN VALUE
RANGE
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
Table 454: Output signals for the MVGGIO (MV01-) function block
Signal Description
VALUE Magnitude of deadband value
RANGE Range
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IEC 61850-8-1 communication protocol Chapter 16
Station communication
810
LON communication protocol Chapter 16
Station communication
3.1 Introduction
An optical network can be used within the Substation Automation system. This enables commu-
nication with the IED through the LON bus from the operators workplace, from the control cen-
ter and also from other terminals.
The LON protocol is specified in LonTalkProtocol Specification Version 3 from Echelon Cor-
poration and is designed for communication in control networks. These networks are character-
ized by high speed for data transfer, short messages (few bytes), peer-to-peer communication,
multiple communication media, low maintenance, multivendor equipment, and low support
costs. LonTalk supports the needs of applications that cover a range of requirements. The pro-
tocol follows the reference model for open system interconnection (OSI) designed by the Inter-
national Standardization Organization (ISO).
In this document the most common addresses for commands and events are available. Other ad-
dresses can be found in a separate document, refer to section 1.5 "Related documents".
It is assumed that the reader is familiar with the LON communication protocol in general.
The LON bus links the different parts of the protection and control system. The measured values,
status information, and event information are spontaneously sent to the higher-level devices.
The higher-level devices can read and write memorized values, setting values, and other param-
eter data when required. The LON bus also enables the bay level devices to communicate with
each other to deliver, for example, interlocking information among the terminals without the
need of a bus master.
The LonTalk protocol supports two types of application layer objects: network variables and ex-
plicit messages. Network variables are used to deliver short messages, such as measuring values,
status information, and interlocking/blocking signals. Explicit messages are used to transfer
longer pieces of information, such as events and explicit read and write messages to access de-
vice data.
The benefits achieved from using the LON bus in protection and control systems include direct
communication among all terminals in the system and support for multi-master implementa-
tions. The LON bus also has an open concept, so that the terminals can communicate with ex-
ternal devices using the same standard of network variables.
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LON protocol
Configuration of LON
Lon Network Tool (LNT 505) is a multi-purpose tool for LonWorks network configuration. All
the functions required for setting up and configuring a LonWorks network is easily accessible
on a single tool program. For details see the Operators manual.
Activate LONCommunication
Activate LON communication in the PST Parameter Setting Tool under Settings -> General set-
tings > Communication > SLM configuration > Rear optical LON, where ADE should be
set to ON.
Vertical communication
Vertical communication describes communication between the monitoring devices and protec-
tion and control IEDs. This communication includes sending of changed process data to moni-
toring devices as events and transfer of commands, parameter data and disturbance recorder
files. This communication is implemented using explicit messages.
Binary events
Binary events are generated in event function blocks EV01 to EV20 in the 670IEDs. The event
function blocks have predefined LON addresses. table 458 shows the LON addresses to the first
input on the event function blocks. The addresses to the other inputs on the event function block
are consecutive after the first input. For example, input 15 on event block EV17 has the address
1280 + 14 (15-1) = 1294.
For double indications only the first eight inputs 18 must be used. Inputs 916 can be used for
other type of events at the same event block.
As basic, 3 event function blocks EV01-EV03 running with a fast loop time (3 ms) is available
in the 670IEDS. The remaining event function blocks EV04-EV09 runs with a loop time on 8
ms and EV10-EV20 runs with a loop time on 100 ms. The event blocks are used to send binary
signals, integers, real time values like analogue data from measuring functions and mA input
modules as well as pulse counter signals.
16 pulse counter value function blocks PC01 to PC16 and 24 mA input service values function
blocks SMMI1_In1 to 6 SMMI4_In1 to 6 are available in the 670IEDs.
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LON communication protocol Chapter 16
Station communication
The first LON address in every event function block is found in table 458
Event masks
The event mask for each input can be set individually from the Parameter Setting Tool (PST)
Under: Settings > General Settings > Monitoring > Event function as.
No events
OnSet, at pick-up of the signal
OnReset, at drop-out of the signal
OnChange, at both pick-up and drop-out of the signal
AutoDetect, event system itself make the reporting decision, (reporting criteria
for integers has no semantic, prefer to be set by the user)
The following type of signals from application functions can be connected to the event function
block.
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LON communication protocol Chapter 16
Station communication
Single indication
Directly connected binary IO signal via binary input function block (SMBI) is always reported
on change, no changed detection is done in the event function block. Other Boolean signals, for
example a start or a trip signal from a protection function is event masked in the event function
block.
Double indications
Double indications can only be reported via switch-control (SCSWI) functions, the event re-
porting is based on information from switch-control, no change detection is done in the event
function block.
Directly connected binary IO signal via binary input function block (SMBI) is not possible to
handle as double indication. Double indications can only be reported for the first 8 inputs on an
event function block.
Analog value
All analog values are reported cyclic, the reporting interval is taken from the connected function
if there is a limit supervised signal, otherwise it is taken from the event function block.
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LON communication protocol Chapter 16
Station communication
Command handling
Commands are transferred using transparent SPA-bus messages. The transparent SPA-bus mes-
sage is an explicit LON message, which contains an ASCII character message following the cod-
ing rules of the SPA-bus protocol. The message is sent using explicit messages with message
code 41H and using acknowledged transport service.
Both the SPA-bus command messages (R or W) and the reply messages (D, A or N) are sent
using the same message code. It is mandatory that one device sends out only one SPA-bus mes-
sage at a time to one node and waits for the reply before sending the next message.
For commands from the operator workplace to the IED for apparatus control, i.e. the function
blocks type SCSWI 1 to 32, SXCBR 1 to 18and SXSWI 1 to 28; the SPA addresses are accord-
ing to table 459
Horizontal communication
Network variables are used for communication between REx 5xx and 670IEDs. The supported
network variable type is SNVT_state (NV type 83). SNVT_state is used to communicate the
state of a set of 1 to 16 Boolean values.
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LON communication protocol Chapter 16
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The multiple command send function block (MTxx) is used to pack the information to one value.
This value is transmitted to the receiving node and presented for the application by a multiple
command function block (CMxx). At horizontal communication the input BOUND on the event
function block (MTxx) must be set to 1. There are 10 MT and 60 CM function blocks available.
The MT and CM function blocks are connected using Lon Network Tool (LNT 505). This tool
also defines the service and addressing on LON.
This is an overview description how to configure the network variables for 670IEDs.
LON
en05000718.vsd
Figure 361: Examples connections between MT and CM function blocks in three terminals.
The network variable connections are done from the NV Connection window. From LNT win-
dow select Connections -> NVConnections -> New
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LON communication protocol Chapter 16
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en05000719.vsd
There are two ways of downloading NV connections. Either you use the drag-and-drop method
where you select all nodes in the device window, drag them to the Download area in the bottom
of the program window and drop them there. Or the traditional menu selection, Configuration
-> Download...
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LON communication protocol Chapter 16
Station communication
en05000720.vsd
Communication ports
The serial communication module (SLM) is used for SPA or IEC 60870-5-103 and LON com-
munication. This module is a mezzanine module, and can be placed on the Main Processing
Module (NUM). The serial communication module can have connectors for two plastic fiber ca-
bles (snap-in) or two glass fiber cables (ST, bayonet) or a combination of plastic and glass fiber.
Three different types are available depending on type of fiber. The incoming optical fiber is con-
nected to the RX receiver input, and the outgoing optical fiber to the TX transmitter output.
When the fiber optic cables are laid out, pay special attention to the instructions concerning the
handling, connection, etc. of the optical fibers. The module is identified with a number on the
label on the module.
Table 459: SPA addresses for commands from the operator workplace to the IED for ap-
paratus control
Name Function SPA Description
block address
BL_CMD SCSWI01 1 I 5115 SPA parameters for block command
BL_CMD SCSWI02 1 I 5139 SPA parameters for block command
BL_CMD SCSWI02 1 I 5161 SPA parameters for block command
BL_CMD SCSWI04 1 I 5186 SPA parameters for block command
BL_CMD SCSWI05 1 I 5210 SPA parameters for block command
BL_CMD SCSWI06 1 I 5234 SPA parameters for block command
BL_CMD SCSWI07 1 I 5258 SPA parameters for block command
BL_CMD SCSWI08 1 I 5283 SPA parameters for block command
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Station communication
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4.1 Introduction
In this section the most common addresses for commands and events are available. Other ad-
dresses can be found in a separate document, refer to section 1.5 "Related documents".
It is assumed that the reader is familiar with the SPA communication protocol in general.
The master requests slave information using request messages and sends information to the slave
in write messages. Furthermore, the master can send all slaves in common a broadcast message
containing time or other data. The inactive state of bus transmit and receive lines is a logical "1".
SPA protocol
The tables below specify the SPA addresses for reading data from and writing data to an
IED 670 with the SPA communication protocol implemented.
The SPA addresses for the mA input service values (MI03-MI16) are found in table463
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The SPA addresses for the pulse counter values PC01 PC16 are found in table 464
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I/O modules
To read binary inputs, the SPA-addresses for the outputs of the I/O-module function block are
used, i.e. the addresses for BI1 BI16. The SPA addresses are found in a separate document,
refer to section 1.5 "Related documents".
The single command function consists of three function blocks; CD01 CD03 for 16 binary out-
put signals each.
The signals can be individually controlled from the operator station, remote-control gateway, or
from the local HMI on the IED. The SPA addresses for the single command function (CD) are
shown in Table 3. For the single command function block, CD01 to CD03, the address is for the
first output. The other outputs follow consecutively after the first one. For example, output 7 on
the CD02 function block has the 5O533 address.
The SPA addresses for the single command functions CD01 CD03 are found in table 465
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Function block SPA address CMD Input SPA address CMD output
CD03-Cmd7 4-S-4711 5-O-549
CD03-Cmd8 4-S-4712 5-O-550
CD03-Cmd9 4-S-4713 5-O-551
CD03-Cmd10 4-S-4714 5-O-552
CD03-Cmd11 4-S-4715 5-O-553
CD03-Cmd12 4-S-4716 5-O-554
CD03-Cmd13 4-S-4717 5-O-555
CD03-Cmd14 4-S-4718 5-O-556
CD03-Cmd15 4-S-4719 5-O-557
CD03-Cmd16 4-S-4720 5-O-558
Table 465 SPA addresses for the signals on the single command functions
Figure 364 shows an application example of how the user can, in a simplified way, connect the
command function via the configuration logic circuit in a protection terminal for control of a cir-
cuit breaker.
A pulse via the binary outputs of the terminal normally performs this type of command control.
The SPA addresses to control the outputs OUT1 OUT16 in CD01 are shown in table 465
Figure 364: Application example showing a simplified logic diagram for control of a circuit
breaker.
The MODE input defines if the output signals from CD01 shall be off, steady or pulsed signals.
This is set in Parameter Setting Tool (PST) under: Setting > General Settings > Control >
Commands > Single Command.
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Event function
This event function is intended to send time-tagged events to the station level (e.g. operator
workplace) over the station bus. The events are there presented in an event list. The events can
be created from both internal logical signals and binary input channels. All must The internal
signals are time tagged in the main processing module, while the binary input channels are time
tagged directly on each I/O module. The events are produced according to the set event masks.
The event masks are treated commonly for both the LON and SPA channels. All events accord-
ing to the event mask are stored in a buffer, which contains up to 1000 events. If new events
appear before the oldest event in the buffer is read, the oldest event is overwritten and an over-
flow alarm appears.
Two special signals for event registration purposes are available in the terminal, Terminal Re-
started (0E50) and Event buffer overflow (0E51).
The input parameters can be set individually from the Parameter Setting Tool (PST) under: Set-
ting > General Setting > Monitoring > Event Function as.
No events
OnSet, at pick-up of the signal
OnReset, at drop-out of the signal
OnChange, at both pick-up and drop-out of the signal
AutoDetect, event system itself make the reporting decision, (reporting criteria
for integers has no semantic, prefer to be set by the user)
The Status and event codes for the Event functions are found in table 466
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1) These values are only applicable if the Event mask is masked OFF.
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Note that corresponding Event mask must be set to an applicable value via the Parameter Setting
Tool (PST), under: Settings > General Settings > Monitoring > Event Function as.
No events
OnSet, at pick-up of the signal
OnReset, at drop-out of the signal
OnChange, at both pick-up and drop-out of the signal
AutoDetect, event system itself make the reporting decision, (reporting criteria
for integers has no semantic, prefer to be set by the user)
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The incoming optical fiber is connected to the RX receiver input, and the outgoing optical fiber
to the TX transmitter output. When the fiber optic cables are laid out, pay special attention to the
instructions concerning the handling, connection, etc. of the optical fibers. The module is iden-
tified with a number on the label on the module.
The procedure to set the transfer rate and slave number can be found in the Installation and com-
missioning manual for respective IED.
4.3 Design
When communicating locally with a Personal Computer (PC) in the station, using the rear SPA
port, the only hardware needed for a station monitoring system is:
Optical fibres
Opto/electrical converter for the PC
PC
When communicating remotely with a PC using the rear SPA port, the same hardware is needed
plus telephone modems.
The software needed in the PC, either local or remote, is PCM 600.
When communicating between the LHMI and a PC, the only hardware required is a front-con-
nection cable.
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5.1 Introduction
The IEC 60870-5-103 communication protocol is mainly used when a protection terminal com-
municates with a third party control or monitoring system. This system must have software that
can interpret the IEC 60870-5-103 communication messages.
Event handling
Report of analog service values (measurements)
Fault location
Command handling
- Autorecloser ON/OFF
- Teleprotection ON/OFF
- Protection ON/OFF
- LED reset
- Characteristics 1 - 4 (Setting groups)
File transfer (disturbance files)
Time synchronization
For detailed information about IEC 60870-5-103, refer to the IEC60870 standard part 5: Trans-
mission protocols, and to the section 103: Companion standard for the informative interface of
protection equipment.
IEC 60870-5-103
The tables in the following sections specify the information types supported by the IED 670
products with the communication protocol IEC 60870-5-103 implemented.
To support the information, corresponding functions must be included in the protection and con-
trol IED.
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Number of instances: 1
Number of instances: 1
Number of instances: 4
FUNCTION TYPE parameter for each block in private range. Default values are defined in
private range 1 - 4. One for each instance.
INFORMATION NUMBER is required for each output signal. Default values are 1 - 8.
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Status
Number of instances: 1
Number of instances: 20
FUNCTION TYPE parameter for each block in private range. Default values are defined in pri-
vate range 5 - 24. One for each instance.
INFORMATION NUMBER is required for each input signal. Default values are defined in
range 1 - 8
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Number of instances: 1
Number of instances: 1
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Number of instances: 1
The instance type is suitable for linediff, transformerdiff, overcurrent and earthfault protection
functions.
Number of instances: 1
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Number of instances: 1
Measurands
Function blocks in monitor direction for input measurands. Typically connected to monitoring
function, for example to power measurement CVMMXU.
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The IED will report all valid measuring types depending on connected signals.
Upper limit for measured currents, active/reactive-power is 2.4 times rated value.
Upper limit for measured voltages and frequency is 1.2 times rated value.
FUNCTION TYPE parameter for each block in private range. Default values are defined in pri-
vate range 25 27. One for each instance.
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Disturbance recordings
The following elements are used in the ASDUs (Application Service Data Units) defined in the
standard.
Analog signals, 40-channels: the channel number for each channel has to be specified. Channels
used in the public range are 1 to 8 and with:
Channel number used for the remaining 32 analog signals are numbers in the private range
64 to 95.
Binary signals, 96-channels: for each channel the user can specify a FUNCTION TYPE and an
INFORMATION NUMBER.
Disturbance Upload
All analog and binary signals that are recorded with disturbance recorder will be reported to the
master. The last eight disturbances that are recorded are available for transfer to the master. A
successfully transferred disturbance (acknowledged by the master) will not be reported to the
master again.
When a new disturbance is recorded by the IED a list of available recorded disturbances will be
sent to the master, an updated list of available disturbances will be sent whenever something has
happened to disturbances in this list. I.e. when a disturbance is deleted (by other client e.g. SPA)
or when a new disturbance has been recorded or when the master has uploaded a disturbance.
Information sent in the disturbance upload is specified by the standard; however, some of the
information are adapted to information available in disturbance recorder in Rex67x.
This section describes all data that is not exactly as specified in the standard.
ASDU23
In list of recorded disturbances (ASDU23) an information element named SOF (status of fault)
exists. This information element consists of 4 bits and indicates whether:
Bit TP: the protection equipment has tripped during the fault
Bit TM: the disturbance data are currently being transmitted
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Bit TEST: the disturbance data have been recorded during normal operation or
test mode.
Bit OTEV: the disturbance data recording has been initiated by another event
than start/pick-up
The only information that is easily available is test-mode status. The other information is always
set (hard coded) to:
Another information element in ASDU23 is the FAN (fault number). According to the standard
this is a number that is incremented when a protection function takes action. In Rex67x FAN is
equal to disturbance number, which is incremented for each disturbance.
ASDU26
When a disturbance has been selected by the master; (by sending ASDU24), the protection
equipment answers by sending ASDU26, which contains an information element named NOF
(number of grid faults). This number should indicate fault number in the power system, i.e. a
fault in the power system with several trip and auto-reclosing has the same NOF (while the FAN
should be incremented). NOF is in Rex67x, just as FAN, equal to disturbance number.
To get INF and FUN for the recorded binary signals there are parameters on the disturbance re-
corder for each input. The user must set these parameters to whatever he connects to the corre-
sponding input.
Supported
Electrical Interface
EIA RS-485 No
number of loads No
Optical interface
glass fibre Yes
plastic fibre Yes
Transmission speed
96000 bit/s Yes
19200 bit/s Yes
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Supported
Link Layer
DFC-bit used Yes
Connectors
connector F-SMA No
connector BFOC/2.5 Yes
Supported
Selection of standard ASDUs in monitoring direction
ASDU Yes
1 Time-tagged message Yes
2 Time-tagged message with rel. time Yes
3 Measurands I Yes
4 Time-tagged message with rel. time Yes
5 Identification Yes
6 Time synchronization Yes
8 End of general interrogation Yes
9 Measurands II Yes
10 Generic data No
11 Generic identification No
23 List of recorded disturbances Yes
26 Ready for transm. of disturbance data Yes
27 Ready for transm. of a channel Yes
28 Ready for transm of tags Yes
29 Transmission of tags Yes
30 Transmission fo disturbance data Yes
31 End of transmission Yes
Selection of standard ASDUs in control direction
ASDU Yes
6 Time synchronization Yes
7 General interrogation Yes
10 Generic data No
20 General command Yes
21 Generic command No
24 Order for disturbance data transmission Yes
25 Acknowledgement for distance data transmission Yes
Selection of basic application functions
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Supported
Test mode No
Blocking of monitoring direction Yes
Disturbance data Yes
Private data Yes
Generic services No
The incoming optical fiber is connected to the RX receiver input, and the outgoing optical fiber
to the TX transmitter output. When the fiber optic cables are laid out, pay special attention to the
instructions concerning the handling, connection, etc. of the optical fibers. The module is iden-
tified with a number on the label on the module.
ICMA-
I103IEDCMD
BLOCK 19-LEDRS
23-GRP1
24-GRP2
25-GRP3
26-GRP4
en05000689.vsd
ICMD-
I103CMD
BLOCK 16-AR
17-DIFF
18-PROT
en05000684.vsd
ICM1-
I103UserCMD
BLOCK OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
en05000693.vsd
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IEV1-
I103IED
BLOCK
19_LEDRS
23_GRP1
24_GRP2
25_GRP3
26_GRP4
21_TESTM
en05000688.vsd
IS01-
I103UsrDef
BLOCK
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
en05000694.vsd
ISU1-
I103Superv
BLOCK
32_MEASI
33_MEASU
37_IBKUP
38_VTFF
46_GRWA
47_GRAL
en05000692.vsd
ISEF-
I103EF
BLOCK
51_EFFW
52_EFREV
en05000685.vsd
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IZ01-
I103FltDis
BLOCK
64_STL1
65_STL2
66_STL3
67_STIN
84_STGEN
69_TRL1
70_TRL2
71_TRL3
68_TRGEN
74_FW
75_REV
78_ZONE1
79_ZONE2
80_ZONE3
81_ZONE4
82_ZONE5
76_TRANS
77_RECEV
73_SCL
FLTLOC
ARINPROG
en05000686.vsd
IFL1-
I103FltStd
BLOCK
64_STL1
65_STL2
66_STL3
67_STIN
84_STGEN
69_TRL1
70_TRL2
71_TRL3
68_TRGEN
74_FW
75_REV
85_BFP
86_MTRL1
87_MTRL2
88_MTRL3
89_MTRN
90_IOC
91_IOC
92_IEF
93_IEF
ARINPROG
en05000687.vsd
IAR1-
I103AR
BLOCK
16_ARACT
128_CBON
130_UNSU
en05000683.vsd
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IMM1-
I103Meas
BLOCK
IL1
IL2
IL3
IN
UL1
UL2
UL3
UL1L2
UN
P
Q
F
en05000690.vsd
IMU1-
I103MeasUsr
BLOCK
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
en05000691.vsd
Table 472: Input signals for the I103IEDCMD (ICMA-) function block
Signal Description
BLOCK Block of commands
Table 473: Input signals for the I103CMD (ICMD-) function block
Signal Description
BLOCK Block of commands
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Table 474: Input signals for the I103IED (IEV1-) function block
Signal Description
BLOCK Block of status reporting
19_LEDRS Information number 19, reset LEDs
23_GRP1 Information number 23, setting group 1 is active
24_GRP2 Information number 24, setting group 2 is active
25_GRP3 Information number 25, setting group 3 is active
26_GRP4 Information number 26, setting group 4 is active
21_TESTM Information number 21, test mode is active
Table 475: Input signals for the I103UserCMD (ICM1-) function block
Signal Description
BLOCK Block of commands
Table 476: Input signals for the I103UsrDef (IS01-) function block
Signal Description
BLOCK Block of status reporting
INPUT1 Binary signal Input 1
INPUT2 Binary signal input 2
INPUT3 Binary signal input 3
INPUT4 Binary signal input 4
INPUT5 Binary signal input 5
INPUT6 Binary signal input 6
INPUT7 Binary signal input 7
INPUT8 Binary signal input 8
Table 477: Input signals for the I103Superv (ISU1-) function block
Signal Description
BLOCK Block of status reporting
32_MEASI Information number 32, measurand supervision of I
33_MEASU Information number 33, measurand supervision of U
37_IBKUP Information number 37, I high-high back-up protection
38_VTFF Information number 38, fuse failure VT
46_GRWA Information number 46, group warning
47_GRAL Information number 47, group alarm
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Table 478: Input signals for the I103EF (ISEF-) function block
Signal Description
BLOCK Block of status reporting
51_EFFW Information number 51, earth-fault forward
52_EFREV Information number 52, earth-fault reverse
Table 479: Input signals for the I103FltDis (IZ01-) function block
Signal Description
BLOCK Block of status reporting
64_STL1 Information number 64, start phase L1
65_STL2 Information number 65, start phase L2
66_STL3 Information number 66, start phase L3
67_STIN Information number 67, start residual current IN
84_STGEN Information number 84, start general
69_TRL1 Information number 69, trip phase L1
70_TRL2 Information number 70, trip phase L2
71_TRL3 Information number 71, trip phase L3
68_TRGEN Information number 68, trip general
74_FW Information number 74, forward/line
75_REV Information number 75, reverse/bus
78_ZONE1 Information number 78, zone 1
79_ZONE2 Information number 79, zone 2
80_ZONE3 Information number 79, zone 3
81_ZONE4 Information number 79, zone 4
82_ZONE5 Information number 79, zone 5
76_TRANS Information number 76, signal transmitted
77_RECEV Information number 77, signal recevied
73_SCL Information number 73, fault location in ohm
FLTLOC Faultlocator faultlocation valid (LMBRFLO-CALCMADE)
ARINPROG Autorecloser in progress (SMBRREC- INPROGR)
Table 480: Input signals for the I103FltStd (IFL1-) function block
Signal Description
BLOCK Block of status reporting
64_STL1 Information number 64, start phase L1
65_STL2 Information number 65, start phase L2
66_STL3 Information number 66, start phase L3
67_STIN Information number 67, start residual curent IN
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Signal Description
84_STGEN Information number 84, start general
69_TRL1 Information number 69, trip phase L1
70_TRL2 Information number 70, trip phase L2
71_TRL3 Information number 71, trip phase L3
68_TRGEN Information number 68, trip general
74_FW Information number 74, forward/line
75_REV Information number 75, reverse/bus
85_BFP Information number 85, breaker failure
86_MTRL1 Information number 86, trip measuring system phase L1
87_MTRL2 Information number 87, trip measuring system phase L2
88_MTRL3 Information number 88, trip measuring system phase L3
89_MTRN Information number 89, trip measuring system neutral N
90_IOC Information number 90, over current trip, stage low
91_IOC Information number 91, over current trip, stage high
92_IEF Information number 92, earth-fault trip, stage low
93_IEF Information number 93, earth-fault trip, stage high
ARINPROG Autorecloser in progress (SMBRREC- INPROGR)
Table 481: Input signals for the I103MeasUsr (IMU1-) function block
Signal Description
BLOCK Block of service value reporting
INPUT1 Service value for measurement on input 1
INPUT2 Service value for measurement on input 2
INPUT3 Service value for measurement on input 3
INPUT4 Service value for measurement on input 4
INPUT5 Service value for measurement on input 5
INPUT6 Service value for measurement on input 6
INPUT7 Service value for measurement on input 7
INPUT8 Service value for measurement on input 8
INPUT9 Service value for measurement on input 9
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Table 482: Input signals for the I103Meas (IMM1-) function block
Signal Description
BLOCK Block of service value reporting
IL1 Service value for current phase L1
IL2 Service value for current phase L2
IL3 Service value for current phase L3
IN Service value for residual current IN
UL1 Service value for voltage phase L1
UL2 Service value for voltage phase L2
UL3 Service value for voltage phase L3
UL1L2 Service value for voltage phase-phase L1-L2
UN Service value for residual voltage UN
P Service value for active power
Q Service value for reactive power
F Service value for system frequency
Table 483: Output signals for the I103IEDCMD (ICMA-) function block
Signal Description
19-LEDRS Information number 19, reset LEDs
23-GRP1 Information number 23, activate setting group 1
24-GRP2 Information number 24, activate setting group 2
25-GRP3 Information number 25, activate setting group 3
26-GRP4 Information number 26, activate setting group 4
Table 484: Output signals for the I103CMD (ICMD-) function block
Signal Description
16-AR Information number 16, block of autorecloser
17-DIFF Information number 17, block of differential protection
18-PROT Information number 18, block of protection
Table 485: Output signals for the I103UserCMD (ICM1-) function block
Signal Description
OUTPUT1 Command output 1
OUTPUT2 Command output 2
OUTPUT3 Command output 3
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Signal Description
OUTPUT4 Command output 4
OUTPUT5 Command output 5
OUTPUT6 Command output 6
OUTPUT7 Command output 7
OUTPUT8 Command output 8
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Table 497: Basic general settings for the I103Meas (IMM1-) function
Parameter Range Step Default Unit Description
RatedIL1 1 - 99999 1 3000 A Rated current phase L1
RatedIL2 1 - 99999 1 3000 A Rated current phase L2
RatedIL3 1 - 99999 1 3000 A Rated current phase L3
RatedIN 1 - 99999 1 3000 A Rated residual current IN
RatedUL1 0.05 - 2000.00 0.05 230.00 kV Rated voltage for phase
L1
RatedUL2 0.05 - 2000.00 0.05 230.00 kV Rated voltage for phase
L2
RatedUL3 0.05 - 2000.00 0.05 230.00 kV Rated voltage for phase
L3
RatedUL1-UL2 0.05 - 2000.00 0.05 400.00 kV Rated voltage for
phase-phase L1-L2
RatedUN 0.05 - 2000.00 0.05 230.00 kV Rated residual voltage
UN
RatedP 0.00 - 2000.00 0.05 1200.00 MW Rated value for active
power
RatedQ 0.00 - 2000.00 0.05 1200.00 MVA Rated value for reactive
power
RatedF 50.0 - 60.0 10.0 50.0 Hz Rated system frequency
FUNTYPE 1 - 255 1 1 FunT Function type (1-255)
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6.1 Introduction
The AUBI function block (or the automation bits function block) is used within the CAP tool in
order to get into the configuration the commands coming through the DNP3.0 protocol. In this
respect, this function block plays the same role as the BinGOOSEReceive (for IEC61850) or
MultiCmdReceive (for LON).
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ABI1-
AutoBits
BLOCK CMDBIT1
PSTO CMDBIT2
NAME1 CMDBIT3
NAME2 CMDBIT4
NAME3 CMDBIT5
NAME4 CMDBIT6
NAME5 CMDBIT7
NAME6 CMDBIT8
NAME7 CMDBIT9
NAME8 CMDBIT10
NAME9 CMDBIT11
NAME10 CMDBIT12
NAME11 CMDBIT13
NAME12 CMDBIT14
NAME13 CMDBIT15
NAME14 CMDBIT16
NAME15 CMDBIT17
NAME16 CMDBIT18
NAME17 CMDBIT19
NAME18 CMDBIT20
NAME19 CMDBIT21
NAME20 CMDBIT22
NAME21 CMDBIT23
NAME22 CMDBIT24
NAME23 CMDBIT25
NAME24 CMDBIT26
NAME25 CMDBIT27
NAME26 CMDBIT28
NAME27 CMDBIT29
NAME28 CMDBIT30
NAME29 CMDBIT31
NAME30 CMDBIT32
NAME31
NAME32
en06000504.vsd
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Automation bits (AUBI) Chapter 16
Station communication
Table 500: Output signals for the AutoBits (ABI1-) function block
Signal Description
CMDBIT1 Command out bit 1
CMDBIT2 Command out bit 2
CMDBIT3 Command out bit 3
CMDBIT4 Command out bit 4
CMDBIT5 Command out bit 5
CMDBIT6 Command out bit 6
CMDBIT7 Command out bit 7
CMDBIT8 Command out bit 8
CMDBIT9 Command out bit 9
CMDBIT10 Command out bit 10
CMDBIT11 Command out bit 11
CMDBIT12 Command out bit 12
CMDBIT13 Command out bit 13
CMDBIT14 Command out bit 14
CMDBIT15 Command out bit 15
CMDBIT16 Command out bit 16
CMDBIT17 Command out bit 17
CMDBIT18 Command out bit 18
CMDBIT19 Command out bit 19
CMDBIT20 Command out bit 20
CMDBIT21 Command out bit 21
CMDBIT22 Command out bit 22
CMDBIT23 Command out bit 23
CMDBIT24 Command out bit 24
CMDBIT25 Command out bit 25
CMDBIT26 Command out bit 26
CMDBIT27 Command out bit 27
CMDBIT28 Command out bit 28
CMDBIT29 Command out bit 29
CMDBIT30 Command out bit 30
CMDBIT31 Command out bit 31
CMDBIT32 Command out bit 32
864
Automation bits (AUBI) Chapter 16
Station communication
Table 502: Basic general settings for the DNP3 (DNP--) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode Off / On
ON
Table 503: Basic general settings for the DNP3Ch1RS485 (DNC1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode
Serial-Mode
BaudRate 300 Bd - 9600 Bd - Baud-rate for serial port
600 Bd
1200 Bd
2400 Bd
4800 Bd
9600 Bd
19200 Bd
WireMode Four-wire - Two-wire - RS485 wire mode
Two-wire
Table 504: Advanced general settings for the DNP3Ch1RS485 (DNC1-) function
Parameter Range Step Default Unit Description
DLinkConfirm Never - Never - Data-link confirm
Sometimes
Always
tDLinkTimeout 0.000 - 60.000 0.001 2.000 s Data-link confirm timeout
in s
DLinkRetries 0 - 255 1 3 - Data-link maximum
retries
tRxToTxMinDel 0.000 - 60.000 0.001 0.000 s Rx to Tx minimum delay
in s
DataBits 5-8 1 8 - Data bits
StopBits 1-2 1 1 - Stop bits
Parity No - Even - Parity
Even
Odd
865
Automation bits (AUBI) Chapter 16
Station communication
Table 505: Basic general settings for the DNP3Ch2TCPIP (DNC2-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode
TCP/IP
UDP-Only
TCPIPLisPort 1 - 65535 1 20000 - TCP/IP listen port
UDPPortAccData 1 - 65535 1 20000 - UDP port to accept UDP
datagrams from master
UDPPortInitNUL 1 - 65535 1 20000 - UDP portfor initial NULL
response
UDPPortCliMast 0 - 65535 1 0 - UDP port to remote cli-
ent/master
Table 506: Basic general settings for the DNP3Ch3TCPIP (DNC3-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode
TCP/IP
UDP-Only
TCPIPLisPort 1 - 65535 1 20000 - TCP/IP listen port
UDPPortAccData 1 - 65535 1 20000 - UDP port to accept UDP
datagrams from master
UDPPortInitNUL 1 - 65535 1 20000 - UDP port for initial NULL
response
UDPPortCliMast 0 - 65535 1 0 - UDP port to remote cli-
ent/master
866
Automation bits (AUBI) Chapter 16
Station communication
Table 507: Basic general settings for the DNP3Ch4TCPIP (DNC4-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode
TCP/IP
UDP-Only
TCPIPLisPort 1 - 65535 1 20000 - TCP/IP listen port
UDPPortAccData 1 - 65535 1 20000 - UDP port to accept UDP
datagrams from master
UDPPortInitNUL 1 - 65535 1 20000 - UDP port for initial NULL
response
UDPPortCliMast 0 - 65535 1 0 - UDP port to remote cli-
ent/master
Table 508: Basic general settings for the DNP3Ch5TCPIP (DNC5-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation mode
TCP/IP
UDP-Only
TCPIPLisPort 1 - 65535 1 20000 - TCP/IP listen port
UDPPortAccData 1 - 65535 1 20000 - UDP port to accept UDP
datagrams from master
UDPPortInitNUL 1 - 65535 1 20000 - UDP port for initial NULL
response
UDPPortCliMast 0 - 65535 1 0 - UDP port to remote cli-
ent/master
Table 509: Basic general settings for the DNP3Mast1RS485 (DNM1-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
ON
SlaveAddress 0 - 65519 1 1 - Slave address
MasterAddres 0 - 65519 1 1 - Master address
Obj1DefVar 1:BISingleBit - 1:BISingleBit - Object 1, default variation
2:BIWithStatus
Obj2DefVar 1:BIChWithout- - 3:BIChWithRel- - Object 2, default variation
Time Time
2:BIChWithTime
3:BIChWithRel-
Time
Obj4DefVar 1:DIChWithout- - 3:DIChWithRel- - Object 4, default variation
Time Time
2:DIChWithTime
3:DIChWithRel-
Time
867
Automation bits (AUBI) Chapter 16
Station communication
Table 510: Advanced general settings for the DNP3Mast1RS485 (DNM1-) function
Parameter Range Step Default Unit Description
ValMasterAddr No - Yes - Validate source (master)
Yes address
AddrQueryEnbl No - Yes - Address query enable
Yes
tApplConfTout 0.00 - 60.00 0.01 10.00 s Application layer confim
timeout
ApplMultFrgRes No - Yes - Enable application for
Yes multiple fragment
response
ConfMultFrag No - Yes - Confirm each multiple
Yes fragment
UREnable No - Yes - Unsolicited response
Yes enabled
URSendOnline No - No - Unsolicited response
Yes sends when on-line
868
Automation bits (AUBI) Chapter 16
Station communication
869
Automation bits (AUBI) Chapter 16
Station communication
Table 511: Basic general settings for the DNP3Mast3TCPIP (DNM3-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
ON
SlaveAddress 0 - 65519 1 1 - Slave address
MasterAddres 0 - 65519 1 1 - Master address
ValMasterAddr No - Yes - Validate source (master)
Yes address
MasterIP-Addr 0 - 18 1 0.0.0.0 - Master IP-address
MasterIPNetMsk 0 - 18 1 255.255.255.255 - Master IP net mask
Obj1DefVar 1:BISingleBit - 1:BISingleBit - Object 1, default variation
2:BIWithStatus
Obj2DefVar 1:BIChWithout- - 3:BIChWithRel- - Object 2, default variation
Time Time
2:BIChWithTime
3:BIChWithRel-
Time
Obj4DefVar 1:DIChWithout- - 3:DIChWithRel- - Object 4, default variation
Time Time
2:DIChWithTime
3:DIChWithRel-
Time
870
Automation bits (AUBI) Chapter 16
Station communication
Table 512: Advanced general settings for the DNP3Mast3TCPIP (DNM3-) function
Parameter Range Step Default Unit Description
AddrQueryEnbl No - Yes - Address query enable
Yes
tApplConfTout 0.00 - 60.00 0.01 10.00 s Application layer confim
timeout
ApplMultFrgRes No - Yes - Enable application for
Yes multiple fragment
response
ConfMultFrag No - Yes - Confirm each multiple
Yes fragment
UREnable No - Yes - Unsolicited response
Yes enabled
URSendOnline No - No - Unsolicited response
Yes sends when on-line
871
Automation bits (AUBI) Chapter 16
Station communication
872
Automation bits (AUBI) Chapter 16
Station communication
Table 513: Basic general settings for the DNP3Mast4TCPIP (DNM4-) function
Parameter Range Step Default Unit Description
Operation Off - Off - Operation Off / On
ON
SlaveAddress 0 - 65519 1 1 - Slave address
MasterAddres 0 - 65519 1 1 - Master address
ValMasterAddr No - Yes - Validate source (master)
Yes address
MasterIP-Addr 0 - 18 1 0.0.0.0 - Master IP-address
MasterIPNetMsk 0 - 18 1 255.255.255.255 - Master IP net mask
Obj1DefVar 1:BISingleBit - 1:BISingleBit - Object 1, default variation
2:BIWithStatus
Obj2DefVar 1:BIChWithout- - 3:BIChWithRel- - Object 2, default variation
Time Time
2:BIChWithTime
3:BIChWithRel-
Time
Obj4DefVar 1:DIChWithout- - 3:DIChWithRel- - Object 4, default variation
Time Time
2:DIChWithTime
3:DIChWithRel-
Time
873
Automation bits (AUBI) Chapter 16
Station communication
Table 514: Advanced general settings for the DNP3Mast4TCPIP (DNM4-) function
Parameter Range Step Default Unit Description
AddrQueryEnbl No - Yes - Address query enable
Yes
tApplConfTout 0.00 - 60.00 0.01 10.00 s Application layer confim
timeout
ApplMultFrgRes No - Yes - Enable application for
Yes multiple fragment
response
ConfMultFrag No - Yes - Confirm each multiple
Yes fragment
UREnable No - Yes - Unsolicited response
Yes enabled
URSendOnline No - No - Unsolicited response
Yes sends when on-line
874
Automation bits (AUBI) Chapter 16
Station communication
875
Automation bits (AUBI) Chapter 16
Station communication
876
Single command, 16 signals (CD) Chapter 16
Station communication
7.1 Introduction
The IEDs can receive commands either from a substation automation system or from the local
human-machine interface, LHMI. The command function block has outputs that can be used, for
example, to control high voltage apparatuses or for other user defined functionality.
The output signals can be of the types Off, Steady, or Pulse. This configuration setting is done
via the LHMI or PCM 600 and is common for the whole function block. The length of the output
pulses are 100 ms. In steady mode the function block has a memory to remember the output val-
ues at power interruption of the IED. Also a BLOCK input is available used to block the updat-
ing of the outputs.
The output signals, here OUT1 to OUT16, are then available for configuration to built-in func-
tions or via the configuration logic circuits to the binary outputs of the IED.
CD01-
SingleCmd
BLOCK OUT1
NAME1 OUT2
NAME2 OUT3
NAME3 OUT4
NAME4 OUT5
NAME5 OUT6
NAME6 OUT7
NAME7 OUT8
NAME8 OUT9
NAME9 OUT10
NAME10 OUT11
NAME11 OUT12
NAME12 OUT13
NAME13 OUT14
NAME14 OUT15
NAME15 OUT16
NAME16
en05000698.vsd
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Single command, 16 signals (CD) Chapter 16
Station communication
Table 516: Output signals for the SingleCmd (CD01-) function block
Signal Description
OUT1 Single command output 1
OUT2 Single command output 2
OUT3 Single command output 3
OUT4 Single command output 4
OUT5 Single command output 5
OUT6 Single command output 6
OUT7 Single command output 7
OUT8 Single command output 8
OUT9 Single command output 9
OUT10 Single command output 10
OUT11 Single command output 11
OUT12 Single command output 12
OUT13 Single command output 13
OUT14 Single command output 14
OUT15 Single command output 15
OUT16 Single command output 16
878
Multiple command (CM) and Multiple transmit Chapter 16
(MT) Station communication
8.1 Introduction
The IED may be provided with a function to send and receive signals to and from other IEDs via
the interbay bus. The send and receive function blocks has 16 outputs/inputs that can be used,
together with the configuration logic circuits, for control purposes within the IED or via binary
outputs. When it is used to communicate with other IEDs, these IEDs have a corresponding Mul-
tiple transmit function block with 16 outputs to send the information received by the command
block.
Sixteen signals can be connected and they will then be sent to the multiple command block in
the other IED. The connections are set with the LON Network Tool (LNT).
Twelve multiple command function block CM12 with fast execution time and 48 multiple com-
mand function blocks CM13-CM60 with slower execution time are available in the IED 670s.
The multiple command function block has 16 outputs combined in one block, which can be con-
trolled from other IEDs.
The output signals, here OUT1 to OUT16, are then available for configuration to built-in func-
tions or via the configuration logic circuits to the binary outputs of the terminal.
The command function also has a supervision function, which sets the output VALID to 0 if the
block did not receive data within set maximum time.
8.3 Design
8.3.1 General
The output signals can be of the types Off, Steady, or Pulse. The setting is done on the MODE
settings, common for the whole block, from the PCM 600 setting tool.
0 = Off sets all outputs to 0, independent of the values sent from the station level,
that is, the operator station or remote-control gateway.
1 = Steady sets the outputs to a steady signal 0 or 1, depending on the values sent
from the station level.
2 = Pulse gives a pulse with one execution cycle duration, if a value sent from the
station level is changed from 0 to 1. That means that the configured logic con-
nected to the command function blocks may not have a cycle time longer than the
execution cycle time for the command function block.
879
Multiple command (CM) and Multiple transmit Chapter 16
(MT) Station communication
CM01-
MultiCmd
BLOCK ERROR
NEWDATA
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
OUTPUT9
OUTPUT10
OUTPUT11
OUTPUT12
OUTPUT13
OUTPUT14
OUTPUT15
OUTPUT16
VALID
en06000007.vsd
MT01-
MultiTransm
BLOCK ERROR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
en06000008.vsd
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Multiple command (CM) and Multiple transmit Chapter 16
(MT) Station communication
Table 519: Input signals for the MultiTransm (MT01-) function block
Signal Description
BLOCK Block of function
INPUT1 Input 1
INPUT2 Input 2
INPUT3 Input 3
INPUT4 Input 4
INPUT5 Input 5
INPUT6 Input 6
INPUT7 Input 7
INPUT8 Input 8
INPUT9 Input 9
INPUT10 Input 10
INPUT11 Input 11
INPUT12 Input 12
INPUT13 Input 13
INPUT14 Input 14
INPUT15 Input 15
INPUT16 Input 16
Table 520: Output signals for the MultiCmd (CM01-) function block
Signal Description
ERROR MultiReceive error
NEWDATA New data is received
OUTPUT1 Output 1
OUTPUT2 Output 2
OUTPUT3 Output 3
OUTPUT4 Output 4
OUTPUT5 Output 5
OUTPUT6 Output 6
OUTPUT7 Output 7
OUTPUT8 Output 8
OUTPUT9 Output 9
OUTPUT10 Output 10
OUTPUT11 Output 11
OUTPUT12 Output 12
881
Multiple command (CM) and Multiple transmit Chapter 16
(MT) Station communication
Signal Description
OUTPUT13 Output 13
OUTPUT14 Output 14
OUTPUT15 Output 15
OUTPUT16 Output 16
VALID Output data is valid
Table 521: Output signals for the MultiTransm (MT01-) function block
Signal Description
ERROR MultiSend error
882
About this chapter Chapter 17
Remote communication
Chapter 17 Remote
communication
883
Binary signal transfer to remote end Chapter 17
Remote communication
1.1 Introduction
The remote end data communication is used either for the transmission of current values togeth-
er with maximum 8 binary signals in the line differential protection in RED670, or for transmis-
sion of only binary signals, up to 192 signals, in the other 600 series IEDs. The binary signals
are freely configurable and can thus be used for any purpose e.g. communication scheme related
signals, transfer trip and/or other binary signals between IEDs.
Communication between two IEDs requires that each IED is equipped with an LDCMs (Line
Data Communication Module). The LDCMs are then interfaces to a 64 kbit/s communication
channel for duplex communication between the IEDs.
Each IED can be equipped with up to four LDCMs, thus enabling communication with four re-
mote IEDs.
Start Stop
Information CRC
flag flag
884
Binary signal transfer to remote end Chapter 17
Remote communication
The start and stop flags are the 0111 1110 sequence (7E hexadecimal), defined in the HDLC
standard. The CRC is designed according to the standard CRC16 definition. The optional ad-
dress field in the HDLC frame is not used instead a separate addressing is included in the data
field.
The address field is used for checking that the received message originates from the correct
equipment. There is always a risk that multiplexers occasionally mix the messages up. Each ter-
minal in the system is given a number. The terminal is then programmed to accept messages
from a specific terminal number. If the CRC function detects a faulty message, the message is
thrown away and not used in the evaluation.
When the communication is used for line differential purpose, the transmitted data consists of
three currents, clock information, trip-, block- and alarm-signals and eight binary signals which
can be used for any purpose. The three currents are represented as sampled values.
When the communication is used exclusively for binary signals, the full data capacity of the
communication channel is used for the binary signal purpose which gives the capacity of
192 signals.
Note!
The function blocks are not represented in CAP 531 configuration tool. The signals appear only
in the SMT tool when a LDCM is included in the configuration with the function selector tool.
In the SMT tool they can be mapped to the desired virtual input (SMBI) of the IED670 and used
internally in the configuration.
885
Binary signal transfer to remote end Chapter 17
Remote communication
CRM1-
LDCMRecBinStat
COMFAIL
YBIT
NOCARR
NOMESS
ADDRERR
LNGTHERR
CRCERROR
TRDELERR
SYNCERR
REMCOMF
REMGPSER
SUBSTITU
LOWLEVEL
en07000043.vsd
CRM2-
LDCMRecBinStat
COMFAIL
YBIT
NOCARR
NOMESS
ADDRERR
LNGTHERR
CRCERROR
TRDELERR
SYNCERR
REMCOMF
REMGPSER
SUBSTITU
LOWLEVEL
en07000044.vsd
CRB1-
LDCMRecBinStat
COMFAIL
YBIT
NOCARR
NOMESS
ADDRERR
LNGT HERR
CRCERROR
REMCOMF
LOWLEVEL
en05000451.vsd
886
Binary signal transfer to remote end Chapter 17
Remote communication
Table 525: Output signals for the LDCMRecBinStat (CRM2-) function block
Signal Description
COMFAIL Detected error in the differential communication
YBIT Detected error in remote end with incoming message
NOCARR No carrier is detected in the incoming message
NOMESS No start and stop flags identified for the incoming message
ADDRERR Incoming message from a wrong terminal
LNGTHERR Wrong length of the incoming message
CRCERROR Identified error by CRC check in incoming message
TRDELERR Transmission time is longer than permitted
SYNCERR Indicates when echo synchronication is used
REMCOMF Remote terminal indicates problem with received message
REMGPSER Remote terminal indicates problem with GPS synchronization
SUBSTITU Link error, values are substituted
LOWLEVEL Low signal level on the receive link
887
Binary signal transfer to remote end Chapter 17
Remote communication
Table 526: Output signals for the LDCMRecBinStat (CRB1-) function block
Signal Description
COMFAIL Detected error in the differential communication
YBIT Detected error in remote end with incoming message
NOCARR No carrier is detected in the incoming message
NOMESS No start and stop flags identified for the incoming message
ADDRERR Incoming message from a wrong terminal
LNGTHERR Wrong length of the incoming message
CRCERROR Identified error by CRC check in incoming message
REMCOMF Remote terminal indicates problem with received message
LOWLEVEL Low signal level on the receive link
888
Binary signal transfer to remote end Chapter 17
Remote communication
Table 528: Basic general settings for the LDCMRecBinStat (CRM2-) function
Parameter Range Step Default Unit Description
ChannelMode Off - ON - Channel mode of LDCM,
ON 0=OFF, 1=ON, 2=OutOf-
OutOfService Service
889
Binary signal transfer to remote end Chapter 17
Remote communication
890
Binary signal transfer to remote end Chapter 17
Remote communication
Table 529: Basic general settings for the LDCMRecBinStat (CRB1-) function
Parameter Range Step Default Unit Description
ChannelMode Off - On - Channel mode of LDCM,
On 0=OFF, 1=ON, 2=OutOf-
OutOfService Service
891
Binary signal transfer to remote end Chapter 17
Remote communication
892
About this chapter Chapter 18
Hardware
Chapter 18 Hardware
893
Overview Chapter 18
Hardware
1 Overview
xx04000458.eps
xx04000459.eps
894
Overview Chapter 18
Hardware
xx05000763.eps
895
Overview Chapter 18
Hardware
xx04000460.eps
xx04000461.eps
896
Overview Chapter 18
Hardware
897
Overview Chapter 18
Hardware
898
Overview Chapter 18
Hardware
899
Overview Chapter 18
Hardware
900
Overview Chapter 18
Hardware
901
Hardware modules Chapter 18
Hardware
2 Hardware modules
2.1 Overview
Table 535: Basic modules, always included
Module Description
Combined backplane module (CBM) A backplane PCB that carries all internal signals
between modules in an IED. Only the TRM is not con-
nected directly to this board.
Universal backplane module (UBM) A backplane PCB that forms part of the IED backplane
with connectors for TRM, ADM etc.
Power supply module (PSM) Including a regulated DC/DC converter that supplies
auxiliary voltage to all static circuits.
An internal fail alarm output is available.
Numerical module (NUM) Module for overall application control. All information is
processed or passed through this module, such as
configuration, settings and communication.
Local Human machine interface (LHMI) The module consists of LED:s, an LCD, a push button
keyboard and an ethernet connector used to connect a
PC to the IED.
Transformer input module (TRM) Transformer module that galvanically separates the
internal circuits from the VT and CT circuits. It has 12
analog inputs.
Analog digital conversion module (ADM) Slot mounted PCB with A/D conversion.
902
Hardware modules Chapter 18
Hardware
2.2.2 Functionality
The Compact PCI makes 3.3V or 5V signaling in the backplane possible. The CBM backplane
and connected modules are 5V PCI-compatible.
Some pins on the Compact PCI connector are connected to the CAN bus, to be able to commu-
nicate with CAN based modules.
If a modules self test discovers an error it informs other modules using the Internal Fail signal
IRF.
2.2.3 Design
There are two basic versions of the CBM:
Each PCI connector consists of 2 compact PCI receptacles. The euro connectors are connected
to the CAN bus and used for I/O modules and power supply.
903
Hardware modules Chapter 18
Hardware
1 2
en05000516.vsd
Pos Description
1 CAN slots
2 CPCI slots
1 2
en05000755.vsd
Pos Description
1 CAN slots
2 CPCI slots
904
Hardware modules Chapter 18
Hardware
en05000756.vsd
Pos Description
1 CBM
2.3.2 Functionality
The Universal Backplane Module connects the CT and VT analog signals from the transformer
input module to the analog digital converter module. The Numerical processing module (NUM)
is also connected to the UBM. The ethernet contact on the front panel as well as the internal eth-
ernet contacts are connected to the UBM which provides the signal path to the NUM board.
2.3.3 Design
It connects the Transformer input module (TRM) to the Analog digital conversion module
(ADM) and the Numerical module (NUM).
for IEDs with two TRM and two ADM. It has four 48 pin euro connectors and
one 96 pin euro connector, see figure 382
for IEDs with one TRM and one ADM. It has two 48 pin euro connectors and one
96 pin euro connector, see figure 383.
905
Hardware modules Chapter 18
Hardware
The 96 pin euro connector is used to connect the NUM board to the backplane. The 48 pin con-
nectors are used to connect the TRM and ADM.
TRM ADM
NUM
AD Data
X1 X2
X3 X4
RS485
X10 X10
Front Ethernet
LHMI connection
port
Ethernet X5
en05000489.vsd
en05000757.vsd
906
Hardware modules Chapter 18
Hardware
en05000758.vsd
en05000759.vsd
Pos Description
1 UBM
907
Hardware modules Chapter 18
Hardware
2.4.2 Design
There are two types of the power supply module. They are designed for different DC input volt-
age ranges see table 537. The power supply module contains a built-in, self-regulated DC/DC
converter that provides full isolation between the terminal and the external battery system.
Block diagram
Input connector
Power
Filter supply
Backplane connector
Supervision
99000516.vsd
908
Hardware modules Chapter 18
Hardware
For communication with high speed modules, e.g. analog input modules and high speed serial
interfaces, the NUM is equipped with a Compact PCI bus. The NUM is the compact PCI system
card i.e. it controls bus mastering, clock distribution and receives interrupts.
2.5.2 Functionality
The NUM, Numeric processing module is a high performance, standard off-the-shelf com-
pact-PCI CPU module. It is 6U high and occupies one slot. Contact with the backplane is via
two compact PCI connectors and an euro connector.
The NUM has one PMC slot (32-bit IEEE P1386.1 compliant) and two PC-MIP slots onto which
mezzanine cards such as SLM or LDCM can be mounted.
To reduce bus loading of the compact PCI bus in the backplane the NUM has one internal PCI
bus for internal resources and the PMC/PC-MIP slots and external PCI accesses through the
backplane are buffered in a PCI/PCI bridge.
The application code and configuration data are stored in flash memory using a flash file system.
The NUM is equipped with a real time clock. It uses a capacitor for power backup of the real
time clock.
No forced cooling is used on this standard module because of the low power dissipation.
909
Hardware modules Chapter 18
Hardware
Compact
Flash Logic
PMC
connector
PC-MIP
connector
UBM
Memory Ethernet
North
bridge
Backplane
connector
PCI-PCI-
bridge
CPU
en04000473.vsd
910
Hardware modules Chapter 18
Hardware
2.7.2 Design
The transformer module has 12 input transformers. There are several versions of the module,
each with a different combination of voltage and current input transformers.
Basic versions:
The TRM is connected to the ADM and NUM via the UBM.
Configuration of the input and output signals, please refer to section 11.
911
Hardware modules Chapter 18
Hardware
2.8.2 Design
The Analog digital conversion module input signals are voltage and current from the transformer
module. Shunts are used to adapt the current signals to the electronic voltage level. To gain dy-
namic range for the current inputs, two shunts with separate A\D channels are used for each in-
put current. In this way a 20 bit dynamic range is obtained with a 16 bit A\D converter.
Input signals are sampled with a sampling freqency of 5 kHz at 50 Hz system frequency and 6
kHz at 60 Hz system frequency.
The A\D converted signals goes through a filter with a cut off frequency of 500 Hz and are re-
ported to the numerical module (NUM) with 1 kHz at 50 Hz system frequency and 1,2 kHz at
60 Hz system frequency.
912
Hardware modules Chapter 18
Hardware
Channel 1
AD1 Channel 2
Channel 3
Channel 4
AD2
Channel 5
1.2v Channel 6
AD3 Channel 7
Channel 8
Channel 9
AD4 Channel 10
Channel 11
Channel 12
PMC
level shift
PC-MIP
2.5v
PCI to PCI
PC-MIP
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Hardware modules Chapter 18
Hardware
2.9.2 Design
The Binary input module contains 16 optical isolated binary inputs. The voltage level of the bi-
nary input is selected at order.
A signal discriminator detects and blocks oscillating signals. When blocked, a hysteresis func-
tion may be set to release the input at a chosen frequency, making it possible to use the input for
pulse counting. The blocking frequency may also be set.
Figure 388 shows the operating characteristics of the binary inputs of the four voltage levels.
The standard version of binary inputs gives an improved capability to withstand disturbances
and should generally be used when pulse counting is not required.
914
Hardware modules Chapter 18
Hardware
[V]
300
176
144
88
72
38
32
19
18
xx06000391.vsd
Guaranteed operation
Operation uncertain
No operation
This binary input module communicates with the Numerical module (NUM) via the CAN-bus
on the backplane.
The design of all binary inputs enables the burn off of the oxide of the relay contact connected
to the input, despite the low, steady-state power consumption, which is shown in figure 389 and
390.
915
Hardware modules Chapter 18
Hardware
[mA]
30
1
35 70 [ms]
en07000104.vsd
Figure 389: Approximate binary input inrush current for the standard version of BIM.
[mA]
30
1
3.5 7.0 [ms]
en07000105.vsd
Figure 390: Approximate binary input inrush current for the BIM version with enhanced pulse
counting capabilities.
916
Hardware modules Chapter 18
Hardware
Process connector
Opto isolated input
Backplane connector
Opto isolated input
Process connector
99000503.vsd
917
Hardware modules Chapter 18
Hardware
Table 541: BIM - Binary input module with enhanced pulse counting capabilities
Quantity Rated value Nominal range
Binary inputs 16 -
DC voltage, RL 24/40 V RL 20%
48/60 V RL 20%
110/125 V RL 20%
220/250 V RL 20%
Power consumption
24/40 V max. 0.05 W/input -
48/60 V max. 0.1 W/input
110/125 V max. 0.2 W/input
220/250 V max. 0.4 W/input
Counter input frequency 10 pulses/s max -
Balanced counter input frequency 40 pulses/s max -
Oscillating signal discriminator Blocking settable 140 Hz
Release settable 130 Hz
918
Hardware modules Chapter 18
Hardware
2.10.2 Design
The binary output module (BOM) has 24 software supervised output relays. Each pair of relays
have a common power source input to the contacts, see figure 392. This should be considered
when connecting the wiring to the connection terminal on the back of the IED.
The high closing and carrying current capability allows connection directly to breaker trip and
closing coils. If breaking capability is required to manage fail of the breaker auxiliary contacts
normally breaking the trip coil current, a parallel reinforcement is required.
Output module
xx00000299.vsd
919
Hardware modules Chapter 18
Hardware
Relay
Relay
Relay
Relay
Relay
Process connector Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Backplane connector
Process connector
Relay Micro-
controller
Relay
Relay
CAN
Relay
Relay Memory
Relay
Relay
99000505.vsd
920
Hardware modules Chapter 18
Hardware
2.11.2 Design
The Static output module (SOM) have 6 normally open (NO) static outputs and 6 electrome-
chanical relay outputs with change over contacts.
An MCU
A CAN-driver
6 static relays outputs
6 electromechanical relay outputs
A DC/DC converter
Connectors interfacing
- CAN-bus to backplane CBM
- IO-connectors to binary outputs (2 pcs.)
921
Hardware modules Chapter 18
Hardware
Drive &
Read back
Drive &
Read back
Process connector
Drive &
Read back
Drive &
Read back
Drive &
Read back
MCU
CAN-
driver
Drive &
Read back
Drive &
Read back
Process connector
Backplane connector
DC/DC
Drive &
Read back
Internal_fail_n
Drive & AC_fail_n
Read back RCAN_ID
Sync
Drive &
Read back
Reset
Drive &
Read back
en07000115.vsd
922
Hardware modules Chapter 18
Hardware
923
Hardware modules Chapter 18
Hardware
2.12.2 Design
The binary input/output module is available in two basic versions, one with unprotected contacts
and one with MOV (Metal Oxide Varistor) protected contacts.
Inputs are designed to allow oxide burn-off from connected contacts, and increase the distur-
bance immunity during normal protection operate times. This is achieved with a high peak in-
rush current while having a low steady-state current, see figure 389. Inputs are debounced by
software.
Well defined input high and input low voltages ensures normal operation at battery supply earth
faults, see figure 388.
I/O events are time stamped locally on each module for minimum time deviance and stored by
the event recorder if present.
924
Hardware modules Chapter 18
Hardware
The binary I/O module, IOM, has eight optically isolated inputs and ten output relays. One of
the outputs has a change-over contact. The nine remaining output contacts are connected in two
groups. One group has five contacts with a common and the other group has four contacts with
a common, to be used as single-output channels, see figure 396.
The binary I/O module also has two high speed output channels where a reed relay is connected
in parallel to the standard output relay.
For configuration of the input and output signals, please refer to section 8 "Signal matrix for bi-
nary inputs (SMBI)" and section 9 "Signal matrix for binary outputs (SMBO)".
Note!
The making capacity of the reed relays are limited.
925
Hardware modules Chapter 18
Hardware
Figure 396: Binary in/out module (IOM), input contacts named XA corresponds to rear posi-
tion X31, X41, etc. and output contacts named XB to rear position X32, X42, etc.
Note!
The test voltage across open contact is lower for this version of the binary input/output module.
926
Hardware modules Chapter 18
Hardware
xx04000069.vsd
927
Hardware modules Chapter 18
Hardware
Function or quantity Trip and signal relays Fast signal relays (parallel reed
relay)
Current carrying capacity
Continuous 8A 8A
1s 10 A 10 A
Making capacity at inductive load
with L/R>10 ms
0.2 s
30 A 0.4 A
1.0 s 10 A 0.4 A
Breaking capacity for AC, 250 V/8.0 A 250 V/8.0 A
cos > 0.4
Breaking capacity for DC with L/R 48 V/1 A 48 V/1 A
< 40 ms
110 V/0.4 A 110 V/0.4 A
125 V/0.35 A 125 V/0.35 A
220 V/0.2 A 220 V/0.2 A
250 V/0.15 A 250 V/0.15 A
Maximum capacitive load - 10 nF
Table 546: IOM with MOV - contact data (reference standard: IEC 60255-23)
Function or quantity Trip and Signal relays Fast signal relays (parallel reed
relay)
Binary outputs IOM: 10 IOM: 2
Max system voltage 250 V AC, DC 250 V AC, DC
Test voltage across open contact, 250 V rms 250 V DC
1 min
Current carrying capacity
Continuous 8A 8A
1s 10 A 10 A
Making capacity at inductive load-
with L/R>10 ms
0.2 s
30 A 0.4 A
1.0 s 10 A 0.4 A
Breaking capacity for AC, cos 250 V/8.0 A 250 V/8.0 A
>0.4
Breaking capacity for DC with L/R 48 V/1 A 48 V/1 A
< 40 ms
110 V/0.4 A 110 V/0.4 A
220 V/0.2 A 220 V/0.2 A
250 V/0.15 A 250 V/0.15 A
Maximum capacitive load - 10 nF
928
Hardware modules Chapter 18
Hardware
The line data communication module is used for binary signal transfer. The module has one op-
tical port with ST connectors see figure 398.
The line data communication module is used for binary signal transfer. Each module has one
optical port, one for each remote end to which the IED communicates.
Alternative cards for Medium range (1310 nm single mode) and Short range (900 nm multi
mode) are available.
Note!
Class 1 laser product. Take adequate measures to protect the eyes. Never look into the laser
beam.
2.13.2 Design
The LDCM is a PCMIP type II single width format module. The LDCM can be mounted on:
the ADM
the NUM
ID
ST
16.000
IO-connector
MHz
32,768
MHz
ST
en07000087.vsd
Figure 398: The SR-LDCM layout. PCMIP type II single width format with two PCI connectors
and one I/O ST type connector
929
Hardware modules Chapter 18
Hardware
X1
C
ADN 2.5V
ID
2841
PCI9054
FPGA TQ176
DS DS
256 FBGA
3904 3904
MAX
3645
3
2
en06000393.vsd
Figure 399: The MR-LDCM and LR-LDCM layout. PCMIP type II single width format with
two PCI connectors and one I/O FC type connector
930
Hardware modules Chapter 18
Hardware
2.14.2 Design
The SLM is a PMC card and it is factory mounted as a mezzanine card on the NUM module.
Three variants of the SLM is available with different combinations of optical fiber connectors,
see figure 400. The plastic fiber connectors are of snap-in type and the glass fiber connectors are
of ST type.
931
Hardware modules Chapter 18
Hardware
932
Hardware modules Chapter 18
Hardware
1 Receiver, LON
2 Transmitter, LON
3 Receiver, SPA/IEC 60870-5-103
4 Transmitter, SPA/IEC 60870-5-103
933
Hardware modules Chapter 18
Hardware
2.15.2 Design
The RS485 is a PMC card and it is factory mounted as a mezzanine card on the NUM module.
The internal structure of the RS485 can be seen in figure 402:
FPGA
32 MHz
Wishbone interconnect switch
Tx
PCI-con
Isolation
Internal UART RS485 6-pole-connector
bus tranceiver
PCI-bus Rx
Local bus Isolation
PCI-
to
Controller
wishbone
PCI-con
Isolation
Status
Register Termination
connector
Info
2-pole
Register
Control
ID-chip
Register Isolated Soft
DC/DC ground
934
Hardware modules Chapter 18
Hardware
Angle
bracket
Screw
1
terminal
X3 2
1
2 RS485
3 PWB
Screw
4
terminal
5
X1
6
Backplane
Soft grounded: The IO is connected to the GND with an RC net parallel with a
MOV
935
Hardware modules Chapter 18
Hardware
2.16.2 Functionality
The Optical Ethernet module (OEM) is used when communication systems according to
IEC6185081 have been implemented.
2.16.3 Design
The Optical Ethernet module (OEM) is a PMC card and mounted as a mezzanine card on the
ADM. The OEM is a 100base Fx module and available as a single channel or double channel
unit.
100Base-FX
Transmitter
ID chip ST fiber optic
Ethernet Controller
connectors
100Base-FX
EEPROM
IO - bus Connector Receiver
en04000472.vsd
936
Hardware modules Chapter 18
Hardware
ID chip
Receiver
IO bus
LED
Ethernet cont.
25MHz oscillator
Transmitter
Receiver
PCI bus
LED
Ethernet cont. PCI to PCI
bridge
25MHz oscillator
Transmitter
en05000472.vsd
2.17.2 Design
The Milliampere Input Module has six independent analog channels with separated protection,
filtering, reference, A/D-conversion and optical isolation for each input making them galvani-
cally isolated from each other and from the rest of the module.
The analog inputs measure DC current in the range of +/- 20 mA. The A/D converter has a digital
filter with selectable filter frequency. All inputs are calibrated separately The filter parameters
and the calibration factors are stored in a non-volatile memory on the module.
937
Hardware modules Chapter 18
Hardware
The calibration circuitry monitors the module temperature and starts an automatical calibration
procedure if the temperature drift is outside the allowed range. The module communicates, like
the other I/O-modules on the serial CAN-bus.
Backplane connector
A/D Converter Opto-
Protection isolation
& filter
Volt-ref DC/DC
CAN
Memory Micro-
controller
99000504.vsd
938
Hardware modules Chapter 18
Hardware
2.18.2 Design
The GPS time synchronization module is 6U high and occupies one slot. The slot closest to the
NUM shall always be used.
The CCM is a carrier board for the GCM mezzanine PMC card and GPS unit, see figure 408.
There is a cable between the external antenna input on the back of the GCM and the GPS-receiv-
er. This is a galvanic connection vulnerable to electro-magnetic interference. The connector is
shielded and directly attached to a grounded plate to reduce the risk. The second cable is a flat
cable that connects the GPS and the GCM. It is used for communication between the GCM and
the GPS-receiver. All communication between the GCM and the NUM is via the CAN-bus.
The CMPPS signal is sent from the GCM to the rest of the time system to provide 1s accuracy
at sampling level.
939
Hardware modules Chapter 18
Hardware
PMC
GPS GPS clock
GPS antenna receiver module
CMPPS
Backplane CAN
CAN
connector
controller CAN
en05000675.vsd
940
Hardware modules Chapter 18
Hardware
en07000086.vsd
1 GPS receiver
2 GPS Clock module (GCM)
3 CAN carrier module (CCM)
4 Antenna connector
Figure 408: A CCM with the GCM and GPS mounted with cables
941
Hardware modules Chapter 18
Hardware
2.19.2 Design
The antenna with a console for mounting on a horizontal or vertical flat surface or on an antenna
mast. See figure 409
942
Hardware modules Chapter 18
Hardware
1 6
4 7
xx04000155.vsd
where:
1 GPS antenna
2 TNC connector
3 Console, 78x150 mm
4 Mounting holes 5.5 mm
5 Tab for securing of antenna cable
6 Vertical mounting position
7 Horizontal mounting position
Always position the antenna and its console so that a continuous clear line-of-sight visibility to
all directions is obtained, preferably more than 75%. A minimum of 50% clear line-of-sight vis-
ibility is required for un-interrupted operation.
943
Hardware modules Chapter 18
Hardware
99001046.vsd
Antenna cable
Use a 50 ohm coaxial cable with a male TNC connector in the antenna end and a male SMA
connector in the receiver end to connect the antenna to GSM. Choose cable type and length so
that the total attenuation is max. 26 dB at 1.6 GHz.
Note!
Make sure that the antenna cable is not charged when connected to the antenna or to the receiver.
Short-circuit the end of the antenna cable with some metal device, when first connected to the
antenna. When the antenna is connected to the cable, connect the cable to the receiver. REx670
must be switched off when the antenna cable is connected.
944
Hardware modules Chapter 18
Hardware
2.20.2 Design
The IRIG-B module have two inputs. One input is for the IRIG-B that can handle both a
pulse-width modulated signal (also called unmodulated) and an amplitude modulated signal (al-
so called sine wave modulated). The other is an optical input type ST for PPS to synchronize the
time between several protections.
32 MHz FPGA
connector
PCI-con
OPTO_INPUT
ST-
PCI-bus
Registers
PCI-Controller
PCI-con
4 mm barrier
IRIG- IRIG_INPUT
connector
Amplitude
ID-chip Decoder
BNC-
modulator
Capture1 Isolated
ZXING
receiver
Zero-cross
Capture2 detector
MPPS
IO-con
PPS
TSU Isolated
DC/DC
CMPPS 5 to +- 12V
en06000303.vsd
Figure 411: IRIG-B block diagram
945
Hardware modules Chapter 18
Hardware
A1
DC//DC
ST
C
Y2
C
C
A1
C
O
T
3
2
O
en06000304.vsd
Figure 412: IRIG-B PC-MIP board with top left ST connector for PPS 820 nm multimode fibre
optic signal input and lower left BNC connector for IRIG-B signal input
946
Dimensions Chapter 18
Hardware
3 Dimensions
K
E
D F
A
C G J
B
H
xx04000448.vsd
xx04000464.vsd
Figure 413: Case without rear cover Figure 414: Case without rear cover with 19 rack
mounting kit
Case size A B C D E F G H J K
(mm)
6U, 1/2 x 19 265.9 223.7 201.1 252.9 205.7 190.5 203.7 - 187.6 -
6U, 3/4 x 19 265.9 336.0 201.1 252.9 318.0 190.5 316.0 - 187.6 -
6U, 1/1 x 19 265.9 448.3 201.1 252.9 430.3 190.5 428.3 465.1 187.6 482.6
The H and K dimensions are defined by the 19 rack mounting kit
947
Dimensions Chapter 18
Hardware
D F
J
G
B H xx05000502.vsd
C
xx05000501.vsd
xx05000503.vsd
Case size A B C D E F G H J K
(mm)
6U, 1/2 x 19 265.9 223.7 242.1 255.8 205.7 190.5 203.7 - 228.6 -
6U, 3/4 x 19 265.9 336.0 242.1 255.8 318.0 190.5 316.0 - 228.6 -
6U, 1/1 x 19 265.9 448.3 242.1 255.8 430.3 190.5 428.3 465.1 228.6 482.6
The H and K dimensions are defined by the 19 rack mounting kit.
948
Dimensions Chapter 18
Hardware
Case size A B C D E F G H J K
(inches)
6U, 1/2 x 19 10.47 8.81 9.53 10.07 8.10 7.50 8.02 - 9.00 -
6U, 3/4 x 19 10.47 13.23 9.53 10.07 12.52 7.50 12.4 - 9.00 -
6U, 1/1 x 19 10.47 17.65 9.53 10.07 16.86 7.50 16.86 18.31 9.00 19.00
The H and K dimensions are defined by the 19 rack mounting kit.
A C
E
D
xx04000465.vsd
949
Dimensions Chapter 18
Hardware
xx06000182.vsd
950
Dimensions Chapter 18
Hardware
D
B
E
F
C
xx05000505.vsd
951
Dimensions Chapter 18
Hardware
B
E
C
D
en04000471.vsd
952
Dimensions Chapter 18
Hardware
[1.48]
[6.97]
[4.02]
Dimension
mm [inches] xx06000232.eps
[7.50]
en06000234.eps
[inches]
Figure 423: Dimension drawing of a three phase high impedance resistor unit
953
Mounting alternatives Chapter 18
Hardware
4 Mounting alternatives
The flush mounting kit are utilized for IEDs of sizes: 1/2 x 19, 3/4 x 19 and 1/1 x 19 and are
also suitable for mounting of RHGS6, 6U 1/4 x 19 cases.
Note!
Flush mounting cannot be used for side-by-side mounted IEDs when IP54 class must be ful-
filled. Only IP20 class can be obtained when mounting two cases side-by-side in one (1) cut-out.
Note!
To obtain IP54 class protection, an additional factory mounted sealing must be ordered when
ordering the IED.
954
Mounting alternatives Chapter 18
Hardware
1
7
2
6
5
3
xx06000246.vsd
955
Mounting alternatives Chapter 18
Hardware
Note!
Please note that the separately ordered rack mounting kit for side-by-side mounted IEDs, or
IEDs together with RHGS cases, is to be selected so that the total size equals 19.
Note!
When mounting the mounting angles, be sure to use screws that follows the recommended di-
mensions. Using screws with other dimensions than the original may damage the PCBs inside
the IED.
956
Mounting alternatives Chapter 18
Hardware
1a
1b
xx04000452.vsd
Note!
When mounting the side plates, be sure to use screws that follows the recommended dimensions.
Using screws with other dimensions than the original may damage the PCBs inside the IED.
957
Mounting alternatives Chapter 18
Hardware
3
4
2
6
xx04000453.vsd
To reach the rear side of the IED, a free space of 80 mmis required on the unhinged side.
958
Mounting alternatives Chapter 18
Hardware
3
1
80 mm 2
en06000135.vsd
Figure 427: How to reach the connectors on the rear side of the IED.
Note!
When mounting the plates and the angles on the IED, be sure to use screws that follows the rec-
ommended dimensions. Using screws with other dimensions than the original may damage the
PCBs inside the IED.
959
Mounting alternatives Chapter 18
Hardware
2
1
xx04000456.vsd
960
Mounting alternatives Chapter 18
Hardware
1 2
1 2 1 2
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
5 5 5 5
6 6 6 6
7 7 7 7
8 8 8 8
xx06000180.vsd
Figure 429: IED 670 (1/2 x 19) mounted with a RHGS6 case containing a test switch module
equipped with only a test switch and a RX2 terminal base.
Note!
With side-by-side flush mounting installation, only IP class 20 is obtained. To reach IP class 54,
it is recommended to mount the IEDs separately. For cut out dimensions of separately mounted
IEDs, see section 4.1 "Flush mounting" on page 956.
Note!
When mounting the plates and the angles on the IED, be sure to use screws that follows the rec-
ommended dimensions. Using screws with other dimensions than the original may damage the
PCBs inside the IED.
Note!
Please contact factory for special add on plates for mounting FT switches on the side (for 1/2
19" case) or bottom of the relay.
961
Mounting alternatives Chapter 18
Hardware
1 2
xx06000181.vsd
Figure 430: Side-by-side flush mounting details (RHGS6 side-by-side with 1/2 x 19 IED).
962
Technical data Chapter 18
Hardware
5 Technical data
5.1 Enclosure
Table 557: Case
Material Steel sheet
Front plate Steel sheet profile with cut-out for HMI
Surface treatment Aluzink preplated steel
Finish Light grey (RAL 7035)
Table 558: Water and dust protection level according to IEC 60529
Front IP40 (IP54 with sealing strip)
Rear, sides, top and bot- IP20
tom
963
Technical data Chapter 18
Hardware
Note!
Because of limitations of space, when ring lug terminal is ordered for Binary I/O connections,
one blank slot is necessary between two adjacent IO cards. Please refer to the ordering particu-
lars for details.
964
Technical data Chapter 18
Hardware
965
Technical data Chapter 18
Hardware
966
About this chapter Chapter 19
Labels
Chapter 19 Labels
967
Different labels Chapter 19
Labels
1 Different labels
2
3
6
6 5
7
xx06000574.eps
968
Different labels Chapter 19
Labels
969
Different labels Chapter 19
Labels
4
en06000573.eps
1 Warning label
2 Caution label
3 Class 1 laser product label
4 Warning label
970
Chapter 20
Connection diagrams
Chapter 20 Connection
diagrams
This chapter includes diagrams of the IED with all slot, terminal block and optical connector
designations. It is a necessary guide when making electrical and optical connections to the IED.
971
Chapter 20
Connection diagrams
972
Chapter 20
Connection diagrams
973
Chapter 20
Connection diagrams
974
Chapter 20
Connection diagrams
975
Chapter 20
Connection diagrams
976
Chapter 20
Connection diagrams
977
Chapter 20
Connection diagrams
978
Chapter 20
Connection diagrams
979
Chapter 20
Connection diagrams
980
Chapter 20
Connection diagrams
981
Chapter 20
Connection diagrams
982
Chapter 20
Connection diagrams
983
Chapter 20
Connection diagrams
984
Chapter 20
Connection diagrams
985
Chapter 20
Connection diagrams
986
About this chapter Chapter 21
Time inverse characteristics
987
Application Chapter 21
Time inverse characteristics
1 Application
In order to assure time selectivity between different overcurrent protections in different points
in the network different time delays for the different relays are normally used. The simplest way
to do this is to use definite time delay. In more sophisticated applications current dependent time
characteristics are used. Both alternatives are shown in a simple application with three overcur-
rent protections connected in series.
Stage 3
Time
Stage 2 Stage 2
Fault point
position
en05000130.vsd
988
Application Chapter 21
Time inverse characteristics
Time
Fault point
position
en05000131.vsd
The inverse time characteristic makes it possible to minimize the fault clearance time and still
assure the selectivity between protections.
To assure selectivity between protections there must be a time margin between the operation
time of the protections. This required time margin is dependent of following factors, in a simple
case with two protections in series:
989
Application Chapter 21
Time inverse characteristics
A1 B1
Feeder
I> I>
Time axis
en05000132.vsd
where:
t=0 is The fault occurs
t=t1 is Protection B1 trips
t=t2 is Breaker at B1 opens
t=t3 is Protection A1 resets
In the case protection B1 shall operate without any intentional delay (instantaneous). When the
fault occurs the protections start to detect the fault current. After the time t1 the protection B1
send a trip signal to the circuit breaker. The protection A1 starts its delay timer at the same time,
with some deviation in time due to differences between the two protections. There is a possibility
that A1 will start before the trip is sent to the B1 circuit breaker.
At the time t2 the circuit breaker B1 has opened its primary contacts and thus the fault current is
interrupted. The breaker time (t2 - t1) can differ between different faults. The maximum opening
time can be given from manuals and test protocols. Still at t2 the timer of protection A1 is active.
In most applications it is required that the delay times shall reset as fast as possible when the
current fed to the protection drops below the set current level, the reset time shall be minimized.
In some applications it is however beneficial to have some type of delayed reset time of the over-
current function. This can be the case in the following applications:
If there is a risk of intermittent faults. If the current relay, close to the faults, starts
and resets there is a risk of unselective trip from other protections in the system.
Delayed resetting could give accelerated fault clearance in case of automatic re-
closing to a permanent fault.
990
Application Chapter 21
Time inverse characteristics
Overcurrent protection functions are sometimes used as release criterion for other
protection functions. It can often be valuable to have a reset delay to assure the
release function.
991
Principle of operation Chapter 21
Time inverse characteristics
2 Principle of operation
If current in any phase exceeds the set start current value (here internal signal startValue), a tim-
er, according to the selected operate mode, is started. The component always uses the maximum
of the three phase current values as the current level used in timing calculations.
In case of definite time the timer will run constantly until the trip time is reached or until the
current drops below the reset value (start value minus the hysteresis) and the reset time has
elapsed.
For definite time delay curve index no 5 (ANSI/IEEE Definite time) or 15 (IEC Definite time)
are chosen.
The general expression for inverse time curves is according to equation 105.
A
t[ s ] = + B k
i p
C
in >
(Equation 105)
where:
p, A, B, C are constants defined for each curve type,
in> is the set start current for step n,
k is set time multiplier for step n and
i is the measured current.
For inverse time characteristics a time will be initiated when the current reaches the set start lev-
el. From the general expression of the characteristic the following can be seen:
992
Principle of operation Chapter 21
Time inverse characteristics
i p
(top B k ) C = Ak
in >
(Equation 106)
where:
top is the operation time of the protection
The time elapsed to the moment of trip is reached when the integral fulfils according to
equation 107, in addition to the constant time delay:
t
i p
in > C dt A k
0
(Equation 107)
For the numerical protection the sum below must fulfil the equation for trip.
n i( j ) p
t C A k
j =1 in >
(Equation 108)
where:
j=1 is the first protection execution cycle when a fault has been detected, i.e. when
i
>1
in >
t is the time interval between two consecutive executions of the protection algorithm,
n is the number of the execution of the algorithm when the trip time equation is fulfilled, i.e.
when a trip is given and
i (j) is the fault current at time j
For inverse time operation, the inverse-time characteristic is selectable. Both the IEC and AN-
SI/IEEE standardized inverse-time characteristics are supported. The list of characteristics in
table 570 matches the list in the IEC 61850-7-4 spec.
993
Principle of operation Chapter 21
Time inverse characteristics
For the ANSI/IEEE characteristics the inverse time curves are defined according to table 571:
For the IEC characteristics the inverse time curves are defined according to table 572:
994
Principle of operation Chapter 21
Time inverse characteristics
For the IEC curves there is also a setting of the minimum time delay of operation, see figure 435.
Operate
time
tnMin
Current
en05000133.vsd
Figure 435: Minimum time delay operation for the IEC curves
In order to fully comply with IEC curves definition setting parameter tMin shall be set to the
value which is equal to the operating time of the selected IEC inverse curve for measured current
of twenty times the set current pickup value. Note that the operating time value is dependent on
the selected setting value for time multiplier k.
In addition to the ANSI and IEC standardized characteristics, there are also two additional
curves available; the 18 = RI time inverse and the 19 = RD time inverse.
The 18 = RI time inverse curve emulates the characteristic of the electromechanical ASEA relay
RI. The curve is described by equation 109:
995
Principle of operation Chapter 21
Time inverse characteristics
k
t[ s ] =
in >
0.339 0.235
i
(Equation 109)
where:
in> is the set start current for step n,
k is set time multiplier for step n and
i is the measured current.
The 19 = RD time inverse curve gives a logarithmic delay, as used in the Combiflex protection
RXIDG. The curve enables a high degree of selectivity required for sensitive residual earth fault
current protection, with ability to detect high resistive earth faults. The curve is described by
equation 110:
i
t[ s ] = 5.8 1.35 ln
k in >
(Equation 110)
where:
in> is the set start current for step n,
k is set time multiplier for step n and
i is the measured current
If the curve type is chosen as 17 the user can make a tailor made inverse time curve according
to the general equation 111.
A
t[ s ] = + B k
i p
C
in >
(Equation 111)
Also the reset time of the delayed function can be controlled. We have the possibility to choose
between three different reset type delays. Available alternatives are listed in table 573.
996
Principle of operation Chapter 21
Time inverse characteristics
If instantaneous reset is chosen the timer will be reset directly when the current drops below the
set start current level minus the hysteresis.
If IEC reset is chosen the timer is reset the timer will be reset after a set constant time when the
current drops below the set start current level minus the hysteresis.
If ANSI reset time is chosen the reset time will be dependent of the current after fault clearance
(when the current drops below the start current level minus the hysteresis). The timer will reset
according to equation 112.
tr
t[ s ] =
i 2
1
in >
(Equation 112)
where:
The set value tr is the reset time in case of zero current after fault clearance.
The possibility of choice of reset characteristics is to some extent dependent of the choice of time
delay characteristic.
For the independent time delay characteristics (type 5 and 15) the possible delay time settings
are instantaneous (1) and IEC (2 = set constant time reset).
For ANSI inverse time delay characteristics (type 1 - 4 and 6 - 8) all three types of reset time
characteristics are available; instantaneous (1), IEC (2 = set constant time reset) and ANSI (3 =
current dependent reset time).
For IEC inverse time delay characteristics (type 9 - 14) the possible delay time settings are in-
stantaneous (1) and IEC (2 = set constant time reset).
For the customer tailor made inverse time delay characteristics (type 17) all three types of reset
time characteristics are available; instantaneous (1), IEC (2 = set constant time reset) and ANSI
(3 = current dependent reset time). If the current dependent type is used settings pr, tr and cr must
be given, see equation 113:
997
Principle of operation Chapter 21
Time inverse characteristics
tr
t[ s ] =
i pr
cr
in >
(Equation 113)
For RI and RD inverse time delay characteristics (type 18 and 19) the possible delay time set-
tings are instantaneous (1) and IEC (2 = set constant time reset).
998
Inverse characteristics Chapter 21
Time inverse characteristics
3 Inverse characteristics
Table 574: Inverse time characteristics ANSI
Function Range or value Accuracy
Operate characteristic: k = 0.05-999 in steps of -
0.01 unless otherwise
stated
A
t = P + B k
( I 1)
Reset characteristic:
tr
t = k
(I 2
1 )
I = Imeasured/Iset
ANSI Extremely Inverse no 1 A=28.2, B=0.1217, P=2.0, ANSI/IEEE C37.112, class 5 +
tr=29.1 30 ms
ANSI Very inverse no 2 A=19.61, B=0.491, P=2.0,
tr=21.6
ANSI Normal Inverse no 3 A=0.0086, B=0.0185,
P=0.02, tr=0.46
ANSI Moderately Inverse no 4 A=0.0515, B=0.1140,
P=0.02, tr=4.85
ANSI Long Time Extremely Inverse no 6 A=64.07, B=0.250, P=2.0,
tr=30
ANSI Long Time Very Inverse no 7 A=28.55, B=0.712, P=2.0,
tr=13.46
ANSI Long Time Inverse no 8 k=(0.01-1.20) in steps of
0.01
A=0.086, B=0.185,
P=0.02, tr=4.6
999
Inverse characteristics Chapter 21
Time inverse characteristics
A
t = P k
( I 1)
I = Imeasured/Iset
Time delay to reset, IEC inverse time (0.000-60.000) s 0.5% of set time 10 ms
IEC Normal Inverse no 9 A=0.14, P=0.02 IEC 60255-3, class 5 + 40 ms
IEC Very inverse no 10 A=13.5, P=1.0
IEC Inverse no 11 A=0.14, P=0.02
IEC Extremely inverse no 12 A=80.0, P=2.0
IEC Short-time inverse no 13 A=0.05, P=0.04
IEC Long-time inverse no 14 A=120, P=1.0
Customer defined characteristic no 17 k=0.5-999 in steps of 0.1 IEC 60255, class 5 + 40 ms
Operate characteristic: A=(0.005-200.000) in
steps of 0.001
B=(0.00-20.00) in steps of
A 0.01
= + B k
(I P C )
t
C=(0.1-10.0) in steps of
0.1
Reset characteristic:
P=(0.005-3.000) in steps of
0.001
TR TR=(0.005-100.000) in
t = k
(I )
PR steps of 0.001
CR
CR=(0.1-10.0) in steps of
I = Imeasured/Iset 0.1
PR=(0.005-3.000) in steps
of 0.001
RI inverse characteristic no 18 k=(0.05-999) in steps of IEC 60255-3, class 5 + 40 ms
0.01
1
t = k
0.236
0.339
I
I = Imeasured/Iset
Logarithmic inverse characteristic no 19 k=(0.05-1.10) in steps of IEC 60255-3, class 5 + 40 ms
0.01
t = 5.8 1.35 In
I
k
I = Imeasured/Iset
1000
Inverse characteristics Chapter 21
Time inverse characteristics
Table 576: Inverse time characteristics for Two step undervoltage protection (PUVM, 27)
Function Range or value Accuracy
Type A curve: k = (0.05-1.10) in steps of Class 5 +40 ms
0.01
k
t =
U < U
U<
U< = Uset
U = UVmeasured
Type B curve: k = (0.05-1.10) in steps of
0.01
k 480
t = + 0.055
32 U < U 0.5
2.0
U <
U< = Uset
U = Umeasured
Programmable curve: k = (0.05-1.10) in steps of
0.01
A = (0.005-200.000) in
steps of 0.001
kA
t = +D B = (0.50-100.00) in steps
U < U
P
of 0.01
B C C = (0.0-1.0) in steps of 0.1
U <
U< = Uset D = (0.000-60.000) in
steps of 0.001
U = Umeasured
P = (0.000-3.000) in steps
of 0.001
1001
Inverse characteristics Chapter 21
Time inverse characteristics
Table 577: Inverse time characteristics for Two step overvoltage protection (POVM, 59)
Function Range or value Accuracy
Type A curve: k = (0.05-1.10) in steps of Class 5 +40 ms
0.01
k
t =
U U >
U>
U> = Uset
U = Umeasured
Type B curve: k = (0.05-1.10) in steps of
0.01
k 480
t =
32 U U > 0.5
2.0
0.035
U >
Type C curve: k = (0.05-1.10) in steps of
0.01
k 480
t =
3.0
32 U U > 0.5
0.035
U >
Programmable curve: k = (0.05-1.10) in steps of
0.01
A = (0.005-200.000) in
kA steps of 0.001
t = +D
B U U >
P
B = (0.50-100.00) in steps
C
U > of 0.01
C = (0.0-1.0) in steps of 0.1
D = (0.000-60.000) in
steps of 0.001
P = (0.000-3.000) in steps
of 0.001
1002
Inverse characteristics Chapter 21
Time inverse characteristics
k
t =
U U >
U>
U> = Uset
U = Umeasured
Type B curve: k = (0.05-1.10) in steps of
0.01
k 480
t =
2.0
32 U U > 0.5
0.035
U >
Type C curve: k = (0.05-1.10) in steps of
0.01
k 480
t =
32 U U > 0.5
3.0
0.035
U >
Programmable curve: k = (0.05-1.10) in steps of
0.01
A = (0.005-200.000) in
kA steps of 0.001
t = +D
B U U >
P
B = (0.50-100.00) in steps
C
U > of 0.01
C = (0.0-1.0) in steps of 0.1
D = (0.000-60.000) in
steps of 0.001
P = (0.000-3.000) in steps
of 0.001
1003
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
k=
15
10
7
1
5
3
2
1
0.1
0.5
0.01
1 10 100 I/I>
xx05000764.vsd
1004
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
k=
15
10
1 7
5
3
2
1
0.1
0.5
0.01
1 10 100 I/I>
xx05000765.vsd
1005
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
k=
15
10
1 7
5
3
2
1
0.1
0.5
0.01
1 10 100 I/I>
xx05000766.vsd
1006
Inverse characteristics Chapter 21
Time inverse characteristics
100
k=
15
10
10
7
5
1
1
0.5
0.1
0.01
1 10 100 I/I>
xx05000767.vsd
1007
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
k=
1.1
0.9
0.7
1 0.5
0.3
0.2
0.1
0.1 0.05
0.01
1 10 100 I/I>
xx05000768.vsd
1008
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
1
k=
1.1
0.9
0.7
0.5
0.3
0.1 0.2
0.1
0.05
0.01
1 10 100 I/I>
xx05000769.vsd
1009
Inverse characteristics Chapter 21
Time inverse characteristics
100
10
k=
0.1 1.1
0.9
0.7
0.5
0.3
0.2
0.01 0.1
1 10 100 I/I>
0.05 xx05000770.vsd
1010
About this chapter Chapter 22
Glossary
Chapter 22 Glossary
1011
Glossary Chapter 22
Glossary
1 Glossary
AC Alternating current
AR Autoreclosing
ArgNegRes Setting parameter/ZD/
CAN Controller Area Network. ISO standard (ISO 11898) for serial communi-
cation
CAP 531 Configuration and programming tool
CB Circuit breaker
1012
Glossary Chapter 22
Glossary
Co-directional Way of transmitting G.703 over a balanced line. Involves two twisted
pairs making it possible to transmit information in both directions
CR Carrier receive
CT Current transformer
DC Direct current
1013
Glossary Chapter 22
Glossary
G.703 Electrical and functional description for digital lines used by local tele-
phone companies. Can be transported over balanced and unbalanced
lines
HDLC protocol High level data link control, protocol based on the HDLC standard
HFBR connector type Plastic fiber connector
HV High voltage
HVDC High voltage direct current
IEEE P1386.1 PCI Mezzanine card (PMC) standard for local bus modules. References
the CMC (IEEE P1386, also known as Common mezzanine card) stan-
dard for the mechanics and the PCI specifications from the PCI SIG
(Special Interest Group) for the electrical EMF Electro Motive Force.
IED Intelligent electronic device
1014
Glossary Chapter 22
Glossary
IP 1. Internet protocol. The network layer for the TCP/IP protocol suite
widely used on Ethernet networks. IP is a connectionless, best-effort
packet switching protocol. It provides packet routing, fragmentation and
re-assembly through the data link layer.
2. Ingression protection according to IEC standard
IP 20 Ingression protection, according to IEC standard, level 20
OV Over voltage
Overreach A term used to describe how the relay behaves during a fault condition.
For example a distance relay is over-reaching when the impedance pre-
sented to it is smaller than the apparent impedance to the fault applied
to the balance point, i.e. the set reach. The relay sees the fault but per-
haps it should not have seen it.
1015
Glossary Chapter 22
Glossary
Process bus Bus or LAN used at the process level, that is, in near proximity to the
measured and/or controlled components
SA Substation Automation
1016
Glossary Chapter 22
Glossary
TCP Transmission control protocol. The most common transport layer proto-
col used on Ethernet and the Internet.
TCP/IP Transmission control protocol over Internet Protocol. The de facto stan-
dard Ethernet protocols incorporated into 4.2BSD Unix. TCP/IP was
developed by DARPA for internet working and encompasses both net-
work layer and transport layer protocols. While TCP and IP specify two
protocols at specific protocol layers, TCP/IP is often used to refer to the
entire US Department of Defense protocol suite based upon these,
including Telnet, FTP, UDP and RDP.
Underreach A term used to describe how the relay behaves during a fault condition.
For example a distance relay is under-reaching when the impedance
presented to it is greater than the apparent impedance to the fault
applied to the balance point, i.e. the set reach. The relay does not see
the fault but perhaps it should have seen it. See also Overreach.
U/I-PISA Process interface components that deliver measured voltage and cur-
rent values
UTC Coordinated universal time. A coordinated time scale, maintained by the
Bureau International des Poids et Mesures (BIPM), which forms the
basis of a coordinated dissemination of standard frequencies and time
signals. UTC is derived from International Atomic Time (TAI) by the addi-
tion of a whole number of "leap seconds" to synchronize it with Universal
Time 1 (UT1), thus allowing for the eccentricity of the Earth"s orbit, the
rotational axis tilt (23.5 degrees), but still showing the Earth"s irregular
rotation, on which UT1 is based. The Coordinated Universal Time is
expressed using a 24-hour clock and uses the Gregorian calendar. It is
used for aeroplane and ship navigation, where it also sometimes known
by the military name, "Zulu time". "Zulu" in the phonetic alphabet stands
for "Z" which stands for longitude zero.
UV Undervoltage
VT Voltage transformer
X.21 A digital signalling interface primarily used for telecom equipment
1017
Glossary Chapter 22
Glossary
1018
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