The Signal & Power Integrity

(SI/PI) Solutions with HDI

Happy Holden

AGENDA
Q Introduction
Q Awareness of New HDI Materials
Q SI & PI Advantages with HDI
Q HDI Design Planning
Q Issues with HDI Fabricators
 New Processors-1366 pin
280 W turbo at 200 amps
3.2 GHz Clock
3 memory channels (DDR3) at 1.6 GHz but only 1.4 V

PDN Design Affects High-Freq Performance

The PDN impedance requirement may be

calculated using the following formula:
Zpdn = (% ripple * V) / Imax

where V is the rail voltage and Imax is the peak

current draw of the IC.
Impedance Ripple Voltage Currentmax
0.007 1.0% 1.4 200
Quad Core
0.035 5.0% 1.4 200
Awareness of New HDI Materials

Materials Comparison Chart

 Relative Material Types
Generic FR-4s

D-140 - DiCY cured, Tg 140 C Traditional Tetrafunctional Laminate

D-150 - DiCY cured, Tg 150 C Traditional Tetrafunctional Laminate
D-170 - DiCY cured, Tg 170 C Traditional Multifunctional Laminate

PN-150 - Phenolic cured, Tg 140 C Lead-Free Tetrafunctional Laminate

PN-170 - Phenolic cured Tg 170 C Lead-Free Multifunctional Laminate
PN-185 - Phenolic cured, Tg 185 C Lead-Free Multifunctional Laminate

HF-150 - DiCY cured, Tg 150 C Lead-Free & Halogen-Free Tetrafunctional Laminate

HF-170 - DiCY or Phenolic cured, Tg 170 C Lead-Free & HF Multifunctional Laminate
HF-185 - Phenolic cured, Tg 185 C Lead-Free & HF Multifunctional Laminate

Names In Laminates
NEW (<10 years)
OLD TIMERS (> 20 years) Korean:
European Doosan
ISOLA LG
American Kolon
Park Nelco Taiwan
Arlon ITEQ
Rogers Elite
Gore TUC
Taconic Leader
Polyclad HK/Chinese
Taiwan Grace
NanYa Plastics Kingboard
Japanese Sheng Yi
Matsushita (Panasonic) Chang Chun
Hitachi Holley
Mitsubishi Hiland
Sumitomo Meadville Tech Group
 Laser Drillable Prepregs
1080
106
1080 & 106 VS LDP

For Laser Drilling 106 (50X)
Solves 4 problems:
1. Fiber weave effect
2. Distributed
Capacitance
3. Laser drilled vias
4. Thin high-voltage
dielectrics
For Laser Drilling 1080 For Laser Drilling 1037 For Laser Drilling 2112 (50X)

As of 2008, now 10
For Laser Drill 1067 For Laser Drilling 1078 For Laser Drill 1086 For Laser Drilling 2113
LD prepregs

For Laser Drilling 2313 For Laser Drilling 2116

Traditional Laminates Around The World

 SI / PI Constraints with HDI

System Level Interconnect

Faster Speeds
Circuit Backplane Circuit
Lpower Board Board Lpower
Lpin Lcon Lcon Lpin
A B
Cpin Ccon Ccon Cpin
Lgnd
Lgnd
High Speed Electrical Path
Circuit
Board
B
A

pin
pin
con con
Backplane

source: DDI
 Harmonic Content vs Rise Time
Time Domain Frequency Domain

source: DDI

Four Families of SI Noise

Source: Eric Bogatin, "Signal Integrity and HDI Substrates",The Board Authority, Vol 1 no.2, June 1999
 Sources of Noise
Components to far apart
Very fast signal rise times
Change in trace width
Plane splits and Via antipads on planes
Cutouts in Power/Ground planes
Insufficient decoupling capacitors
Insufficient plane capabilities
Power rail collapse
Excessive stubs, branched or bifurcated traces
Component lead frames
Improper impedance matching and termination networks
Coupling between signals
Varying loads and logic families

Many of these are created by the layout of the board!

HDI Features and SI Problems They Help

Solve
Reduction of noise
Reflections
Crosstalk
Simultaneous switching
EMI/RFI reductions
Improved signal propagation and lower attenuation
Power supply coupling and reduced impedance

Signal Cross Switching EMI

HDI features quality talk Noise
Short interconnect lengths X X
Low dielectric constant X X
Small vias and small features X X
Vias in pads X
Fine lines and thin dielectric X X X
Power Coupled to Ground X X X
 Capacitive Loading: PTH
Multidrop Transmission Line
Hole barrel capacitance with
respect to planes (approximately
0.5 pf to 1.5 pf based on geometry)
~0.038 pf per plane layer

source: DDI

Capacitive Loading: X-Y Traces

y Thin dielectric layers increase
interlayercapacitance between signal Zo
Traces, but lower it to GND planes
Cm
Cm
y Impedance

Cx

Co
y Propogation Delay

Co= Distributed Capacitance (pf/in)

Cm Cx Cx= Crossover capacitance (pf)
Cl= Load capacitance (total Cx+Cv)
Co Cv= Via hole capacitance (pf)
Cm= Mutual capacitance (pf)
Signal Trace Tpd= Propagation delay (ps/in)
Cv Via hole Cv Cv Tpd'= Loaded propagation delay (ps/in)
Zo= Impedance (ohms)
Zo'= Loaded Impedance (ohms)

source: DDI
Conventional Laser Drilled Hole Geometry
Microvia 12 Buried via (epoxy filled)
Microvia 13 Drilled PTH

HDI Sequential HDI

BU Layers (+2) Dielectric
Layers

4 Layer
MLB
Core
Laser Drilled Microvia
L1 - L2

HDI Sequential
BU Layers (+2)

2+4+2 HDI Substrate

Aspect ratio on Microvias approximately 0.5:1max.
Laser Drilled Microvia
Microvia 1-> 3 require larger hole diameter L1 - L2 & L3
source: DDI

Capacitive Loading: HDI - Microvia

Multidrop Transmission Line
Microvia barrel capacitance
with respect to internal plane
is 0.038 pf

0.038 pf

source: DDI
 Problem With Through-Holes
Via Hole Inductance

Via length (GND) Via length (+5)

Ground +5v

Power plane
4h
L = 5.08 h ln +1
d
Ground plane

Where:
Power and Ground Connections
0.010dia L = Via inductance (nH)
h = Effective via length (in.)
2 0.025dia d = Via diameter (in.)
1.5 0.050dia
Inductance
(nH) 1
0.5

20 40 60 80 100
Length of via h (0.001)
source: DDI

Microvia Advantage
Stubless Nets
equivalent circuit for 'long' stub (conventional drilled via):

propagation delay t1 propagation delay t2

Vin Vout

stub = -1/3 for impedance equal on all

prop delay t3

three lines in the equiv.. circuit

voltage V Vin Net Settling Time

t1 + t2 + 2*t3 Vout
Vih min

(1+ ) * Vin
Transition Receiver
Region of
Thresholds
Receiver
t1 + t2
Vil max

time t
 Noise From Stubs (dB Loss)

Via Capacitance vs Cu Planes

COPYRIGHT 2007 Happy Holden

source: DDI
 Noise On Critical Nets

micro vias standard vias

Impedance steps: TDR measurement results

EMI Profile:
Through-Hole Vs. HDI Faraday Cage

FCC standard FCC standard

Good Good

Conventional (No GND shield) HDI (GND shield)

(source:Zissou Technology 1997-8)
 BGA Routing w/Microvias

Power Supply Impedance

Impedance vs Frequency
100
Power Supply Components
Im p e d a n c e (O h m s )

Wire inductance
10
power supply

Board level decoupling

capacitors
1
Distributed decoupling
capacitor

0.1 Integral P&G plane

capacitance

Buried capacitance
0.01
1.E-01 1.E+01 1.E+03 1.E+05 1.E+07 1.E+09
Frequency (MHz)
 HDI Power and Ground

0.002
Low Inductance Through hole signal via
microvia (0.030 nH)
Ground plane

Power plane

Laminate based
MLB core
Epoxy resin
(er = 3.4 3.6)

Thin HDI dielectric layer produces approximately 400~20k pf/in.2

Reduced plane separation lowers inductance and radiations of the

copper planes
Microvias significantly reduce hole barrel inductance by 12X

External plane layers are Cu foil + electroplated Cu (0.002 thick)

source: DDI

Plane Capacitance and Inductance

As a Function of Plane Separation
5000 0.35
Dk=16.0
4500
0.3
4000
Dk=4.0
0.25
Capacitance (pF/sq.in.)

Inductance (nH/S quare)

3500
3000 Capacitance
0.2
Inductance
2500
0.15
2000

1500 0.1
1000
0.05
500
0 0
0 1 2 3 4 5 6 7 8 9 10
Dielectric/ Thickness (mil)
 Current Distributed Capacitance Options
A number of different approaches are being developed to provide material
for buried capacitance.

Dk @ Dj @
1MHz 1MHz

Inductance of Decoupling
Capacitor

Component

Ground
Conventional
Power

Capacitor

Component

Better Ground
Power

Capacitor

Component/Ground

Best Power
Distributed Capacitance Reduces
Power Bus Noise

Power Distribution Radiation

 Noise on
The Power
Distribution
Network
(PDN)

Noise on The PDN

 High-Speed Constraints
Q Layer stack-up
Stackup visualization
Impedance planning
Q Single-ended
Q Differential
Q Width/gap curve Layer Stackup
Design: vidar, Designer: jdube.

Layer parameters Stackup

1 th, Er = 1.1
0.7 th, SIGNAL_1, Z0 = 69.7 ohms, width = 8 th
2 th, Er = 4

Q Dielectric height 0.7 th, SIGNAL_2, Z0 = 57.9 ohms, width = 6 th

5 th, Er = 4
1.4 th, PLANE_3

Q Loss tangent 5 th, Er = 4

1.4 th, PLANE_4
6 th, Er = 4
0.7 th, SIGNAL_5, Z0 = 57.3 ohms, width = 5 th

Q Dielectric constant 5 th, Er = 4

0.7 th, SIGNAL_6, Z0 = 57.3 ohms, width = 5 th
6 th, Er = 4

Copper weight
1.4 th, PLANE_7

Q 6 th, Er = 4
0.7 th, SIGNAL_8, Z0 = 57.3 ohms, width = 5 th
92.4 th 5 th, Er = 4
0.7 th, SIGNAL_9, Z0 = 57.3 ohms, width = 5 th
6 th, Er = 4
1.4 th, PLANE_10
6 th, Er = 4
0.7 th, SIGNAL_11, Z0 = 57.3 ohms, width = 5 th
5 th, Er = 4
0.7 th, SIGNAL_12, Z0 = 57.3 ohms, width = 5 th
6 th, Er = 4
1.4 th, PLANE_13
5 th, Er = 4
1.4 th, PLANE_14
5 th, Er = 4
0.7 th, SIGNAL_15, Z0 = 57.9 ohms, width = 6 th
2 th, Er = 4
0.7 th, SIGNAL_16, Z0 = 69.7 ohms, width = 8 th
1 th, Er = 1.1

PCB HDI SI Simulation

 HDI PI Design Tool Challenges
High Speed & Power Analysis, Complex Modeling
Q Power integrity
Ground bounce
Decoupling analysis
DC drop analysis
Plane resonances
Mixed Signal Integrity / Power Integrity
analysis
Q Complex via modeling
Q 3D wirebond modeling

Signal injected at a via

Resulting noise
distribution between
the planes in a t-plane

New Challenges in High-Speed Design

What this means for design tools is that we have to pay
attention to details that we didnt before, especially:
Vias, which we used to model simplistically
Power and ground planes, which we used to ignore

entirely
And things attached between:
Decoupling capacitors
Stitching vias

Voltage regulator modules

(i.e., power supplies)

Vias are especially troubling,
because they cause high-speed
signals to interact with planes
 Power Integrity

16-Layer TH 12-Layer HDI

Source: DesignCon 2009 PI Effects of HDI

Power Integrity

Q Alternative Via
Stackups

Source: DesignCon 2009 PI Effects of HDI

 Original Design
Q 16 layers
Q Through-hole technology
Q 1517-pin FPBGA
Dominates the board
Many 50-ohm signals
Many 100-ohm diff pairs
Q 940-pin BGA
Q 498-pin BGA
Q 16 144-pin flash memory
Pins at 0.8mm pitch
Q 10x7.8 inches
Q Full 1.5V power plane, split 1.25V, 2.5V, and 3.3V power
plane

Power Integrity

16-Layer TH 12-Layer HDI

Source: DesignCon 2009 PI Effects of HDI
Reducing Plane Separation - Example

Q 28 0402 capacitors
25 0.01uF
1 0.1uF
1 1uF
1 10uF

Q On 1x1 board
Q Connected to top
Q Planes on top 2 layers
Q PDN measure at
5 mil plane separation
3 mil plane separation

Same Example, Bigger Board

Q Board changed from 1x1 to 10x10

 Special dielectrics

Q Instead of standard FR4 materials, dedicated

embedded capacitance materials can be used
In this example, Er=16 and thickness = 1 mil

Capacitor Parasitics

Q Inherent Parasitics
Effective Series Resistance (ESR)
Effective Series Inductance (ESL)

Q Mounting parasitics
Mounted inductance R
Q Dominant inductance
Mounted resistance
C
Q Usually much less than ESR
 Mounting Inductance

Q The mounting of a capacitor is the most vital

element in determining its performance
Q Inductance of a capacitor is dominated by its
mounting
Q Intrinsic resistance (ESR) dominates the
capacitors resistance, unless it is poorly mounted
Q Poor mounting can render a cap useless

L R C

Differences in PI
Q Caps on HDI design have less mounted inductance
Use via-in-pad technology
Have power planes close to caps
Q Top/first inner layer
Q Bottom/last inner layer
Have minimal distance between planes
Q 0.3 mil
Q HDI design has superior plane capacitance
Use of C-ply material
Q Less caps on HDI design
HDI design still has lower PDN impedance
 Minimizing Via Separation - Example
Q 0402 0.01uF cap mounted with vias at distance of
Q 0.01uF cap mounted with vias
80 mils
depth-to-plane of
40 mils
62 mils
0 mils
30 mils

0 mils

top

mid

Current loop
bottom

Minimizing Via Separation - Example

Q 0402 0.01uF cap mounted with vias at distance of
80 mils
40 mils

0 mils
Via Length (Z) Example - Results

Power Plane Voltage Drop

Source: DesignCon 2009 PI Effects of HDI

 Power Plane Current Density

Plane Swiss
Cheese effect

vias@0.8mm pitch
TH @0.8mm pitch
Source: DesignCon 2009 PI Effects of HDI

PDN Impedance at BGA Pinfield

TH @0.8mm pitch

vias@0.8mm pitch

Source: DesignCon 2009 PI Effects of HDI

 PDN Impedance With Thin Matls on 10x10
0.8-mil C-Ply
0.1
C-Ply w/o 0.01uF caps
w/o
dec.
caps

0.1

3-mil FR4
0.8-mil C-Ply

0.1

5-mil FR4 PP
3-mil FR4 PP

Source: DesignCon 2009 PI Effects of HDI

PDN impedance for 3.3V

Q Original design Q HDI design

100 0.01uF caps 12 0.01uF caps
60 0.1uF caps 14 0.1uF caps
1 1200uF cap 1 1200uF cap

0.1
 PDN impedance for 2.5V

Q Original design Q HDI design

30 0.01uF caps 4 0.01uF caps
88 0.1uF caps 42 0.1uF caps
1 10uF cap 1 10uF cap

0.1

Reference Books
Holden, Happy, The HDI Handbook,
http://communities.mentor.com/mgcx/community/pcb/blogs/happy_holden

631 ppg, Jan 2009, pcb007

Free Download

Fjelstad, Joseph, Flexible Circuit

Technology-Third Edition 2007,
220 ppg,, Jan 1994, pcb007
(http://www.pcb007.com/resources.aspx)
PDF Free
 Click to edit Master title style

THANK-YOU

Happy Holden
Senior PCB Technologist
Systems Design Division

PCD-PHOENIX 2009

Some HDI Feedback

 L-3 Paper on HDI Implementation

Length: 6.299 Width: 3.937 Density: 429.8 pins/sq. inch

PRI Side Parts: 228 PRI Side Pins: 5229
SEC Side Parts: 1139 SEC Side Pins: 2506

From 26-Layers TH to 16-Layers HDI

SOURCE: MICRO VIA and HDI:WHEN HAPPYS IDEAS ARE IMPLEMENTED
JAYSON HARAMES , L-3 COMMUNICATIONS

L-3 Paper on HDI Implementation

We use patterns

64 SOURCE: MICRO VIA and HDI:WHEN HAPPYS IDEAS ARE IMPLEMENTED

JHH, Micro Via and HDI..., August 2008 JAYSON HARAMES , L-3 COMMUNICATIONS
L-3 Paper: Signal Integrity

SOURCE: MICRO VIA and HDI:WHEN HAPPYS IDEAS ARE IMPLEMENTED

JAYSON HARAMES , L-3 COMMUNICATIONS

L-3 Paper: Conclusion

SOURCE: MICRO VIA and HDI:WHEN HAPPYS IDEAS ARE IMPLEMENTED

JAYSON HARAMES , L-3 COMMUNICATIONS