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The FLAGS register is the status register in Intel x86 microprocessors that contains the

current state of the processor. This register is 16 bits wide. Its successors,
the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The
wider registers retain compatibility with their smaller predecessors.
The fixed bits at bit positions 1, 3 and 5, and carry, parity, adjust, zero and sign flags are
inherited from an even earlier architecture, 8080. The adjust flag used to be called
auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.

Carry flag (usually indicated as the C flag) is a single bit in a system status (flag)
register used to indicate when an arithmetic carry or borrow has been generated out of
the most significant ALU bit position. The carry flag enables numbers larger than a
single ALU width to be added/subtracted by carrying (adding) a binary digit from a
partial addition/subtraction to the least significant bit position of a more significant word.
It is also used to extend bit shifts and rotates in a similar manner on many processors
(sometimes done via a dedicated X flag). For subtractive operations, two (opposite)
conventions are employed as most machines set the carry flag on borrow while some
machines (such as the 6502 and the PIC) instead reset the carry flag on borrow (and
vice versa).
Parity flag indicates if the number of set bits is odd or even in the binary representation
of the result of the last operation. It is normally a single bit in a processor status register.
For example, assume a machine where a set parity flag indicates even parity. If the
result of the last operation were 26 (11010 in binary), the parity flag would be 0 since
the number of set bits is odd. Similarly, if the result were 10 (1010 in binary) then the
parity flag would be 1.
The Adjust flag (also known as the Auxiliary flag) is a CPU flag in the FLAGS
register of all x86-compatible CPUs. It is located at bit position 4. It indicates when
an arithmetic carry or borrow has been generated out of the four least significant bits, or
lower nibble. It is primarily used to support binary-coded decimal (BCD) arithmetic.
Auxiliary flag is set (to 1) if there is a carry from the low nibble (lowest four bits) to the
high nibble (upper four bits), or a borrow from the high nibble to the low nibble, in the
low-order 8-bit portion of an addition or subtraction operation. Otherwise, if no such
carry or borrow occurs, the flag is cleared (reset to 0).
Zero flag is a single bit flag that is a central feature on most
conventional CPU architectures (including x86, ARM, PDP-11, 68000, 6502, and
numerous others). It is often stored in a dedicated register, typically called status
register or flag register, along with other flags. The zero flag is typically
abbreviated Z or ZF or similar in most documentation and assembly languages.
Along with a carry flag, a sign flag and an overflow flag, the zero flag is used to check
the result of an arithmetic operation, including bitwise logical instructions. It is set if an
arithmetic result is zero, and reset otherwise. This includes results which are not stored,
as most traditional instruction sets implement the compare instruction as a subtract
where the result is discarded. It is also common that processors have a bitwise AND-
instruction that does not store the result.
In most processors, the zero flag is mainly used in conditional branch instructions,
which alter control flow on previous instruction results, but there are often other uses as
well.
In some instruction sets such as the MIPS architecture, a dedicated flag register is not
used; jump instructions instead check a register for zero.
Negative flag or Sign flag is a single bit in a system status (flag) register used to
indicate whether the result of the last mathematical operation resulted in a value whose
most significant bit was set. In a two's complement interpretation of the result, the
negative flag is set if the result was negative.
For example, in an 8-bit signed number system, -37 will be represented as 1101 1011 in
binary (the most significant bit is 1), while +37 will be represented as 0010 0101 (the
most significant bit is 0).
The negative flag is set according to the result in the x86 series processors by the
following instructions (referring to the Intel 80386 manual [1]):
A trap flag permits operation of a processor in single-step mode. If such a flag is
available, debuggers can use it to step through the execution of a computer program.
IF (Interrupt Flag) is a system flag bit in the x86 architecture's FLAGS register, which
determines whether or not the CPU will handle maskable hardware interrupts.[1]
The bit, which is bit 9 of the FLAGS register, may be set or cleared by programs with
sufficient privileges, as usually determined by the Operating System. If the flag is set to
1, maskable hardware interrupts will be handled. If cleared (set to 0), such interrupts will
be ignored. IF does not affect the handling of non-maskable interrupts or software
interrupts generated by the INT instruction.

Direction flag is a flag that controls the left-to-right or right-to-left direction


of string processing,[1] stored in the FLAGS register on all x86-compatible CPUs.[2] It
is bit number 10.
This flag is used to determine the direction (forward or backward) in which several bytes
of data will be copied from one place in the memory, to another. The direction is
important mainly when the original data position in memory and the target data position
overlap.

If it is set to 0 (using the clear-direction-flag instruction CLD) it means that


string is processed beginning from lowest to highest address;
such instructions mode is called auto-incrementing mode. Both the source
index and destination index (like MOVS) will increase them;

In case it is set to 1 (using the set-direction-flag instruction STD) the string is


processed from highest to lowest address. This is called auto-decrementing mode.

Overflow flag (sometimes called V flag) is usually a single bit in a system status
register used to indicate when an arithmetic overflow has occurred in an operation,
indicating that the signed two's-complement result would not fit in the number of bits
used for the operation (the ALU width). Some architectures may be configured to
automatically generate an exception on an operation resulting in overflow.

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