TMS320C5xFamilly of Digital Signal

Proceessors
Fifth generation digital signal processors from
Texas Instruments
16 bit floating point processors-using
p CMOS
technology
Have advanced Harvard architecture
Can execute 50 Million Instructions Per Second
(MIPS)
 Features of TMS320C5xFam
mily of Digital Signal
Processors
16 bit CPU
20 to 50 ns single cycle instruction execuution time
Single cycle 16x16-bit MAC (Multiply and Accumulate) Unit
64k x 16-bit
16 bit external
t l program memory address
add space
64k x 16-bit external data memory addreess space
64k x 16-bit external IO address space
32kk x 16-bit
bi externall global
l b l memory adddddress space
2k to 32k x 16-bit single access On chip PROM
1k to 9k x 16-bit single access On chip program
p / data RAM
1k x 16-bit dual access On chip program m / data RAM
Synchronous , TDM and buffered serial ports
Programmable timer and PLL
IEEE standard JTAG ports
5V /3V operation with low power dissipaation and power down modes
DMA interfaces
100/128/132/144 pins in plastic QFP andd TQFP
 Architecture of TMS320C5x
TMS320C5x has an advanced version of Harvard architecture (separate bus for data and program)
simultaneous access of data and program

Program bus separate lines to transmit data and add

dress

Data bus separate lines to transmit data and address

Architecture of TMS320C5x - three major areas CP

PU , memory and peripherals

Functional units of CPU Parallel Logic Units (PLU

U) , central ALU, Auxiliary Register Arithmetic Unit
(ARAU) , Program controller

On-chip memory (Internal) Program ROM ( 2k to 32k words) , Data/ Program Dual Access RAM
(DARAM) (1024+32 = 1056 words) , Data/ Program Single Access RAM (SARAM) (1k to 9k words)

On-chip peripheral (Internal) - clock generator , hardware timer , software programmable wait state
generators , parallel IO ports , Host Port Interface (HPI)
( , serial port , Buffered Serial port (BSP), Time
Division Multiplexed (TDM) serial port and user masskable interrupts
 Architecture of TMS320C5x
TMS320C5x have a total meemory address space of 224k
(i l di
(including on-chip
hi memory)) with
ith addressability
dd bilit (memory
(
word size) of 16 bits.

Address space divided in to 4 seelectable address spaces

64k Program memory
memor address sppace
64k Local data memory address space
32k Global data memory addresss space
64k IO ports address space
Architecture of TMS320C5x
 Functional Units of CPU
C of TMS320C5x
Parallel logic unit (PLU)
PLU is an additional logic unit
Performs logic operations withoout affecting accumulator or
product register.
Perform Boolean operations or bit manipulations
It can set, clear, test or toggle bits
b in the status register, control
register and in any data memoryy locations
Central Arithmetic Logic unit (CALU)
multiplying two 16 bit 2s com
mplement number to 32 bit product
in a single machine cycle.
cycle
One operand is temporary regg TREG0 and other operand is data
/immediate operand in the innstruction. Result stored in 32 bit
product register (PREG)
Memory mapped registers
ADDRESS

DEC HEX NAME DESCRIPTION

03
0-3 03
0-3 nil
il RESERVED
S

4 4 IMR Interrupt Mask Register

5 5 GREG Global memory allocation reg

gister

6 6 IFR I
Interrupt Flag
Fl register
i

7 7 PMST Processor mode status register

8 8 RPTC Repeat Counter register

9 9 BRCR Bl k Repeat
Block R Counter
C registe
i er

10 A PASR Block Repeat program addresss start register

11 B PAER Block Repeat program addresss end register

12 C TREG0 T
Temporary reg 0(used
0( d for
f mu
ultiplicand)
l i li d)

13 D TREG1 Temporary reg 1(used for dyn

namic shift count)

14 E TRGG2 Temporary reg 2(used as bit pointer

p in dynamic bit test)

15 F DBMR D
Dynamic
i bit manipulation
i l ti regg
 Memory mapped registers

96 Nos of 16 bit memory-mappeed register

Mapped in to page 0 of data mem mory space
Includes various control and stattus register for CPU ,serial port
s/w wait state generator
16 memory mappedd IO O ports
TMS320C50 memoryy map
p
TMS320C54 memoryymap
TMS320C54memoryy map
 ARAU
Contains 16 bit auxiliaryy regg AR
R0-AR7

A 3 bit ARP

A 16 BIT INDEX REGISTER

A 16 BIT Auxiliary Register Com

mparison Register (ARCR)

an unsigned 16 bit arithmetic unnit in ARAU

CALU is relieved from task of aaddress manipulation

It is free from other operation inn parallel

 Program Controller

Contains logic ckts that decodees the instructions, manages the CPU
pipeline stores the stack of CPU
U operation and decodes the condition
operation due to parallelism in architecture,
a
The PC can perform 3 concurrrent or simultaneous memory opn in
any given machine cycle.
cycle
Fetch , read , write
16 bit program counter,16 bit status register STO and ST1,PMST-
Processor Mode Status Regisster, CBCR-Circular Buffer Control
Register
16x16 bit H/W stack
Address generation logic, instrruction register ,interrupt flag register
and mask register
 STATUS register
2 -16
16 bit ST0,ST1-holds
ST0 ST1 holds the status of ALU
A result pointer for in direct addressing
result,
and various bit for interrupt ctrl ,hold mode
m and product shift mode
Status register can be stored in data mem
mory and leading for data mempory thereby
allowing processor status to be saved an
nd restored for subroutines
The LST writes to ST0 and ST1
SST- reads from ST0 and ST1
ST0 and ST1 each have an associateed 1-level deep
p shadow register
g stack for
automatic context saving when an interrrupt occurs
INTM and OVM bits in ST0
C,CNF,HM,SXM,TC and XF in ST
T1 can be individually set using SETC
instruction and can be cleared using CR
RLC instruction
 On Chip Memoryy in TMS320C5x
On-Chip
Program ROM
The processors have internal-maskablee- program ROM (PROM) of size 2K to 3K
words.
The processor has an option for inccluding or excluding the on-chip PROM
addresses in the processor program mem
mory address space
The main purpose of PROM is to permanently
p Store the program code for a
specific
ifi application
li i during
d i manufacturi
f iing off the
h chip
hi itself.
i lf
The has an option of boot loading the content
c of PROM to internal/external RAM
during power-ON reset.
The content of the PROM can be proteccted so that any external device cannot have
access to the program code.
 DATA /PROGRAM DUAL ACC
ACC
CESS RAM(DARAM)

Th TMS processors has

The h 1056 words
d [10566*16 bits]
bit ] on-chip
hi dual
d l access RAM
Which is divided into three blocks, B0, B1
1 and B2.
1.The block B0 has 512 words[512*16
[ bitts]] data / p
program
g RAM.
2.The block B1 has 512 words[512*16 bitts] data RAM.
3.The block B2 has 32 words[512*16 bitss] data RAM.
 DATA / PROGRAM single acces
accesss RAM (SARAM)

The various models or TMS320c5X

X processors has 1k words to 9k words of
SARAM.

The internal SARAM can be con

nfigured as data memory,
memory program and
combination of data and program meemory.

The SARAM can be divided into blocck of 1k/2k words with continuous address.
address

The processor CPU can access one block for reading while writing in another
block.
block
 On Chip peripherals of TMS320C5x
T Processors
Clock
Cl k generator
t
Consist of an internal Oscillator and a phase locked loop
Driven byy external crystal
y resonator circuit or
o supplied
pp byy an external clock source
The PLL generate an internal CPU by clocck by multiplying the clock source by a specified
factor
CPU-driven by high frequency clock & clock source -used as source for other peripherals
which run at low frequency clock
Hardware Timer
A 16 bit hardware timer with a 4 bit pre-scaller is available in TMS320C5x.
Programmable
g Timer ggenerates clock-rate between 1/2 & 1/32 of machine cycle
y rate
(CLKOUT1) depend on timer divide down ratio.
The timer can be stopped, restarted, reset or disabled by special status bit.
The processors has three registers to controol & operate the timer & they are Timer Control
Registers(TCR), Timer Counter Registers(TIIM), Timer Period Register(PRD)
 Timer counter Register gives the current couunt of the timer
Timer Period Register defines the period off the Timer
The 16 bit Timer Control Registers controlss the operations of the timer
Software Programmable wait-State Geenerators
Generate/insert wait states in external bus cycles for interfacing with slow speed external
memory and IO devices.
The Processors consists of multiple wait
wait-st
sttate generating circuits , and each circuits is user
programmable to insert different number off wait states for external memory accesses.
Wait state generator can extend the externall bus cycles up to seven machine cycles.
Parallel IO parts
TMS3205Cx has 64k IO address space useed as 64 IO ports - 16 are memory mapped in
data memory space.
Each ports are addressed with IN and OUT
T instructions
Memoryy mapped
pp IO-accessed with anyy insttructions that reads from or writes to data
memory
 TMS320C5x-generates a hardware signal IS
S during IO access to indicate a read or write -
through an IO port
TMS320C5x can easily interface with exterrnal IO devices through IO ports with minimal
external address decoding circuits.
Host Port Interface
Available on-TMS320C57S & TMS320LC557
HPI-8 bit parallel IO port-provides interface to a host processor for information exchange
b/w the Digital Signal Processors & the host processor
DSP-has 2k word-on chip memory that is accessible to both the host processor and DSP.
HPI is connected to this memory through a dedicated bus, so that
that-CPU
CPU works uninterrupted
while host processor accesses the memory from
f host port.
Serial Ports
Three kinds of serial ports-General purposee serial ports, Time Division Multiplexed (TDM)
serial port and Buffered Serial Port (BSP)
TMS320C5x contains atleast one-general
one general purpose,
purpose high sped,
sped full duplexed serial port-
port
used for direct communication with serial devices
d as codec, serial analog to digital & other
serial systems.
Continued.

Serial port operate upto-1/4th of machine cycle rate(CLKOUT1)

The transmitter and receiver are double bufffered and individually controlled by maskable
i t
interrupt
t signals.
i l
For serial port the data is framed either as bytess or as words.
Buffered Serial Port ((BSP)) consist full duplex
p x double Buffered Serial Port Interface ((SPI)) and
an Auto-Buffering Unit (ABU).
ABU allows the SPI to read/write directly to processor
p internal memory using a dedicated bus
which enhances the speed of serial communicattions
Time Division Multiplexed (TDM) serial ports can be used for serial communications between
multiple processors.
processors
A maximum of 8 processors having TDM porrts can be connected via a pair of data lines and
pair of Address lines for serial communication.
 Addressinng modes
Types
T off addressing
dd i modes
d
Direct addressing :
lower 7 bits of data memory sspecified
s directly in the instruction it
self. Upper 9 bits of the addrress- content of data memory page
pointer (DP)in status register -0 (ST0)

TMS320C5x data memory-512 pages- 2 power 9-each page

having128 locations =64k.
DP holds the 9 bit current page address and the 7 bit address in the
instruction is the page offset add
dress.
dress
 Addressinng modes
Memory mapped register addressinng :
The address of memory mappedd register specified as direct address
in the instruction
Special case of direct addressinng in which only page offset address
is used to access the memory annd the default page address is 000h.
The data ppointer need not be looaded with ppage
g address for this
addressing modes

Memory mapped registers of TMS

T 320C5x are mapped to page 0
of data memory address space.
space
 Addressinng modes
Indirect addressing :
The data memory address - speecified by the content of one of the 8
auxiliary registers AR-AR7

AR used for accessing data -de

deenoted by ARP (Auxiliary Register
Pointer)

h content off AR can be

The b upda
datedd automatically
i ll either
i h after
f or
before the operand is fetched.
 Syntax
S t forf modifying
dif i AR in
i indirect
i di t addressing
dd i
 Addressinng modes
Bit reversed addressing :
The data memory address - speciified by AR like indirect addressing

The content of AR incrementedd / decremented in order to generate

the data memory address in thee bit reversal order
Bit reversal addressing special case of indirect addressing
 Addressinng modes
Immediate addressing :
The data - specified as part of the
t instruction

The instruction 8/9/13 /16-bit

/16 bit constant
c ,which
which is the data to be
operated by the instrcution

The immediate constant is speccified with # symbol

 Addressinng modes
Dedicated Register addressing :
The address of the one of the opperand s is specified by a dedicated
CPU register BMAR (Block Moove Address Register)
In this addressing the address of
o the memory block to be accessed
can be changed during executionn of the program
one of the operands is the conteent of a dedicated CPU register
DBMR ((Dynamic
y Bit Manipula
p ation Register)
g )
 Addressinng modes
Circular addressing :
Similar to indirect addressing

Allows the specified memory buuffer to be accessed sequentially with

a pointer that automatically wrraps around to the beginning of the
buffer when the last location is accessed
a

When the address pointer is inccremented , the address in AR will be

checked with the end address off the circular buffer and if it exceeds
the end address then the addresss is made equal to start address of the
circular buffer
 Addressinng modes
In order to hold the start and ennd address of the circular buffer ,the
TMS320C5x has four circular buffer
b registers

CBSR1 : Circular Buffer -1 Start Register

CBSR2 : Circular Buffer -2 Start Register
CBER1 : Circular Buffer -1
1 End Register
R
CBER 2 : Circular Buffer -2 End Register

With the
th help
h l off above
b regist
i ters
t ,att any one time,
ti t
two circular
i l
buffers can be defined. A Circullar Buffer Control Register (CBCR)
is used to enable / disable the ciircular buffers