ACMA: Accuracy-Configurable Multiplier
Architecture for Error-Resilient System-on-Chip
Kartikeya Bhardwaj and Pravin S. Mane
Electrical and Electronics Engineering
BITS Pilani-Goa Campus, Goa 403 726, India
Email: bhardwajkartikeya@gmail.com, pravinmane@goa.bits-pilani.ac.in
AbstractIn nanometer regime, optimization of System-on-
Chip (SoC) designs w.r.t. speed, power and area is a major
concern for VLSI designers today. Imprecise/approximate design
obviates the constraints on accuracy, stemming a novel Speed-
Power-Accuracy-Area (SPAA) metrics which can pilot to tremen-
dous improvements in speed and/or power with a feeble accord
in accuracy. This astonishingly expediency captivated researchers
to delve into imprecise/approximate VLSI design evolution. In
this paper, we present a new accuracy-configurable multiplier
architecture (ACMA) for error-resilient systems. The ACMA uses
a technique called Carry-in Prediction for approximate multipli-
cation based on efficient precomputation logic that increases its
throughput. The proposed multiplication reduces the latency of
an accurate multiplier by almost half by reducing its critical
path. The simulation results suggest that SPAA metrics can be
administered by exploiting the design for apposite number of
iterations. The results for 16-bit multiplication show the mean
accuracy of 99.85% to 99.9% in case there is no lower bound
on the size of operands and if size of operands are 10-bit or more
(numbers > 1000), it results into a mean accuracy of 99.965%.
Index TermsApproximate Arithmetic; Error-Resilient De-
signs, multiplier architecture; Accuracy-Configurable multiplier
I. I NTRODUCTION
With the recent spectacular progress in sub-nanometer tech-
nology, shrinking of transistor sizes has led to integration of
many cores on a single chip, thereby increasing system per-
formance. This continuous technology scaling is putting forth
new design challenges because of the contradictory design
specifications such as low-power and high-speed. Further, it
would be ridiculous to entertain these design specifications
by dilating the design with exorbitant costs of manufac-
turing, verification, and test. The International Technology
Roadmap for Semiconductors (ITRS) [1] has anticipated im-
precise/approximate designs that became a state-of-the art
demand in view of the emerging class of killer applications
that manifest inherent error-resilience such as multimedia,
graphics, and wireless communications. In complex multi-
media applications, DSP blocks are implemented as cores
that process signals relevant to human senses, e.g., sight and
hearing. The verity of limited perception of human senses
alleviate the constraints on accuracy, resulting into error-
resilient System-on-Chip (SoC) designs.
In the SoC design for aforementioned applications, adders
and multipliers are used as basic building blocks and
in accordance with error-resilient system design, impre-
978-1-4673-6180-4/13/$31.00 2013 IEEE
cise/approximate designs have attracted significant research
interest in recent years. Conventional wisdom investigated
several mechanisms such as truncation [2] [3], over-clocking,
and voltage over-scaling (VOS) [4], which could not config-
ure Speed-Power-Accuracy-Area (SPAA) metrics effectively.
Apart from these, other design techniques rely on functional
approximations and mostly focus on imprecise/approximate
adders via the concept of shortening the carry-chain to elevate
design performance. Lu [5] proposed a -bit carry look-ahead
adder in which only previous bits are considered to estimate
current carry signal. Lus adder is found unattractive due to
low probability of getting a correct sum and increased area
overhead. Shin et al. [6] reduce data-path delay and re-design
the data-path modules and cuts the critical-path in carry-
chain to exploit a given error rate to improve parametric
yield. Further, Shin et al. [7] explored a logic synthesis
approach to exploit a given error rate to reduce the area of
imprecise/approximate circuits.
Zhu et al.[8] [9] reveal four error-tolerant adders: ETA-I,
ETA-II, ETA-IIM, and ETA-IV. ETA-I [8] segments inputs
into: 1) Accurate part, and 2) Inaccurate part, in which no
carry signal is considered at any bit position. ETA-II [9]
concurrently completes carry propagation by dividing the path
into a number of short paths. In ETA-IIM, more MSBs
are considered in evaluating carry signal at the expense of
degradation in speed performance and ETA-IV uses Carry
Select Adder (CSL). Gupta et al. [10] target low-power to
leverage error-resiliency and propose five different versions
of mirror adder by reducing the number of transistors and
internal node capacitances. Verma et al. [11] proposed a
Variable Latency Speculative Adder (VLSA) which provides
approximate/accurate results but land up in delay and large
area overhead. Kahng et. al [12] demonstrated an accuracy-
configurable adder (ACA) with reduced critical-path delay and
error rate. The ACA provides for a better trade-off between
accuracy, speed and power but with the large area overhead.
In comparison to the above work on adders, very few
researchers reported their work on approximate multipliers.
Sullivan et al. [13] investigated an iterative approximate mul-
tiplier based on (TEC) in which
a small amount of error correcting circuitry is added for each
iteration. This circuitry inexpensively replicates the effects of
multiple pipeline iterations for the most problematic inputs.
Kulkarni et al. [14] presented a 2 2 underdesigned multiplier
block and built arbitrarily large power efficient inaccurate AH XL

multipliers. Khaing et al. [15] developed an Error Tolerant AH XH AL XL

Multiplier (ETM) algorithm in which the input operands are AL XH

b bits b bits
split into two parts: a multiplication part that includes a 2b bits

number of higher order bits and a non-multiplication part Final Product

4b bits

that is of the remaining lower order bits. The multiplication (a) (b)
process begins at the point where the bits split and move
simultaneously towards in the two opposite directions till all Fig. 1. (a) Recursive Multiplication (b) Recursive Tree (Each box represents
bits are taken care of. The ETM is able to achieve a reduction a partial product of equal size.)
in the delay, power saving and hardware cost as compared to
2b1 2b1
the traditional 12-bit multipliers. AH XH
Multiplier
Most of the above design approaches of approximate mul- (bxb)

tipliers are based on the concept of shortening the carry- XH AH AH XL

Multiplier
chains in which error is configurable and to provide course (bxb)
Addition Stage

and fine tuning to dynamically update the probability of input AH XL Final Product
(2bx2b)
combinations exhibiting accurate results which bound SPAA AL XH
AH XH AL XL

metrics much tightly. However, the algorithms for approximate XL AL

Multiplier
(bxb)
AL XH

multiplication of smaller numbers are employed in the designs AL XL

and most of them give large magnitude of error as the bit-width Multiplier
(bxb)
of operands increases. Therefore, in this paper we propose 0 0

an efficient accuracy configurable approximate multiplier that

gives fairly accurate results for large numbers (numbers having
bit-width of around 10 bit or more). Our contributions are as
follows:
We propose a new accuracy-configurable multiplier ar-
chitecture (ACMA) for error-resilient SoC designs.
Since our aim is make approximate multiplier fast, we
present a novel Carry-in Prediction Logic that signifi-
cantly reduces the horizontal critical path.
The proposed multiplication reduces the latency of an
accurate multiplier by almost half by reducing its critical
path. It also increases the throughput of the ACMA.
We obtain a mean error between 0.1% to 0.15% (mean
accuracy of 99.85% to 99.9%) for a 16-bit multiplication
in case of no lower bound on the size of operands.
However, if the size of operands are 10 bits or more
(numbers > 1000), the mean error drops to merely
0.035%, giving a mean accuracy of 99.965%.
Rest of the paper is organized in various sections. We first dis-
cuss the recursive multiplication procedure and then propose
an approximate multiplier architecture in Section 2. Section
3 gives the design of accuracy configurable multiplier. The
simulation results and their analysis for the proposed multiplier
are given in Section 4. Finally, we conclude and report the
future scope of our work in Section 5 of the paper.
II. A PPROXIMATE M ULTIPLIER A RCHITECTURE
In this section, we begin with the recursive multiplication
procedure and then propose a new approximate pipelined
multiplier architecture. Since the focus is to design a fast
approximate multiplier with low-power consumption, we in-
troduce and explain a novel Carry-in Prediction Logic here.
Fig. 2. A Pipelined Architecture for Recursive Multiplication
performed in the same clock cycle. Let be the multiplicand
and be the multiplier and assume that both are of 2 bits
each. and can be written as
= and =
Here, , , , and are of bits each.
The multiplication will be a 2 2 multiplication
which can be recursively carried out as shown in Figure 1 (a).
In this multiplication, , , , and
are partial products, each being a multiplication. Hence,
a 22 multiplication is divided into four multiplications
followed by additions. In general, the recursive multiplication
builds a recursive tree as shown in Figure 1 (b).
In case we further divide multiplication into very small
partial products (e.g. a 16 16 multiplication broken down
into 2 2 multiplications), the size of recursive tree will be
very large. As a result, the overhead required for addition
stage will increase substantially. Further, this approach will
not be helpful in reducing the critical path. In our approach,
we consider a pipelined architecture of a 2 2 recursive
multiplier broken down into four multiplications as shown
in Figure 2. This pipelined architecture is found to be more
optimum because further dividing multiplication ( ) into
smaller partial products would not only increase the overhead
of the addition stage but may require either more clock cycles
to complete the addition or may need a longer clock period.
We now explain the approximate pipelined multiplier archi-
tecture as follows.

A. Recursive Multiplication B. Proposed Architecture

A given multiplication can be recursively broken down into In the proposed architecture, we first focus on its accuracy,
several smaller-size multiplications, each of which can be that is minimizing error in the final product of and .
 Accurate = Partial Product
Partial Product pi q j
2b bits

AH XH AL XL

AL XH

AH XL
Accurate to a
Large Extent b bits

Final Product
4b bits

Critical Column

Fig. 3. Achieving upper 2 bits as accurate to a high extent 1 1 1 1

Accurate to a Accurate
Large Extent Completely
However, in order to minimize the error, we derive a logic Inaccurate

that gives us accurate results for certain most significant bits b bits b bits
(MSBs). In our logic, we render most significant 2 bits (out ACCURATE PART INACCURATE PART

of a total of 4 bits) as accurate to a large extent. Note that Fig. 4. Carry-in Prediction for = 8 i.e. 16 16 multiplication
here the objective is to make upper 2 bits accurate to a high
extent and not completely accurate. This will minimize the
degree of error involved and at the same time will give a In order to make the approximate partial product multipliers
suitable tradeoff between accuracy and power consumed in the fast, it is necessary to break the carry chain which reduces
multiplication. Further, out of the least significant 2 bits that the horizontal critical path. Therefore, we propose a novel
remain, lower /2 bits will be accurate and upper 3/2 bits will Carry-in Prediction Logic. This logic reduces the horizontal
be inaccurate. We make the lower /2 bits as accurate because critical path by half and makes the upper bits of approximate
it doesnt take a lot of hardware and at the same time increases partial product multipliers accurate to some extent. We divide
accuracy. In other words, out of 4 bits in the final product, the products , and of 2 bits each into
least significant /2 bits will be accurate and most significant two parts: Accurate to a large extent part and inaccurate
2 bits will be accurate to a large extent and remaining 3/2 part. Both these parts are of bits each as shown in the
bits will be inaccurate. This kind of arrangement will not only Figure 4 for = 8. The circles in figure represent the
provide accuracy but also give promising results for speed, tree of partial products ( ) obtained from multiplication of
power and area. As we shall see, this is achieved by employing multiplicand (say = 1 2 ...1 0 ) and multiplier (say
approximate multipliers for , and = 1 2 ...1 0 ). Please note, here can take values of
computation in Figure 2 and an accurate multiplier is or and can take values of or as required
used for evaluation. for , and evaluation. As evident from
In order to obtain most significant bits accurate (out of 4 the figure, inaccurate part further consists of a completely
bits in final product), we make ( multiplication) inaccurate part and a completely accurate part of /2 bits
completely accurate. Further, we reduce critical path to a large each. In rest of the paper, we denote the accurate to a large
extent by dividing the approximate partial product computation extent part as Accurate part and the remaining lower bits
into two parts: accurate part and inaccurate part. We now of approximate partial product as Inaccurate part.
introduce a new concept named as carry-in prediction logic Figure 4 further shows a critical column which is the column
which is used in approximate partial product computation only containing the maximum number of partial products. Carry-
( , and ) and not for accurate . in Prediction logic exploits the fact that if there are two or
more 1s in the critical column, then a carry of atleast 1 is
C. Carry-in Prediction Logic
definitely propagated to the next column. When is large
In the proposed architecture, our aim is to make the most (greater than 5 i.e. for operands of size 10 bits or so) we
significant 2 (out of a total of 4 bits) as accurate to a make the carry-in propagated to the accurate part as 1 if one
large extent and we achieve this as illustrated in Figure 3. or more of the circles in the critical column are 1, since there
In this illustration, the most significant bits of the is a very low probability of 0 carry being propagated. In fact,
approximate partial products ( , , and ) for such a magnitude of , there is a good probability that
must be accurate to a certain extent so that the sum of upper the carry propagated to accurate part from most significant bit
bits of , upper bits of and the 2 bits of of inaccurate part will be more than 1. In order to minimize
achieves higher degree of accuracy. this error we make the upper /2 bits of inaccurate part as a
 2b bits
AH XL
b bits
AHH X HL
AHH X HH AL XL
AHL X HL
b A
HL
X
HH
2 b bits b bits
b AL XH
2
2b bits
Final Product
4b bits
Fig. 5. Reducing the critical path of first stage of pipelined approximate
multiplier
series of 1s. The error is minimized because the difference
in actual and approximate partial products will be analogous
to that between 128 and 127 i.e. in binary, 128 is represented
as 10000000 and 127 is given by 01111111 (128 just passes
an extra carry). Now that we have a carry-in for accurate
part beforehand, we can start the multiplication procedure
simultaneously from both sides, thus reducing the horizontal
critical path by half. This completes the so-called Carry-in
Prediction Logic and its impact on reducing the critical path
in accuracy configurable multiplier design as described next.
III. ACCURACY-C ONFIGURABLE M ULTIPLIER
In this section, we present the design of an accuracy
configurable 16 16 approximate multiplier. The first stage
of the pipelined multiplier uses a total of 4 multipliers: 1
accurate (8 8) and 3 approximate (8 8). Because the
inaccurate multiplier is inherently faster than a corresponding
accurate multiplier, using an accurate 8 8 multiplier in the
same pipeline stage as other approximate ones would give no
improvement in critical path. Therefore, to reduce the critical
path of stage 1, we further recursively divide the 88 accurate
product into four 4 4 accurate partial products as shown in
Figure 5. We then add them up together in the second stage.
In other words, the stage 1 of the pipelined approximate
multiplier effectively consists of 7 multipliers, namely -
, , and which are 1) Overall Error (OE): It is the absolute error between
4 4 and accurate and , and which are
8 8 and inaccurate. Although, this decreases the latency of
stage 1 significantly when compared to an accurate 16 16
pipelined multiplier, it appears that this methodology increases
the latency of stage 2 as we need to compute more number
of additions. It can be observed that the latency of stage 2
remains unaffected in case we perform addition of all the
partial products in parallel i.e. addition of and
( bits) and that of resulting sum with ,
( + 1 bits) in parallel with the addition of
and (2 bits). Since the size of operands of the former
two additions is just and + 1 respectively, they almost
take same time to complete their addition process as the latter
addition of 2 bits. Further from Figure 5, it is observed
that carry out emerging from latter 2 bit addition can be
propagated using half adders and a 1 bit full adder can be
employed at the position where a carry-out emerges from the
former +1 addition to add the 3 bits together at that position.
The carry-out thus produced will be further propagated using
half adders till the MSB. Hence, we significantly reduce the
latency of stage 1 and get almost same latency for stage 2 using
the methodology discussed above, thus reducing the overall
critical path of the said multiplier.
Now that we have 7 multipliers in stage 1, we can vary
the accuracy level of the proposed multiplier by varying the
number of multipliers that are accurate. In any case, we keep
the as always accurate, so that the accuracy level
does not fall below a certain level. Therefore, we obtain
an Accuracy Configurable Multiplier whose accuracy can be
adjusted according to error tolerance of the application. The
number of inaccurate multipliers used will directly determine
the amount of power saved by the multiplier. Also, because
the algorithm has been designed in general for 2 2
multiplications, it is also configurable according to bit-width
of operands, i.e. size of inaccurate part in the approximate
partial products will always be equal to bits. For instance, if
bit-width of operands is scaled to 12 bits, value of becomes
6, and there will be three approximate partial products of 66
and four accurate partial products of 3 3 each. Hence, the
proposed algorithm is reconfigurable with operand bit width
as well as accuracy configurable.
Next, we present experimental results by considering a
simple and suitable tradeoff between accuracy and power -
3 partial products as inaccurate (8 8) and 1 partial product
as accurate (further recursively divided into 4 accurate partial
products that are 4 4) to reduce latency. Theoretical analysis
of power, area and latency is also described in the later part
of the next section.
IV. E XPERIMENTAL R ESULTS AND A NALYSIS
We simulate the proposed ACMA by writing a C - Program
and generating 5000 random numbers to compute accurate and
approximate products for all possible combinations without
repetition. We use the following design metrics [8], [12] for
the analysis of the proposed multiplier:
approximate and accurate products. It is given by =
, where is the correct result and is the
result obtained from approximate arithmetic circuit. All
the numbers here are in decimal numbers.
2) Relative Error: Relative Error is simply (/ )
100%. It gives the percentage of error involved in the
result of an algorithm.
3) Accuracy ( ): It is given by
(1 ) 100%. It measures the degree
of correctness of the output of certain approximate
algorithm.
 TABLE I
S IMULATION R ESULTS U SING C-P ROGRAM
Run Operand Mean Mean Acceptance
No. Range Error Accuracy Probability
1 > 1000 0.034% 99.966% 99.72%
2 >1 0.10% 99.90% 98.44%
3 >1 0.11% 99.89% 98.37%
4 >1 0.13% 99.87% 97.93%
5 >1 0.15% 99.85% 98.00%
4) Mean Error: Mean error is the average of relative errors
of all the combinations tested in an algorithm. Similarly
mean accuracy can also be defined as an average of
(or alternatively as 100 - Mean Error) of all
the individual values tested by the algorithm. Both of
these are expressed in percentages.
5) Minimum Acceptable Accuracy (MAA): Minimum Ac-
ceptable Accuracy is the minimum level of accuracy that
an application can tolerate. It is determined solely by the
application. (100 )% would give the maximum
error that can be tolerated by an application.
6) Acceptance Probability (AP): It is the probability that
accuracy of the approximate arithmetic circuit is higher
than the minimum acceptable accuracy. Its value is given
by = ( > ) Fig. 7. Percentage Reduction in Critical Path of Stage 1 vs. Half Operand
A. Simulation Results
The proposed algorithm is simulated using a C - Program
for a minimum acceptable accuracy ( ) of 99%. It
generates results like , relative error, , mean error clock period and plot them vs. half of operand bit-width (b)
and Acceptance Probability. The results are tabulated in the
Table I for various runs conducted. There is no difference as
such between the runs but they have been provided here to
emphasize that the results are consistent, not random.
The table shows spectacular results for accuracy levels. The
Acceptance Probability of more than 98% for a minimum
acceptable accuracy of 99% means that for all possible com-
binations of total number of random numbers generated, more
than 98% cases give an accuracy greater than 99%. Also, as
explained earlier, for larger numbers (operand size > 1000 i.e.
> 10 bits or so i.e. >= 5 or so), accuracy level shoots up
to as high as 99.966%.
B. Theoretical Analysis of Power, Area and Latency
We analyze our proposed approximate multiplier design
w.r.t. power, area and latency theoretically and validate results
experimentally. For simplicity, we take a very basic multiplier
and show the degree of advantages of using our approximate
algorithm on it. We consider a pipelined multiplier, each
of the four partial products of which are evaluated by a
simple combinational multiplier as shown in the Figure 6. We
apply the proposed approximate multiplication algorithm on
this pipelined multiplier. Therefore, partial products ( ) in
approximate multipliers are added using ripple carry adders.
Theoretically, we calculate critical path delay reduction in
b bit Ripple Carry Adder
b bit Ripple Carry Adder
b times
b bit Ripple Carry Adder
b bit Ripple Carry Adder
2b bits
Fig. 6. Combinational multiplier used for impementing individual
partial products of a combinational multiplier
75
Percentage Critical Path Reduction vs. Half Bitwidth of Operands
Critical Path Delay Reduction in stage1(%)
70
65
60
55
50
0 10 20 30 40 50 60 70
Half Bitwidth(b)
Bit-width
stage 1, normalized clock period and percentage reduction in
in MATLAB to see the reduction in Latency.
We have considered the individual delay of the two stages
because the net clock period is decided by the maximum delay
of both the stages, Since the proposed algorithm is concerned
only with improvement in stage 1, we discuss the plot of
Critical Path Reduction in stage 1 and the half bit-width () as
shown in Figure 7. It can be observed that as increases over
64 bits, percentage critical path reduction saturates at around
51%. Figure 8 shows the normalized clock period vs. . It
basically describes the rate at which the clock period increases
as the bit-width of operands rises i.e. 2. As evident from the
figure, the rate of increase of clock period for approximate
multiplier (green line) is far less than that of an accurate
one (blue line). It takes into account both the stages of the
multiplier and not just the stage 1.
Figure 9 is obtained by simply taking the difference between
the two curves drawn in Figure 8. It shows that the proposed
algorithm will give maximum reduction in clock period when
= 12 i.e. for 24 24 multiplication. Practically speaking,
24 24 multiplications are widely used in Multiply Accumu-
late Units which help in evaluation of Discrete Cosine Trans-
form and Quantization process for image/video compression
application. This is a kind of application where error can be
tolerated to a certain extent.
The reduction in power is also theoretically calculated based
 Normalized Clock Period vs. Half Bitwidth of Operands
1200 logic is employed to increase its throughput. The proposed
design reduced the latency of an accurate multiplier by almost
1000
half by reducing its critical path. The simulation results for
16-bit multiplication are reported into two parts: 1) When
Normalized Clock Period
800

there is no lower bound on the size of operands, the mean

accuracy comes out to be 99.85% to 99.9% and 2) When the
600

400 size of operands are 10-bit or more (numbers > 1000), the
mean accuracy is found to be 99.965%. These results demon-
200
strate the effectiveness of the proposed accuracy-configurable
0
approximate multiplier design w.r.t. the SPAA design metrics.
0 5 10 15 20 25 30 35
Half Bitwidth(b) As far as future scope of this research is concerned, the
proposed ACMA design can be employed in Error-Resilient
Fig. 8. Normalized Clock Period vs. Half Operand Bit-width System Architectures for well-known Recognition, Mining and
Synthesis (RMS) applications and also in the error-tolerant
Percentage Reduction in Clock Period vs. Half Bitwidth of Operands
60 processor designs where speed, power, and area are major
design concerns and not the accuracy.
50
Percentage Reduction in Clock Period

40
30
20
10
0
5 10
Fig. 9. Percentage Clock Period Reduction vs. Half Operand Bit-width
TABLE II
R ESULTS OF RTL C OMPILER
Approximate
Accurate
% Reduction
on the reduction of number of full adders. For instance, in
the case of a 16 16 multiplier, for a single approximate
partial product (8 8), reduction in the number of adders
is about 40%. But a 16 16 pipelined multiplier requires
4 such multiplications, so the net reduction in number of
adders is about 30% in stage 1. Therefore, this provides atleast
30% reduction in power. We verified this hypothesis using
Cadence RTL Compiler and the results obtained are tabulated
in Table II. We used a 45 standard cell library called
Nangate Opencell Library for RTL Synthesis. Further, it can
be observed from the Table II that power and area results are
in agreement with the theoretical results.
V. C ONCLUSION AND F UTURE S COPE OF THE W ORK
In this paper, we proposed an Accuracy-Configurable Multi-
plier Architecture (ACMA) for error-resilient System-on-Chip
designs. The ACMA design is based on a new algorithm for
approximate multiplication where an efficient precomputation
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