Comparing

the State-of-the-Art
SiC MOSFETs
Test results reveal characteristics of four major
manufacturers 900-V and 1.2-kV SiC devices

istockphoto.com/sputnikos

F
or decades, silicon (Si)-based semiconductors were the solution for
power electronics applications due to their mature technology and
low manufacturing costs. However, such semiconductors seem to
be approaching their limits of operation in terms of blocking volt-
by Alinaghi Marzoughi, age, working temperature, and switching speed [1]. The voltage rat-
Amy Romero, ing of commercial Si insulated-gate bipolar transistors (IGBTs) is limited to
Rolando Burgos, 6.5 kV, and at higher voltages, the maximum switching frequency featured
by these semiconductors is no more than several hundred hertz. The devel-
and Dushan Boroyevich opment of optimal switching schemes, such as selective harmonics elimina-
tion and selective harmonics mitigation, was mainly due to the limitation in
switching performance of Si-based semiconductors for high-power convert-
ers [2], [3]. Moreover, no Si-based semiconductor is reported to be capable
of operating beyond 200 C [1].
Digital Object Identifier 10.1109/MPEL.2017.2692309
Due to superior material properties [4], [5], the wide-bandgap semiconduc-
Date of publication: 23 June 2017 tors, such as gallium nitride and silicon carbide (SiC), enable higher voltages,

36 IEEE Power Electronics Magazine z June 2017 2329-9207/172017IEEE

switching frequencies, and operating temperatures when the latest-generation 900-V and 1.2-kV SiC MOSFETs from
compared to conventional Si technology. Since the realiza- four well-known semiconductor manufacturers: Wolf-
tion of the first SiC metaloxidesemiconductor field-effect speed, ROHM Semiconductor, Monolith Semiconductor,
transistor (MOSFET) in 1992 [6], a tremendous amount of and Sumitomo Electric Industries (SEI), where not all of
attention has been devoted to these semiconductors. Now, the investigated devices are yet commercialized. Complete
several generations of SiC field-effect transistors (FETs) evaluation of these SiC MOSFETs is done by extracting
are commercially available at an intermediate voltage range both static and dynamic performance characteristics for
from 650 V to 1.7 kV, with current ratings up to hundreds all of the devices under test (DUTs), under the same con-
of amperes [1], [7]. Meanwhile, researchers have been try- ditions, so that an unbiased assessment of device perfor-
ing to expand the penetration range of SiC MOSFETs to the mance can be made.
medium-voltage range, which has resulted in laboratory pro-
totypes or sample semiconductors in the range of 3.3 kV up The Devices Under Test
to 10 kV, with current ratings up to 1,500 A [8], [9]. A total of six SiC MOSFETs are under test in this article.
Besides allowing for improvements to existing topolo- Table 1 indicates the part number, nominal blocking voltage,
gies, SiC semiconductors can lead to the emergence of new continuous current rating (at room temperature), maximum
topologies that were not feasible due to the limitations of Si operating junction temperature, chip area, and recom-
semiconductors. The main application areas of wide-band- mended gate-to-source driving voltage for all of the devices.
gap semiconductors are expected to be traction systems, The 35-A device from Wolfspeed (marked as Wolfspeed #1)
renewable energies, and downhole drilling [1], [5]. The higher is in a TO-220 package, and the rest of the MOSFETs are in
switching frequencies enabled by the use of SiC MOSFETs TO-247 packaging. Both Wolfspeed MOSFETs are rated at
can result in smaller filter size, higher power density, and 900 V, while the rest of the devices under test are rated at
higher efficiency for drive systems [10]. Regarding renew- 1.2 kV. From a structural point of view, the SiC MOSFET
able energy sources and other grid-connected applications, from SEI is a vertical MOSFET (VMOSFET) while the rest
SiC FETs can feature higher efficiency, while power quality of the DUTs are double-implanted MOSFETs (DMOSFETs).
can also be improved by increasing the switching frequen- Note that, at the time of this research, the SiC MOS-
cies [11]. In downhole drilling applications, where cooling FETs were not commercialized, with the exception of the
restrictions make the operating temperature higher, SiC Wolfspeed X3M0050090G (marked as Wolfspeed #1) and
MOSFETs can be game-changing devices because of their the ROHM SCT3080KL. The characteristics of the noncom-
better thermal conductivity and higher maximum operat- mercialized devices are extracted using samples provided
ing temperatures [1]. In addition, several more applications, by the manufacturers to the Center for Power Electronics
such as dc-dc converters and FACTS, among others, can be Systems, Virginia Polytechnic Institute and State Univer-
listed where wide-bandgap semiconductors can have a con- sity, Blacksburg.
siderable positive impact [12][16].
At the same time, along with the efforts being made to Static Characterization
improve the performance of existing SiC MOSFETs and All of the static characterizations are done by using the
to expand their penetration range into medium voltages, B1505 curve tracer from Keysight Technologies. For each of
researchers have been interested in evaluating the com- the devices, this process includes acquisition of the output
parative performance of sample or commercial SiC devices.
The characterization and modeling of 1.2-kV, 20-A SiC
MOSFETs is shown in [17]. The authors of [18] performed
Table 1. The part numbers
a characterization and comparison of SiC MOSFETs, junc- and key parameters of the DUTs.
tion FETs (JFETs), bipolar junction transfer (BJT), and SiC
ID-cont Tmax Die Area
junction transistor (SiC) and extracted critical data needed
Device VDS (V) (A) (C) (mm2) VGS (V)
for loss calculation of the SiC-based semiconductors for
Wolfspeed #1 900 35 150 7.56 4/+15
any target application. The characterization and modeling
X3M0050090G
of 10-kV, 5-A SiC MOSFETs is shown in [19], where perfor-
Wolfspeed #2 900 160 175 31.65 4/+15
mance of the MOSFET in a boost converter application was
C3M0010090D-ES
also investigated. The characterization and scalable model-
ROHM 1,200 31 175 7.75 2/+18
ing of SiC MOSFETs and Si IGBTs for an optimized traction
SCT3080KL
inverter design was shown in [20]. The system efficiency
SEI 1,200 30 175 9 5/+15
and leakage current of Si IGBTs and SiC FETs in a variable-
XSM3012J-ST01
frequency drive is compared in [10], c onsidering different
Monolith #1 1,200 36 175 10 5/+20
filtering options. MSA12N080A
This article will build upon the work in [7] to provide
insight into the performance of state-of-the-art SiC power Monolith #2 1,200 120 175 31 5/+20
MSA12N025A
MOSFETs. This is accomplished by fully characterizing

June 2017 z IEEE Power Electronics Magazine 37

 Output Characteristics
60
Figure 1 shows the drain current I D versus drain-to-source
50 voltage of the MOSFET V DS for all DUTs at 25 C and
150 C. The recommended driving voltages are fed to the
40 devices when capturing the output characteristics. From the
output characteristics, an estimation of on-state resistances
ID (A)

30
can be made. According to Figure 1, the Wolfspeed #2 semi-
20 conductor features the smallest on-state resistance
compared to the other devices, while the ROHM semicon-
10
ductor has the highest on resistance.
0 The results reveal that the on-state resistance in
0 1 2 3 4 5 6 7 8 creases as the temperature rises. This is due to the fact
VDS (V) that the JFET-region resistance and drift-layer resistance
Wolfspeed #1 25 C Wolfspeed #1 150 C (which are the dominant resistances of SiC MOSFETs for
ROHM 25 C ROHM 150 C a wide range of operating conditions, except at low gate-
SEI 25 C SEI 150 C to-source voltages) both rise as temperature increases. At
Monolith #1 25 C Monolith #1 150 C
Wolfspeed #2 25 C Wolfspeed #2 150 C
low gate voltages, the channel resistance dominates the
Monolith #2 25 C Monolith #2 150 C on-state resistance.

FIG 1 The output characteristics of the DUTs. For capturing the Transfer Characteristics
output characteristics, the recommended VGS is applied for The transfer characteristic gives a measure of the thresh-
each device. old voltages of the devices as well as their gain at a con-
stant V DS . The transfer characteristics of the MOSFETs at
a 20-V drain-to-source voltage are shown in Figure 2 at
60 room temperature and at 150 C. The positive temperature
coefficient of transconductance (meaning that transcon-
50
ductance increases with rising temperature) seen from
40 Figure 2 is due to the increase in the metal-oxide-semicon-
ductor (MOS) channel inversion charge and inversion
ID (A)

30 mobility as temperature rises [22]. From this curve, the

smallest threshold voltage is expected from the Wolfspeed
20
#2 MOSFET, while the ROHM semiconductor features the
10 highest threshold gate-to-source voltage.

0
0 2 4 6 8 10 12 14 16 18 Specific On-State Resistance
VGS (V) The on-state resistances are measured for each of the MOS-
FETs at two temperatures. Then the resistance results are
Wolfspeed #1 25 C Wolfspeed #1 150 C
ROHM 25 C ROHM 150 C normalized with respect to the die size of the corresponding
SEI 25 C SEI 150 C devices. This is important since a smaller die size results in
Monolith #1 25 C Monolith #1 150 C a larger resistance for a given semiconductor technology.
Wolfspeed #2 25 C Wolfspeed #2 150 C Thus, the appropriate way is to normalize the on resistance
Monolith #2 25 C Monolith #2 150 C
with respect to the die area and derive the degree of merit
of the semiconductors based on their die size. A part of the
FIG 2 The transfer characteristics of the DUTs. The VDS is set to total die area should be used for edge termination as well as
20 V when capturing the transfer characteristics.
bonding pads, and the percentage of the active area to the
total die size varies for devices with different current rat-
characteristic, transfer characteristic, threshold voltage, ings. In this article, however, we did not have access to the
specific on-state resistance, and junction capacitances. All active areas of all of the semiconductors, so the calculation
of these characteristics, except the parasitic junction capac- is done by using the total die area given in Table 1 for each
itances, are measured from room temperature up to 150 C, device. However, this will penalize the lower-current-rating
since it was shown in [21] that junction capacitances are devices more compared to the large-current-rating devices,
temperature invariant. Based on the variation of the results since the percentage of the active area in a small die is
with temperature change, an assessment can be made of the lower compared to a large die.
temperature dependency of the static parameters. For high- The specific on-state resistances versus drain current
temperature measurements, a hot plate is utilized, and the are shown in Figure 3 in milliohm square centimeters for
device is mounted on it. both room temperature (solid lines) and 150 C (dashed

38 IEEE Power Electronics Magazine z June 2017

lines). Similar to the output characteristic acquisition,
here the recommended VGS of the devices is applied to the
DUTs. The SEI MOSFET has the smallest specific on-state
resistance, with a value around than 3.6 mX-cm 2 . The Wolf-
speed #2 MOSFET also has a specific on-resistance smaller
than 4 mX-cm 2, which indicates significant improvement
compared to previous generations of SiC MOSFETs at simi-
lar voltage and current ratings.
The change in the on resistance of SiC MOSFETs at
150C compared to 25 C is typically about 50%. Compared
to the typically greater-than-100% temperature depen-
dency of on resistance in Si-based power MOSFETs, SiC
MOSFETs will feature less change in conduction losses as
the temperature varies. The change in the on resistance
from room temperature to 150 C occurs in a linear man-
ner. Thus, interpolation of the results can be used to derive
the specific on resistance at any given temperature.
Threshold Voltages
Figure 4 demonstrates the plot of the threshold voltages ver-
sus temperature for all of the SiC MOSFETs investigated.
The threshold voltage in this study is defined as the voltage
across the gate and source of the MOSFET so that 50 mA of
drain current flows through the drain, while the V DS is set to
20 V. The threshold voltage is measured for each of the
MOSFETs at six different temperatures, from 25 C to
150C, to better assess the temperature dependency.
The Wolfspeed #2 MOSFET has the smallest threshold
voltage, which makes it more critical for it to be driven
by negative voltage at the turn-off state to prevent false
switching. The negative temperature coefficient of the
threshold voltage for the SiC MOSFETs comes from the
increase in the intrinsic carrier concentration with
increased temperature [23]. The SEI MOSFET, which is a
VMOSFET, shows less dependency of threshold voltage on
14
12
Resistance (m-cm2)
Specific On-State
10
8
6 3.5
4
2 2
0 1.5
0 10 20 30 40 50 60 70
ID (A)
Wolfspeed #1 25 C Wolfspeed #1 150 C
ROHM 25 C ROHM 150 C
SEI 25 C SEI 150 C
Monolith #1 25 C Monolith #1 150 C
Wolfspeed #2 25 C Wolfspeed #2 150 C
Monolith #2 25 C Monolith #2 150 C
FIG 3 The specific on-state resistances at 25 C and 150 C.
temperature in comparison to the other devices, which are
DMOSFETs. The threshold voltage falls approximately
25% for the Wolfspeed, ROHM, and Monolith MOSFETs
at 150 C with respect to 25C, while this change is only
12% for the SEI MOSFET.
To compare the threshold voltage of devices with dif-
ferent current ratings, the threshold current is sometimes
scaled proportional to the devices nominal current rating.
For instance, the threshold current of the Wolfspeed #2
MOSFET had to be increased compared to that of the Wolf-
speed #1; then the Wolfspeed #2 would feature a threshold
voltage similar to the Wolfspeed #1s. However, in this arti-
cle, the threshold current is set to a constant value for all of
the DUTs regardless of their current rating.
Junction Capacitances
The junction capacitances of all of the SiC MOSFET sam-
ples are measured under variant dc voltage up to 600 V at
100-kHz frequency. In this study, measurements of the
input capacitance C iss ^= C GS + C GDh, output capacitance
C oss ^= C DS + C GDh, and Miller capacitance C rss ^= C GDh are
performed, and the results are shown in Figure 5.
As shown in Figure 5, the input capacitance is the small-
est for the Wolfspeed #1 and ROHM MOSFETs. The input
capacitance and input gate resistance are the most impor-
tant factors contributing to switching losses; thus, these
power MOSFETs benefit from the smaller input capaci-
tance. From this point of view, the Monolith #2 device has
the highest capacitance, which comes primarily from its
larger die because of its higher current rating.
Regarding the output capacitance, the value is larger
for the Wolfspeed #2 and Monolith #2 devices because of
their higher current rating, while for the rest of the MOS-
FETs the output capacitance is similar. According to the
literature, discharging and charging of the drain-to-source
6
5.5
5
4.5
4
Vth (V)
3
2.5
80 1
25 50 75 100 125 150
Temperature (C)
Wolfspeed #1 ROHM
SEI Wolfspeed #2
Monolith #1 Monolith #2
FIG 4 The threshold voltages versus temperature, from 25 C
up to 150 C.
June 2017 z IEEE Power Electronics Magazine 39
 capacitance at turn-on and turn-off of the DUT will con-
tribute to switching-on and switching-off losses, and will
increase the turn-off losses and reduce the turn-on losses
3E09 with the same magnitude. However, the total switching loss

Ciss
is free of this bias [21].
Capacitance (F)

Last but not least, the Miller capacitance is the least for the
3E10
Wolfspeed #1 MOSFET, while the other devices have Miller

Coss
capacitances not far from each other. The Miller capacitance
3E11 is the main cause of the Miller effect and false turn-on when

Crss
the devices are connected in phase-leg configuration. Also,
this capacitance will contribute to the slew rate of the V DS
3E12
0 100 200 300 400 500 600 and thus will affect the switching losses. A higher Miller
dc Voltage (V) capacitance increases both turn-on and turn-off losses [21].
Crss SEI Ciss SEI Coss SEI
Crss ROHM Ciss ROHM Coss ROHM Test Circuit Design and Dynamic Characterization
Crss Wolfspeed #2 Ciss Wolfspeed #2 Coss Wolfspeed #2
In this section, we present the designed dynamic test circuit
Crss Wolfspeed #1 Ciss Wolfspeed #1 Coss Wolfspeed #1
Crss Monolith #1 Ciss Monolith #1 and the protection and measurement methods used. The
Coss Monolith #1
Crss Monolith #2 Ciss Monolith #2 well-known double-pulse test (DPT) technique is used to
Coss Monolith #2
extract the dynamic behavior of the semiconductors under
test. The overall schematic of the DPT circuit is shown in
FIG 5 The junction capacitances as a function of dc voltage Figure 6(a). The top switch for testing the discrete MOS-
measured at 100-kHz frequency. FETs is a Schottky barrier diode. For SiC MOSFETs in the
3040-A current rating range, the Cree
C4D10120 diode is used as the top
switch. However, for the larger-than-
Isolation Stage 600 V 100-A SiC MOSFETs from Wolfspeed
Input 20-V Input/30-V Output
Voltage and Monolith, the diode with the part
Lload FWD number C4D20120 from Cree with a
20 V higher current rating is utilized. Since
in real applications the top switch cur-
rent rating is selected proportional to
4/5 V 4/5
+15/+20 V the current rating of the device, using
Input Ground
different diodes does not introduce
dc/dc inequality in the DUT test conditions.
Buffer An inductive load is used for testing
Driver IC the devices. The resistor in series with
IXDD614 Rshunt
the switch is a current measurement
Gate Signal MOSFET Ground
ISO 7221 shunt, which is used to capture the
(a) drain current waveform.
IGBT Driving each device with its rec-
Isolation Stage
Input
12-V Input/12-V Output 1.2 kV, 80 A ommended gate-to-source voltage is
Voltage one of the important aspects of pro-
12 V viding equal conditions for the DUTs.
Input Ground Saturation To achieve this, the gate driver circuit
Voltage must be capable of providing variable
Current Booster driving voltages. As seen in Figure 6(a),
10-A Maximum a combination of Zener diodes and an
isolated dcdc power supply from
Traco Power are used to provide the
Single-Channel,
Current-Sensing IGBT Ground variable voltages needed. The gate sig-
IGBT Driver nal is created by a Tektronix AFG3102
IR21271 dual-channel function generator, and
(b) on the printed circuit board (PCB), it is
being isolated and buffered via an ISO
FIG 6 (a) The overall circuit schematics of the SiC MOSFET DPT setup and the gate 7221 optocoupler. The dcdc buffer
driver and (b) the overall schematics of the IGBT desaturation o vercurrent protection. needs isolated supply voltages for the

40 IEEE Power Electronics Magazine z June 2017

primary and secondary sides, so the primary-side voltage is
generated directly from the input voltage using a Zenerdiode.
The Traco Power dcdc converter has a 30-V output volt-
age (2 15 V in series). The summation of the positive and
negative gate voltages (for example, 20 V for the summation
of 5 V and 15 V in the SEI MOSFET) is created out of the 30-V
dcdc converter output by using a Zener diode. Then, using
another Zener diode stage, the resulting voltage (20 V in this
example) is divided into positive and negative voltages (+15 V
and 5 V with respect to the device source in the SEI MOS-
FET). The gate driving voltages are biased and decoupled
with four capacitors with magnitudes of 6.8 nF, 470 nF,
100 nF, and 10 nF in closest proximity to the driver integrated
circuit (IC). Finally, an IXDD614 high-speed, high-current
gate driver IC that can source or sink up to 14 A of current
is selected to be used in the gate driver circuit. The output
stage of this IC is a P-type MOS-N-type MOS totem pole with
matched turn-on and turn-off resistances of around 0.16 .
Like any other semiconductors, the DUTs are prone to
failure, especially under high-temperature dynamic tests.
To protect the setup and the oscilloscope channels from the
DUTs possible failure, an external IGBT desaturation over-
current protection is utilized with the test system. External
protection is used because different DUTs have different
output characteristics. Also, it has been shown that desatu-
ration protection is not as effective on SiC MOSFETs as on
Si IGBTs [24]. The IGBT used has a proper current rating,
and a current-sensing single-channel driver IC is used to
drive it, as shown in Figure 6(b).
The dc bus in the DPT is 600 V for all of the DUTs. In the
final design, four bulk capacitors are placed on the protec-
tion board to minimize stray inductances on the power loop
caused by the wires between the power supply and the test
setup. Placement of the bulk capacitors on the protection
PCB rather than on the double-pulse tester is because, in
case of a failure on the tester board, the energy stored in the
capacitors themselves can considerably increase the induc-
tor current and may take the inductor to saturation, causing
damage to the current shunt and the scope channel.
For decoupling purposes, a combination of film and
ceramic capacitors are placed on the DPT PCB. Three
100-nF, 1-kVdc film capacitors and one 330-nF, 1-kVdc film
capacitor are placed for decoupling the 600-V dc bus. Also
ten 100-nF, 1-kVdc ceramic capacitors are placed in maxi-
mum proximity to the switch via planar connections to pro-
vide better decoupling for the high-frequency components
of the switching current.
According to Figure 6(a), the load is a 1-mH inductor.
The inductor equivalent parasitic capacitance, together
with the junction capacitance of the diode, will contribute
to the switching-on transient. For that reason, it is of great
importance to minimize the inductor EPC. In this article, the
designed inductor has about 14 pF of EPC, which is negligi-
ble compared to the junction capacitance of the diodes used.
Three surface-mount device resistor slots are placed on
the PCB for providing gate resistances and to minimize the
FIG 7 The designed four-layer PCB for the double-pulse tester.
gate loop inductance. An additional resistor slot is series-
connected with a diode to make the double-pulse tester
capable of having separate turn-on and turn-off gate resis-
tances, if necessary. Since the dv/dt rates are expected to be
high, when designing the board, the common-mode immu-
nity of the system is reinforced by using common-mode
chokes with an impedance of 800 X at 100 MHz. Once the
signal and power stages of the double-pulse tester were
designed, the PCB was made. When designing the PCB,
repetitive Quest3D simulations were done to minimize the
gate and power loop inductances as well as the parasitic
capacitances. The achieved gate and power loop induc-
tances on the designed PCB were measured to be around 4.3
and 9.8 nH, respectively. The designed PCB for the double-
pulse tester is shown in Figure 7.
The waveforms resulting from the DPT are rich in high-
frequency harmonics. Thus, accurate loss calculation
requires the utilization of high-bandwidth measurement
methods for the waveforms. In this article, a 100-mX shunt
resistor with a 2-GHz bandwidth is utilized to measure the
drain current. For gate-to-source and drain-to-source volt-
ages, on the other hand, a low-voltage passive probe with
a 1-GHz bandwidth and the Tektronix P5100 high-voltage
probe with a 250-MHz bandwidth are used, respectively.
Room-Temperature DPTs
Having the DPT board prepared, the dynamic tests are per-
formed on all six DUTs. Table 2 shows the internal gate
resistance measured for each of the SiC MOSFETs, using
Table 2. The internal, external, and total gate
resistances used in the DPT.
Device Rg-int () Rg-ext () Rg-total ()
Wolfspeed #1 X3M0050090G 4.21 2.8 7.01
Wolfspeed #2 C3M0010090D-ES 2.03 3.1 5.13
ROHM SCT2080KE 12 0 12
SEI XSM3012J-ST01 4.04 2.3 6.34
Monolith #1 MSA12N080A 1.44 4.1 5.54
Monolith #2 MSA12N025A 0.78 4 4.78
June 2017 z IEEE Power Electronics Magazine 41
 200 4,000
180 Monolith #2 Switching-Off
SwitchingOff Energy (J)
3,500 Wolfspeed #2 Switching-Off
160

Switching Energy (J)

140 3,000 Monolith #2 Switching-On
Wolfspeed #2 Switching-On
120 2,500
100 2,000
80
1,500
60
40 1,000
20 500
0 0
5 10 15 20 25 30 35 0 20 40 60 80 100
Load Current (A) Load Current (A)
(a)
900 FIG 9 The switching-on and switching-off losses for the
olfspeed #2 and Monolith #2 SiC MOSFETs versus current at
W
800
SwitchingOn Energy (J)

the total gate resistances shown in Table 2 and at 25 C.

700
600
500 when applying zero external gate resistance, its switching
400 transients are not as large as the other MOSFETs. Finally,
300
the last column of Table 2 shows the total gate resistance
for each MOSFET.
200
For each power MOSFET, the DPT is performed from
100
a 5-A load current up to the devices nominal current or
0
5 10 15 20 25 30 35 100A, whichever happens first. For better resolution of the
Load Current (A) dynamic test results at lower currents, Figure 8(a)(c) dem-
(b) onstrates the switching-off, switching-on, and total switch-
ing losses, of all of the devices up to a 35-A load current.
1,200
Then in Figure 9, the turn-off and turn-on switching losses
Total Switching Energy (J)

1,000 are shown for the Wolfspeed #2 and Monolith #2 power

MOSFETs, up to 100 A.
800 According to Figure 8, the Wolfspeed #1 MOSFET fea-
600
tures the smallest switching losses among all of the DUTs
at both turn-off and turn-on. This is mainly attributed to
400 the small input and Miller capacitances of the Wolfspeed
#1 device compared to the others, although it has a rela-
200
tively large total input gate resistance. On the other side, the
0 Wolfspeed #2 and Monolith #2 power MOSFETs have larger
5 10 15 20 25 30 35
Load Current (A) switching losses, which is due to their larger current rating
(c) (larger die), resulting in larger parasitic capacitances. As
previously mentioned, larger parasitic capacitances slow
ROHM SEI
Wolfspeed #1 Monolith #1 down the switching transients of the device and increase
Wolfspeed #2 Monolith #2 the switching losses.
Although the ROHM semiconductor has an input capac-
FIG 8 (a) The switching-on losses, (b) switching-off losses, and itance as small as the Wolfspeed #1 MOSFET, its larger
(c) total switching losses for all six SiC MOSFETs under test input gate resistance causes larger switching losses com-
versus load current at the total gate resistances shown in pared to the Wolfspeed #1. The Monolith #1 power semi-
Table2 and at 25 C.
conductor features around the same switching losses as
the ROHM MOSFET, since it has a larger input capacitance
an Agilent 4294A impedance analyzer while the drain and but a smaller gate resistance, and the turn-off and turn-on
source terminals were isolated. The third column of the losses of the SEI MOSFET are larger than the Wolfspeed #1
table shows the external gate resistance selected for each but smaller than the other devices. Figures 8 and 9 reveal
device. The external gate resistances are selected to feature that the majority of the switching losses in SiC MOSFETs
the fastest switching speed for each of the devices before is caused when switching on. Thus, by using soft-switching
significant switching transients start to emerge. The ROHM methods and eliminating turn-on switching losses, the total
device has the largest internal gate resistance, and even system efficiency can be significantly improved.

42 IEEE Power Electronics Magazine z June 2017

High-Temperature DPTs each MOSFET, the external gate resistance was selected
To be able to test a device at high temperatures, a hot plate to have similar switching transients. The static character-
is used. Referring to Figure 10, the device is bent 90 and ization included the acquisition of output characteristics,
mounted at the bottom of the PCB. In this way, the DUT can transfer characteristics, specific on-resistances, threshold
touch the hot plate. In addition, the device leads are as short voltages, and parasitic capacitances. Also, in the dynamic
as possible to minimize additional inductances in the gate characterization using the designed chopper circuit, the
and power loops. A fan is used to cool the PCB and the MOSFETs turn-on and turn-off losses were measured at
components thereon so they do not experience high temper- different load currents and temperatures. Table 3 summa-
atures when the device is heated up to 200 C. rizes key specifications and a summary of the data acquired,
For a high-temperature DPT, the hot plate needs to where the blocking voltage, nominal continuous current
be isolated from the DUT. This is due to the fact that the rating, specific on-state resistance (at a 20-A drain current),
device case, which has to be in touch with the hot plate, threshold voltage, junction capacitances (input, output, and
is connected to the drain, while the hot plate is grounded. Miller capacitances at 600 V), and switching losses (at a
A layer of Kapton tape is applied on the hot plate to pro- 30-A load current) are shown for all of the semiconductors
vide isolation. For better thermal conductivity and also at room temperature.
to create an even-temperature surface, a layer of thermal
padding is applied both under and above the Kapton tape. Temperature Sensor
The high-temperature tests are performed at three tem-
peratures other than the room temperature: 100 C, 150C,
and 200 C. Although the DUTs are not capable of con-
tinuous operation at 200 C, it is assumed that heating the
device to 200 C for a short time and triggering it twice at
that temperature cannot change its properties in a signifi- Fan
cant way. High-temperature tests are performed at 5 A up to Function
20 A, with steps of 5 A, and higher load currents are avoided Generator
for higher reliability and safety purposes.
The high-temperature test results reveal that the tem-
perature dependency of switching losses is negligible for
SiC MOSFETs, an outstanding feature contributing to easier
Hot Plate DESAT
system design and more reliable operation. Figure 11, for Inductor Protection
instance, shows switching-off and switching-on losses for
the Wolfspeed #1 MOSFET as a reference, where the total FIG 10 The test setup for high-temperature DPTs. DESAT:
desaturation.
switching loss change at 200 C compared to 25 C is about
6%. Also, as expected, as temperature increases, the turn-
off losses of SiC MOSFETs increase and the turn-on losses
200
decline. This is mainly due to the reduction of the plateau
Turn-On
180
and threshold voltages as temperature increases [21], caus- 160
ing faster switching transients in the turn-on phase and 140
Energy (J)

a slower turn-off process. Figure 12 shows the switching 120 25 C

100 C
waveforms in the Wolfspeed #1 DUT, where the effect of 100 150 C
80 200 C
temperature on switching transients can be seen.
60
Turn-Off

40
Summary and Conclusions 20
This article presented the static and dynamic characteriza- 0
5 10 15 20
tion results for six SiC MOSFETs for a wide range of tem-
Load Current (A)
peratures, from 25 C to 200 C. Following the design of a
double-pulse tester system capable of providing variable Switching-Off at 25 C
gate-driving voltages, commercial and sample SiC MOSFETs Switching-Off at 150 C
Switching-Off at 100 C
from Wolfspeed, ROHM, Monolith, and SEI were tested. Switching-Off at 200 C
Also, the dynamic test circuit design criteria and the neces- Switching-On at 25 C
sity of achieving minimum parasitics for the gate loop, Switching-On at 150 C
Switching-On at 100 C
power loop, and load inductor were explained.
Switching-On at 200 C
In the test procedure, equal conditions were created for
all of the devices to enable an unbiased comparison between FIG 11 The turn-on and turn-off switching losses versus
them. The recommended gate voltages were applied to all of junction temperature for the Wolfspeed X3M0050090G SiC
the devices in both the static and dynamic tests. Also, for MOSFET under test at various temperatures.

June 2017 z IEEE Power Electronics Magazine 43

 40 40

VDS /20 (V); ID (A)

VDS /20 (V); ID (A)
30 30
ID VDS
20 20
10 10
VDS ID
0 0
10 10
4.0425

4.0435

4.0445

4.0455

4.0465

4.0475

4.0485

4.0495

4.152

4.153

4.154

4.155

4.156

4.157

4.158

4.159
Time (ns) 104 Time (ns) 104
20 30
20 VGS
VGS (V)

10 VGS

VGS (V)
10
0
0

10 10
4.0425

4.0435

4.0445

4.0455

4.0465

4.0475

4.0485

4.0495

4.152

4.153

4.154

4.155

4.156

4.157

4.158

4.159
Time (ns) 104 Time (ns) 104
(a) (b)

FIG 12 (a) Switching-off and (b) switching-on waveforms of the Wolfspeed X3M0050090G MOSFET at four different temperatures:
25 C (blue), 100 C (green), 150 C (yellow), and 200 C (red).

Table 3. A summary of the properties and static and dynamic characterization results
acquired from different semiconductors.
RDSon
Device VDS (V) ID-cont (A) (mcm2) Vth (V) Ciss (nF) Coss (pF) Crss (pF) Eon (J) Eoff (J)
Wolfspeed #1 900 35 4.45 3 0.85 76.2 3.38 398.2 49.8
X3M0050090G
Wolfspeed #2 900 160 3.82 2.02 3.87 343 12.2 642.3 127.88
C3M0010090D-ES
ROHM 1,200 31 5.4 5.6 0.85 57.3 24.1 574.5 63.6
SCT3080KL
SEI 1,200 30 3.65 3.85 2.04 78.4 28.6 501.4 60.3
XSM3012J-ST01
Monolith #1 1,200 36 6.7 3.4 1.9 97.9 14.9 579.1 62.2
MSA12N080A
Monolith #2 1,200 120 6.65 2.52 6.24 316 47 649.5 167.2
MSA12N025A

The on-state resistance and switching losses of the SiC SiC material compared to Si material), and higher voltage
MOSFETs showed smaller change versus temperature com- operation capabilities, SiC MOSFETs are expected to domi-
pared to Si power MOSFETs. According to the study, a typi- nate in a wide variety of power electronics applications.
cal change of around 50% was observed in the on resistance
when the temperature was increased from 25 C to 150 C. About the Authors
This change in SiC MOSFETs is less than the dependency of Alinaghi Marzoughi (am87@vt.edu) received his B.S.
Si power MOSFETs, which is typically more than 100%. Also, and M.S. degrees in electrical engineering from the Univer-
the dynamic characterization conducted at high tempera- sity of Tehran, Iran, in 2010 and 2013, respectively. He is
tures revealed that the SiC MOSFETs experience a negligible currently working toward his Ph.D. degree at the Center
change in total switching loss. As an example, the switching for Power Electronics Systems, Virginia Polytechnic Insti-
losses of the Wolfspeed #1 MOSFET changed approximately tute and State University, Blacksburg. His research inter-
6% when the temperature increased from 25C to 200 C. Con- ests include power electronic converter modeling and con-
sidering their high-temperature operation capability, smaller trol, wide-bandgap semiconductors, and grid interface for
switching losses, three times better thermal conductivity (for renewable energy systems.

44 IEEE Power Electronics Magazine z June 2017

 Amy Romero (amym93@vt.edu) received her B.S.
degree in electrical engineering from Virginia Polytechnic
Institute and State University, Blacksburg, in 2015, where
she is currently continuing her studies, p ursuing her M.S.
degree and conducting research at the Center for Power
Electronics Systems. Her research has focused on charac-
terizing wide-bandgap devices.
Rolando Burgos (rolando@vt.edu) received his B.S.,
M.S., and Ph.D. degrees in electrical engineering from the
University of Concepcin, Chile, in 1995, 1999, and 2002,
respectively. He is currently an associate professor in the
Bradley Department of Electrical and Computer Engineering
and Center for Power Electronics Systems faculty at Virginia
Polytechnic Institute and State University, Blacksburg.
Dushan Boroyevich (dushan@ieee.org) received his
Dipl.Ing. degree from the University of Belgrade in 1976
and his M.S. degree from the University of Novi Sad in 1982,
in what was then Yugoslavia. He received his Ph.D. degree
in 1986 from Virginia Polytechnic Institute and State Univer-
sity, Blacksburg. From 1986 to 1990, he was an assis-
tant professor and director of the Power and Industrial
Electronics Research Program in the Institute for Power
and Electronic Engineering, University of Novi Sad. He then
joined the Bradley Department of Electrical and Computer
Engineering at Virginia Polytechnic Institute and State Uni-
versity, Blacksburg, as an associate professor, and he is cur-
rently the American Electric Power Professor and codirec-
tor of the Center for Power Electronics Systems.
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June 2017 z IEEE Power Electronics Magazine 45