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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. I Sem., I Mid-Term Examinations, September - 2017
COMPUTER ORGANIZATION
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
1. Which of the following mapping procedure is not used in organization of cache memory. [ ]
a) associative mapping b) page mapping c) direct mapping d) set associative mapping
2. In which addressing mode the effective address mode is equal to the address part of instruction
[ ]
a) Indirect addressing mode b) Index addressing mode
c) Relative addressing mode d) direct addressing mode
4. The bit used to signify that the cache location is updated is ________. [ ]
a) Dirty bit b) Update bit c) Reference bit d) Flag bit
5. The signal sent to the device from the processor to the device after receiving an interrupt is
[ ]
a) Interrupt-acknowledge b) Return signal c) Service signal d) Permission signal
10. The algorithm to remove and place new contents into the cache is called _______. [ ]
a) Replacement algorithm b) Renewal algorithm c) Updation d) None
Cont..2
Code No: 117BZ :2: Set No. 1
11. ________program is used to start computer software operation when the power is turned on.
12. ________________ RAM stores information in the form of electric charges applied to capacitors.
15. When CPU refers to memory and not finds the word in cache, but in main memory the process is called
_____.
17. The command which is used to test various status conditions in the interface and peripheral is called
________.
18. The unit which performs arithmetic and logical operations is called ____________________.
20. Interrupts arise from illegal or erroneous use of an instruction is called ________________ .
-oOo-
Code No: 117BZ Set No. 2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B. Tech. I Sem., I Mid-Term Examinations, September - 2017
COMPUTER ORGANIZATION
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
1. The bit used to signify that the cache location is updated is ________. [ ]
a) Dirty bit b) Update bit c) Reference bit d) Flag bit
2. The signal sent to the device from the processor to the device after receiving an interrupt is
[ ]
a) Interrupt-acknowledge b) Return signal c) Service signal d) Permission signal
7. The algorithm to remove and place new contents into the cache is called _______. [ ]
a) Replacement algorithm b) Renewal algorithm c) Updation d) None
8. Which of the following mapping procedure is not used in organization of cache memory. [ ]
a) associative mapping b) page mapping c) direct mapping d) set associative mapping
9. In which addressing mode the effective address mode is equal to the address part of instruction
[ ]
a) Indirect addressing mode b) Index addressing mode
c) Relative addressing mode d) direct addressing mode
Cont..2
Code No: 117BZ :2: Set No. 2
12. When CPU refers to memory and not finds the word in cache, but in main memory the process is called
_____.
14. The command which is used to test various status conditions in the interface and peripheral is called
________.
15. The unit which performs arithmetic and logical operations is called ____________________.
17. Interrupts arise from illegal or erroneous use of an instruction is called ________________ .
18. ________program is used to start computer software operation when the power is turned on.
19. ________________ RAM stores information in the form of electric charges applied to capacitors.
-oOo-
Code No: 117BZ Set No. 3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B. Tech. I Sem., I Mid-Term Examinations, September - 2017
COMPUTER ORGANIZATION
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
5. The algorithm to remove and place new contents into the cache is called _______. [ ]
a) Replacement algorithm b) Renewal algorithm c) Updation d) None
6. Which of the following mapping procedure is not used in organization of cache memory. [ ]
a) associative mapping b) page mapping c) direct mapping d) set associative mapping
7. In which addressing mode the effective address mode is equal to the address part of instruction
[ ]
a) Indirect addressing mode b) Index addressing mode
c) Relative addressing mode d) direct addressing mode
9. The bit used to signify that the cache location is updated is ________. [ ]
a) Dirty bit b) Update bit c) Reference bit d) Flag bit
10. The signal sent to the device from the processor to the device after receiving an interrupt is
[ ]
a) Interrupt-acknowledge b) Return signal c) Service signal d) Permission signal
Cont..2
Code No: 117BZ :2: Set No. 3
12. The command which is used to test various status conditions in the interface and peripheral is called
________.
13. The unit which performs arithmetic and logical operations is called ____________________.
15. Interrupts arise from illegal or erroneous use of an instruction is called ________________ .
16. ________program is used to start computer software operation when the power is turned on.
17. ________________ RAM stores information in the form of electric charges applied to capacitors.
20. When CPU refers to memory and not finds the word in cache, but in main memory the process is called
_____.
-oOo-
Code No: 117BZ Set No. 4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B. Tech. I Sem., I Mid-Term Examinations, September - 2017
COMPUTER ORGANIZATION
Objective Exam
Name: ______________________________ Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.
3. The algorithm to remove and place new contents into the cache is called _______. [ ]
a) Replacement algorithm b) Renewal algorithm c) Updation d) None
4. Which of the following mapping procedure is not used in organization of cache memory. [ ]
a) associative mapping b) page mapping c) direct mapping d) set associative mapping
5. In which addressing mode the effective address mode is equal to the address part of instruction
[ ]
a) Indirect addressing mode b) Index addressing mode
c) Relative addressing mode d) direct addressing mode
7. The bit used to signify that the cache location is updated is ________. [ ]
a) Dirty bit b) Update bit c) Reference bit d) Flag bit
8. The signal sent to the device from the processor to the device after receiving an interrupt is
[ ]
a) Interrupt-acknowledge b) Return signal c) Service signal d) Permission signal
Cont..2
Code No: 117BZ :2: Set No. 4
11. The unit which performs arithmetic and logical operations is called ____________________.
13. Interrupts arise from illegal or erroneous use of an instruction is called ________________ .
14. ________program is used to start computer software operation when the power is turned on.
15. ________________ RAM stores information in the form of electric charges applied to capacitors.
18. When CPU refers to memory and not finds the word in cache, but in main memory the process is called
_____.
20. The command which is used to test various status conditions in the interface and peripheral is called
________.
-oOo-