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Kuwait University Electrical Engineering Department

EE434 Electronics III laboratory

Pass Transistor and transmission gate logics


LEARNING OBJECTIVES

• The characteristics and operation of pass NMOS and PMOS transistor logic.
• The characteristics and operation of CMOS transmission gate logic.
• The resistance behavior for both logic

Theory

A conceptually simple approach for implementing logic functions utilizes series and parallel
combinations of switches that are controlled by input logic variables to connect the input and
output nodes. Each of the switches can be implemented either by a single NMOS transistor
(Fig. 1 known as pass-transistor logic (PTL)) or by a pair of complementary MOS transistors
connected in what is known as the CMOS transmission-gate configuration (Fig. 2). The pass
transistor logic reduces the number of transistors required to implement the logic. NMOS
transistors pass a strong 0 but a weak 1(threshold voltage drop. High =Vdd-Vtn) and PMOS
transistors pass a strong 1 but a weak 0(threshold voltage drop. Low= Vtp)

Fig. 1: Pass transistor Fig. 2: Transmission gate

Also the pass transistor logic can not be cascaded as shown in Fig.3 but can be cascaded as
shown in Fig. 4.

1
2
Spice model for the NMOS transistor in the laboratory is:

.model MbreakN-X NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10


+ NSUB=6.108619E+14 VTO=1.2 KP=500u GAMMA=2.2
+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000
+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=0.01
+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000
+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10
+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000

2.0V

1.5V

1.0V

0.5V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M3:d)
V_VIN

Vout versus Vin for NMOSFET pass transistor

5.0K
2.0M

4.0K

1.5M

3.0K

1.0M

2.0K

0.5M
1.0K

0 0
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V 1.6V 1.8V
ABS((V1(VIN)-V(R4:1))/I(VIN)) ABS((V1(VIN)-V(R4:1))/I(VIN))
V_VIN V_VIN

Resistance of NMOSFET vs. VIN Ron of NMOSFET vs. VIN

The solution of the output signal loss is solved by connecting the output node of the PTL to
the input of CMOS inverter. A PMOS transistor QR whose gate is controlled by the output of
the inverter and its drain connected to the output of the PTL as shown A3 in the discussion.

3
Great improvements in static and dynamic performance are obtained when the switches
implemented with CMOS transmission gates. The transmission gate utilizes a pair of
complementary transistors connected in parallel. It acts as an excellent switch, providing
bidirectional current flow (Fig. 5), and it exhibits an on-resistance that remains almost
constant for wide ranges of input voltage. These characteristics make the transmission gate
not only an excellent switch in digital applications but also an excellent analog switch in such
applications data converters and switched-capacitor filters.

4
5
5.0V

4.0V

3.0V

2.0V

1.0V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(R4:2)
V_V1

Vout versus Vin for Transmission Gate

Experimentally

A) NMOS & PMOS Pass Transistor Logic


PARTS AND MATERIALS

• CD4007 MOSFET gate.


• Pro board power supply.
• Semiconductor Parameter Analyzer hp 4145B
• Digital Multimeter.

For figure A1: Fig. A1:

1- Select an NMOSFET from the CD4007.


2- Set VA to 5V.
3- Change VIN from 0 to 5V IN STEP of 0.25V.
4- Measure the output voltage and the input current.

For figure A2: Fig. A2:

5- Connect the above circuit.


6- Prove the truth table.
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For figure A3: Fig. A3:

7- Connect the circuit of Figure A3.


8- Set VA to 5V.
9- Change VIN from 0 to 5V IN STEP of 0.25V.
10- Measure the output voltage Vo1.

B) Transmission Gate Logic


PARTS AND MATERIALS

• CD4007 MOSFET gate.


• Pro board power supply.
• Semiconductor Parameter Analyzer hp 4145B
• Digital Multimeter.

For figure B1:

11- Set VA to 5V.


12- Change VIN from 0 to 5V IN STEP of 0.25V.
13- Measure the output voltage and the input current.

Fig. B1:

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For figure B2:

Fig. B2:

14- Connect the above circuit.


15- Prove the truth table.

Discussion:
For figure A1:

1- Plot the experimental Vo versus VIN.


2- Using SPICE plot Vo versus VIN.
3- From the experimental part, calculate the NMOSFET resistance at the different values
of VIN.
4- Plot the calculated resistance versus Vin
5- Plot the on resistance only versus corresponding Vin
6- Using SPICE plot the resistance R and Ron of NMOS versus VIN
7- Comment on the plot.

For figure A2:

8- Comment on the measured truth table.

For figure A3:

9- Using SPICE plot Vo versus VIN when VA=5V.

For figure B1:

10- Plot the experimental Vo versus VIN.


11- Using SPICE plot Vo versus VIN.
12- From the experimental part, calculate the Transmission gate resistances at the
different values of VIN.
13- Plot the calculated resistances versus Vin.
14- Using SPICE plot the resistance of Transmission Gate versus VIN and compare with
experimental one.
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For figure B2:

15- Comment on the measured truth table.

Spice model for the PMOS transistor in the laboratory is:

.model MbreakP-X PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10


+ NSUB=1.056124E+16 VTO=-1.2 KP=600u GAMMA=0.5
+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9
+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=.05
+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000
+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10
+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000